2 * S3C2416/2450 CPUfreq Support
4 * Copyright 2011 Heiko Stuebner <heiko@sntech.de>
6 * based on s3c64xx_cpufreq.c
8 * Copyright 2009 Wolfson Microelectronics plc
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/init.h>
18 #include <linux/cpufreq.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/reboot.h>
23 #include <linux/module.h>
25 static DEFINE_MUTEX(cpufreq_lock
);
32 unsigned long regulator_latency
;
33 #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
34 struct regulator
*vddarm
;
37 struct cpufreq_frequency_table
*freq_table
;
43 static struct s3c2416_data s3c2416_cpufreq
;
46 unsigned int vddarm_min
;
47 unsigned int vddarm_max
;
50 /* pseudo-frequency for dvs mode */
51 #define FREQ_DVS 132333
53 /* frequency to sleep and reboot in
54 * it's essential to leave dvs, as some boards do not reconfigure the
57 #define FREQ_SLEEP 133333
59 /* Sources for the ARMCLK */
61 #define SOURCE_ARMDIV 1
63 #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
64 /* S3C2416 only supports changing the voltage in the dvs-mode.
65 * Voltages down to 1.0V seem to work, so we take what the regulator
68 static struct s3c2416_dvfs s3c2416_dvfs_table
[] = {
69 [SOURCE_HCLK
] = { 950000, 1250000 },
70 [SOURCE_ARMDIV
] = { 1250000, 1350000 },
74 static struct cpufreq_frequency_table s3c2416_freq_table
[] = {
75 { SOURCE_HCLK
, FREQ_DVS
},
76 { SOURCE_ARMDIV
, 133333 },
77 { SOURCE_ARMDIV
, 266666 },
78 { SOURCE_ARMDIV
, 400000 },
79 { 0, CPUFREQ_TABLE_END
},
82 static struct cpufreq_frequency_table s3c2450_freq_table
[] = {
83 { SOURCE_HCLK
, FREQ_DVS
},
84 { SOURCE_ARMDIV
, 133500 },
85 { SOURCE_ARMDIV
, 267000 },
86 { SOURCE_ARMDIV
, 534000 },
87 { 0, CPUFREQ_TABLE_END
},
90 static unsigned int s3c2416_cpufreq_get_speed(unsigned int cpu
)
92 struct s3c2416_data
*s3c_freq
= &s3c2416_cpufreq
;
97 /* return our pseudo-frequency when in dvs mode */
101 return clk_get_rate(s3c_freq
->armclk
) / 1000;
104 static int s3c2416_cpufreq_set_armdiv(struct s3c2416_data
*s3c_freq
,
109 if (clk_get_rate(s3c_freq
->armdiv
) / 1000 != freq
) {
110 ret
= clk_set_rate(s3c_freq
->armdiv
, freq
* 1000);
112 pr_err("cpufreq: Failed to set armdiv rate %dkHz: %d\n",
121 static int s3c2416_cpufreq_enter_dvs(struct s3c2416_data
*s3c_freq
, int idx
)
123 #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
124 struct s3c2416_dvfs
*dvfs
;
128 if (s3c_freq
->is_dvs
) {
129 pr_debug("cpufreq: already in dvs mode, nothing to do\n");
133 pr_debug("cpufreq: switching armclk to hclk (%lukHz)\n",
134 clk_get_rate(s3c_freq
->hclk
) / 1000);
135 ret
= clk_set_parent(s3c_freq
->armclk
, s3c_freq
->hclk
);
137 pr_err("cpufreq: Failed to switch armclk to hclk: %d\n", ret
);
141 #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
142 /* changing the core voltage is only allowed when in dvs mode */
143 if (s3c_freq
->vddarm
) {
144 dvfs
= &s3c2416_dvfs_table
[idx
];
146 pr_debug("cpufreq: setting regulator to %d-%d\n",
147 dvfs
->vddarm_min
, dvfs
->vddarm_max
);
148 ret
= regulator_set_voltage(s3c_freq
->vddarm
,
152 /* when lowering the voltage failed, there is nothing to do */
154 pr_err("cpufreq: Failed to set VDDARM: %d\n", ret
);
158 s3c_freq
->is_dvs
= 1;
163 static int s3c2416_cpufreq_leave_dvs(struct s3c2416_data
*s3c_freq
, int idx
)
165 #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
166 struct s3c2416_dvfs
*dvfs
;
170 if (!s3c_freq
->is_dvs
) {
171 pr_debug("cpufreq: not in dvs mode, so can't leave\n");
175 #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
176 if (s3c_freq
->vddarm
) {
177 dvfs
= &s3c2416_dvfs_table
[idx
];
179 pr_debug("cpufreq: setting regulator to %d-%d\n",
180 dvfs
->vddarm_min
, dvfs
->vddarm_max
);
181 ret
= regulator_set_voltage(s3c_freq
->vddarm
,
185 pr_err("cpufreq: Failed to set VDDARM: %d\n", ret
);
191 /* force armdiv to hclk frequency for transition from dvs*/
192 if (clk_get_rate(s3c_freq
->armdiv
) > clk_get_rate(s3c_freq
->hclk
)) {
193 pr_debug("cpufreq: force armdiv to hclk frequency (%lukHz)\n",
194 clk_get_rate(s3c_freq
->hclk
) / 1000);
195 ret
= s3c2416_cpufreq_set_armdiv(s3c_freq
,
196 clk_get_rate(s3c_freq
->hclk
) / 1000);
198 pr_err("cpufreq: Failed to set the armdiv to %lukHz: %d\n",
199 clk_get_rate(s3c_freq
->hclk
) / 1000, ret
);
204 pr_debug("cpufreq: switching armclk parent to armdiv (%lukHz)\n",
205 clk_get_rate(s3c_freq
->armdiv
) / 1000);
207 ret
= clk_set_parent(s3c_freq
->armclk
, s3c_freq
->armdiv
);
209 pr_err("cpufreq: Failed to switch armclk clock parent to armdiv: %d\n",
214 s3c_freq
->is_dvs
= 0;
219 static int s3c2416_cpufreq_set_target(struct cpufreq_policy
*policy
,
222 struct s3c2416_data
*s3c_freq
= &s3c2416_cpufreq
;
223 struct cpufreq_freqs freqs
;
224 int idx
, ret
, to_dvs
= 0;
226 mutex_lock(&cpufreq_lock
);
228 idx
= s3c_freq
->freq_table
[index
].driver_data
;
230 if (idx
== SOURCE_HCLK
)
233 /* switching to dvs when it's not allowed */
234 if (to_dvs
&& s3c_freq
->disable_dvs
) {
235 pr_debug("cpufreq: entering dvs mode not allowed\n");
241 freqs
.old
= s3c_freq
->is_dvs
? FREQ_DVS
242 : clk_get_rate(s3c_freq
->armclk
) / 1000;
244 /* When leavin dvs mode, always switch the armdiv to the hclk rate
245 * The S3C2416 has stability issues when switching directly to
246 * higher frequencies.
248 freqs
.new = (s3c_freq
->is_dvs
&& !to_dvs
)
249 ? clk_get_rate(s3c_freq
->hclk
) / 1000
250 : s3c_freq
->freq_table
[index
].frequency
;
252 pr_debug("cpufreq: Transition %d-%dkHz\n", freqs
.old
, freqs
.new);
254 if (!to_dvs
&& freqs
.old
== freqs
.new)
257 cpufreq_notify_transition(policy
, &freqs
, CPUFREQ_PRECHANGE
);
260 pr_debug("cpufreq: enter dvs\n");
261 ret
= s3c2416_cpufreq_enter_dvs(s3c_freq
, idx
);
262 } else if (s3c_freq
->is_dvs
) {
263 pr_debug("cpufreq: leave dvs\n");
264 ret
= s3c2416_cpufreq_leave_dvs(s3c_freq
, idx
);
266 pr_debug("cpufreq: change armdiv to %dkHz\n", freqs
.new);
267 ret
= s3c2416_cpufreq_set_armdiv(s3c_freq
, freqs
.new);
270 cpufreq_notify_transition(policy
, &freqs
, CPUFREQ_POSTCHANGE
);
273 mutex_unlock(&cpufreq_lock
);
278 #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
279 static void __init
s3c2416_cpufreq_cfg_regulator(struct s3c2416_data
*s3c_freq
)
281 int count
, v
, i
, found
;
282 struct cpufreq_frequency_table
*freq
;
283 struct s3c2416_dvfs
*dvfs
;
285 count
= regulator_count_voltages(s3c_freq
->vddarm
);
287 pr_err("cpufreq: Unable to check supported voltages\n");
291 freq
= s3c_freq
->freq_table
;
292 while (count
> 0 && freq
->frequency
!= CPUFREQ_TABLE_END
) {
293 if (freq
->frequency
== CPUFREQ_ENTRY_INVALID
)
296 dvfs
= &s3c2416_dvfs_table
[freq
->driver_data
];
299 /* Check only the min-voltage, more is always ok on S3C2416 */
300 for (i
= 0; i
< count
; i
++) {
301 v
= regulator_list_voltage(s3c_freq
->vddarm
, i
);
302 if (v
>= dvfs
->vddarm_min
)
307 pr_debug("cpufreq: %dkHz unsupported by regulator\n",
309 freq
->frequency
= CPUFREQ_ENTRY_INVALID
;
316 s3c_freq
->regulator_latency
= 1 * 1000 * 1000;
320 static int s3c2416_cpufreq_reboot_notifier_evt(struct notifier_block
*this,
321 unsigned long event
, void *ptr
)
323 struct s3c2416_data
*s3c_freq
= &s3c2416_cpufreq
;
326 mutex_lock(&cpufreq_lock
);
328 /* disable further changes */
329 s3c_freq
->disable_dvs
= 1;
331 mutex_unlock(&cpufreq_lock
);
333 /* some boards don't reconfigure the regulator on reboot, which
334 * could lead to undervolting the cpu when the clock is reset.
335 * Therefore we always leave the DVS mode on reboot.
337 if (s3c_freq
->is_dvs
) {
338 pr_debug("cpufreq: leave dvs on reboot\n");
339 ret
= cpufreq_driver_target(cpufreq_cpu_get(0), FREQ_SLEEP
, 0);
347 static struct notifier_block s3c2416_cpufreq_reboot_notifier
= {
348 .notifier_call
= s3c2416_cpufreq_reboot_notifier_evt
,
351 static int __init
s3c2416_cpufreq_driver_init(struct cpufreq_policy
*policy
)
353 struct s3c2416_data
*s3c_freq
= &s3c2416_cpufreq
;
354 struct cpufreq_frequency_table
*freq
;
359 if (policy
->cpu
!= 0)
362 msysclk
= clk_get(NULL
, "msysclk");
363 if (IS_ERR(msysclk
)) {
364 ret
= PTR_ERR(msysclk
);
365 pr_err("cpufreq: Unable to obtain msysclk: %d\n", ret
);
370 * S3C2416 and S3C2450 share the same processor-ID and also provide no
371 * other means to distinguish them other than through the rate of
372 * msysclk. On S3C2416 msysclk runs at 800MHz and on S3C2450 at 533MHz.
374 rate
= clk_get_rate(msysclk
);
375 if (rate
== 800 * 1000 * 1000) {
376 pr_info("cpufreq: msysclk running at %lukHz, using S3C2416 frequency table\n",
378 s3c_freq
->freq_table
= s3c2416_freq_table
;
379 policy
->cpuinfo
.max_freq
= 400000;
380 } else if (rate
/ 1000 == 534000) {
381 pr_info("cpufreq: msysclk running at %lukHz, using S3C2450 frequency table\n",
383 s3c_freq
->freq_table
= s3c2450_freq_table
;
384 policy
->cpuinfo
.max_freq
= 534000;
387 /* not needed anymore */
390 if (s3c_freq
->freq_table
== NULL
) {
391 pr_err("cpufreq: No frequency information for this CPU, msysclk at %lukHz\n",
396 s3c_freq
->is_dvs
= 0;
398 s3c_freq
->armdiv
= clk_get(NULL
, "armdiv");
399 if (IS_ERR(s3c_freq
->armdiv
)) {
400 ret
= PTR_ERR(s3c_freq
->armdiv
);
401 pr_err("cpufreq: Unable to obtain ARMDIV: %d\n", ret
);
405 s3c_freq
->hclk
= clk_get(NULL
, "hclk");
406 if (IS_ERR(s3c_freq
->hclk
)) {
407 ret
= PTR_ERR(s3c_freq
->hclk
);
408 pr_err("cpufreq: Unable to obtain HCLK: %d\n", ret
);
412 /* chech hclk rate, we only support the common 133MHz for now
413 * hclk could also run at 66MHz, but this not often used
415 rate
= clk_get_rate(s3c_freq
->hclk
);
416 if (rate
< 133 * 1000 * 1000) {
417 pr_err("cpufreq: HCLK not at 133MHz\n");
418 clk_put(s3c_freq
->hclk
);
423 s3c_freq
->armclk
= clk_get(NULL
, "armclk");
424 if (IS_ERR(s3c_freq
->armclk
)) {
425 ret
= PTR_ERR(s3c_freq
->armclk
);
426 pr_err("cpufreq: Unable to obtain ARMCLK: %d\n", ret
);
430 #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
431 s3c_freq
->vddarm
= regulator_get(NULL
, "vddarm");
432 if (IS_ERR(s3c_freq
->vddarm
)) {
433 ret
= PTR_ERR(s3c_freq
->vddarm
);
434 pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret
);
438 s3c2416_cpufreq_cfg_regulator(s3c_freq
);
440 s3c_freq
->regulator_latency
= 0;
443 freq
= s3c_freq
->freq_table
;
444 while (freq
->frequency
!= CPUFREQ_TABLE_END
) {
445 /* special handling for dvs mode */
446 if (freq
->driver_data
== 0) {
447 if (!s3c_freq
->hclk
) {
448 pr_debug("cpufreq: %dkHz unsupported as it would need unavailable dvs mode\n",
450 freq
->frequency
= CPUFREQ_ENTRY_INVALID
;
457 /* Check for frequencies we can generate */
458 rate
= clk_round_rate(s3c_freq
->armdiv
,
459 freq
->frequency
* 1000);
461 if (rate
!= freq
->frequency
) {
462 pr_debug("cpufreq: %dkHz unsupported by clock (clk_round_rate return %lu)\n",
463 freq
->frequency
, rate
);
464 freq
->frequency
= CPUFREQ_ENTRY_INVALID
;
470 /* Datasheet says PLL stabalisation time must be at least 300us,
471 * so but add some fudge. (reference in LOCKCON0 register description)
473 ret
= cpufreq_generic_init(policy
, s3c_freq
->freq_table
,
474 (500 * 1000) + s3c_freq
->regulator_latency
);
478 register_reboot_notifier(&s3c2416_cpufreq_reboot_notifier
);
483 #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
484 regulator_put(s3c_freq
->vddarm
);
487 clk_put(s3c_freq
->armclk
);
489 clk_put(s3c_freq
->hclk
);
491 clk_put(s3c_freq
->armdiv
);
496 static struct cpufreq_driver s3c2416_cpufreq_driver
= {
498 .verify
= cpufreq_generic_frequency_table_verify
,
499 .target_index
= s3c2416_cpufreq_set_target
,
500 .get
= s3c2416_cpufreq_get_speed
,
501 .init
= s3c2416_cpufreq_driver_init
,
503 .attr
= cpufreq_generic_attr
,
506 static int __init
s3c2416_cpufreq_init(void)
508 return cpufreq_register_driver(&s3c2416_cpufreq_driver
);
510 module_init(s3c2416_cpufreq_init
);