2 * Copyright 2009 Wolfson Microelectronics plc
4 * S3C64xx CPUfreq Support
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) "cpufreq: " fmt
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/init.h>
16 #include <linux/cpufreq.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/module.h>
22 static struct clk
*armclk
;
23 static struct regulator
*vddarm
;
24 static unsigned long regulator_latency
;
26 #ifdef CONFIG_CPU_S3C6410
28 unsigned int vddarm_min
;
29 unsigned int vddarm_max
;
32 static struct s3c64xx_dvfs s3c64xx_dvfs_table
[] = {
33 [0] = { 1000000, 1150000 },
34 [1] = { 1050000, 1150000 },
35 [2] = { 1100000, 1150000 },
36 [3] = { 1200000, 1350000 },
37 [4] = { 1300000, 1350000 },
40 static struct cpufreq_frequency_table s3c64xx_freq_table
[] = {
53 { 0, CPUFREQ_TABLE_END
},
57 static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu
)
62 return clk_get_rate(armclk
) / 1000;
65 static int s3c64xx_cpufreq_set_target(struct cpufreq_policy
*policy
,
66 unsigned int target_freq
,
67 unsigned int relation
)
71 struct cpufreq_freqs freqs
;
72 struct s3c64xx_dvfs
*dvfs
;
74 ret
= cpufreq_frequency_table_target(policy
, s3c64xx_freq_table
,
75 target_freq
, relation
, &i
);
79 freqs
.old
= clk_get_rate(armclk
) / 1000;
80 freqs
.new = s3c64xx_freq_table
[i
].frequency
;
82 dvfs
= &s3c64xx_dvfs_table
[s3c64xx_freq_table
[i
].driver_data
];
84 if (freqs
.old
== freqs
.new)
87 pr_debug("Transition %d-%dkHz\n", freqs
.old
, freqs
.new);
89 cpufreq_notify_transition(policy
, &freqs
, CPUFREQ_PRECHANGE
);
91 #ifdef CONFIG_REGULATOR
92 if (vddarm
&& freqs
.new > freqs
.old
) {
93 ret
= regulator_set_voltage(vddarm
,
97 pr_err("Failed to set VDDARM for %dkHz: %d\n",
99 freqs
.new = freqs
.old
;
105 ret
= clk_set_rate(armclk
, freqs
.new * 1000);
107 pr_err("Failed to set rate %dkHz: %d\n",
109 freqs
.new = freqs
.old
;
113 cpufreq_notify_transition(policy
, &freqs
, CPUFREQ_POSTCHANGE
);
117 #ifdef CONFIG_REGULATOR
118 if (vddarm
&& freqs
.new < freqs
.old
) {
119 ret
= regulator_set_voltage(vddarm
,
123 pr_err("Failed to set VDDARM for %dkHz: %d\n",
130 pr_debug("Set actual frequency %lukHz\n",
131 clk_get_rate(armclk
) / 1000);
136 if (clk_set_rate(armclk
, freqs
.old
* 1000) < 0)
137 pr_err("Failed to restore original clock rate\n");
139 cpufreq_notify_transition(policy
, &freqs
, CPUFREQ_POSTCHANGE
);
144 #ifdef CONFIG_REGULATOR
145 static void __init
s3c64xx_cpufreq_config_regulator(void)
147 int count
, v
, i
, found
;
148 struct cpufreq_frequency_table
*freq
;
149 struct s3c64xx_dvfs
*dvfs
;
151 count
= regulator_count_voltages(vddarm
);
153 pr_err("Unable to check supported voltages\n");
156 freq
= s3c64xx_freq_table
;
157 while (count
> 0 && freq
->frequency
!= CPUFREQ_TABLE_END
) {
158 if (freq
->frequency
== CPUFREQ_ENTRY_INVALID
)
161 dvfs
= &s3c64xx_dvfs_table
[freq
->index
];
164 for (i
= 0; i
< count
; i
++) {
165 v
= regulator_list_voltage(vddarm
, i
);
166 if (v
>= dvfs
->vddarm_min
&& v
<= dvfs
->vddarm_max
)
171 pr_debug("%dkHz unsupported by regulator\n",
173 freq
->frequency
= CPUFREQ_ENTRY_INVALID
;
179 /* Guess based on having to do an I2C/SPI write; in future we
180 * will be able to query the regulator performance here. */
181 regulator_latency
= 1 * 1000 * 1000;
185 static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy
*policy
)
188 struct cpufreq_frequency_table
*freq
;
190 if (policy
->cpu
!= 0)
193 if (s3c64xx_freq_table
== NULL
) {
194 pr_err("No frequency information for this CPU\n");
198 armclk
= clk_get(NULL
, "armclk");
199 if (IS_ERR(armclk
)) {
200 pr_err("Unable to obtain ARMCLK: %ld\n",
202 return PTR_ERR(armclk
);
205 #ifdef CONFIG_REGULATOR
206 vddarm
= regulator_get(NULL
, "vddarm");
207 if (IS_ERR(vddarm
)) {
208 ret
= PTR_ERR(vddarm
);
209 pr_err("Failed to obtain VDDARM: %d\n", ret
);
210 pr_err("Only frequency scaling available\n");
213 s3c64xx_cpufreq_config_regulator();
217 freq
= s3c64xx_freq_table
;
218 while (freq
->frequency
!= CPUFREQ_TABLE_END
) {
221 /* Check for frequencies we can generate */
222 r
= clk_round_rate(armclk
, freq
->frequency
* 1000);
224 if (r
!= freq
->frequency
) {
225 pr_debug("%dkHz unsupported by clock\n",
227 freq
->frequency
= CPUFREQ_ENTRY_INVALID
;
230 /* If we have no regulator then assume startup
231 * frequency is the maximum we can support. */
232 if (!vddarm
&& freq
->frequency
> s3c64xx_cpufreq_get_speed(0))
233 freq
->frequency
= CPUFREQ_ENTRY_INVALID
;
238 /* Datasheet says PLL stabalisation time (if we were to use
239 * the PLLs, which we don't currently) is ~300us worst case,
240 * but add some fudge.
242 ret
= cpufreq_generic_init(policy
, s3c64xx_freq_table
,
243 (500 * 1000) + regulator_latency
);
245 pr_err("Failed to configure frequency table: %d\n",
247 regulator_put(vddarm
);
254 static struct cpufreq_driver s3c64xx_cpufreq_driver
= {
256 .verify
= cpufreq_generic_frequency_table_verify
,
257 .target
= s3c64xx_cpufreq_set_target
,
258 .get
= s3c64xx_cpufreq_get_speed
,
259 .init
= s3c64xx_cpufreq_driver_init
,
263 static int __init
s3c64xx_cpufreq_init(void)
265 return cpufreq_register_driver(&s3c64xx_cpufreq_driver
);
267 module_init(s3c64xx_cpufreq_init
);