drivers/cpufreq/s5pv210-cpufreq.c

   1 /*
   2  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * CPU frequency scaling for S5PC110/S5PV210
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/types.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/cpufreq.h>
  19 #include <linux/reboot.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/suspend.h>
  22
  23 #include <mach/map.h>
  24 #include <mach/regs-clock.h>
  25
  26 static struct clk *cpu_clk;
  27 static struct clk *dmc0_clk;
  28 static struct clk *dmc1_clk;
  29 static struct cpufreq_freqs freqs;
  30 static DEFINE_MUTEX(set_freq_lock);
  31
  32 /* APLL M,P,S values for 1G/800Mhz */
  33 #define APLL_VAL_1000   ((1 << 31) | (125 << 16) | (3 << 8) | 1)
  34 #define APLL_VAL_800    ((1 << 31) | (100 << 16) | (3 << 8) | 1)
  35
  36 /* Use 800MHz when entering sleep mode */
  37 #define SLEEP_FREQ      (800 * 1000)
  38
  39 /* Tracks if cpu freqency can be updated anymore */
  40 static bool no_cpufreq_access;
  41
  42 /*
  43  * DRAM configurations to calculate refresh counter for changing
  44  * frequency of memory.
  45  */
  46 struct dram_conf {
  47         unsigned long freq;     /* HZ */
  48         unsigned long refresh;  /* DRAM refresh counter * 1000 */
  49 };
  50
  51 /* DRAM configuration (DMC0 and DMC1) */
  52 static struct dram_conf s5pv210_dram_conf[2];
  53
  54 enum perf_level {
  55         L0, L1, L2, L3, L4,
  56 };
  57
  58 enum s5pv210_mem_type {
  59         LPDDR   = 0x1,
  60         LPDDR2  = 0x2,
  61         DDR2    = 0x4,
  62 };
  63
  64 enum s5pv210_dmc_port {
  65         DMC0 = 0,
  66         DMC1,
  67 };
  68
  69 static struct cpufreq_frequency_table s5pv210_freq_table[] = {
  70         {L0, 1000*1000},
  71         {L1, 800*1000},
  72         {L2, 400*1000},
  73         {L3, 200*1000},
  74         {L4, 100*1000},
  75         {0, CPUFREQ_TABLE_END},
  76 };
  77
  78 static struct regulator *arm_regulator;
  79 static struct regulator *int_regulator;
  80
  81 struct s5pv210_dvs_conf {
  82         int arm_volt;   /* uV */
  83         int int_volt;   /* uV */
  84 };
  85
  86 static const int arm_volt_max = 1350000;
  87 static const int int_volt_max = 1250000;
  88
  89 static struct s5pv210_dvs_conf dvs_conf[] = {
  90         [L0] = {
  91                 .arm_volt       = 1250000,
  92                 .int_volt       = 1100000,
  93         },
  94         [L1] = {
  95                 .arm_volt       = 1200000,
  96                 .int_volt       = 1100000,
  97         },
  98         [L2] = {
  99                 .arm_volt       = 1050000,
 100                 .int_volt       = 1100000,
 101         },
 102         [L3] = {
 103                 .arm_volt       = 950000,
 104                 .int_volt       = 1100000,
 105         },
 106         [L4] = {
 107                 .arm_volt       = 950000,
 108                 .int_volt       = 1000000,
 109         },
 110 };
 111
 112 static u32 clkdiv_val[5][11] = {
 113         /*
 114          * Clock divider value for following
 115          * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
 116          *   HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
 117          *   ONEDRAM, MFC, G3D }
 118          */
 119
 120         /* L0 : [1000/200/100][166/83][133/66][200/200] */
 121         {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
 122
 123         /* L1 : [800/200/100][166/83][133/66][200/200] */
 124         {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
 125
 126         /* L2 : [400/200/100][166/83][133/66][200/200] */
 127         {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
 128
 129         /* L3 : [200/200/100][166/83][133/66][200/200] */
 130         {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
 131
 132         /* L4 : [100/100/100][83/83][66/66][100/100] */
 133         {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
 134 };
 135
 136 /*
 137  * This function set DRAM refresh counter
 138  * accoriding to operating frequency of DRAM
 139  * ch: DMC port number 0 or 1
 140  * freq: Operating frequency of DRAM(KHz)
 141  */
 142 static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
 143 {
 144         unsigned long tmp, tmp1;
 145         void __iomem *reg = NULL;
 146
 147         if (ch == DMC0) {
 148                 reg = (S5P_VA_DMC0 + 0x30);
 149         } else if (ch == DMC1) {
 150                 reg = (S5P_VA_DMC1 + 0x30);
 151         } else {
 152                 printk(KERN_ERR "Cannot find DMC port\n");
 153                 return;
 154         }
 155
 156         /* Find current DRAM frequency */
 157         tmp = s5pv210_dram_conf[ch].freq;
 158
 159         do_div(tmp, freq);
 160
 161         tmp1 = s5pv210_dram_conf[ch].refresh;
 162
 163         do_div(tmp1, tmp);
 164
 165         __raw_writel(tmp1, reg);
 166 }
 167
 168 static unsigned int s5pv210_getspeed(unsigned int cpu)
 169 {
 170         if (cpu)
 171                 return 0;
 172
 173         return clk_get_rate(cpu_clk) / 1000;
 174 }
 175
 176 static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
 177 {
 178         unsigned long reg;
 179         unsigned int priv_index;
 180         unsigned int pll_changing = 0;
 181         unsigned int bus_speed_changing = 0;
 182         int arm_volt, int_volt;
 183         int ret = 0;
 184
 185         mutex_lock(&set_freq_lock);
 186
 187         if (no_cpufreq_access) {
 188 #ifdef CONFIG_PM_VERBOSE
 189                 pr_err("%s:%d denied access to %s as it is disabled"
 190                                 "temporarily\n", __FILE__, __LINE__, __func__);
 191 #endif
 192                 ret = -EINVAL;
 193                 goto exit;
 194         }
 195
 196         freqs.old = s5pv210_getspeed(0);
 197         freqs.new = s5pv210_freq_table[index].frequency;
 198
 199         /* Finding current running level index */
 200         if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
 201                                            freqs.old, CPUFREQ_RELATION_H,
 202                                            &priv_index)) {
 203                 ret = -EINVAL;
 204                 goto exit;
 205         }
 206
 207         arm_volt = dvs_conf[index].arm_volt;
 208         int_volt = dvs_conf[index].int_volt;
 209
 210         if (freqs.new > freqs.old) {
 211                 ret = regulator_set_voltage(arm_regulator,
 212                                 arm_volt, arm_volt_max);
 213                 if (ret)
 214                         goto exit;
 215
 216                 ret = regulator_set_voltage(int_regulator,
 217                                 int_volt, int_volt_max);
 218                 if (ret)
 219                         goto exit;
 220         }
 221
 222         cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
 223
 224         /* Check if there need to change PLL */
 225         if ((index == L0) || (priv_index == L0))
 226                 pll_changing = 1;
 227
 228         /* Check if there need to change System bus clock */
 229         if ((index == L4) || (priv_index == L4))
 230                 bus_speed_changing = 1;
 231
 232         if (bus_speed_changing) {
 233                 /*
 234                  * Reconfigure DRAM refresh counter value for minimum
 235                  * temporary clock while changing divider.
 236                  * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
 237                  */
 238                 if (pll_changing)
 239                         s5pv210_set_refresh(DMC1, 83000);
 240                 else
 241                         s5pv210_set_refresh(DMC1, 100000);
 242
 243                 s5pv210_set_refresh(DMC0, 83000);
 244         }
 245
 246         /*
 247          * APLL should be changed in this level
 248          * APLL -> MPLL(for stable transition) -> APLL
 249          * Some clock source's clock API are not prepared.
 250          * Do not use clock API in below code.
 251          */
 252         if (pll_changing) {
 253                 /*
 254                  * 1. Temporary Change divider for MFC and G3D
 255                  * SCLKA2M(200/1=200)->(200/4=50)Mhz
 256                  */
 257                 reg = __raw_readl(S5P_CLK_DIV2);
 258                 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
 259                 reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
 260                         (3 << S5P_CLKDIV2_MFC_SHIFT);
 261                 __raw_writel(reg, S5P_CLK_DIV2);
 262
 263                 /* For MFC, G3D dividing */
 264                 do {
 265                         reg = __raw_readl(S5P_CLKDIV_STAT0);
 266                 } while (reg & ((1 << 16) | (1 << 17)));
 267
 268                 /*
 269                  * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
 270                  * (200/4=50)->(667/4=166)Mhz
 271                  */
 272                 reg = __raw_readl(S5P_CLK_SRC2);
 273                 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
 274                 reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
 275                         (1 << S5P_CLKSRC2_MFC_SHIFT);
 276                 __raw_writel(reg, S5P_CLK_SRC2);
 277
 278                 do {
 279                         reg = __raw_readl(S5P_CLKMUX_STAT1);
 280                 } while (reg & ((1 << 7) | (1 << 3)));
 281
 282                 /*
 283                  * 3. DMC1 refresh count for 133Mhz if (index == L4) is
 284                  * true refresh counter is already programed in upper
 285                  * code. 0x287@83Mhz
 286                  */
 287                 if (!bus_speed_changing)
 288                         s5pv210_set_refresh(DMC1, 133000);
 289
 290                 /* 4. SCLKAPLL -> SCLKMPLL */
 291                 reg = __raw_readl(S5P_CLK_SRC0);
 292                 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
 293                 reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
 294                 __raw_writel(reg, S5P_CLK_SRC0);
 295
 296                 do {
 297                         reg = __raw_readl(S5P_CLKMUX_STAT0);
 298                 } while (reg & (0x1 << 18));
 299
 300         }
 301
 302         /* Change divider */
 303         reg = __raw_readl(S5P_CLK_DIV0);
 304
 305         reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
 306                 S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
 307                 S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
 308                 S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
 309
 310         reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
 311                 (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
 312                 (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
 313                 (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
 314                 (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
 315                 (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
 316                 (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
 317                 (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
 318
 319         __raw_writel(reg, S5P_CLK_DIV0);
 320
 321         do {
 322                 reg = __raw_readl(S5P_CLKDIV_STAT0);
 323         } while (reg & 0xff);
 324
 325         /* ARM MCS value changed */
 326         reg = __raw_readl(S5P_ARM_MCS_CON);
 327         reg &= ~0x3;
 328         if (index >= L3)
 329                 reg |= 0x3;
 330         else
 331                 reg |= 0x1;
 332
 333         __raw_writel(reg, S5P_ARM_MCS_CON);
 334
 335         if (pll_changing) {
 336                 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
 337                 __raw_writel(0x2cf, S5P_APLL_LOCK);
 338
 339                 /*
 340                  * 6. Turn on APLL
 341                  * 6-1. Set PMS values
 342                  * 6-2. Wait untile the PLL is locked
 343                  */
 344                 if (index == L0)
 345                         __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
 346                 else
 347                         __raw_writel(APLL_VAL_800, S5P_APLL_CON);
 348
 349                 do {
 350                         reg = __raw_readl(S5P_APLL_CON);
 351                 } while (!(reg & (0x1 << 29)));
 352
 353                 /*
 354                  * 7. Change souce clock from SCLKMPLL(667Mhz)
 355                  * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
 356                  * (667/4=166)->(200/4=50)Mhz
 357                  */
 358                 reg = __raw_readl(S5P_CLK_SRC2);
 359                 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
 360                 reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
 361                         (0 << S5P_CLKSRC2_MFC_SHIFT);
 362                 __raw_writel(reg, S5P_CLK_SRC2);
 363
 364                 do {
 365                         reg = __raw_readl(S5P_CLKMUX_STAT1);
 366                 } while (reg & ((1 << 7) | (1 << 3)));
 367
 368                 /*
 369                  * 8. Change divider for MFC and G3D
 370                  * (200/4=50)->(200/1=200)Mhz
 371                  */
 372                 reg = __raw_readl(S5P_CLK_DIV2);
 373                 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
 374                 reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
 375                         (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
 376                 __raw_writel(reg, S5P_CLK_DIV2);
 377
 378                 /* For MFC, G3D dividing */
 379                 do {
 380                         reg = __raw_readl(S5P_CLKDIV_STAT0);
 381                 } while (reg & ((1 << 16) | (1 << 17)));
 382
 383                 /* 9. Change MPLL to APLL in MSYS_MUX */
 384                 reg = __raw_readl(S5P_CLK_SRC0);
 385                 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
 386                 reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
 387                 __raw_writel(reg, S5P_CLK_SRC0);
 388
 389                 do {
 390                         reg = __raw_readl(S5P_CLKMUX_STAT0);
 391                 } while (reg & (0x1 << 18));
 392
 393                 /*
 394                  * 10. DMC1 refresh counter
 395                  * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
 396                  * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
 397                  */
 398                 if (!bus_speed_changing)
 399                         s5pv210_set_refresh(DMC1, 200000);
 400         }
 401
 402         /*
 403          * L4 level need to change memory bus speed, hence onedram clock divier
 404          * and memory refresh parameter should be changed
 405          */
 406         if (bus_speed_changing) {
 407                 reg = __raw_readl(S5P_CLK_DIV6);
 408                 reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
 409                 reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
 410                 __raw_writel(reg, S5P_CLK_DIV6);
 411
 412                 do {
 413                         reg = __raw_readl(S5P_CLKDIV_STAT1);
 414                 } while (reg & (1 << 15));
 415
 416                 /* Reconfigure DRAM refresh counter value */
 417                 if (index != L4) {
 418                         /*
 419                          * DMC0 : 166Mhz
 420                          * DMC1 : 200Mhz
 421                          */
 422                         s5pv210_set_refresh(DMC0, 166000);
 423                         s5pv210_set_refresh(DMC1, 200000);
 424                 } else {
 425                         /*
 426                          * DMC0 : 83Mhz
 427                          * DMC1 : 100Mhz
 428                          */
 429                         s5pv210_set_refresh(DMC0, 83000);
 430                         s5pv210_set_refresh(DMC1, 100000);
 431                 }
 432         }
 433
 434         cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 435
 436         if (freqs.new < freqs.old) {
 437                 regulator_set_voltage(int_regulator,
 438                                 int_volt, int_volt_max);
 439
 440                 regulator_set_voltage(arm_regulator,
 441                                 arm_volt, arm_volt_max);
 442         }
 443
 444         printk(KERN_DEBUG "Perf changed[L%d]\n", index);
 445
 446 exit:
 447         mutex_unlock(&set_freq_lock);
 448         return ret;
 449 }
 450
 451 #ifdef CONFIG_PM
 452 static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
 453 {
 454         return 0;
 455 }
 456
 457 static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
 458 {
 459         return 0;
 460 }
 461 #endif
 462
 463 static int check_mem_type(void __iomem *dmc_reg)
 464 {
 465         unsigned long val;
 466
 467         val = __raw_readl(dmc_reg + 0x4);
 468         val = (val & (0xf << 8));
 469
 470         return val >> 8;
 471 }
 472
 473 static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
 474 {
 475         unsigned long mem_type;
 476         int ret;
 477
 478         cpu_clk = clk_get(NULL, "armclk");
 479         if (IS_ERR(cpu_clk))
 480                 return PTR_ERR(cpu_clk);
 481
 482         dmc0_clk = clk_get(NULL, "sclk_dmc0");
 483         if (IS_ERR(dmc0_clk)) {
 484                 ret = PTR_ERR(dmc0_clk);
 485                 goto out_dmc0;
 486         }
 487
 488         dmc1_clk = clk_get(NULL, "hclk_msys");
 489         if (IS_ERR(dmc1_clk)) {
 490                 ret = PTR_ERR(dmc1_clk);
 491                 goto out_dmc1;
 492         }
 493
 494         if (policy->cpu != 0) {
 495                 ret = -EINVAL;
 496                 goto out_dmc1;
 497         }
 498
 499         /*
 500          * check_mem_type : This driver only support LPDDR & LPDDR2.
 501          * other memory type is not supported.
 502          */
 503         mem_type = check_mem_type(S5P_VA_DMC0);
 504
 505         if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
 506                 printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
 507                 ret = -EINVAL;
 508                 goto out_dmc1;
 509         }
 510
 511         /* Find current refresh counter and frequency each DMC */
 512         s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
 513         s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
 514
 515         s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
 516         s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
 517
 518         return cpufreq_generic_init(policy, s5pv210_freq_table, 40000);
 519
 520 out_dmc1:
 521         clk_put(dmc0_clk);
 522 out_dmc0:
 523         clk_put(cpu_clk);
 524         return ret;
 525 }
 526
 527 static int s5pv210_cpufreq_notifier_event(struct notifier_block *this,
 528                                           unsigned long event, void *ptr)
 529 {
 530         int ret;
 531
 532         switch (event) {
 533         case PM_SUSPEND_PREPARE:
 534                 ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, 0);
 535                 if (ret < 0)
 536                         return NOTIFY_BAD;
 537
 538                 /* Disable updation of cpu frequency */
 539                 no_cpufreq_access = true;
 540                 return NOTIFY_OK;
 541         case PM_POST_RESTORE:
 542         case PM_POST_SUSPEND:
 543                 /* Enable updation of cpu frequency */
 544                 no_cpufreq_access = false;
 545                 cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, 0);
 546
 547                 return NOTIFY_OK;
 548         }
 549
 550         return NOTIFY_DONE;
 551 }
 552
 553 static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this,
 554                                                  unsigned long event, void *ptr)
 555 {
 556         int ret;
 557
 558         ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, 0);
 559         if (ret < 0)
 560                 return NOTIFY_BAD;
 561
 562         no_cpufreq_access = true;
 563         return NOTIFY_DONE;
 564 }
 565
 566 static struct cpufreq_driver s5pv210_driver = {
 567         .flags          = CPUFREQ_STICKY,
 568         .verify         = cpufreq_generic_frequency_table_verify,
 569         .target_index   = s5pv210_target,
 570         .get            = s5pv210_getspeed,
 571         .init           = s5pv210_cpu_init,
 572         .name           = "s5pv210",
 573 #ifdef CONFIG_PM
 574         .suspend        = s5pv210_cpufreq_suspend,
 575         .resume         = s5pv210_cpufreq_resume,
 576 #endif
 577 };
 578
 579 static struct notifier_block s5pv210_cpufreq_notifier = {
 580         .notifier_call = s5pv210_cpufreq_notifier_event,
 581 };
 582
 583 static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
 584         .notifier_call = s5pv210_cpufreq_reboot_notifier_event,
 585 };
 586
 587 static int __init s5pv210_cpufreq_init(void)
 588 {
 589         arm_regulator = regulator_get(NULL, "vddarm");
 590         if (IS_ERR(arm_regulator)) {
 591                 pr_err("failed to get regulator vddarm");
 592                 return PTR_ERR(arm_regulator);
 593         }
 594
 595         int_regulator = regulator_get(NULL, "vddint");
 596         if (IS_ERR(int_regulator)) {
 597                 pr_err("failed to get regulator vddint");
 598                 regulator_put(arm_regulator);
 599                 return PTR_ERR(int_regulator);
 600         }
 601
 602         register_pm_notifier(&s5pv210_cpufreq_notifier);
 603         register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier);
 604
 605         return cpufreq_register_driver(&s5pv210_driver);
 606 }
 607
 608 late_initcall(s5pv210_cpufreq_init);