2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * CPU frequency scaling for S5PC110/S5PV210
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/cpufreq.h>
19 #include <linux/reboot.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/suspend.h>
24 #include <mach/regs-clock.h>
26 static struct clk
*cpu_clk
;
27 static struct clk
*dmc0_clk
;
28 static struct clk
*dmc1_clk
;
29 static DEFINE_MUTEX(set_freq_lock
);
31 /* APLL M,P,S values for 1G/800Mhz */
32 #define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
33 #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
35 /* Use 800MHz when entering sleep mode */
36 #define SLEEP_FREQ (800 * 1000)
38 /* Tracks if cpu freqency can be updated anymore */
39 static bool no_cpufreq_access
;
42 * DRAM configurations to calculate refresh counter for changing
43 * frequency of memory.
46 unsigned long freq
; /* HZ */
47 unsigned long refresh
; /* DRAM refresh counter * 1000 */
50 /* DRAM configuration (DMC0 and DMC1) */
51 static struct dram_conf s5pv210_dram_conf
[2];
57 enum s5pv210_mem_type
{
63 enum s5pv210_dmc_port
{
68 static struct cpufreq_frequency_table s5pv210_freq_table
[] = {
74 {0, CPUFREQ_TABLE_END
},
77 static struct regulator
*arm_regulator
;
78 static struct regulator
*int_regulator
;
80 struct s5pv210_dvs_conf
{
81 int arm_volt
; /* uV */
82 int int_volt
; /* uV */
85 static const int arm_volt_max
= 1350000;
86 static const int int_volt_max
= 1250000;
88 static struct s5pv210_dvs_conf dvs_conf
[] = {
111 static u32 clkdiv_val
[5][11] = {
113 * Clock divider value for following
114 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
115 * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
116 * ONEDRAM, MFC, G3D }
119 /* L0 : [1000/200/100][166/83][133/66][200/200] */
120 {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
122 /* L1 : [800/200/100][166/83][133/66][200/200] */
123 {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
125 /* L2 : [400/200/100][166/83][133/66][200/200] */
126 {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
128 /* L3 : [200/200/100][166/83][133/66][200/200] */
129 {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
131 /* L4 : [100/100/100][83/83][66/66][100/100] */
132 {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
136 * This function set DRAM refresh counter
137 * accoriding to operating frequency of DRAM
138 * ch: DMC port number 0 or 1
139 * freq: Operating frequency of DRAM(KHz)
141 static void s5pv210_set_refresh(enum s5pv210_dmc_port ch
, unsigned long freq
)
143 unsigned long tmp
, tmp1
;
144 void __iomem
*reg
= NULL
;
147 reg
= (S5P_VA_DMC0
+ 0x30);
148 } else if (ch
== DMC1
) {
149 reg
= (S5P_VA_DMC1
+ 0x30);
151 printk(KERN_ERR
"Cannot find DMC port\n");
155 /* Find current DRAM frequency */
156 tmp
= s5pv210_dram_conf
[ch
].freq
;
160 tmp1
= s5pv210_dram_conf
[ch
].refresh
;
164 __raw_writel(tmp1
, reg
);
167 static unsigned int s5pv210_getspeed(unsigned int cpu
)
172 return clk_get_rate(cpu_clk
) / 1000;
175 static int s5pv210_target(struct cpufreq_policy
*policy
, unsigned int index
)
178 unsigned int priv_index
;
179 unsigned int pll_changing
= 0;
180 unsigned int bus_speed_changing
= 0;
181 unsigned int old_freq
, new_freq
;
182 int arm_volt
, int_volt
;
185 mutex_lock(&set_freq_lock
);
187 if (no_cpufreq_access
) {
188 #ifdef CONFIG_PM_VERBOSE
189 pr_err("%s:%d denied access to %s as it is disabled"
190 "temporarily\n", __FILE__
, __LINE__
, __func__
);
196 old_freq
= s5pv210_getspeed(0);
197 new_freq
= s5pv210_freq_table
[index
].frequency
;
199 /* Finding current running level index */
200 if (cpufreq_frequency_table_target(policy
, s5pv210_freq_table
,
201 old_freq
, CPUFREQ_RELATION_H
,
207 arm_volt
= dvs_conf
[index
].arm_volt
;
208 int_volt
= dvs_conf
[index
].int_volt
;
210 if (new_freq
> old_freq
) {
211 ret
= regulator_set_voltage(arm_regulator
,
212 arm_volt
, arm_volt_max
);
216 ret
= regulator_set_voltage(int_regulator
,
217 int_volt
, int_volt_max
);
222 /* Check if there need to change PLL */
223 if ((index
== L0
) || (priv_index
== L0
))
226 /* Check if there need to change System bus clock */
227 if ((index
== L4
) || (priv_index
== L4
))
228 bus_speed_changing
= 1;
230 if (bus_speed_changing
) {
232 * Reconfigure DRAM refresh counter value for minimum
233 * temporary clock while changing divider.
234 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
237 s5pv210_set_refresh(DMC1
, 83000);
239 s5pv210_set_refresh(DMC1
, 100000);
241 s5pv210_set_refresh(DMC0
, 83000);
245 * APLL should be changed in this level
246 * APLL -> MPLL(for stable transition) -> APLL
247 * Some clock source's clock API are not prepared.
248 * Do not use clock API in below code.
252 * 1. Temporary Change divider for MFC and G3D
253 * SCLKA2M(200/1=200)->(200/4=50)Mhz
255 reg
= __raw_readl(S5P_CLK_DIV2
);
256 reg
&= ~(S5P_CLKDIV2_G3D_MASK
| S5P_CLKDIV2_MFC_MASK
);
257 reg
|= (3 << S5P_CLKDIV2_G3D_SHIFT
) |
258 (3 << S5P_CLKDIV2_MFC_SHIFT
);
259 __raw_writel(reg
, S5P_CLK_DIV2
);
261 /* For MFC, G3D dividing */
263 reg
= __raw_readl(S5P_CLKDIV_STAT0
);
264 } while (reg
& ((1 << 16) | (1 << 17)));
267 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
268 * (200/4=50)->(667/4=166)Mhz
270 reg
= __raw_readl(S5P_CLK_SRC2
);
271 reg
&= ~(S5P_CLKSRC2_G3D_MASK
| S5P_CLKSRC2_MFC_MASK
);
272 reg
|= (1 << S5P_CLKSRC2_G3D_SHIFT
) |
273 (1 << S5P_CLKSRC2_MFC_SHIFT
);
274 __raw_writel(reg
, S5P_CLK_SRC2
);
277 reg
= __raw_readl(S5P_CLKMUX_STAT1
);
278 } while (reg
& ((1 << 7) | (1 << 3)));
281 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
282 * true refresh counter is already programed in upper
285 if (!bus_speed_changing
)
286 s5pv210_set_refresh(DMC1
, 133000);
288 /* 4. SCLKAPLL -> SCLKMPLL */
289 reg
= __raw_readl(S5P_CLK_SRC0
);
290 reg
&= ~(S5P_CLKSRC0_MUX200_MASK
);
291 reg
|= (0x1 << S5P_CLKSRC0_MUX200_SHIFT
);
292 __raw_writel(reg
, S5P_CLK_SRC0
);
295 reg
= __raw_readl(S5P_CLKMUX_STAT0
);
296 } while (reg
& (0x1 << 18));
301 reg
= __raw_readl(S5P_CLK_DIV0
);
303 reg
&= ~(S5P_CLKDIV0_APLL_MASK
| S5P_CLKDIV0_A2M_MASK
|
304 S5P_CLKDIV0_HCLK200_MASK
| S5P_CLKDIV0_PCLK100_MASK
|
305 S5P_CLKDIV0_HCLK166_MASK
| S5P_CLKDIV0_PCLK83_MASK
|
306 S5P_CLKDIV0_HCLK133_MASK
| S5P_CLKDIV0_PCLK66_MASK
);
308 reg
|= ((clkdiv_val
[index
][0] << S5P_CLKDIV0_APLL_SHIFT
) |
309 (clkdiv_val
[index
][1] << S5P_CLKDIV0_A2M_SHIFT
) |
310 (clkdiv_val
[index
][2] << S5P_CLKDIV0_HCLK200_SHIFT
) |
311 (clkdiv_val
[index
][3] << S5P_CLKDIV0_PCLK100_SHIFT
) |
312 (clkdiv_val
[index
][4] << S5P_CLKDIV0_HCLK166_SHIFT
) |
313 (clkdiv_val
[index
][5] << S5P_CLKDIV0_PCLK83_SHIFT
) |
314 (clkdiv_val
[index
][6] << S5P_CLKDIV0_HCLK133_SHIFT
) |
315 (clkdiv_val
[index
][7] << S5P_CLKDIV0_PCLK66_SHIFT
));
317 __raw_writel(reg
, S5P_CLK_DIV0
);
320 reg
= __raw_readl(S5P_CLKDIV_STAT0
);
321 } while (reg
& 0xff);
323 /* ARM MCS value changed */
324 reg
= __raw_readl(S5P_ARM_MCS_CON
);
331 __raw_writel(reg
, S5P_ARM_MCS_CON
);
334 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
335 __raw_writel(0x2cf, S5P_APLL_LOCK
);
339 * 6-1. Set PMS values
340 * 6-2. Wait untile the PLL is locked
343 __raw_writel(APLL_VAL_1000
, S5P_APLL_CON
);
345 __raw_writel(APLL_VAL_800
, S5P_APLL_CON
);
348 reg
= __raw_readl(S5P_APLL_CON
);
349 } while (!(reg
& (0x1 << 29)));
352 * 7. Change souce clock from SCLKMPLL(667Mhz)
353 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
354 * (667/4=166)->(200/4=50)Mhz
356 reg
= __raw_readl(S5P_CLK_SRC2
);
357 reg
&= ~(S5P_CLKSRC2_G3D_MASK
| S5P_CLKSRC2_MFC_MASK
);
358 reg
|= (0 << S5P_CLKSRC2_G3D_SHIFT
) |
359 (0 << S5P_CLKSRC2_MFC_SHIFT
);
360 __raw_writel(reg
, S5P_CLK_SRC2
);
363 reg
= __raw_readl(S5P_CLKMUX_STAT1
);
364 } while (reg
& ((1 << 7) | (1 << 3)));
367 * 8. Change divider for MFC and G3D
368 * (200/4=50)->(200/1=200)Mhz
370 reg
= __raw_readl(S5P_CLK_DIV2
);
371 reg
&= ~(S5P_CLKDIV2_G3D_MASK
| S5P_CLKDIV2_MFC_MASK
);
372 reg
|= (clkdiv_val
[index
][10] << S5P_CLKDIV2_G3D_SHIFT
) |
373 (clkdiv_val
[index
][9] << S5P_CLKDIV2_MFC_SHIFT
);
374 __raw_writel(reg
, S5P_CLK_DIV2
);
376 /* For MFC, G3D dividing */
378 reg
= __raw_readl(S5P_CLKDIV_STAT0
);
379 } while (reg
& ((1 << 16) | (1 << 17)));
381 /* 9. Change MPLL to APLL in MSYS_MUX */
382 reg
= __raw_readl(S5P_CLK_SRC0
);
383 reg
&= ~(S5P_CLKSRC0_MUX200_MASK
);
384 reg
|= (0x0 << S5P_CLKSRC0_MUX200_SHIFT
);
385 __raw_writel(reg
, S5P_CLK_SRC0
);
388 reg
= __raw_readl(S5P_CLKMUX_STAT0
);
389 } while (reg
& (0x1 << 18));
392 * 10. DMC1 refresh counter
393 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
394 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
396 if (!bus_speed_changing
)
397 s5pv210_set_refresh(DMC1
, 200000);
401 * L4 level need to change memory bus speed, hence onedram clock divier
402 * and memory refresh parameter should be changed
404 if (bus_speed_changing
) {
405 reg
= __raw_readl(S5P_CLK_DIV6
);
406 reg
&= ~S5P_CLKDIV6_ONEDRAM_MASK
;
407 reg
|= (clkdiv_val
[index
][8] << S5P_CLKDIV6_ONEDRAM_SHIFT
);
408 __raw_writel(reg
, S5P_CLK_DIV6
);
411 reg
= __raw_readl(S5P_CLKDIV_STAT1
);
412 } while (reg
& (1 << 15));
414 /* Reconfigure DRAM refresh counter value */
420 s5pv210_set_refresh(DMC0
, 166000);
421 s5pv210_set_refresh(DMC1
, 200000);
427 s5pv210_set_refresh(DMC0
, 83000);
428 s5pv210_set_refresh(DMC1
, 100000);
432 if (new_freq
< old_freq
) {
433 regulator_set_voltage(int_regulator
,
434 int_volt
, int_volt_max
);
436 regulator_set_voltage(arm_regulator
,
437 arm_volt
, arm_volt_max
);
440 printk(KERN_DEBUG
"Perf changed[L%d]\n", index
);
443 mutex_unlock(&set_freq_lock
);
448 static int s5pv210_cpufreq_suspend(struct cpufreq_policy
*policy
)
453 static int s5pv210_cpufreq_resume(struct cpufreq_policy
*policy
)
459 static int check_mem_type(void __iomem
*dmc_reg
)
463 val
= __raw_readl(dmc_reg
+ 0x4);
464 val
= (val
& (0xf << 8));
469 static int __init
s5pv210_cpu_init(struct cpufreq_policy
*policy
)
471 unsigned long mem_type
;
474 cpu_clk
= clk_get(NULL
, "armclk");
476 return PTR_ERR(cpu_clk
);
478 dmc0_clk
= clk_get(NULL
, "sclk_dmc0");
479 if (IS_ERR(dmc0_clk
)) {
480 ret
= PTR_ERR(dmc0_clk
);
484 dmc1_clk
= clk_get(NULL
, "hclk_msys");
485 if (IS_ERR(dmc1_clk
)) {
486 ret
= PTR_ERR(dmc1_clk
);
490 if (policy
->cpu
!= 0) {
496 * check_mem_type : This driver only support LPDDR & LPDDR2.
497 * other memory type is not supported.
499 mem_type
= check_mem_type(S5P_VA_DMC0
);
501 if ((mem_type
!= LPDDR
) && (mem_type
!= LPDDR2
)) {
502 printk(KERN_ERR
"CPUFreq doesn't support this memory type\n");
507 /* Find current refresh counter and frequency each DMC */
508 s5pv210_dram_conf
[0].refresh
= (__raw_readl(S5P_VA_DMC0
+ 0x30) * 1000);
509 s5pv210_dram_conf
[0].freq
= clk_get_rate(dmc0_clk
);
511 s5pv210_dram_conf
[1].refresh
= (__raw_readl(S5P_VA_DMC1
+ 0x30) * 1000);
512 s5pv210_dram_conf
[1].freq
= clk_get_rate(dmc1_clk
);
514 return cpufreq_generic_init(policy
, s5pv210_freq_table
, 40000);
523 static int s5pv210_cpufreq_notifier_event(struct notifier_block
*this,
524 unsigned long event
, void *ptr
)
529 case PM_SUSPEND_PREPARE
:
530 ret
= cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ
, 0);
534 /* Disable updation of cpu frequency */
535 no_cpufreq_access
= true;
537 case PM_POST_RESTORE
:
538 case PM_POST_SUSPEND
:
539 /* Enable updation of cpu frequency */
540 no_cpufreq_access
= false;
541 cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ
, 0);
549 static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block
*this,
550 unsigned long event
, void *ptr
)
554 ret
= cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ
, 0);
558 no_cpufreq_access
= true;
562 static struct cpufreq_driver s5pv210_driver
= {
563 .flags
= CPUFREQ_STICKY
,
564 .verify
= cpufreq_generic_frequency_table_verify
,
565 .target_index
= s5pv210_target
,
566 .get
= s5pv210_getspeed
,
567 .init
= s5pv210_cpu_init
,
570 .suspend
= s5pv210_cpufreq_suspend
,
571 .resume
= s5pv210_cpufreq_resume
,
575 static struct notifier_block s5pv210_cpufreq_notifier
= {
576 .notifier_call
= s5pv210_cpufreq_notifier_event
,
579 static struct notifier_block s5pv210_cpufreq_reboot_notifier
= {
580 .notifier_call
= s5pv210_cpufreq_reboot_notifier_event
,
583 static int __init
s5pv210_cpufreq_init(void)
585 arm_regulator
= regulator_get(NULL
, "vddarm");
586 if (IS_ERR(arm_regulator
)) {
587 pr_err("failed to get regulator vddarm");
588 return PTR_ERR(arm_regulator
);
591 int_regulator
= regulator_get(NULL
, "vddint");
592 if (IS_ERR(int_regulator
)) {
593 pr_err("failed to get regulator vddint");
594 regulator_put(arm_regulator
);
595 return PTR_ERR(int_regulator
);
598 register_pm_notifier(&s5pv210_cpufreq_notifier
);
599 register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier
);
601 return cpufreq_register_driver(&s5pv210_driver
);
604 late_initcall(s5pv210_cpufreq_init
);