2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * CPU frequency scaling for S5PC110/S5PV210
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/cpufreq.h>
19 #include <linux/reboot.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/suspend.h>
24 #include <mach/regs-clock.h>
26 static struct clk
*cpu_clk
;
27 static struct clk
*dmc0_clk
;
28 static struct clk
*dmc1_clk
;
29 static struct cpufreq_freqs freqs
;
30 static DEFINE_MUTEX(set_freq_lock
);
32 /* APLL M,P,S values for 1G/800Mhz */
33 #define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
34 #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
36 /* Use 800MHz when entering sleep mode */
37 #define SLEEP_FREQ (800 * 1000)
39 /* Tracks if cpu freqency can be updated anymore */
40 static bool no_cpufreq_access
;
43 * DRAM configurations to calculate refresh counter for changing
44 * frequency of memory.
47 unsigned long freq
; /* HZ */
48 unsigned long refresh
; /* DRAM refresh counter * 1000 */
51 /* DRAM configuration (DMC0 and DMC1) */
52 static struct dram_conf s5pv210_dram_conf
[2];
58 enum s5pv210_mem_type
{
64 enum s5pv210_dmc_port
{
69 static struct cpufreq_frequency_table s5pv210_freq_table
[] = {
75 {0, CPUFREQ_TABLE_END
},
78 static struct regulator
*arm_regulator
;
79 static struct regulator
*int_regulator
;
81 struct s5pv210_dvs_conf
{
82 int arm_volt
; /* uV */
83 int int_volt
; /* uV */
86 static const int arm_volt_max
= 1350000;
87 static const int int_volt_max
= 1250000;
89 static struct s5pv210_dvs_conf dvs_conf
[] = {
112 static u32 clkdiv_val
[5][11] = {
114 * Clock divider value for following
115 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
116 * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
117 * ONEDRAM, MFC, G3D }
120 /* L0 : [1000/200/100][166/83][133/66][200/200] */
121 {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
123 /* L1 : [800/200/100][166/83][133/66][200/200] */
124 {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
126 /* L2 : [400/200/100][166/83][133/66][200/200] */
127 {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
129 /* L3 : [200/200/100][166/83][133/66][200/200] */
130 {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
132 /* L4 : [100/100/100][83/83][66/66][100/100] */
133 {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
137 * This function set DRAM refresh counter
138 * accoriding to operating frequency of DRAM
139 * ch: DMC port number 0 or 1
140 * freq: Operating frequency of DRAM(KHz)
142 static void s5pv210_set_refresh(enum s5pv210_dmc_port ch
, unsigned long freq
)
144 unsigned long tmp
, tmp1
;
145 void __iomem
*reg
= NULL
;
148 reg
= (S5P_VA_DMC0
+ 0x30);
149 } else if (ch
== DMC1
) {
150 reg
= (S5P_VA_DMC1
+ 0x30);
152 printk(KERN_ERR
"Cannot find DMC port\n");
156 /* Find current DRAM frequency */
157 tmp
= s5pv210_dram_conf
[ch
].freq
;
161 tmp1
= s5pv210_dram_conf
[ch
].refresh
;
165 __raw_writel(tmp1
, reg
);
168 static unsigned int s5pv210_getspeed(unsigned int cpu
)
173 return clk_get_rate(cpu_clk
) / 1000;
176 static int s5pv210_target(struct cpufreq_policy
*policy
, unsigned int index
)
179 unsigned int priv_index
;
180 unsigned int pll_changing
= 0;
181 unsigned int bus_speed_changing
= 0;
182 int arm_volt
, int_volt
;
185 mutex_lock(&set_freq_lock
);
187 if (no_cpufreq_access
) {
188 #ifdef CONFIG_PM_VERBOSE
189 pr_err("%s:%d denied access to %s as it is disabled"
190 "temporarily\n", __FILE__
, __LINE__
, __func__
);
196 freqs
.old
= s5pv210_getspeed(0);
197 freqs
.new = s5pv210_freq_table
[index
].frequency
;
199 /* Finding current running level index */
200 if (cpufreq_frequency_table_target(policy
, s5pv210_freq_table
,
201 freqs
.old
, CPUFREQ_RELATION_H
,
207 arm_volt
= dvs_conf
[index
].arm_volt
;
208 int_volt
= dvs_conf
[index
].int_volt
;
210 if (freqs
.new > freqs
.old
) {
211 ret
= regulator_set_voltage(arm_regulator
,
212 arm_volt
, arm_volt_max
);
216 ret
= regulator_set_voltage(int_regulator
,
217 int_volt
, int_volt_max
);
222 cpufreq_notify_transition(policy
, &freqs
, CPUFREQ_PRECHANGE
);
224 /* Check if there need to change PLL */
225 if ((index
== L0
) || (priv_index
== L0
))
228 /* Check if there need to change System bus clock */
229 if ((index
== L4
) || (priv_index
== L4
))
230 bus_speed_changing
= 1;
232 if (bus_speed_changing
) {
234 * Reconfigure DRAM refresh counter value for minimum
235 * temporary clock while changing divider.
236 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
239 s5pv210_set_refresh(DMC1
, 83000);
241 s5pv210_set_refresh(DMC1
, 100000);
243 s5pv210_set_refresh(DMC0
, 83000);
247 * APLL should be changed in this level
248 * APLL -> MPLL(for stable transition) -> APLL
249 * Some clock source's clock API are not prepared.
250 * Do not use clock API in below code.
254 * 1. Temporary Change divider for MFC and G3D
255 * SCLKA2M(200/1=200)->(200/4=50)Mhz
257 reg
= __raw_readl(S5P_CLK_DIV2
);
258 reg
&= ~(S5P_CLKDIV2_G3D_MASK
| S5P_CLKDIV2_MFC_MASK
);
259 reg
|= (3 << S5P_CLKDIV2_G3D_SHIFT
) |
260 (3 << S5P_CLKDIV2_MFC_SHIFT
);
261 __raw_writel(reg
, S5P_CLK_DIV2
);
263 /* For MFC, G3D dividing */
265 reg
= __raw_readl(S5P_CLKDIV_STAT0
);
266 } while (reg
& ((1 << 16) | (1 << 17)));
269 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
270 * (200/4=50)->(667/4=166)Mhz
272 reg
= __raw_readl(S5P_CLK_SRC2
);
273 reg
&= ~(S5P_CLKSRC2_G3D_MASK
| S5P_CLKSRC2_MFC_MASK
);
274 reg
|= (1 << S5P_CLKSRC2_G3D_SHIFT
) |
275 (1 << S5P_CLKSRC2_MFC_SHIFT
);
276 __raw_writel(reg
, S5P_CLK_SRC2
);
279 reg
= __raw_readl(S5P_CLKMUX_STAT1
);
280 } while (reg
& ((1 << 7) | (1 << 3)));
283 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
284 * true refresh counter is already programed in upper
287 if (!bus_speed_changing
)
288 s5pv210_set_refresh(DMC1
, 133000);
290 /* 4. SCLKAPLL -> SCLKMPLL */
291 reg
= __raw_readl(S5P_CLK_SRC0
);
292 reg
&= ~(S5P_CLKSRC0_MUX200_MASK
);
293 reg
|= (0x1 << S5P_CLKSRC0_MUX200_SHIFT
);
294 __raw_writel(reg
, S5P_CLK_SRC0
);
297 reg
= __raw_readl(S5P_CLKMUX_STAT0
);
298 } while (reg
& (0x1 << 18));
303 reg
= __raw_readl(S5P_CLK_DIV0
);
305 reg
&= ~(S5P_CLKDIV0_APLL_MASK
| S5P_CLKDIV0_A2M_MASK
|
306 S5P_CLKDIV0_HCLK200_MASK
| S5P_CLKDIV0_PCLK100_MASK
|
307 S5P_CLKDIV0_HCLK166_MASK
| S5P_CLKDIV0_PCLK83_MASK
|
308 S5P_CLKDIV0_HCLK133_MASK
| S5P_CLKDIV0_PCLK66_MASK
);
310 reg
|= ((clkdiv_val
[index
][0] << S5P_CLKDIV0_APLL_SHIFT
) |
311 (clkdiv_val
[index
][1] << S5P_CLKDIV0_A2M_SHIFT
) |
312 (clkdiv_val
[index
][2] << S5P_CLKDIV0_HCLK200_SHIFT
) |
313 (clkdiv_val
[index
][3] << S5P_CLKDIV0_PCLK100_SHIFT
) |
314 (clkdiv_val
[index
][4] << S5P_CLKDIV0_HCLK166_SHIFT
) |
315 (clkdiv_val
[index
][5] << S5P_CLKDIV0_PCLK83_SHIFT
) |
316 (clkdiv_val
[index
][6] << S5P_CLKDIV0_HCLK133_SHIFT
) |
317 (clkdiv_val
[index
][7] << S5P_CLKDIV0_PCLK66_SHIFT
));
319 __raw_writel(reg
, S5P_CLK_DIV0
);
322 reg
= __raw_readl(S5P_CLKDIV_STAT0
);
323 } while (reg
& 0xff);
325 /* ARM MCS value changed */
326 reg
= __raw_readl(S5P_ARM_MCS_CON
);
333 __raw_writel(reg
, S5P_ARM_MCS_CON
);
336 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
337 __raw_writel(0x2cf, S5P_APLL_LOCK
);
341 * 6-1. Set PMS values
342 * 6-2. Wait untile the PLL is locked
345 __raw_writel(APLL_VAL_1000
, S5P_APLL_CON
);
347 __raw_writel(APLL_VAL_800
, S5P_APLL_CON
);
350 reg
= __raw_readl(S5P_APLL_CON
);
351 } while (!(reg
& (0x1 << 29)));
354 * 7. Change souce clock from SCLKMPLL(667Mhz)
355 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
356 * (667/4=166)->(200/4=50)Mhz
358 reg
= __raw_readl(S5P_CLK_SRC2
);
359 reg
&= ~(S5P_CLKSRC2_G3D_MASK
| S5P_CLKSRC2_MFC_MASK
);
360 reg
|= (0 << S5P_CLKSRC2_G3D_SHIFT
) |
361 (0 << S5P_CLKSRC2_MFC_SHIFT
);
362 __raw_writel(reg
, S5P_CLK_SRC2
);
365 reg
= __raw_readl(S5P_CLKMUX_STAT1
);
366 } while (reg
& ((1 << 7) | (1 << 3)));
369 * 8. Change divider for MFC and G3D
370 * (200/4=50)->(200/1=200)Mhz
372 reg
= __raw_readl(S5P_CLK_DIV2
);
373 reg
&= ~(S5P_CLKDIV2_G3D_MASK
| S5P_CLKDIV2_MFC_MASK
);
374 reg
|= (clkdiv_val
[index
][10] << S5P_CLKDIV2_G3D_SHIFT
) |
375 (clkdiv_val
[index
][9] << S5P_CLKDIV2_MFC_SHIFT
);
376 __raw_writel(reg
, S5P_CLK_DIV2
);
378 /* For MFC, G3D dividing */
380 reg
= __raw_readl(S5P_CLKDIV_STAT0
);
381 } while (reg
& ((1 << 16) | (1 << 17)));
383 /* 9. Change MPLL to APLL in MSYS_MUX */
384 reg
= __raw_readl(S5P_CLK_SRC0
);
385 reg
&= ~(S5P_CLKSRC0_MUX200_MASK
);
386 reg
|= (0x0 << S5P_CLKSRC0_MUX200_SHIFT
);
387 __raw_writel(reg
, S5P_CLK_SRC0
);
390 reg
= __raw_readl(S5P_CLKMUX_STAT0
);
391 } while (reg
& (0x1 << 18));
394 * 10. DMC1 refresh counter
395 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
396 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
398 if (!bus_speed_changing
)
399 s5pv210_set_refresh(DMC1
, 200000);
403 * L4 level need to change memory bus speed, hence onedram clock divier
404 * and memory refresh parameter should be changed
406 if (bus_speed_changing
) {
407 reg
= __raw_readl(S5P_CLK_DIV6
);
408 reg
&= ~S5P_CLKDIV6_ONEDRAM_MASK
;
409 reg
|= (clkdiv_val
[index
][8] << S5P_CLKDIV6_ONEDRAM_SHIFT
);
410 __raw_writel(reg
, S5P_CLK_DIV6
);
413 reg
= __raw_readl(S5P_CLKDIV_STAT1
);
414 } while (reg
& (1 << 15));
416 /* Reconfigure DRAM refresh counter value */
422 s5pv210_set_refresh(DMC0
, 166000);
423 s5pv210_set_refresh(DMC1
, 200000);
429 s5pv210_set_refresh(DMC0
, 83000);
430 s5pv210_set_refresh(DMC1
, 100000);
434 cpufreq_notify_transition(policy
, &freqs
, CPUFREQ_POSTCHANGE
);
436 if (freqs
.new < freqs
.old
) {
437 regulator_set_voltage(int_regulator
,
438 int_volt
, int_volt_max
);
440 regulator_set_voltage(arm_regulator
,
441 arm_volt
, arm_volt_max
);
444 printk(KERN_DEBUG
"Perf changed[L%d]\n", index
);
447 mutex_unlock(&set_freq_lock
);
452 static int s5pv210_cpufreq_suspend(struct cpufreq_policy
*policy
)
457 static int s5pv210_cpufreq_resume(struct cpufreq_policy
*policy
)
463 static int check_mem_type(void __iomem
*dmc_reg
)
467 val
= __raw_readl(dmc_reg
+ 0x4);
468 val
= (val
& (0xf << 8));
473 static int __init
s5pv210_cpu_init(struct cpufreq_policy
*policy
)
475 unsigned long mem_type
;
478 cpu_clk
= clk_get(NULL
, "armclk");
480 return PTR_ERR(cpu_clk
);
482 dmc0_clk
= clk_get(NULL
, "sclk_dmc0");
483 if (IS_ERR(dmc0_clk
)) {
484 ret
= PTR_ERR(dmc0_clk
);
488 dmc1_clk
= clk_get(NULL
, "hclk_msys");
489 if (IS_ERR(dmc1_clk
)) {
490 ret
= PTR_ERR(dmc1_clk
);
494 if (policy
->cpu
!= 0) {
500 * check_mem_type : This driver only support LPDDR & LPDDR2.
501 * other memory type is not supported.
503 mem_type
= check_mem_type(S5P_VA_DMC0
);
505 if ((mem_type
!= LPDDR
) && (mem_type
!= LPDDR2
)) {
506 printk(KERN_ERR
"CPUFreq doesn't support this memory type\n");
511 /* Find current refresh counter and frequency each DMC */
512 s5pv210_dram_conf
[0].refresh
= (__raw_readl(S5P_VA_DMC0
+ 0x30) * 1000);
513 s5pv210_dram_conf
[0].freq
= clk_get_rate(dmc0_clk
);
515 s5pv210_dram_conf
[1].refresh
= (__raw_readl(S5P_VA_DMC1
+ 0x30) * 1000);
516 s5pv210_dram_conf
[1].freq
= clk_get_rate(dmc1_clk
);
518 return cpufreq_generic_init(policy
, s5pv210_freq_table
, 40000);
527 static int s5pv210_cpufreq_notifier_event(struct notifier_block
*this,
528 unsigned long event
, void *ptr
)
533 case PM_SUSPEND_PREPARE
:
534 ret
= cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ
, 0);
538 /* Disable updation of cpu frequency */
539 no_cpufreq_access
= true;
541 case PM_POST_RESTORE
:
542 case PM_POST_SUSPEND
:
543 /* Enable updation of cpu frequency */
544 no_cpufreq_access
= false;
545 cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ
, 0);
553 static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block
*this,
554 unsigned long event
, void *ptr
)
558 ret
= cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ
, 0);
562 no_cpufreq_access
= true;
566 static struct cpufreq_driver s5pv210_driver
= {
567 .flags
= CPUFREQ_STICKY
,
568 .verify
= cpufreq_generic_frequency_table_verify
,
569 .target_index
= s5pv210_target
,
570 .get
= s5pv210_getspeed
,
571 .init
= s5pv210_cpu_init
,
574 .suspend
= s5pv210_cpufreq_suspend
,
575 .resume
= s5pv210_cpufreq_resume
,
579 static struct notifier_block s5pv210_cpufreq_notifier
= {
580 .notifier_call
= s5pv210_cpufreq_notifier_event
,
583 static struct notifier_block s5pv210_cpufreq_reboot_notifier
= {
584 .notifier_call
= s5pv210_cpufreq_reboot_notifier_event
,
587 static int __init
s5pv210_cpufreq_init(void)
589 arm_regulator
= regulator_get(NULL
, "vddarm");
590 if (IS_ERR(arm_regulator
)) {
591 pr_err("failed to get regulator vddarm");
592 return PTR_ERR(arm_regulator
);
595 int_regulator
= regulator_get(NULL
, "vddint");
596 if (IS_ERR(int_regulator
)) {
597 pr_err("failed to get regulator vddint");
598 regulator_put(arm_regulator
);
599 return PTR_ERR(int_regulator
);
602 register_pm_notifier(&s5pv210_cpufreq_notifier
);
603 register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier
);
605 return cpufreq_register_driver(&s5pv210_driver
);
608 late_initcall(s5pv210_cpufreq_init
);