4 * Support Blackfin CRC HW acceleration.
6 * Copyright 2012 Analog Devices Inc.
8 * Licensed under the GPL-2.
11 #include <linux/err.h>
12 #include <linux/device.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/platform_device.h>
21 #include <linux/scatterlist.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/delay.h>
24 #include <linux/unaligned/access_ok.h>
25 #include <linux/crypto.h>
26 #include <linux/cryptohash.h>
27 #include <crypto/scatterwalk.h>
28 #include <crypto/algapi.h>
29 #include <crypto/hash.h>
30 #include <crypto/internal/hash.h>
32 #include <asm/blackfin.h>
33 #include <asm/bfin_crc.h>
35 #include <asm/portmux.h>
37 #define CRC_CCRYPTO_QUEUE_LENGTH 5
39 #define DRIVER_NAME "bfin-hmac-crc"
40 #define CHKSUM_DIGEST_SIZE 4
41 #define CHKSUM_BLOCK_SIZE 1
43 #define CRC_MAX_DMA_DESC 100
45 #define CRC_CRYPTO_STATE_UPDATE 1
46 #define CRC_CRYPTO_STATE_FINALUPDATE 2
47 #define CRC_CRYPTO_STATE_FINISH 3
49 struct bfin_crypto_crc
{
50 struct list_head list
;
57 volatile struct crc_register
*regs
;
59 struct ahash_request
*req
; /* current request in operation */
60 struct dma_desc_array
*sg_cpu
; /* virt addr of sg dma descriptors */
61 dma_addr_t sg_dma
; /* phy addr of sg dma descriptors */
64 struct tasklet_struct done_task
;
65 struct crypto_queue queue
; /* waiting requests */
67 u8 busy
:1; /* crc device in operation flag */
70 static struct bfin_crypto_crc_list
{
71 struct list_head dev_list
;
75 struct bfin_crypto_crc_reqctx
{
76 struct bfin_crypto_crc
*crc
;
78 unsigned int total
; /* total request bytes */
79 size_t sg_buflen
; /* bytes for this update */
80 unsigned int sg_nents
;
81 struct scatterlist
*sg
; /* sg list head for this update*/
82 struct scatterlist bufsl
[2]; /* chained sg list */
86 u8 bufnext
[CHKSUM_DIGEST_SIZE
]; /* extra bytes for next udpate */
87 u8 buflast
[CHKSUM_DIGEST_SIZE
]; /* extra bytes from last udpate */
92 struct bfin_crypto_crc_ctx
{
93 struct bfin_crypto_crc
*crc
;
99 * derive number of elements in scatterlist
101 static int sg_count(struct scatterlist
*sg_list
)
103 struct scatterlist
*sg
= sg_list
;
109 while (!sg_is_last(sg
)) {
111 sg
= scatterwalk_sg_next(sg
);
118 * get element in scatter list by given index
120 static struct scatterlist
*sg_get(struct scatterlist
*sg_list
, unsigned int nents
,
123 struct scatterlist
*sg
= NULL
;
126 for_each_sg(sg_list
, sg
, nents
, i
)
133 static int bfin_crypto_crc_init_hw(struct bfin_crypto_crc
*crc
, u32 key
)
135 crc
->regs
->datacntrld
= 0;
136 crc
->regs
->control
= MODE_CALC_CRC
<< OPMODE_OFFSET
;
137 crc
->regs
->curresult
= key
;
139 /* setup CRC interrupts */
140 crc
->regs
->status
= CMPERRI
| DCNTEXPI
;
141 crc
->regs
->intrenset
= CMPERRI
| DCNTEXPI
;
146 static int bfin_crypto_crc_init(struct ahash_request
*req
)
148 struct crypto_ahash
*tfm
= crypto_ahash_reqtfm(req
);
149 struct bfin_crypto_crc_ctx
*crc_ctx
= crypto_ahash_ctx(tfm
);
150 struct bfin_crypto_crc_reqctx
*ctx
= ahash_request_ctx(req
);
151 struct bfin_crypto_crc
*crc
;
153 dev_dbg(ctx
->crc
->dev
, "crc_init\n");
154 spin_lock_bh(&crc_list
.lock
);
155 list_for_each_entry(crc
, &crc_list
.dev_list
, list
) {
159 spin_unlock_bh(&crc_list
.lock
);
161 if (sg_count(req
->src
) > CRC_MAX_DMA_DESC
) {
162 dev_dbg(ctx
->crc
->dev
, "init: requested sg list is too big > %d\n",
168 ctx
->bufnext_len
= 0;
169 ctx
->buflast_len
= 0;
174 /* init crc results */
175 put_unaligned_le32(crc_ctx
->key
, req
->result
);
177 dev_dbg(ctx
->crc
->dev
, "init: digest size: %d\n",
178 crypto_ahash_digestsize(tfm
));
180 return bfin_crypto_crc_init_hw(crc
, crc_ctx
->key
);
183 static void bfin_crypto_crc_config_dma(struct bfin_crypto_crc
*crc
)
185 struct scatterlist
*sg
;
186 struct bfin_crypto_crc_reqctx
*ctx
= ahash_request_ctx(crc
->req
);
188 unsigned long dma_config
;
189 unsigned int dma_count
;
190 unsigned int dma_addr
;
191 unsigned int mid_dma_count
= 0;
194 dma_map_sg(crc
->dev
, ctx
->sg
, ctx
->sg_nents
, DMA_TO_DEVICE
);
196 for_each_sg(ctx
->sg
, sg
, ctx
->sg_nents
, j
) {
197 dma_config
= DMAFLOW_ARRAY
| RESTART
| NDSIZE_3
| DMAEN
| PSIZE_32
;
198 dma_addr
= sg_dma_address(sg
);
199 /* deduce extra bytes in last sg */
201 dma_count
= sg_dma_len(sg
) - ctx
->bufnext_len
;
203 dma_count
= sg_dma_len(sg
);
206 /* Append last middle dma buffer to 4 bytes with first
207 bytes in current sg buffer. Move addr of current
208 sg and deduce the length of current sg.
210 memcpy(crc
->sg_mid_buf
+((i
-1) << 2) + mid_dma_count
,
212 CHKSUM_DIGEST_SIZE
- mid_dma_count
);
213 dma_addr
+= CHKSUM_DIGEST_SIZE
- mid_dma_count
;
214 dma_count
-= CHKSUM_DIGEST_SIZE
- mid_dma_count
;
216 /* chop current sg dma len to multiple of 32 bits */
217 mid_dma_count
= dma_count
% 4;
220 if (dma_addr
% 4 == 0) {
221 dma_config
|= WDSIZE_32
;
224 } else if (dma_addr
% 2 == 0) {
225 dma_config
|= WDSIZE_16
;
229 dma_config
|= WDSIZE_8
;
233 crc
->sg_cpu
[i
].start_addr
= dma_addr
;
234 crc
->sg_cpu
[i
].cfg
= dma_config
;
235 crc
->sg_cpu
[i
].x_count
= dma_count
;
236 crc
->sg_cpu
[i
].x_modify
= dma_mod
;
237 dev_dbg(crc
->dev
, "%d: crc_dma: start_addr:0x%lx, "
238 "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
239 i
, crc
->sg_cpu
[i
].start_addr
,
240 crc
->sg_cpu
[i
].cfg
, crc
->sg_cpu
[i
].x_count
,
241 crc
->sg_cpu
[i
].x_modify
);
245 /* copy extra bytes to next middle dma buffer */
246 dma_config
= DMAFLOW_ARRAY
| RESTART
| NDSIZE_3
|
247 DMAEN
| PSIZE_32
| WDSIZE_32
;
248 memcpy(crc
->sg_mid_buf
+ (i
<< 2),
249 (void *)(dma_addr
+ (dma_count
<< 2)),
251 /* setup new dma descriptor for next middle dma */
252 crc
->sg_cpu
[i
].start_addr
= dma_map_single(crc
->dev
,
253 crc
->sg_mid_buf
+ (i
<< 2),
254 CHKSUM_DIGEST_SIZE
, DMA_TO_DEVICE
);
255 crc
->sg_cpu
[i
].cfg
= dma_config
;
256 crc
->sg_cpu
[i
].x_count
= 1;
257 crc
->sg_cpu
[i
].x_modify
= CHKSUM_DIGEST_SIZE
;
258 dev_dbg(crc
->dev
, "%d: crc_dma: start_addr:0x%lx, "
259 "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
260 i
, crc
->sg_cpu
[i
].start_addr
,
261 crc
->sg_cpu
[i
].cfg
, crc
->sg_cpu
[i
].x_count
,
262 crc
->sg_cpu
[i
].x_modify
);
267 dma_config
= DMAFLOW_ARRAY
| RESTART
| NDSIZE_3
| DMAEN
| PSIZE_32
| WDSIZE_32
;
268 /* For final update req, append the buffer for next update as well*/
269 if (ctx
->bufnext_len
&& (ctx
->flag
== CRC_CRYPTO_STATE_FINALUPDATE
||
270 ctx
->flag
== CRC_CRYPTO_STATE_FINISH
)) {
271 crc
->sg_cpu
[i
].start_addr
= dma_map_single(crc
->dev
, ctx
->bufnext
,
272 CHKSUM_DIGEST_SIZE
, DMA_TO_DEVICE
);
273 crc
->sg_cpu
[i
].cfg
= dma_config
;
274 crc
->sg_cpu
[i
].x_count
= 1;
275 crc
->sg_cpu
[i
].x_modify
= CHKSUM_DIGEST_SIZE
;
276 dev_dbg(crc
->dev
, "%d: crc_dma: start_addr:0x%lx, "
277 "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
278 i
, crc
->sg_cpu
[i
].start_addr
,
279 crc
->sg_cpu
[i
].cfg
, crc
->sg_cpu
[i
].x_count
,
280 crc
->sg_cpu
[i
].x_modify
);
287 /* Set the last descriptor to stop mode */
288 crc
->sg_cpu
[i
- 1].cfg
&= ~(DMAFLOW
| NDSIZE
);
289 crc
->sg_cpu
[i
- 1].cfg
|= DI_EN
;
290 set_dma_curr_desc_addr(crc
->dma_ch
, (unsigned long *)crc
->sg_dma
);
291 set_dma_x_count(crc
->dma_ch
, 0);
292 set_dma_x_modify(crc
->dma_ch
, 0);
293 set_dma_config(crc
->dma_ch
, dma_config
);
296 static int bfin_crypto_crc_handle_queue(struct bfin_crypto_crc
*crc
,
297 struct ahash_request
*req
)
299 struct crypto_async_request
*async_req
, *backlog
;
300 struct bfin_crypto_crc_reqctx
*ctx
;
301 struct scatterlist
*sg
;
304 unsigned int nextlen
;
307 spin_lock_irqsave(&crc
->lock
, flags
);
309 ret
= ahash_enqueue_request(&crc
->queue
, req
);
311 spin_unlock_irqrestore(&crc
->lock
, flags
);
314 backlog
= crypto_get_backlog(&crc
->queue
);
315 async_req
= crypto_dequeue_request(&crc
->queue
);
318 spin_unlock_irqrestore(&crc
->lock
, flags
);
324 backlog
->complete(backlog
, -EINPROGRESS
);
326 req
= ahash_request_cast(async_req
);
328 ctx
= ahash_request_ctx(req
);
333 dev_dbg(crc
->dev
, "handling new req, flag=%u, nbytes: %d\n",
334 ctx
->flag
, req
->nbytes
);
336 if (ctx
->flag
== CRC_CRYPTO_STATE_FINISH
) {
337 if (ctx
->bufnext_len
== 0) {
342 /* Pack last crc update buffer to 32bit */
343 memset(ctx
->bufnext
+ ctx
->bufnext_len
, 0,
344 CHKSUM_DIGEST_SIZE
- ctx
->bufnext_len
);
346 /* Pack small data which is less than 32bit to buffer for next update. */
347 if (ctx
->bufnext_len
+ req
->nbytes
< CHKSUM_DIGEST_SIZE
) {
348 memcpy(ctx
->bufnext
+ ctx
->bufnext_len
,
349 sg_virt(req
->src
), req
->nbytes
);
350 ctx
->bufnext_len
+= req
->nbytes
;
351 if (ctx
->flag
== CRC_CRYPTO_STATE_FINALUPDATE
&&
360 if (ctx
->bufnext_len
) {
361 /* Chain in extra bytes of last update */
362 ctx
->buflast_len
= ctx
->bufnext_len
;
363 memcpy(ctx
->buflast
, ctx
->bufnext
, ctx
->buflast_len
);
365 nsg
= ctx
->sg_buflen
? 2 : 1;
366 sg_init_table(ctx
->bufsl
, nsg
);
367 sg_set_buf(ctx
->bufsl
, ctx
->buflast
, ctx
->buflast_len
);
369 scatterwalk_sg_chain(ctx
->bufsl
, nsg
,
371 ctx
->sg
= ctx
->bufsl
;
375 /* Chop crc buffer size to multiple of 32 bit */
376 nsg
= ctx
->sg_nents
= sg_count(ctx
->sg
);
377 ctx
->sg_buflen
= ctx
->buflast_len
+ req
->nbytes
;
378 ctx
->bufnext_len
= ctx
->sg_buflen
% 4;
379 ctx
->sg_buflen
&= ~0x3;
381 if (ctx
->bufnext_len
) {
382 /* copy extra bytes to buffer for next update */
383 memset(ctx
->bufnext
, 0, CHKSUM_DIGEST_SIZE
);
384 nextlen
= ctx
->bufnext_len
;
385 for (i
= nsg
- 1; i
>= 0; i
--) {
386 sg
= sg_get(ctx
->sg
, nsg
, i
);
387 j
= min(nextlen
, sg_dma_len(sg
));
388 memcpy(ctx
->bufnext
+ nextlen
- j
,
389 sg_virt(sg
) + sg_dma_len(sg
) - j
, j
);
390 if (j
== sg_dma_len(sg
))
400 if (ctx
->bufnext_len
&& (ctx
->flag
== CRC_CRYPTO_STATE_FINALUPDATE
||
401 ctx
->flag
== CRC_CRYPTO_STATE_FINISH
))
402 ctx
->sg_buflen
+= CHKSUM_DIGEST_SIZE
;
404 /* set CRC data count before start DMA */
405 crc
->regs
->datacnt
= ctx
->sg_buflen
>> 2;
407 /* setup and enable CRC DMA */
408 bfin_crypto_crc_config_dma(crc
);
410 /* finally kick off CRC operation */
411 crc
->regs
->control
|= BLKEN
;
416 static int bfin_crypto_crc_update(struct ahash_request
*req
)
418 struct bfin_crypto_crc_reqctx
*ctx
= ahash_request_ctx(req
);
423 dev_dbg(ctx
->crc
->dev
, "crc_update\n");
424 ctx
->total
+= req
->nbytes
;
425 ctx
->flag
= CRC_CRYPTO_STATE_UPDATE
;
427 return bfin_crypto_crc_handle_queue(ctx
->crc
, req
);
430 static int bfin_crypto_crc_final(struct ahash_request
*req
)
432 struct crypto_ahash
*tfm
= crypto_ahash_reqtfm(req
);
433 struct bfin_crypto_crc_ctx
*crc_ctx
= crypto_ahash_ctx(tfm
);
434 struct bfin_crypto_crc_reqctx
*ctx
= ahash_request_ctx(req
);
436 dev_dbg(ctx
->crc
->dev
, "crc_final\n");
437 ctx
->flag
= CRC_CRYPTO_STATE_FINISH
;
440 return bfin_crypto_crc_handle_queue(ctx
->crc
, req
);
443 static int bfin_crypto_crc_finup(struct ahash_request
*req
)
445 struct crypto_ahash
*tfm
= crypto_ahash_reqtfm(req
);
446 struct bfin_crypto_crc_ctx
*crc_ctx
= crypto_ahash_ctx(tfm
);
447 struct bfin_crypto_crc_reqctx
*ctx
= ahash_request_ctx(req
);
449 dev_dbg(ctx
->crc
->dev
, "crc_finishupdate\n");
450 ctx
->total
+= req
->nbytes
;
451 ctx
->flag
= CRC_CRYPTO_STATE_FINALUPDATE
;
454 return bfin_crypto_crc_handle_queue(ctx
->crc
, req
);
457 static int bfin_crypto_crc_digest(struct ahash_request
*req
)
461 ret
= bfin_crypto_crc_init(req
);
465 return bfin_crypto_crc_finup(req
);
468 static int bfin_crypto_crc_setkey(struct crypto_ahash
*tfm
, const u8
*key
,
471 struct bfin_crypto_crc_ctx
*crc_ctx
= crypto_ahash_ctx(tfm
);
473 dev_dbg(crc_ctx
->crc
->dev
, "crc_setkey\n");
474 if (keylen
!= CHKSUM_DIGEST_SIZE
) {
475 crypto_ahash_set_flags(tfm
, CRYPTO_TFM_RES_BAD_KEY_LEN
);
479 crc_ctx
->key
= get_unaligned_le32(key
);
484 static int bfin_crypto_crc_cra_init(struct crypto_tfm
*tfm
)
486 struct bfin_crypto_crc_ctx
*crc_ctx
= crypto_tfm_ctx(tfm
);
489 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm
),
490 sizeof(struct bfin_crypto_crc_reqctx
));
495 static void bfin_crypto_crc_cra_exit(struct crypto_tfm
*tfm
)
499 static struct ahash_alg algs
= {
500 .init
= bfin_crypto_crc_init
,
501 .update
= bfin_crypto_crc_update
,
502 .final
= bfin_crypto_crc_final
,
503 .finup
= bfin_crypto_crc_finup
,
504 .digest
= bfin_crypto_crc_digest
,
505 .setkey
= bfin_crypto_crc_setkey
,
506 .halg
.digestsize
= CHKSUM_DIGEST_SIZE
,
508 .cra_name
= "hmac(crc32)",
509 .cra_driver_name
= DRIVER_NAME
,
511 .cra_flags
= CRYPTO_ALG_TYPE_AHASH
|
513 .cra_blocksize
= CHKSUM_BLOCK_SIZE
,
514 .cra_ctxsize
= sizeof(struct bfin_crypto_crc_ctx
),
516 .cra_module
= THIS_MODULE
,
517 .cra_init
= bfin_crypto_crc_cra_init
,
518 .cra_exit
= bfin_crypto_crc_cra_exit
,
522 static void bfin_crypto_crc_done_task(unsigned long data
)
524 struct bfin_crypto_crc
*crc
= (struct bfin_crypto_crc
*)data
;
526 bfin_crypto_crc_handle_queue(crc
, NULL
);
529 static irqreturn_t
bfin_crypto_crc_handler(int irq
, void *dev_id
)
531 struct bfin_crypto_crc
*crc
= dev_id
;
533 if (crc
->regs
->status
& DCNTEXP
) {
534 crc
->regs
->status
= DCNTEXP
;
536 /* prepare results */
537 put_unaligned_le32(crc
->regs
->result
, crc
->req
->result
);
539 crc
->regs
->control
&= ~BLKEN
;
542 if (crc
->req
->base
.complete
)
543 crc
->req
->base
.complete(&crc
->req
->base
, 0);
545 tasklet_schedule(&crc
->done_task
);
554 * bfin_crypto_crc_suspend - suspend crc device
555 * @pdev: device being suspended
556 * @state: requested suspend state
558 static int bfin_crypto_crc_suspend(struct platform_device
*pdev
, pm_message_t state
)
560 struct bfin_crypto_crc
*crc
= platform_get_drvdata(pdev
);
563 while ((crc
->regs
->control
& BLKEN
) && --i
)
572 # define bfin_crypto_crc_suspend NULL
575 #define bfin_crypto_crc_resume NULL
578 * bfin_crypto_crc_probe - Initialize module
581 static int bfin_crypto_crc_probe(struct platform_device
*pdev
)
583 struct device
*dev
= &pdev
->dev
;
584 struct resource
*res
;
585 struct bfin_crypto_crc
*crc
;
586 unsigned int timeout
= 100000;
589 crc
= devm_kzalloc(dev
, sizeof(*crc
), GFP_KERNEL
);
591 dev_err(&pdev
->dev
, "fail to malloc bfin_crypto_crc\n");
597 INIT_LIST_HEAD(&crc
->list
);
598 spin_lock_init(&crc
->lock
);
599 tasklet_init(&crc
->done_task
, bfin_crypto_crc_done_task
, (unsigned long)crc
);
600 crypto_init_queue(&crc
->queue
, CRC_CCRYPTO_QUEUE_LENGTH
);
602 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
604 dev_err(&pdev
->dev
, "Cannot get IORESOURCE_MEM\n");
608 crc
->regs
= devm_ioremap_resource(dev
, res
);
609 if (IS_ERR((void *)crc
->regs
)) {
610 dev_err(&pdev
->dev
, "Cannot map CRC IO\n");
611 return PTR_ERR((void *)crc
->regs
);
614 crc
->irq
= platform_get_irq(pdev
, 0);
616 dev_err(&pdev
->dev
, "No CRC DCNTEXP IRQ specified\n");
620 ret
= devm_request_irq(dev
, crc
->irq
, bfin_crypto_crc_handler
,
621 IRQF_SHARED
, dev_name(dev
), crc
);
623 dev_err(&pdev
->dev
, "Unable to request blackfin crc irq\n");
627 res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
629 dev_err(&pdev
->dev
, "No CRC DMA channel specified\n");
632 crc
->dma_ch
= res
->start
;
634 ret
= request_dma(crc
->dma_ch
, dev_name(dev
));
636 dev_err(&pdev
->dev
, "Unable to attach Blackfin CRC DMA channel\n");
640 crc
->sg_cpu
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
, &crc
->sg_dma
, GFP_KERNEL
);
641 if (crc
->sg_cpu
== NULL
) {
646 * need at most CRC_MAX_DMA_DESC sg + CRC_MAX_DMA_DESC middle +
647 * 1 last + 1 next dma descriptors
649 crc
->sg_mid_buf
= (u8
*)(crc
->sg_cpu
+ ((CRC_MAX_DMA_DESC
+ 1) << 1));
651 crc
->regs
->control
= 0;
652 crc
->regs
->poly
= crc
->poly
= (u32
)pdev
->dev
.platform_data
;
654 while (!(crc
->regs
->status
& LUTDONE
) && (--timeout
) > 0)
658 dev_info(&pdev
->dev
, "init crc poly timeout\n");
660 spin_lock(&crc_list
.lock
);
661 list_add(&crc
->list
, &crc_list
.dev_list
);
662 spin_unlock(&crc_list
.lock
);
664 platform_set_drvdata(pdev
, crc
);
666 ret
= crypto_register_ahash(&algs
);
668 spin_lock(&crc_list
.lock
);
669 list_del(&crc
->list
);
670 spin_unlock(&crc_list
.lock
);
671 dev_err(&pdev
->dev
, "Cann't register crypto ahash device\n");
675 dev_info(&pdev
->dev
, "initialized\n");
681 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, crc
->sg_cpu
, crc
->sg_dma
);
682 free_dma(crc
->dma_ch
);
688 * bfin_crypto_crc_remove - Initialize module
691 static int bfin_crypto_crc_remove(struct platform_device
*pdev
)
693 struct bfin_crypto_crc
*crc
= platform_get_drvdata(pdev
);
698 spin_lock(&crc_list
.lock
);
699 list_del(&crc
->list
);
700 spin_unlock(&crc_list
.lock
);
702 crypto_unregister_ahash(&algs
);
703 tasklet_kill(&crc
->done_task
);
704 free_dma(crc
->dma_ch
);
709 static struct platform_driver bfin_crypto_crc_driver
= {
710 .probe
= bfin_crypto_crc_probe
,
711 .remove
= bfin_crypto_crc_remove
,
712 .suspend
= bfin_crypto_crc_suspend
,
713 .resume
= bfin_crypto_crc_resume
,
716 .owner
= THIS_MODULE
,
721 * bfin_crypto_crc_mod_init - Initialize module
723 * Checks the module params and registers the platform driver.
724 * Real work is in the platform probe function.
726 static int __init
bfin_crypto_crc_mod_init(void)
730 pr_info("Blackfin hardware CRC crypto driver\n");
732 INIT_LIST_HEAD(&crc_list
.dev_list
);
733 spin_lock_init(&crc_list
.lock
);
735 ret
= platform_driver_register(&bfin_crypto_crc_driver
);
737 pr_info(KERN_ERR
"unable to register driver\n");
745 * bfin_crypto_crc_mod_exit - Deinitialize module
747 static void __exit
bfin_crypto_crc_mod_exit(void)
749 platform_driver_unregister(&bfin_crypto_crc_driver
);
752 module_init(bfin_crypto_crc_mod_init
);
753 module_exit(bfin_crypto_crc_mod_exit
);
755 MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
756 MODULE_DESCRIPTION("Blackfin CRC hardware crypto driver");
757 MODULE_LICENSE("GPL");