1 /* * CAAM control-plane driver backend
2 * Controller-level driver, kernel property detection, initialization
4 * Copyright 2008-2012 Freescale Semiconductor, Inc.
7 #include <linux/device.h>
8 #include <linux/of_address.h>
9 #include <linux/of_irq.h>
15 #include "desc_constr.h"
19 * i.MX targets tend to have clock control subsystems that can
20 * enable/disable clocking to our device.
22 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
23 static inline struct clk
*caam_drv_identify_clk(struct device
*dev
,
26 return devm_clk_get(dev
, clk_name
);
29 static inline struct clk
*caam_drv_identify_clk(struct device
*dev
,
37 * Descriptor to instantiate RNG State Handle 0 in normal mode and
38 * load the JDKEK, TDKEK and TDSK registers
40 static void build_instantiation_desc(u32
*desc
, int handle
, int do_sk
)
42 u32
*jump_cmd
, op_flags
;
44 init_job_desc(desc
, 0);
46 op_flags
= OP_TYPE_CLASS1_ALG
| OP_ALG_ALGSEL_RNG
|
47 (handle
<< OP_ALG_AAI_SHIFT
) | OP_ALG_AS_INIT
;
49 /* INIT RNG in non-test mode */
50 append_operation(desc
, op_flags
);
52 if (!handle
&& do_sk
) {
54 * For SH0, Secure Keys must be generated as well
58 jump_cmd
= append_jump(desc
, JUMP_CLASS_CLASS1
);
59 set_jump_tgt_here(desc
, jump_cmd
);
62 * load 1 to clear written reg:
63 * resets the done interrrupt and returns the RNG to idle.
65 append_load_imm_u32(desc
, 1, LDST_SRCDST_WORD_CLRW
);
67 /* Initialize State Handle */
68 append_operation(desc
, OP_TYPE_CLASS1_ALG
| OP_ALG_ALGSEL_RNG
|
72 append_jump(desc
, JUMP_CLASS_CLASS1
| JUMP_TYPE_HALT
);
75 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
76 static void build_deinstantiation_desc(u32
*desc
, int handle
)
78 init_job_desc(desc
, 0);
80 /* Uninstantiate State Handle 0 */
81 append_operation(desc
, OP_TYPE_CLASS1_ALG
| OP_ALG_ALGSEL_RNG
|
82 (handle
<< OP_ALG_AAI_SHIFT
) | OP_ALG_AS_INITFINAL
);
84 append_jump(desc
, JUMP_CLASS_CLASS1
| JUMP_TYPE_HALT
);
88 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
89 * the software (no JR/QI used).
90 * @ctrldev - pointer to device
91 * @status - descriptor status, after being run
93 * Return: - 0 if no error occurred
94 * - -ENODEV if the DECO couldn't be acquired
95 * - -EAGAIN if an error occurred while executing the descriptor
97 static inline int run_descriptor_deco0(struct device
*ctrldev
, u32
*desc
,
100 struct caam_drv_private
*ctrlpriv
= dev_get_drvdata(ctrldev
);
101 struct caam_ctrl __iomem
*ctrl
= ctrlpriv
->ctrl
;
102 struct caam_deco __iomem
*deco
= ctrlpriv
->deco
;
103 unsigned int timeout
= 100000;
104 u32 deco_dbg_reg
, flags
;
108 if (ctrlpriv
->virt_en
== 1) {
109 setbits32(&ctrl
->deco_rsr
, DECORSR_JR0
);
111 while (!(rd_reg32(&ctrl
->deco_rsr
) & DECORSR_VALID
) &&
118 setbits32(&ctrl
->deco_rq
, DECORR_RQD0ENABLE
);
120 while (!(rd_reg32(&ctrl
->deco_rq
) & DECORR_DEN0
) &&
125 dev_err(ctrldev
, "failed to acquire DECO 0\n");
126 clrbits32(&ctrl
->deco_rq
, DECORR_RQD0ENABLE
);
130 for (i
= 0; i
< desc_len(desc
); i
++)
131 wr_reg32(&deco
->descbuf
[i
], *(desc
+ i
));
133 flags
= DECO_JQCR_WHL
;
135 * If the descriptor length is longer than 4 words, then the
136 * FOUR bit in JRCTRL register must be set.
138 if (desc_len(desc
) >= 4)
139 flags
|= DECO_JQCR_FOUR
;
141 /* Instruct the DECO to execute it */
142 setbits32(&deco
->jr_ctl_hi
, flags
);
146 deco_dbg_reg
= rd_reg32(&deco
->desc_dbg
);
148 * If an error occured in the descriptor, then
149 * the DECO status field will be set to 0x0D
151 if ((deco_dbg_reg
& DESC_DBG_DECO_STAT_MASK
) ==
152 DESC_DBG_DECO_STAT_HOST_ERR
)
155 } while ((deco_dbg_reg
& DESC_DBG_DECO_STAT_VALID
) && --timeout
);
157 *status
= rd_reg32(&deco
->op_status_hi
) &
158 DECO_OP_STATUS_HI_ERR_MASK
;
160 if (ctrlpriv
->virt_en
== 1)
161 clrbits32(&ctrl
->deco_rsr
, DECORSR_JR0
);
163 /* Mark the DECO as free */
164 clrbits32(&ctrl
->deco_rq
, DECORR_RQD0ENABLE
);
173 * instantiate_rng - builds and executes a descriptor on DECO0,
174 * which initializes the RNG block.
175 * @ctrldev - pointer to device
176 * @state_handle_mask - bitmask containing the instantiation status
177 * for the RNG4 state handles which exist in
178 * the RNG4 block: 1 if it's been instantiated
179 * by an external entry, 0 otherwise.
180 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
181 * Caution: this can be done only once; if the keys need to be
182 * regenerated, a POR is required
184 * Return: - 0 if no error occurred
185 * - -ENOMEM if there isn't enough memory to allocate the descriptor
186 * - -ENODEV if DECO0 couldn't be acquired
187 * - -EAGAIN if an error occurred when executing the descriptor
188 * f.i. there was a RNG hardware error due to not "good enough"
189 * entropy being aquired.
191 static int instantiate_rng(struct device
*ctrldev
, int state_handle_mask
,
194 struct caam_drv_private
*ctrlpriv
= dev_get_drvdata(ctrldev
);
195 struct caam_ctrl __iomem
*ctrl
;
196 u32
*desc
, status
= 0, rdsta_val
;
199 ctrl
= (struct caam_ctrl __iomem
*)ctrlpriv
->ctrl
;
200 desc
= kmalloc(CAAM_CMD_SZ
* 7, GFP_KERNEL
);
204 for (sh_idx
= 0; sh_idx
< RNG4_MAX_HANDLES
; sh_idx
++) {
206 * If the corresponding bit is set, this state handle
207 * was initialized by somebody else, so it's left alone.
209 if ((1 << sh_idx
) & state_handle_mask
)
212 /* Create the descriptor for instantiating RNG State Handle */
213 build_instantiation_desc(desc
, sh_idx
, gen_sk
);
215 /* Try to run it through DECO0 */
216 ret
= run_descriptor_deco0(ctrldev
, desc
, &status
);
219 * If ret is not 0, or descriptor status is not 0, then
220 * something went wrong. No need to try the next state
221 * handle (if available), bail out here.
222 * Also, if for some reason, the State Handle didn't get
223 * instantiated although the descriptor has finished
224 * without any error (HW optimizations for later
225 * CAAM eras), then try again.
227 rdsta_val
= rd_reg32(&ctrl
->r4tst
[0].rdsta
) & RDSTA_IFMASK
;
228 if ((status
&& status
!= JRSTA_SSRC_JUMP_HALT_CC
) ||
229 !(rdsta_val
& (1 << sh_idx
)))
233 dev_info(ctrldev
, "Instantiated RNG4 SH%d\n", sh_idx
);
234 /* Clear the contents before recreating the descriptor */
235 memset(desc
, 0x00, CAAM_CMD_SZ
* 7);
244 * deinstantiate_rng - builds and executes a descriptor on DECO0,
245 * which deinitializes the RNG block.
246 * @ctrldev - pointer to device
247 * @state_handle_mask - bitmask containing the instantiation status
248 * for the RNG4 state handles which exist in
249 * the RNG4 block: 1 if it's been instantiated
251 * Return: - 0 if no error occurred
252 * - -ENOMEM if there isn't enough memory to allocate the descriptor
253 * - -ENODEV if DECO0 couldn't be acquired
254 * - -EAGAIN if an error occurred when executing the descriptor
256 static int deinstantiate_rng(struct device
*ctrldev
, int state_handle_mask
)
261 desc
= kmalloc(CAAM_CMD_SZ
* 3, GFP_KERNEL
);
265 for (sh_idx
= 0; sh_idx
< RNG4_MAX_HANDLES
; sh_idx
++) {
267 * If the corresponding bit is set, then it means the state
268 * handle was initialized by us, and thus it needs to be
269 * deintialized as well
271 if ((1 << sh_idx
) & state_handle_mask
) {
273 * Create the descriptor for deinstantating this state
276 build_deinstantiation_desc(desc
, sh_idx
);
278 /* Try to run it through DECO0 */
279 ret
= run_descriptor_deco0(ctrldev
, desc
, &status
);
283 "Failed to deinstantiate RNG4 SH%d\n",
287 dev_info(ctrldev
, "Deinstantiated RNG4 SH%d\n", sh_idx
);
296 static int caam_remove(struct platform_device
*pdev
)
298 struct device
*ctrldev
;
299 struct caam_drv_private
*ctrlpriv
;
300 struct caam_ctrl __iomem
*ctrl
;
303 ctrldev
= &pdev
->dev
;
304 ctrlpriv
= dev_get_drvdata(ctrldev
);
305 ctrl
= (struct caam_ctrl __iomem
*)ctrlpriv
->ctrl
;
307 /* Remove platform devices for JobRs */
308 for (ring
= 0; ring
< ctrlpriv
->total_jobrs
; ring
++) {
309 if (ctrlpriv
->jrpdev
[ring
])
310 of_device_unregister(ctrlpriv
->jrpdev
[ring
]);
313 /* De-initialize RNG state handles initialized by this driver. */
314 if (ctrlpriv
->rng4_sh_init
)
315 deinstantiate_rng(ctrldev
, ctrlpriv
->rng4_sh_init
);
317 /* Shut down debug views */
318 #ifdef CONFIG_DEBUG_FS
319 debugfs_remove_recursive(ctrlpriv
->dfs_root
);
322 /* Unmap controller region */
325 /* shut clocks off before finalizing shutdown */
326 clk_disable_unprepare(ctrlpriv
->caam_ipg
);
327 clk_disable_unprepare(ctrlpriv
->caam_mem
);
328 clk_disable_unprepare(ctrlpriv
->caam_aclk
);
329 clk_disable_unprepare(ctrlpriv
->caam_emi_slow
);
335 * kick_trng - sets the various parameters for enabling the initialization
336 * of the RNG4 block in CAAM
337 * @pdev - pointer to the platform device
338 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
340 static void kick_trng(struct platform_device
*pdev
, int ent_delay
)
342 struct device
*ctrldev
= &pdev
->dev
;
343 struct caam_drv_private
*ctrlpriv
= dev_get_drvdata(ctrldev
);
344 struct caam_ctrl __iomem
*ctrl
;
345 struct rng4tst __iomem
*r4tst
;
348 ctrl
= (struct caam_ctrl __iomem
*)ctrlpriv
->ctrl
;
349 r4tst
= &ctrl
->r4tst
[0];
351 /* put RNG4 into program mode */
352 setbits32(&r4tst
->rtmctl
, RTMCTL_PRGM
);
355 * Performance-wise, it does not make sense to
356 * set the delay to a value that is lower
357 * than the last one that worked (i.e. the state handles
358 * were instantiated properly. Thus, instead of wasting
359 * time trying to set the values controlling the sample
360 * frequency, the function simply returns.
362 val
= (rd_reg32(&r4tst
->rtsdctl
) & RTSDCTL_ENT_DLY_MASK
)
363 >> RTSDCTL_ENT_DLY_SHIFT
;
364 if (ent_delay
<= val
) {
365 /* put RNG4 into run mode */
366 clrbits32(&r4tst
->rtmctl
, RTMCTL_PRGM
);
370 val
= rd_reg32(&r4tst
->rtsdctl
);
371 val
= (val
& ~RTSDCTL_ENT_DLY_MASK
) |
372 (ent_delay
<< RTSDCTL_ENT_DLY_SHIFT
);
373 wr_reg32(&r4tst
->rtsdctl
, val
);
374 /* min. freq. count, equal to 1/4 of the entropy sample length */
375 wr_reg32(&r4tst
->rtfrqmin
, ent_delay
>> 2);
376 /* disable maximum frequency count */
377 wr_reg32(&r4tst
->rtfrqmax
, RTFRQMAX_DISABLE
);
378 /* read the control register */
379 val
= rd_reg32(&r4tst
->rtmctl
);
381 * select raw sampling in both entropy shifter
382 * and statistical checker
384 setbits32(&val
, RTMCTL_SAMP_MODE_RAW_ES_SC
);
385 /* put RNG4 into run mode */
386 clrbits32(&val
, RTMCTL_PRGM
);
387 /* write back the control register */
388 wr_reg32(&r4tst
->rtmctl
, val
);
392 * caam_get_era() - Return the ERA of the SEC on SoC, based
393 * on "sec-era" propery in the DTS. This property is updated by u-boot.
395 int caam_get_era(void)
397 struct device_node
*caam_node
;
401 caam_node
= of_find_compatible_node(NULL
, NULL
, "fsl,sec-v4.0");
402 ret
= of_property_read_u32(caam_node
, "fsl,sec-era", &prop
);
403 of_node_put(caam_node
);
405 return IS_ERR_VALUE(ret
) ? -ENOTSUPP
: prop
;
407 EXPORT_SYMBOL(caam_get_era
);
409 /* Probe routine for CAAM top (controller) level */
410 static int caam_probe(struct platform_device
*pdev
)
412 int ret
, ring
, rspec
, gen_sk
, ent_delay
= RTSDCTL_ENT_DLY_MIN
;
415 struct device_node
*nprop
, *np
;
416 struct caam_ctrl __iomem
*ctrl
;
417 struct caam_drv_private
*ctrlpriv
;
419 #ifdef CONFIG_DEBUG_FS
420 struct caam_perfmon
*perfmon
;
422 u32 scfgr
, comp_params
;
425 int BLOCK_OFFSET
= 0;
427 ctrlpriv
= devm_kzalloc(&pdev
->dev
, sizeof(struct caam_drv_private
),
433 dev_set_drvdata(dev
, ctrlpriv
);
434 ctrlpriv
->pdev
= pdev
;
435 nprop
= pdev
->dev
.of_node
;
437 /* Enable clocking */
438 clk
= caam_drv_identify_clk(&pdev
->dev
, "ipg");
442 "can't identify CAAM ipg clk: %d\n", ret
);
445 ctrlpriv
->caam_ipg
= clk
;
447 clk
= caam_drv_identify_clk(&pdev
->dev
, "mem");
451 "can't identify CAAM mem clk: %d\n", ret
);
454 ctrlpriv
->caam_mem
= clk
;
456 clk
= caam_drv_identify_clk(&pdev
->dev
, "aclk");
460 "can't identify CAAM aclk clk: %d\n", ret
);
463 ctrlpriv
->caam_aclk
= clk
;
465 clk
= caam_drv_identify_clk(&pdev
->dev
, "emi_slow");
469 "can't identify CAAM emi_slow clk: %d\n", ret
);
472 ctrlpriv
->caam_emi_slow
= clk
;
474 ret
= clk_prepare_enable(ctrlpriv
->caam_ipg
);
476 dev_err(&pdev
->dev
, "can't enable CAAM ipg clock: %d\n", ret
);
480 ret
= clk_prepare_enable(ctrlpriv
->caam_mem
);
482 dev_err(&pdev
->dev
, "can't enable CAAM secure mem clock: %d\n",
487 ret
= clk_prepare_enable(ctrlpriv
->caam_aclk
);
489 dev_err(&pdev
->dev
, "can't enable CAAM aclk clock: %d\n", ret
);
493 ret
= clk_prepare_enable(ctrlpriv
->caam_emi_slow
);
495 dev_err(&pdev
->dev
, "can't enable CAAM emi slow clock: %d\n",
500 /* Get configuration properties from device tree */
501 /* First, get register page */
502 ctrl
= of_iomap(nprop
, 0);
504 dev_err(dev
, "caam: of_iomap() failed\n");
507 /* Finding the page size for using the CTPR_MS register */
508 comp_params
= rd_reg32(&ctrl
->perfmon
.comp_parms_ms
);
509 pg_size
= (comp_params
& CTPR_MS_PG_SZ_MASK
) >> CTPR_MS_PG_SZ_SHIFT
;
511 /* Allocating the BLOCK_OFFSET based on the supported page size on
515 BLOCK_OFFSET
= PG_SIZE_4K
;
517 BLOCK_OFFSET
= PG_SIZE_64K
;
519 ctrlpriv
->ctrl
= (struct caam_ctrl __force
*)ctrl
;
520 ctrlpriv
->assure
= (struct caam_assurance __force
*)
522 BLOCK_OFFSET
* ASSURE_BLOCK_NUMBER
524 ctrlpriv
->deco
= (struct caam_deco __force
*)
526 BLOCK_OFFSET
* DECO_BLOCK_NUMBER
529 /* Get the IRQ of the controller (for security violations only) */
530 ctrlpriv
->secvio_irq
= irq_of_parse_and_map(nprop
, 0);
533 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
534 * long pointers in master configuration register
536 clrsetbits_32(&ctrl
->mcr
, MCFGR_AWCACHE_MASK
, MCFGR_AWCACHE_CACH
|
537 MCFGR_WDENABLE
| (sizeof(dma_addr_t
) == sizeof(u64
) ?
538 MCFGR_LONG_PTR
: 0));
541 * Read the Compile Time paramters and SCFGR to determine
542 * if Virtualization is enabled for this platform
544 scfgr
= rd_reg32(&ctrl
->scfgr
);
546 ctrlpriv
->virt_en
= 0;
547 if (comp_params
& CTPR_MS_VIRT_EN_INCL
) {
548 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
549 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
551 if ((comp_params
& CTPR_MS_VIRT_EN_POR
) ||
552 (!(comp_params
& CTPR_MS_VIRT_EN_POR
) &&
553 (scfgr
& SCFGR_VIRT_EN
)))
554 ctrlpriv
->virt_en
= 1;
556 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
557 if (comp_params
& CTPR_MS_VIRT_EN_POR
)
558 ctrlpriv
->virt_en
= 1;
561 if (ctrlpriv
->virt_en
== 1)
562 setbits32(&ctrl
->jrstart
, JRSTART_JR0_START
|
563 JRSTART_JR1_START
| JRSTART_JR2_START
|
566 if (sizeof(dma_addr_t
) == sizeof(u64
))
567 if (of_device_is_compatible(nprop
, "fsl,sec-v5.0"))
568 dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(40));
570 dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(36));
572 dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(32));
575 * Detect and enable JobRs
576 * First, find out how many ring spec'ed, allocate references
577 * for all, then go probe each one.
580 for_each_available_child_of_node(nprop
, np
)
581 if (of_device_is_compatible(np
, "fsl,sec-v4.0-job-ring") ||
582 of_device_is_compatible(np
, "fsl,sec4.0-job-ring"))
585 ctrlpriv
->jrpdev
= devm_kzalloc(&pdev
->dev
,
586 sizeof(struct platform_device
*) * rspec
,
588 if (ctrlpriv
->jrpdev
== NULL
) {
594 ctrlpriv
->total_jobrs
= 0;
595 for_each_available_child_of_node(nprop
, np
)
596 if (of_device_is_compatible(np
, "fsl,sec-v4.0-job-ring") ||
597 of_device_is_compatible(np
, "fsl,sec4.0-job-ring")) {
598 ctrlpriv
->jrpdev
[ring
] =
599 of_platform_device_create(np
, NULL
, dev
);
600 if (!ctrlpriv
->jrpdev
[ring
]) {
601 pr_warn("JR%d Platform device creation error\n",
605 ctrlpriv
->jr
[ring
] = (struct caam_job_ring __force
*)
607 (ring
+ JR_BLOCK_NUMBER
) *
610 ctrlpriv
->total_jobrs
++;
614 /* Check to see if QI present. If so, enable */
615 ctrlpriv
->qi_present
=
616 !!(rd_reg32(&ctrl
->perfmon
.comp_parms_ms
) &
618 if (ctrlpriv
->qi_present
) {
619 ctrlpriv
->qi
= (struct caam_queue_if __force
*)
621 BLOCK_OFFSET
* QI_BLOCK_NUMBER
623 /* This is all that's required to physically enable QI */
624 wr_reg32(&ctrlpriv
->qi
->qi_control_lo
, QICTL_DQEN
);
627 /* If no QI and no rings specified, quit and go home */
628 if ((!ctrlpriv
->qi_present
) && (!ctrlpriv
->total_jobrs
)) {
629 dev_err(dev
, "no queues configured, terminating\n");
634 cha_vid_ls
= rd_reg32(&ctrl
->perfmon
.cha_id_ls
);
637 * If SEC has RNG version >= 4 and RNG state handle has not been
638 * already instantiated, do RNG instantiation
640 if ((cha_vid_ls
& CHA_ID_LS_RNG_MASK
) >> CHA_ID_LS_RNG_SHIFT
>= 4) {
641 ctrlpriv
->rng4_sh_init
=
642 rd_reg32(&ctrl
->r4tst
[0].rdsta
);
644 * If the secure keys (TDKEK, JDKEK, TDSK), were already
645 * generated, signal this to the function that is instantiating
646 * the state handles. An error would occur if RNG4 attempts
647 * to regenerate these keys before the next POR.
649 gen_sk
= ctrlpriv
->rng4_sh_init
& RDSTA_SKVN
? 0 : 1;
650 ctrlpriv
->rng4_sh_init
&= RDSTA_IFMASK
;
653 rd_reg32(&ctrl
->r4tst
[0].rdsta
) &
656 * If either SH were instantiated by somebody else
657 * (e.g. u-boot) then it is assumed that the entropy
658 * parameters are properly set and thus the function
659 * setting these (kick_trng(...)) is skipped.
660 * Also, if a handle was instantiated, do not change
661 * the TRNG parameters.
663 if (!(ctrlpriv
->rng4_sh_init
|| inst_handles
)) {
665 "Entropy delay = %u\n",
667 kick_trng(pdev
, ent_delay
);
671 * if instantiate_rng(...) fails, the loop will rerun
672 * and the kick_trng(...) function will modfiy the
673 * upper and lower limits of the entropy sampling
674 * interval, leading to a sucessful initialization of
677 ret
= instantiate_rng(dev
, inst_handles
,
681 * if here, the loop will rerun,
682 * so don't hog the CPU
685 } while ((ret
== -EAGAIN
) && (ent_delay
< RTSDCTL_ENT_DLY_MAX
));
687 dev_err(dev
, "failed to instantiate RNG");
692 * Set handles init'ed by this module as the complement of the
693 * already initialized ones
695 ctrlpriv
->rng4_sh_init
= ~ctrlpriv
->rng4_sh_init
& RDSTA_IFMASK
;
697 /* Enable RDB bit so that RNG works faster */
698 setbits32(&ctrl
->scfgr
, SCFGR_RDBENABLE
);
701 /* NOTE: RTIC detection ought to go here, around Si time */
703 caam_id
= (u64
)rd_reg32(&ctrl
->perfmon
.caam_id_ms
) << 32 |
704 (u64
)rd_reg32(&ctrl
->perfmon
.caam_id_ls
);
706 /* Report "alive" for developer to see */
707 dev_info(dev
, "device ID = 0x%016llx (Era %d)\n", caam_id
,
709 dev_info(dev
, "job rings = %d, qi = %d\n",
710 ctrlpriv
->total_jobrs
, ctrlpriv
->qi_present
);
712 #ifdef CONFIG_DEBUG_FS
714 * FIXME: needs better naming distinction, as some amalgamation of
715 * "caam" and nprop->full_name. The OF name isn't distinctive,
716 * but does separate instances
718 perfmon
= (struct caam_perfmon __force
*)&ctrl
->perfmon
;
720 ctrlpriv
->dfs_root
= debugfs_create_dir(dev_name(dev
), NULL
);
721 ctrlpriv
->ctl
= debugfs_create_dir("ctl", ctrlpriv
->dfs_root
);
723 /* Controller-level - performance monitor counters */
724 ctrlpriv
->ctl_rq_dequeued
=
725 debugfs_create_u64("rq_dequeued",
726 S_IRUSR
| S_IRGRP
| S_IROTH
,
727 ctrlpriv
->ctl
, &perfmon
->req_dequeued
);
728 ctrlpriv
->ctl_ob_enc_req
=
729 debugfs_create_u64("ob_rq_encrypted",
730 S_IRUSR
| S_IRGRP
| S_IROTH
,
731 ctrlpriv
->ctl
, &perfmon
->ob_enc_req
);
732 ctrlpriv
->ctl_ib_dec_req
=
733 debugfs_create_u64("ib_rq_decrypted",
734 S_IRUSR
| S_IRGRP
| S_IROTH
,
735 ctrlpriv
->ctl
, &perfmon
->ib_dec_req
);
736 ctrlpriv
->ctl_ob_enc_bytes
=
737 debugfs_create_u64("ob_bytes_encrypted",
738 S_IRUSR
| S_IRGRP
| S_IROTH
,
739 ctrlpriv
->ctl
, &perfmon
->ob_enc_bytes
);
740 ctrlpriv
->ctl_ob_prot_bytes
=
741 debugfs_create_u64("ob_bytes_protected",
742 S_IRUSR
| S_IRGRP
| S_IROTH
,
743 ctrlpriv
->ctl
, &perfmon
->ob_prot_bytes
);
744 ctrlpriv
->ctl_ib_dec_bytes
=
745 debugfs_create_u64("ib_bytes_decrypted",
746 S_IRUSR
| S_IRGRP
| S_IROTH
,
747 ctrlpriv
->ctl
, &perfmon
->ib_dec_bytes
);
748 ctrlpriv
->ctl_ib_valid_bytes
=
749 debugfs_create_u64("ib_bytes_validated",
750 S_IRUSR
| S_IRGRP
| S_IROTH
,
751 ctrlpriv
->ctl
, &perfmon
->ib_valid_bytes
);
753 /* Controller level - global status values */
754 ctrlpriv
->ctl_faultaddr
=
755 debugfs_create_u64("fault_addr",
756 S_IRUSR
| S_IRGRP
| S_IROTH
,
757 ctrlpriv
->ctl
, &perfmon
->faultaddr
);
758 ctrlpriv
->ctl_faultdetail
=
759 debugfs_create_u32("fault_detail",
760 S_IRUSR
| S_IRGRP
| S_IROTH
,
761 ctrlpriv
->ctl
, &perfmon
->faultdetail
);
762 ctrlpriv
->ctl_faultstatus
=
763 debugfs_create_u32("fault_status",
764 S_IRUSR
| S_IRGRP
| S_IROTH
,
765 ctrlpriv
->ctl
, &perfmon
->status
);
767 /* Internal covering keys (useful in non-secure mode only) */
768 ctrlpriv
->ctl_kek_wrap
.data
= &ctrlpriv
->ctrl
->kek
[0];
769 ctrlpriv
->ctl_kek_wrap
.size
= KEK_KEY_SIZE
* sizeof(u32
);
770 ctrlpriv
->ctl_kek
= debugfs_create_blob("kek",
774 &ctrlpriv
->ctl_kek_wrap
);
776 ctrlpriv
->ctl_tkek_wrap
.data
= &ctrlpriv
->ctrl
->tkek
[0];
777 ctrlpriv
->ctl_tkek_wrap
.size
= KEK_KEY_SIZE
* sizeof(u32
);
778 ctrlpriv
->ctl_tkek
= debugfs_create_blob("tkek",
782 &ctrlpriv
->ctl_tkek_wrap
);
784 ctrlpriv
->ctl_tdsk_wrap
.data
= &ctrlpriv
->ctrl
->tdsk
[0];
785 ctrlpriv
->ctl_tdsk_wrap
.size
= KEK_KEY_SIZE
* sizeof(u32
);
786 ctrlpriv
->ctl_tdsk
= debugfs_create_blob("tdsk",
790 &ctrlpriv
->ctl_tdsk_wrap
);
795 static struct of_device_id caam_match
[] = {
797 .compatible
= "fsl,sec-v4.0",
800 .compatible
= "fsl,sec4.0",
804 MODULE_DEVICE_TABLE(of
, caam_match
);
806 static struct platform_driver caam_driver
= {
809 .of_match_table
= caam_match
,
812 .remove
= caam_remove
,
815 module_platform_driver(caam_driver
);
817 MODULE_LICENSE("GPL");
818 MODULE_DESCRIPTION("FSL CAAM request backend");
819 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");