2 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/scatterlist.h>
30 #include <linux/highmem.h>
31 #include <linux/interrupt.h>
32 #include <linux/crypto.h>
34 #include <crypto/algapi.h>
35 #include <crypto/des.h>
37 #include <asm/kmap_types.h>
45 #define dprintk(f, a...) printk(f, ##a)
47 #define dprintk(f, a...) do {} while (0)
50 static atomic_t hifn_dev_number
;
52 #define ACRYPTO_OP_DECRYPT 0
53 #define ACRYPTO_OP_ENCRYPT 1
54 #define ACRYPTO_OP_HMAC 2
55 #define ACRYPTO_OP_RNG 3
57 #define ACRYPTO_MODE_ECB 0
58 #define ACRYPTO_MODE_CBC 1
59 #define ACRYPTO_MODE_CFB 2
60 #define ACRYPTO_MODE_OFB 3
62 #define ACRYPTO_TYPE_AES_128 0
63 #define ACRYPTO_TYPE_AES_192 1
64 #define ACRYPTO_TYPE_AES_256 2
65 #define ACRYPTO_TYPE_3DES 3
66 #define ACRYPTO_TYPE_DES 4
68 #define PCI_VENDOR_ID_HIFN 0x13A3
69 #define PCI_DEVICE_ID_HIFN_7955 0x0020
70 #define PCI_DEVICE_ID_HIFN_7956 0x001d
72 /* I/O region sizes */
74 #define HIFN_BAR0_SIZE 0x1000
75 #define HIFN_BAR1_SIZE 0x2000
76 #define HIFN_BAR2_SIZE 0x8000
80 #define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
81 #define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */
82 #define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */
83 #define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */
84 #define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */
85 #define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */
86 #define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */
87 #define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */
88 #define HIFN_CHIP_ID 0x98 /* Chip ID */
91 * Processing Unit Registers (offset from BASEREG0)
93 #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
94 #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
95 #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
96 #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
97 #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
98 #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
99 #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
100 #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
101 #define HIFN_0_SPACESIZE 0x20 /* Register space size */
103 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
104 #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
105 #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
106 #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
107 #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
108 #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
110 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
111 #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
112 #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
113 #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
114 #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
115 #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
116 #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
117 #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
118 #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
119 #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
120 #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
122 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
123 #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
124 #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
125 #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
126 #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
127 #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
128 #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
129 #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
130 #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
131 #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
132 #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
133 #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
134 #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
135 #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
136 #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
137 #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
138 #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
139 #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
140 #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
141 #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
142 #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
143 #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
144 #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
145 #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
147 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
148 #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
149 #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
150 #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
151 #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
152 #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
153 #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
154 #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
155 #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
156 #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
157 #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
159 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
160 #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
161 #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
162 #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
163 #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
164 #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
165 #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
166 #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
167 #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
168 #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
169 #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
170 #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
171 #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
172 #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
173 #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
174 #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
175 #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
176 #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
178 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
179 #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
180 #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
182 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
183 #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */
186 * DMA Interface Registers (offset from BASEREG1)
188 #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
189 #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
190 #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
191 #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
192 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
193 #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
194 #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
195 #define HIFN_1_PLL 0x4c /* 795x: PLL config */
196 #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
197 #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
198 #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
199 #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
200 #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
201 #define HIFN_1_REVID 0x98 /* Revision ID */
202 #define HIFN_1_UNLOCK_SECRET1 0xf4
203 #define HIFN_1_UNLOCK_SECRET2 0xfc
204 #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
205 #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
206 #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */
207 #define HIFN_1_PUB_OP 0x308 /* Public Operand */
208 #define HIFN_1_PUB_STATUS 0x30c /* Public Status */
209 #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
210 #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
211 #define HIFN_1_RNG_DATA 0x318 /* RNG data */
212 #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
213 #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
215 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
216 #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
217 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
218 #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
219 #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
220 #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
221 #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
222 #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
223 #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
224 #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
225 #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
226 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
227 #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
228 #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
229 #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
230 #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
231 #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
232 #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
233 #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
234 #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
235 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
236 #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
237 #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
238 #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
239 #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
240 #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
241 #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
242 #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
243 #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
244 #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
245 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
246 #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
247 #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
248 #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
249 #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
250 #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
251 #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
252 #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
253 #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
255 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
256 #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
257 #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
258 #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
259 #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
260 #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
261 #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
262 #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
263 #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
264 #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
265 #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
266 #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
267 #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
268 #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
269 #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
270 #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
271 #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
272 #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
273 #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
274 #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
275 #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
276 #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
277 #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
279 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
280 #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
281 #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
282 #define HIFN_DMACNFG_UNLOCK 0x00000800
283 #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
284 #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
285 #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
286 #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
287 #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
289 #define HIFN_PLL_7956 0x00001d18 /* 7956 PLL config value */
291 /* Public key reset register (HIFN_1_PUB_RESET) */
292 #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
294 /* Public base address register (HIFN_1_PUB_BASE) */
295 #define HIFN_PUBBASE_ADDR 0x00003fff /* base address */
297 /* Public operand length register (HIFN_1_PUB_OPLEN) */
298 #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */
299 #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */
300 #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */
301 #define HIFN_PUBOPLEN_EXP_S 7 /* exponent lenght shift */
302 #define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */
303 #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */
305 /* Public operation register (HIFN_1_PUB_OP) */
306 #define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */
307 #define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */
308 #define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */
309 #define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */
310 #define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */
311 #define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */
312 #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
313 #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
314 #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
315 #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
316 #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
317 #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
318 #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
319 #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
320 #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
321 #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
322 #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
323 #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
324 #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */
325 #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */
327 /* Public status register (HIFN_1_PUB_STATUS) */
328 #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
329 #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
331 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
332 #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
334 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
335 #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
337 #define HIFN_NAMESIZE 32
338 #define HIFN_MAX_RESULT_ORDER 5
340 #define HIFN_D_CMD_RSIZE 24*4
341 #define HIFN_D_SRC_RSIZE 80*4
342 #define HIFN_D_DST_RSIZE 80*4
343 #define HIFN_D_RES_RSIZE 24*4
345 #define HIFN_QUEUE_LENGTH HIFN_D_CMD_RSIZE-5
347 #define AES_MIN_KEY_SIZE 16
348 #define AES_MAX_KEY_SIZE 32
350 #define HIFN_DES_KEY_LENGTH 8
351 #define HIFN_3DES_KEY_LENGTH 24
352 #define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE
353 #define HIFN_IV_LENGTH 8
354 #define HIFN_AES_IV_LENGTH 16
355 #define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH
357 #define HIFN_MAC_KEY_LENGTH 64
358 #define HIFN_MD5_LENGTH 16
359 #define HIFN_SHA1_LENGTH 20
360 #define HIFN_MAC_TRUNC_LENGTH 12
362 #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)
363 #define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)
364 #define HIFN_USED_RESULT 12
373 struct hifn_desc cmdr
[HIFN_D_CMD_RSIZE
+1];
374 struct hifn_desc srcr
[HIFN_D_SRC_RSIZE
+1];
375 struct hifn_desc dstr
[HIFN_D_DST_RSIZE
+1];
376 struct hifn_desc resr
[HIFN_D_RES_RSIZE
+1];
378 u8 command_bufs
[HIFN_D_CMD_RSIZE
][HIFN_MAX_COMMAND
];
379 u8 result_bufs
[HIFN_D_CMD_RSIZE
][HIFN_MAX_RESULT
];
381 u64 test_src
, test_dst
;
384 * Our current positions for insertion and removal from the descriptor
387 volatile int cmdi
, srci
, dsti
, resi
;
388 volatile int cmdu
, srcu
, dstu
, resu
;
389 int cmdk
, srck
, dstk
, resk
;
392 #define HIFN_FLAG_CMD_BUSY (1<<0)
393 #define HIFN_FLAG_SRC_BUSY (1<<1)
394 #define HIFN_FLAG_DST_BUSY (1<<2)
395 #define HIFN_FLAG_RES_BUSY (1<<3)
396 #define HIFN_FLAG_OLD_KEY (1<<4)
398 #define HIFN_DEFAULT_ACTIVE_NUM 5
402 char name
[HIFN_NAMESIZE
];
406 struct pci_dev
*pdev
;
407 void __iomem
*bar
[3];
409 unsigned long result_mem
;
417 void *sa
[HIFN_D_RES_RSIZE
];
425 struct delayed_work work
;
427 unsigned long success
;
428 unsigned long prev_success
;
432 struct tasklet_struct tasklet
;
434 struct crypto_queue queue
;
435 struct list_head alg_list
;
438 #define HIFN_D_LENGTH 0x0000ffff
439 #define HIFN_D_NOINVALID 0x01000000
440 #define HIFN_D_MASKDONEIRQ 0x02000000
441 #define HIFN_D_DESTOVER 0x04000000
442 #define HIFN_D_OVER 0x08000000
443 #define HIFN_D_LAST 0x20000000
444 #define HIFN_D_JUMP 0x40000000
445 #define HIFN_D_VALID 0x80000000
447 struct hifn_base_command
450 volatile u16 session_num
;
451 volatile u16 total_source_count
;
452 volatile u16 total_dest_count
;
455 #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */
456 #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */
457 #define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */
458 #define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */
459 #define HIFN_BASE_CMD_DECODE 0x2000
460 #define HIFN_BASE_CMD_SRCLEN_M 0xc000
461 #define HIFN_BASE_CMD_SRCLEN_S 14
462 #define HIFN_BASE_CMD_DSTLEN_M 0x3000
463 #define HIFN_BASE_CMD_DSTLEN_S 12
464 #define HIFN_BASE_CMD_LENMASK_HI 0x30000
465 #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
468 * Structure to help build up the command data structure.
470 struct hifn_crypt_command
473 volatile u16 header_skip
;
474 volatile u16 source_count
;
475 volatile u16 reserved
;
478 #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
479 #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
480 #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
481 #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
482 #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
483 #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
484 #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
485 #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
486 #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
487 #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
488 #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
489 #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
490 #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
491 #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
492 #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
493 #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
494 #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
495 #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
496 #define HIFN_CRYPT_CMD_SRCLEN_S 14
499 * Structure to help build up the command data structure.
501 struct hifn_mac_command
504 volatile u16 header_skip
;
505 volatile u16 source_count
;
506 volatile u16 reserved
;
509 #define HIFN_MAC_CMD_ALG_MASK 0x0001
510 #define HIFN_MAC_CMD_ALG_SHA1 0x0000
511 #define HIFN_MAC_CMD_ALG_MD5 0x0001
512 #define HIFN_MAC_CMD_MODE_MASK 0x000c
513 #define HIFN_MAC_CMD_MODE_HMAC 0x0000
514 #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
515 #define HIFN_MAC_CMD_MODE_HASH 0x0008
516 #define HIFN_MAC_CMD_MODE_FULL 0x0004
517 #define HIFN_MAC_CMD_TRUNC 0x0010
518 #define HIFN_MAC_CMD_RESULT 0x0020
519 #define HIFN_MAC_CMD_APPEND 0x0040
520 #define HIFN_MAC_CMD_SRCLEN_M 0xc000
521 #define HIFN_MAC_CMD_SRCLEN_S 14
524 * MAC POS IPsec initiates authentication after encryption on encodes
525 * and before decryption on decodes.
527 #define HIFN_MAC_CMD_POS_IPSEC 0x0200
528 #define HIFN_MAC_CMD_NEW_KEY 0x0800
530 struct hifn_comp_command
533 volatile u16 header_skip
;
534 volatile u16 source_count
;
535 volatile u16 reserved
;
538 #define HIFN_COMP_CMD_SRCLEN_M 0xc000
539 #define HIFN_COMP_CMD_SRCLEN_S 14
540 #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */
541 #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */
542 #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */
543 #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */
544 #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */
545 #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */
546 #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */
547 #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */
549 struct hifn_base_result
552 volatile u16 session
;
553 volatile u16 src_cnt
; /* 15:0 of source count */
554 volatile u16 dst_cnt
; /* 15:0 of dest count */
557 #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */
558 #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */
559 #define HIFN_BASE_RES_SRCLEN_S 14
560 #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */
561 #define HIFN_BASE_RES_DSTLEN_S 12
563 struct hifn_comp_result
569 #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */
570 #define HIFN_COMP_RES_LCB_S 8
571 #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */
572 #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */
573 #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */
575 struct hifn_mac_result
578 volatile u16 reserved
;
579 /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
582 #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */
583 #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */
585 struct hifn_crypt_result
588 volatile u16 reserved
;
591 #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */
593 #ifndef HIFN_POLL_FREQUENCY
594 #define HIFN_POLL_FREQUENCY 0x1
597 #ifndef HIFN_POLL_SCALAR
598 #define HIFN_POLL_SCALAR 0x0
601 #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
602 #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
604 struct hifn_crypto_alg
606 struct list_head entry
;
607 struct crypto_alg alg
;
608 struct hifn_device
*dev
;
611 #define ASYNC_SCATTERLIST_CACHE 16
613 #define ASYNC_FLAGS_MISALIGNED (1<<0)
615 struct ablkcipher_walk
617 struct scatterlist cache
[ASYNC_SCATTERLIST_CACHE
];
624 u8 key
[HIFN_MAX_CRYPT_KEY_LENGTH
], *iv
;
625 struct hifn_device
*dev
;
626 unsigned int keysize
, ivsize
;
627 u8 op
, type
, mode
, unused
;
628 struct ablkcipher_walk walk
;
632 #define crypto_alg_to_hifn(alg) container_of(alg, struct hifn_crypto_alg, alg)
634 static inline u32
hifn_read_0(struct hifn_device
*dev
, u32 reg
)
638 ret
= readl((char *)(dev
->bar
[0]) + reg
);
643 static inline u32
hifn_read_1(struct hifn_device
*dev
, u32 reg
)
647 ret
= readl((char *)(dev
->bar
[1]) + reg
);
652 static inline void hifn_write_0(struct hifn_device
*dev
, u32 reg
, u32 val
)
654 writel(val
, (char *)(dev
->bar
[0]) + reg
);
657 static inline void hifn_write_1(struct hifn_device
*dev
, u32 reg
, u32 val
)
659 writel(val
, (char *)(dev
->bar
[1]) + reg
);
662 static void hifn_wait_puc(struct hifn_device
*dev
)
667 for (i
=10000; i
> 0; --i
) {
668 ret
= hifn_read_0(dev
, HIFN_0_PUCTRL
);
669 if (!(ret
& HIFN_PUCTRL_RESET
))
676 dprintk("%s: Failed to reset PUC unit.\n", dev
->name
);
679 static void hifn_reset_puc(struct hifn_device
*dev
)
681 hifn_write_0(dev
, HIFN_0_PUCTRL
, HIFN_PUCTRL_DMAENA
);
685 static void hifn_stop_device(struct hifn_device
*dev
)
687 hifn_write_1(dev
, HIFN_1_DMA_CSR
,
688 HIFN_DMACSR_D_CTRL_DIS
| HIFN_DMACSR_R_CTRL_DIS
|
689 HIFN_DMACSR_S_CTRL_DIS
| HIFN_DMACSR_C_CTRL_DIS
);
690 hifn_write_0(dev
, HIFN_0_PUIER
, 0);
691 hifn_write_1(dev
, HIFN_1_DMA_IER
, 0);
694 static void hifn_reset_dma(struct hifn_device
*dev
, int full
)
696 hifn_stop_device(dev
);
699 * Setting poll frequency and others to 0.
701 hifn_write_1(dev
, HIFN_1_DMA_CNFG
, HIFN_DMACNFG_MSTRESET
|
702 HIFN_DMACNFG_DMARESET
| HIFN_DMACNFG_MODE
);
709 hifn_write_1(dev
, HIFN_1_DMA_CNFG
, HIFN_DMACNFG_MODE
);
712 hifn_write_1(dev
, HIFN_1_DMA_CNFG
, HIFN_DMACNFG_MODE
|
713 HIFN_DMACNFG_MSTRESET
);
717 hifn_write_1(dev
, HIFN_1_DMA_CNFG
, HIFN_DMACNFG_MSTRESET
|
718 HIFN_DMACNFG_DMARESET
| HIFN_DMACNFG_MODE
);
723 static u32
hifn_next_signature(u_int32_t a
, u_int cnt
)
728 for (i
= 0; i
< cnt
; i
++) {
738 a
= (v
& 1) ^ (a
<< 1);
744 static struct pci2id
{
751 PCI_DEVICE_ID_HIFN_7955
,
752 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
753 0x00, 0x00, 0x00, 0x00, 0x00 }
757 PCI_DEVICE_ID_HIFN_7956
,
758 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
759 0x00, 0x00, 0x00, 0x00, 0x00 }
763 static int hifn_init_pubrng(struct hifn_device
*dev
)
767 hifn_write_1(dev
, HIFN_1_PUB_RESET
, hifn_read_1(dev
, HIFN_1_PUB_RESET
) |
770 for (i
=100; i
> 0; --i
) {
773 if ((hifn_read_1(dev
, HIFN_1_PUB_RESET
) & HIFN_PUBRST_RESET
) == 0)
778 dprintk("Chip %s: Failed to initialise public key engine.\n",
781 hifn_write_1(dev
, HIFN_1_PUB_IEN
, HIFN_PUBIEN_DONE
);
782 dev
->dmareg
|= HIFN_DMAIER_PUBDONE
;
783 hifn_write_1(dev
, HIFN_1_DMA_IER
, dev
->dmareg
);
785 dprintk("Chip %s: Public key engine has been sucessfully "
786 "initialised.\n", dev
->name
);
793 hifn_write_1(dev
, HIFN_1_RNG_CONFIG
,
794 hifn_read_1(dev
, HIFN_1_RNG_CONFIG
) | HIFN_RNGCFG_ENA
);
795 dprintk("Chip %s: RNG engine has been successfully initialised.\n",
801 static int hifn_enable_crypto(struct hifn_device
*dev
)
807 for (i
= 0; i
< sizeof(pci2id
)/sizeof(pci2id
[0]); i
++) {
808 if (pci2id
[i
].pci_vendor
== dev
->pdev
->vendor
&&
809 pci2id
[i
].pci_prod
== dev
->pdev
->device
) {
810 offtbl
= pci2id
[i
].card_id
;
815 if (offtbl
== NULL
) {
816 dprintk("Chip %s: Unknown card!\n", dev
->name
);
820 dmacfg
= hifn_read_1(dev
, HIFN_1_DMA_CNFG
);
822 hifn_write_1(dev
, HIFN_1_DMA_CNFG
,
823 HIFN_DMACNFG_UNLOCK
| HIFN_DMACNFG_MSTRESET
|
824 HIFN_DMACNFG_DMARESET
| HIFN_DMACNFG_MODE
);
826 addr
= hifn_read_1(dev
, HIFN_1_UNLOCK_SECRET1
);
828 hifn_write_1(dev
, HIFN_1_UNLOCK_SECRET2
, 0);
831 for (i
=0; i
<12; ++i
) {
832 addr
= hifn_next_signature(addr
, offtbl
[i
] + 0x101);
833 hifn_write_1(dev
, HIFN_1_UNLOCK_SECRET2
, addr
);
837 hifn_write_1(dev
, HIFN_1_DMA_CNFG
, dmacfg
);
839 dprintk("Chip %s: %s.\n", dev
->name
, pci_name(dev
->pdev
));
844 static void hifn_init_dma(struct hifn_device
*dev
)
846 struct hifn_dma
*dma
= (struct hifn_dma
*)dev
->desc_virt
;
847 u32 dptr
= dev
->desc_dma
;
850 for (i
=0; i
<HIFN_D_CMD_RSIZE
; ++i
)
851 dma
->cmdr
[i
].p
= __cpu_to_le32(dptr
+
852 offsetof(struct hifn_dma
, command_bufs
[i
][0]));
853 for (i
=0; i
<HIFN_D_RES_RSIZE
; ++i
)
854 dma
->resr
[i
].p
= __cpu_to_le32(dptr
+
855 offsetof(struct hifn_dma
, result_bufs
[i
][0]));
858 * Setup LAST descriptors.
860 dma
->cmdr
[HIFN_D_CMD_RSIZE
].p
= __cpu_to_le32(dptr
+
861 offsetof(struct hifn_dma
, cmdr
[0]));
862 dma
->srcr
[HIFN_D_SRC_RSIZE
].p
= __cpu_to_le32(dptr
+
863 offsetof(struct hifn_dma
, srcr
[0]));
864 dma
->dstr
[HIFN_D_DST_RSIZE
].p
= __cpu_to_le32(dptr
+
865 offsetof(struct hifn_dma
, dstr
[0]));
866 dma
->resr
[HIFN_D_RES_RSIZE
].p
= __cpu_to_le32(dptr
+
867 offsetof(struct hifn_dma
, resr
[0]));
869 dma
->cmdu
= dma
->srcu
= dma
->dstu
= dma
->resu
= 0;
870 dma
->cmdi
= dma
->srci
= dma
->dsti
= dma
->resi
= 0;
871 dma
->cmdk
= dma
->srck
= dma
->dstk
= dma
->resk
= 0;
874 static void hifn_init_registers(struct hifn_device
*dev
)
876 u32 dptr
= dev
->desc_dma
;
878 /* Initialization magic... */
879 hifn_write_0(dev
, HIFN_0_PUCTRL
, HIFN_PUCTRL_DMAENA
);
880 hifn_write_0(dev
, HIFN_0_FIFOCNFG
, HIFN_FIFOCNFG_THRESHOLD
);
881 hifn_write_0(dev
, HIFN_0_PUIER
, HIFN_PUIER_DSTOVER
);
883 /* write all 4 ring address registers */
884 hifn_write_1(dev
, HIFN_1_DMA_CRAR
, __cpu_to_le32(dptr
+
885 offsetof(struct hifn_dma
, cmdr
[0])));
886 hifn_write_1(dev
, HIFN_1_DMA_SRAR
, __cpu_to_le32(dptr
+
887 offsetof(struct hifn_dma
, srcr
[0])));
888 hifn_write_1(dev
, HIFN_1_DMA_DRAR
, __cpu_to_le32(dptr
+
889 offsetof(struct hifn_dma
, dstr
[0])));
890 hifn_write_1(dev
, HIFN_1_DMA_RRAR
, __cpu_to_le32(dptr
+
891 offsetof(struct hifn_dma
, resr
[0])));
895 hifn_write_1(dev
, HIFN_1_DMA_CSR
,
896 HIFN_DMACSR_D_CTRL_DIS
| HIFN_DMACSR_R_CTRL_DIS
|
897 HIFN_DMACSR_S_CTRL_DIS
| HIFN_DMACSR_C_CTRL_DIS
|
898 HIFN_DMACSR_D_ABORT
| HIFN_DMACSR_D_DONE
| HIFN_DMACSR_D_LAST
|
899 HIFN_DMACSR_D_WAIT
| HIFN_DMACSR_D_OVER
|
900 HIFN_DMACSR_R_ABORT
| HIFN_DMACSR_R_DONE
| HIFN_DMACSR_R_LAST
|
901 HIFN_DMACSR_R_WAIT
| HIFN_DMACSR_R_OVER
|
902 HIFN_DMACSR_S_ABORT
| HIFN_DMACSR_S_DONE
| HIFN_DMACSR_S_LAST
|
904 HIFN_DMACSR_C_ABORT
| HIFN_DMACSR_C_DONE
| HIFN_DMACSR_C_LAST
|
907 HIFN_DMACSR_PUBDONE
);
909 hifn_write_1(dev
, HIFN_1_DMA_CSR
,
910 HIFN_DMACSR_C_CTRL_ENA
| HIFN_DMACSR_S_CTRL_ENA
|
911 HIFN_DMACSR_D_CTRL_ENA
| HIFN_DMACSR_R_CTRL_ENA
|
912 HIFN_DMACSR_D_ABORT
| HIFN_DMACSR_D_DONE
| HIFN_DMACSR_D_LAST
|
913 HIFN_DMACSR_D_WAIT
| HIFN_DMACSR_D_OVER
|
914 HIFN_DMACSR_R_ABORT
| HIFN_DMACSR_R_DONE
| HIFN_DMACSR_R_LAST
|
915 HIFN_DMACSR_R_WAIT
| HIFN_DMACSR_R_OVER
|
916 HIFN_DMACSR_S_ABORT
| HIFN_DMACSR_S_DONE
| HIFN_DMACSR_S_LAST
|
918 HIFN_DMACSR_C_ABORT
| HIFN_DMACSR_C_DONE
| HIFN_DMACSR_C_LAST
|
921 HIFN_DMACSR_PUBDONE
);
923 hifn_read_1(dev
, HIFN_1_DMA_CSR
);
925 dev
->dmareg
|= HIFN_DMAIER_R_DONE
| HIFN_DMAIER_C_ABORT
|
926 HIFN_DMAIER_D_OVER
| HIFN_DMAIER_R_OVER
|
927 HIFN_DMAIER_S_ABORT
| HIFN_DMAIER_D_ABORT
| HIFN_DMAIER_R_ABORT
|
929 dev
->dmareg
&= ~HIFN_DMAIER_C_WAIT
;
931 hifn_write_1(dev
, HIFN_1_DMA_IER
, dev
->dmareg
);
932 hifn_read_1(dev
, HIFN_1_DMA_IER
);
934 hifn_write_0(dev
, HIFN_0_PUCNFG
, HIFN_PUCNFG_ENCCNFG
|
935 HIFN_PUCNFG_DRFR_128
| HIFN_PUCNFG_TCALLPHASES
|
936 HIFN_PUCNFG_TCDRVTOTEM
| HIFN_PUCNFG_BUS32
|
939 hifn_write_0(dev
, HIFN_0_PUCNFG
, 0x10342);
941 hifn_write_1(dev
, HIFN_1_PLL
, HIFN_PLL_7956
);
943 hifn_write_0(dev
, HIFN_0_PUISR
, HIFN_PUISR_DSTOVER
);
944 hifn_write_1(dev
, HIFN_1_DMA_CNFG
, HIFN_DMACNFG_MSTRESET
|
945 HIFN_DMACNFG_DMARESET
| HIFN_DMACNFG_MODE
| HIFN_DMACNFG_LAST
|
946 ((HIFN_POLL_FREQUENCY
<< 16 ) & HIFN_DMACNFG_POLLFREQ
) |
947 ((HIFN_POLL_SCALAR
<< 8) & HIFN_DMACNFG_POLLINVAL
));
950 static int hifn_setup_base_command(struct hifn_device
*dev
, u8
*buf
,
951 unsigned dlen
, unsigned slen
, u16 mask
, u8 snum
)
953 struct hifn_base_command
*base_cmd
;
956 base_cmd
= (struct hifn_base_command
*)buf_pos
;
957 base_cmd
->masks
= __cpu_to_le16(mask
);
958 base_cmd
->total_source_count
=
959 __cpu_to_le16(slen
& HIFN_BASE_CMD_LENMASK_LO
);
960 base_cmd
->total_dest_count
=
961 __cpu_to_le16(dlen
& HIFN_BASE_CMD_LENMASK_LO
);
965 base_cmd
->session_num
= __cpu_to_le16(snum
|
966 ((slen
<< HIFN_BASE_CMD_SRCLEN_S
) & HIFN_BASE_CMD_SRCLEN_M
) |
967 ((dlen
<< HIFN_BASE_CMD_DSTLEN_S
) & HIFN_BASE_CMD_DSTLEN_M
));
969 return sizeof(struct hifn_base_command
);
972 static int hifn_setup_crypto_command(struct hifn_device
*dev
,
973 u8
*buf
, unsigned dlen
, unsigned slen
,
974 u8
*key
, int keylen
, u8
*iv
, int ivsize
, u16 mode
)
976 struct hifn_dma
*dma
= (struct hifn_dma
*)dev
->desc_virt
;
977 struct hifn_crypt_command
*cry_cmd
;
981 cry_cmd
= (struct hifn_crypt_command
*)buf_pos
;
983 cry_cmd
->source_count
= __cpu_to_le16(dlen
& 0xffff);
985 cry_cmd
->masks
= __cpu_to_le16(mode
|
986 ((dlen
<< HIFN_CRYPT_CMD_SRCLEN_S
) &
987 HIFN_CRYPT_CMD_SRCLEN_M
));
988 cry_cmd
->header_skip
= 0;
989 cry_cmd
->reserved
= 0;
991 buf_pos
+= sizeof(struct hifn_crypt_command
);
995 dev
->dmareg
|= HIFN_DMAIER_C_WAIT
;
996 hifn_write_1(dev
, HIFN_1_DMA_IER
, dev
->dmareg
);
1000 memcpy(buf_pos
, key
, keylen
);
1004 memcpy(buf_pos
, iv
, ivsize
);
1008 cmd_len
= buf_pos
- buf
;
1013 static int hifn_setup_src_desc(struct hifn_device
*dev
, struct page
*page
,
1014 unsigned int offset
, unsigned int size
)
1016 struct hifn_dma
*dma
= (struct hifn_dma
*)dev
->desc_virt
;
1020 addr
= pci_map_page(dev
->pdev
, page
, offset
, size
, PCI_DMA_TODEVICE
);
1024 dma
->srcr
[idx
].p
= __cpu_to_le32(addr
);
1025 dma
->srcr
[idx
].l
= __cpu_to_le32(size
) | HIFN_D_VALID
|
1026 HIFN_D_MASKDONEIRQ
| HIFN_D_NOINVALID
| HIFN_D_LAST
;
1028 if (++idx
== HIFN_D_SRC_RSIZE
) {
1029 dma
->srcr
[idx
].l
= __cpu_to_le32(HIFN_D_VALID
|
1031 HIFN_D_MASKDONEIRQ
| HIFN_D_LAST
);
1038 if (!(dev
->flags
& HIFN_FLAG_SRC_BUSY
)) {
1039 hifn_write_1(dev
, HIFN_1_DMA_CSR
, HIFN_DMACSR_S_CTRL_ENA
);
1040 dev
->flags
|= HIFN_FLAG_SRC_BUSY
;
1046 static void hifn_setup_res_desc(struct hifn_device
*dev
)
1048 struct hifn_dma
*dma
= (struct hifn_dma
*)dev
->desc_virt
;
1050 dma
->resr
[dma
->resi
].l
= __cpu_to_le32(HIFN_USED_RESULT
|
1051 HIFN_D_VALID
| HIFN_D_LAST
);
1053 * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
1054 * HIFN_D_LAST | HIFN_D_NOINVALID);
1057 if (++dma
->resi
== HIFN_D_RES_RSIZE
) {
1058 dma
->resr
[HIFN_D_RES_RSIZE
].l
= __cpu_to_le32(HIFN_D_VALID
|
1059 HIFN_D_JUMP
| HIFN_D_MASKDONEIRQ
| HIFN_D_LAST
);
1065 if (!(dev
->flags
& HIFN_FLAG_RES_BUSY
)) {
1066 hifn_write_1(dev
, HIFN_1_DMA_CSR
, HIFN_DMACSR_R_CTRL_ENA
);
1067 dev
->flags
|= HIFN_FLAG_RES_BUSY
;
1071 static void hifn_setup_dst_desc(struct hifn_device
*dev
, struct page
*page
,
1072 unsigned offset
, unsigned size
)
1074 struct hifn_dma
*dma
= (struct hifn_dma
*)dev
->desc_virt
;
1078 addr
= pci_map_page(dev
->pdev
, page
, offset
, size
, PCI_DMA_FROMDEVICE
);
1081 dma
->dstr
[idx
].p
= __cpu_to_le32(addr
);
1082 dma
->dstr
[idx
].l
= __cpu_to_le32(size
| HIFN_D_VALID
|
1083 HIFN_D_MASKDONEIRQ
| HIFN_D_NOINVALID
| HIFN_D_LAST
);
1085 if (++idx
== HIFN_D_DST_RSIZE
) {
1086 dma
->dstr
[idx
].l
= __cpu_to_le32(HIFN_D_VALID
|
1087 HIFN_D_JUMP
| HIFN_D_MASKDONEIRQ
|
1088 HIFN_D_LAST
| HIFN_D_NOINVALID
);
1094 if (!(dev
->flags
& HIFN_FLAG_DST_BUSY
)) {
1095 hifn_write_1(dev
, HIFN_1_DMA_CSR
, HIFN_DMACSR_D_CTRL_ENA
);
1096 dev
->flags
|= HIFN_FLAG_DST_BUSY
;
1100 static int hifn_setup_dma(struct hifn_device
*dev
, struct page
*spage
, unsigned int soff
,
1101 struct page
*dpage
, unsigned int doff
, unsigned int nbytes
, void *priv
,
1102 struct hifn_context
*ctx
)
1104 struct hifn_dma
*dma
= (struct hifn_dma
*)dev
->desc_virt
;
1105 int cmd_len
, sa_idx
;
1109 dprintk("%s: spage: %p, soffset: %u, dpage: %p, doffset: %u, nbytes: %u, priv: %p, ctx: %p.\n",
1110 dev
->name
, spage
, soff
, dpage
, doff
, nbytes
, priv
, ctx
);
1114 hifn_setup_src_desc(dev
, spage
, soff
, nbytes
);
1116 buf_pos
= buf
= dma
->command_bufs
[dma
->cmdi
];
1120 case ACRYPTO_OP_DECRYPT
:
1121 mask
= HIFN_BASE_CMD_CRYPT
| HIFN_BASE_CMD_DECODE
;
1123 case ACRYPTO_OP_ENCRYPT
:
1124 mask
= HIFN_BASE_CMD_CRYPT
;
1126 case ACRYPTO_OP_HMAC
:
1127 mask
= HIFN_BASE_CMD_MAC
;
1133 buf_pos
+= hifn_setup_base_command(dev
, buf_pos
, nbytes
,
1134 nbytes
, mask
, dev
->snum
);
1136 if (ctx
->op
== ACRYPTO_OP_ENCRYPT
|| ctx
->op
== ACRYPTO_OP_DECRYPT
) {
1140 md
|= HIFN_CRYPT_CMD_NEW_KEY
;
1141 if (ctx
->iv
&& ctx
->mode
!= ACRYPTO_MODE_ECB
)
1142 md
|= HIFN_CRYPT_CMD_NEW_IV
;
1144 switch (ctx
->mode
) {
1145 case ACRYPTO_MODE_ECB
:
1146 md
|= HIFN_CRYPT_CMD_MODE_ECB
;
1148 case ACRYPTO_MODE_CBC
:
1149 md
|= HIFN_CRYPT_CMD_MODE_CBC
;
1151 case ACRYPTO_MODE_CFB
:
1152 md
|= HIFN_CRYPT_CMD_MODE_CFB
;
1154 case ACRYPTO_MODE_OFB
:
1155 md
|= HIFN_CRYPT_CMD_MODE_OFB
;
1161 switch (ctx
->type
) {
1162 case ACRYPTO_TYPE_AES_128
:
1163 if (ctx
->keysize
!= 16)
1165 md
|= HIFN_CRYPT_CMD_KSZ_128
|
1166 HIFN_CRYPT_CMD_ALG_AES
;
1168 case ACRYPTO_TYPE_AES_192
:
1169 if (ctx
->keysize
!= 24)
1171 md
|= HIFN_CRYPT_CMD_KSZ_192
|
1172 HIFN_CRYPT_CMD_ALG_AES
;
1174 case ACRYPTO_TYPE_AES_256
:
1175 if (ctx
->keysize
!= 32)
1177 md
|= HIFN_CRYPT_CMD_KSZ_256
|
1178 HIFN_CRYPT_CMD_ALG_AES
;
1180 case ACRYPTO_TYPE_3DES
:
1181 if (ctx
->keysize
!= 24)
1183 md
|= HIFN_CRYPT_CMD_ALG_3DES
;
1185 case ACRYPTO_TYPE_DES
:
1186 if (ctx
->keysize
!= 8)
1188 md
|= HIFN_CRYPT_CMD_ALG_DES
;
1194 buf_pos
+= hifn_setup_crypto_command(dev
, buf_pos
,
1195 nbytes
, nbytes
, ctx
->key
, ctx
->keysize
,
1196 ctx
->iv
, ctx
->ivsize
, md
);
1199 dev
->sa
[sa_idx
] = priv
;
1201 cmd_len
= buf_pos
- buf
;
1202 dma
->cmdr
[dma
->cmdi
].l
= __cpu_to_le32(cmd_len
| HIFN_D_VALID
|
1203 HIFN_D_LAST
| HIFN_D_MASKDONEIRQ
);
1205 if (++dma
->cmdi
== HIFN_D_CMD_RSIZE
) {
1206 dma
->cmdr
[dma
->cmdi
].l
= __cpu_to_le32(HIFN_MAX_COMMAND
|
1207 HIFN_D_VALID
| HIFN_D_LAST
|
1208 HIFN_D_MASKDONEIRQ
| HIFN_D_JUMP
);
1211 dma
->cmdr
[dma
->cmdi
-1].l
|= __cpu_to_le32(HIFN_D_VALID
);
1213 if (!(dev
->flags
& HIFN_FLAG_CMD_BUSY
)) {
1214 hifn_write_1(dev
, HIFN_1_DMA_CSR
, HIFN_DMACSR_C_CTRL_ENA
);
1215 dev
->flags
|= HIFN_FLAG_CMD_BUSY
;
1218 hifn_setup_dst_desc(dev
, dpage
, doff
, nbytes
);
1219 hifn_setup_res_desc(dev
);
1227 static int ablkcipher_walk_init(struct ablkcipher_walk
*w
,
1228 int num
, gfp_t gfp_flags
)
1232 num
= min(ASYNC_SCATTERLIST_CACHE
, num
);
1233 sg_init_table(w
->cache
, num
);
1236 for (i
=0; i
<num
; ++i
) {
1237 struct page
*page
= alloc_page(gfp_flags
);
1238 struct scatterlist
*s
;
1245 sg_set_page(s
, page
, PAGE_SIZE
, 0);
1252 static void ablkcipher_walk_exit(struct ablkcipher_walk
*w
)
1256 for (i
=0; i
<w
->num
; ++i
) {
1257 struct scatterlist
*s
= &w
->cache
[i
];
1259 __free_page(sg_page(s
));
1267 static int ablkcipher_add(void *daddr
, unsigned int *drestp
, struct scatterlist
*src
,
1268 unsigned int size
, unsigned int *nbytesp
)
1270 unsigned int copy
, drest
= *drestp
, nbytes
= *nbytesp
;
1274 if (drest
< size
|| size
> nbytes
)
1278 copy
= min(drest
, src
->length
);
1280 saddr
= kmap_atomic(sg_page(src
), KM_SOFTIRQ1
);
1281 memcpy(daddr
, saddr
+ src
->offset
, copy
);
1282 kunmap_atomic(saddr
, KM_SOFTIRQ1
);
1289 dprintk("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
1290 __func__
, copy
, size
, drest
, nbytes
);
1302 static int ablkcipher_walk(struct ablkcipher_request
*req
,
1303 struct ablkcipher_walk
*w
)
1305 unsigned blocksize
=
1306 crypto_ablkcipher_blocksize(crypto_ablkcipher_reqtfm(req
));
1307 unsigned alignmask
=
1308 crypto_ablkcipher_alignmask(crypto_ablkcipher_reqtfm(req
));
1309 struct scatterlist
*src
, *dst
, *t
;
1311 unsigned int nbytes
= req
->nbytes
, offset
, copy
, diff
;
1317 if (idx
>= w
->num
&& (w
->flags
& ASYNC_FLAGS_MISALIGNED
))
1320 src
= &req
->src
[idx
];
1321 dst
= &req
->dst
[idx
];
1323 dprintk("\n%s: slen: %u, dlen: %u, soff: %u, doff: %u, offset: %u, "
1324 "blocksize: %u, nbytes: %u.\n",
1325 __func__
, src
->length
, dst
->length
, src
->offset
,
1326 dst
->offset
, offset
, blocksize
, nbytes
);
1328 if (src
->length
& (blocksize
- 1) ||
1329 src
->offset
& (alignmask
- 1) ||
1330 dst
->length
& (blocksize
- 1) ||
1331 dst
->offset
& (alignmask
- 1) ||
1333 unsigned slen
= src
->length
- offset
;
1334 unsigned dlen
= PAGE_SIZE
;
1338 daddr
= kmap_atomic(sg_page(t
), KM_SOFTIRQ0
);
1339 err
= ablkcipher_add(daddr
, &dlen
, src
, slen
, &nbytes
);
1345 copy
= slen
& ~(blocksize
- 1);
1346 diff
= slen
& (blocksize
- 1);
1348 if (dlen
< nbytes
) {
1350 * Destination page does not have enough space
1351 * to put there additional blocksized chunk,
1352 * so we mark that page as containing only
1353 * blocksize aligned chunks:
1354 * t->length = (slen & ~(blocksize - 1));
1355 * and increase number of bytes to be processed
1362 * Temporary of course...
1363 * Kick author if you will catch this one.
1365 printk(KERN_ERR
"%s: dlen: %u, nbytes: %u,"
1366 "slen: %u, offset: %u.\n",
1367 __func__
, dlen
, nbytes
, slen
, offset
);
1368 printk(KERN_ERR
"%s: please contact author to fix this "
1369 "issue, generally you should not catch "
1370 "this path under any condition but who "
1371 "knows how did you use crypto code.\n"
1372 "Thank you.\n", __func__
);
1375 copy
+= diff
+ nbytes
;
1377 src
= &req
->src
[idx
];
1379 err
= ablkcipher_add(daddr
+ slen
, &dlen
, src
, nbytes
, &nbytes
);
1389 kunmap_atomic(daddr
, KM_SOFTIRQ0
);
1391 nbytes
-= src
->length
;
1401 kunmap_atomic(daddr
, KM_SOFTIRQ0
);
1405 static int hifn_setup_session(struct ablkcipher_request
*req
)
1407 struct hifn_context
*ctx
= crypto_tfm_ctx(req
->base
.tfm
);
1408 struct hifn_device
*dev
= ctx
->dev
;
1409 struct page
*spage
, *dpage
;
1410 unsigned long soff
, doff
, flags
;
1411 unsigned int nbytes
= req
->nbytes
, idx
= 0, len
;
1412 int err
= -EINVAL
, sg_num
;
1413 struct scatterlist
*src
, *dst
, *t
;
1414 unsigned blocksize
=
1415 crypto_ablkcipher_blocksize(crypto_ablkcipher_reqtfm(req
));
1416 unsigned alignmask
=
1417 crypto_ablkcipher_alignmask(crypto_ablkcipher_reqtfm(req
));
1419 if (ctx
->iv
&& !ctx
->ivsize
&& ctx
->mode
!= ACRYPTO_MODE_ECB
)
1422 ctx
->walk
.flags
= 0;
1425 src
= &req
->src
[idx
];
1426 dst
= &req
->dst
[idx
];
1428 if (src
->length
& (blocksize
- 1) ||
1429 src
->offset
& (alignmask
- 1) ||
1430 dst
->length
& (blocksize
- 1) ||
1431 dst
->offset
& (alignmask
- 1)) {
1432 ctx
->walk
.flags
|= ASYNC_FLAGS_MISALIGNED
;
1435 nbytes
-= src
->length
;
1439 if (ctx
->walk
.flags
& ASYNC_FLAGS_MISALIGNED
) {
1440 err
= ablkcipher_walk_init(&ctx
->walk
, idx
, GFP_ATOMIC
);
1445 nbytes
= req
->nbytes
;
1448 sg_num
= ablkcipher_walk(req
, &ctx
->walk
);
1450 atomic_set(&ctx
->sg_num
, sg_num
);
1452 spin_lock_irqsave(&dev
->lock
, flags
);
1453 if (dev
->started
+ sg_num
> HIFN_QUEUE_LENGTH
) {
1459 dev
->started
+= sg_num
;
1462 src
= &req
->src
[idx
];
1463 dst
= &req
->dst
[idx
];
1464 t
= &ctx
->walk
.cache
[idx
];
1467 spage
= dpage
= sg_page(t
);
1471 spage
= sg_page(src
);
1474 dpage
= sg_page(dst
);
1482 err
= hifn_setup_dma(dev
, spage
, soff
, dpage
, doff
, nbytes
,
1490 dev
->active
= HIFN_DEFAULT_ACTIVE_NUM
;
1491 spin_unlock_irqrestore(&dev
->lock
, flags
);
1496 spin_unlock_irqrestore(&dev
->lock
, flags
);
1498 if (err
&& printk_ratelimit())
1499 dprintk("%s: iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
1500 "type: %u, err: %d.\n",
1501 dev
->name
, ctx
->iv
, ctx
->ivsize
,
1502 ctx
->key
, ctx
->keysize
,
1503 ctx
->mode
, ctx
->op
, ctx
->type
, err
);
1508 static int hifn_test(struct hifn_device
*dev
, int encdec
, u8 snum
)
1512 struct hifn_context ctx
;
1513 u8 fips_aes_ecb_from_zero
[16] = {
1514 0x66, 0xE9, 0x4B, 0xD4,
1515 0xEF, 0x8A, 0x2C, 0x3B,
1516 0x88, 0x4C, 0xFA, 0x59,
1517 0xCA, 0x34, 0x2B, 0x2E};
1519 memset(src
, 0, sizeof(src
));
1520 memset(ctx
.key
, 0, sizeof(ctx
.key
));
1526 ctx
.op
= (encdec
)?ACRYPTO_OP_ENCRYPT
:ACRYPTO_OP_DECRYPT
;
1527 ctx
.mode
= ACRYPTO_MODE_ECB
;
1528 ctx
.type
= ACRYPTO_TYPE_AES_128
;
1529 atomic_set(&ctx
.sg_num
, 1);
1531 err
= hifn_setup_dma(dev
,
1532 virt_to_page(src
), offset_in_page(src
),
1533 virt_to_page(src
), offset_in_page(src
),
1534 sizeof(src
), NULL
, &ctx
);
1540 dprintk("%s: decoded: ", dev
->name
);
1541 for (n
=0; n
<sizeof(src
); ++n
)
1542 dprintk("%02x ", src
[n
]);
1544 dprintk("%s: FIPS : ", dev
->name
);
1545 for (n
=0; n
<sizeof(fips_aes_ecb_from_zero
); ++n
)
1546 dprintk("%02x ", fips_aes_ecb_from_zero
[n
]);
1549 if (!memcmp(src
, fips_aes_ecb_from_zero
, sizeof(fips_aes_ecb_from_zero
))) {
1550 printk(KERN_INFO
"%s: AES 128 ECB test has been successfully "
1551 "passed.\n", dev
->name
);
1556 printk(KERN_INFO
"%s: AES 128 ECB test has been failed.\n", dev
->name
);
1560 static int hifn_start_device(struct hifn_device
*dev
)
1564 hifn_reset_dma(dev
, 1);
1566 err
= hifn_enable_crypto(dev
);
1570 hifn_reset_puc(dev
);
1574 hifn_init_registers(dev
);
1576 hifn_init_pubrng(dev
);
1581 static int ablkcipher_get(void *saddr
, unsigned int *srestp
, unsigned int offset
,
1582 struct scatterlist
*dst
, unsigned int size
, unsigned int *nbytesp
)
1584 unsigned int srest
= *srestp
, nbytes
= *nbytesp
, copy
;
1588 if (srest
< size
|| size
> nbytes
)
1593 copy
= min(dst
->length
, srest
);
1595 daddr
= kmap_atomic(sg_page(dst
), KM_IRQ0
);
1596 memcpy(daddr
+ dst
->offset
+ offset
, saddr
, copy
);
1597 kunmap_atomic(daddr
, KM_IRQ0
);
1605 dprintk("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
1606 __func__
, copy
, size
, srest
, nbytes
);
1618 static void hifn_process_ready(struct ablkcipher_request
*req
, int error
)
1620 struct hifn_context
*ctx
= crypto_tfm_ctx(req
->base
.tfm
);
1621 struct hifn_device
*dev
;
1623 dprintk("%s: req: %p, ctx: %p.\n", __func__
, req
, ctx
);
1626 dprintk("%s: req: %p, started: %d, sg_num: %d.\n",
1627 __func__
, req
, dev
->started
, atomic_read(&ctx
->sg_num
));
1629 if (--dev
->started
< 0)
1632 if (atomic_dec_and_test(&ctx
->sg_num
)) {
1633 unsigned int nbytes
= req
->nbytes
;
1635 struct scatterlist
*dst
, *t
;
1638 if (ctx
->walk
.flags
& ASYNC_FLAGS_MISALIGNED
) {
1640 t
= &ctx
->walk
.cache
[idx
];
1641 dst
= &req
->dst
[idx
];
1643 dprintk("\n%s: sg_page(t): %p, t->length: %u, "
1644 "sg_page(dst): %p, dst->length: %u, "
1646 __func__
, sg_page(t
), t
->length
,
1647 sg_page(dst
), dst
->length
, nbytes
);
1650 nbytes
-= dst
->length
;
1655 saddr
= kmap_atomic(sg_page(t
), KM_IRQ1
);
1657 err
= ablkcipher_get(saddr
, &t
->length
, t
->offset
,
1658 dst
, nbytes
, &nbytes
);
1660 kunmap_atomic(saddr
, KM_IRQ1
);
1665 kunmap_atomic(saddr
, KM_IRQ1
);
1668 ablkcipher_walk_exit(&ctx
->walk
);
1671 req
->base
.complete(&req
->base
, error
);
1675 static void hifn_check_for_completion(struct hifn_device
*dev
, int error
)
1678 struct hifn_dma
*dma
= (struct hifn_dma
*)dev
->desc_virt
;
1680 for (i
=0; i
<HIFN_D_RES_RSIZE
; ++i
) {
1681 struct hifn_desc
*d
= &dma
->resr
[i
];
1683 if (!(d
->l
& __cpu_to_le32(HIFN_D_VALID
)) && dev
->sa
[i
]) {
1686 hifn_process_ready(dev
->sa
[i
], error
);
1690 if (d
->l
& __cpu_to_le32(HIFN_D_DESTOVER
| HIFN_D_OVER
))
1691 if (printk_ratelimit())
1692 printk("%s: overflow detected [d: %u, o: %u] "
1693 "at %d resr: l: %08x, p: %08x.\n",
1695 !!(d
->l
& __cpu_to_le32(HIFN_D_DESTOVER
)),
1696 !!(d
->l
& __cpu_to_le32(HIFN_D_OVER
)),
1701 static void hifn_clear_rings(struct hifn_device
*dev
)
1703 struct hifn_dma
*dma
= (struct hifn_dma
*)dev
->desc_virt
;
1706 dprintk("%s: ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1707 "k: %d.%d.%d.%d.\n",
1709 dma
->cmdi
, dma
->srci
, dma
->dsti
, dma
->resi
,
1710 dma
->cmdu
, dma
->srcu
, dma
->dstu
, dma
->resu
,
1711 dma
->cmdk
, dma
->srck
, dma
->dstk
, dma
->resk
);
1713 i
= dma
->resk
; u
= dma
->resu
;
1715 if (dma
->resr
[i
].l
& __cpu_to_le32(HIFN_D_VALID
))
1718 if (i
!= HIFN_D_RES_RSIZE
)
1721 if (++i
== (HIFN_D_RES_RSIZE
+ 1))
1724 dma
->resk
= i
; dma
->resu
= u
;
1726 i
= dma
->srck
; u
= dma
->srcu
;
1728 if (i
== HIFN_D_SRC_RSIZE
)
1730 if (dma
->srcr
[i
].l
& __cpu_to_le32(HIFN_D_VALID
))
1734 dma
->srck
= i
; dma
->srcu
= u
;
1736 i
= dma
->cmdk
; u
= dma
->cmdu
;
1738 if (dma
->cmdr
[i
].l
& __cpu_to_le32(HIFN_D_VALID
))
1740 if (i
!= HIFN_D_CMD_RSIZE
)
1742 if (++i
== (HIFN_D_CMD_RSIZE
+ 1))
1745 dma
->cmdk
= i
; dma
->cmdu
= u
;
1747 i
= dma
->dstk
; u
= dma
->dstu
;
1749 if (i
== HIFN_D_DST_RSIZE
)
1751 if (dma
->dstr
[i
].l
& __cpu_to_le32(HIFN_D_VALID
))
1755 dma
->dstk
= i
; dma
->dstu
= u
;
1757 dprintk("%s: ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1758 "k: %d.%d.%d.%d.\n",
1760 dma
->cmdi
, dma
->srci
, dma
->dsti
, dma
->resi
,
1761 dma
->cmdu
, dma
->srcu
, dma
->dstu
, dma
->resu
,
1762 dma
->cmdk
, dma
->srck
, dma
->dstk
, dma
->resk
);
1765 static void hifn_work(struct work_struct
*work
)
1767 struct delayed_work
*dw
= container_of(work
, struct delayed_work
, work
);
1768 struct hifn_device
*dev
= container_of(dw
, struct hifn_device
, work
);
1769 unsigned long flags
;
1773 spin_lock_irqsave(&dev
->lock
, flags
);
1774 if (dev
->active
== 0) {
1775 struct hifn_dma
*dma
= (struct hifn_dma
*)dev
->desc_virt
;
1777 if (dma
->cmdu
== 0 && (dev
->flags
& HIFN_FLAG_CMD_BUSY
)) {
1778 dev
->flags
&= ~HIFN_FLAG_CMD_BUSY
;
1779 r
|= HIFN_DMACSR_C_CTRL_DIS
;
1781 if (dma
->srcu
== 0 && (dev
->flags
& HIFN_FLAG_SRC_BUSY
)) {
1782 dev
->flags
&= ~HIFN_FLAG_SRC_BUSY
;
1783 r
|= HIFN_DMACSR_S_CTRL_DIS
;
1785 if (dma
->dstu
== 0 && (dev
->flags
& HIFN_FLAG_DST_BUSY
)) {
1786 dev
->flags
&= ~HIFN_FLAG_DST_BUSY
;
1787 r
|= HIFN_DMACSR_D_CTRL_DIS
;
1789 if (dma
->resu
== 0 && (dev
->flags
& HIFN_FLAG_RES_BUSY
)) {
1790 dev
->flags
&= ~HIFN_FLAG_RES_BUSY
;
1791 r
|= HIFN_DMACSR_R_CTRL_DIS
;
1794 hifn_write_1(dev
, HIFN_1_DMA_CSR
, r
);
1798 if (dev
->prev_success
== dev
->success
&& dev
->started
)
1800 dev
->prev_success
= dev
->success
;
1801 spin_unlock_irqrestore(&dev
->lock
, flags
);
1804 dprintk("%s: r: %08x, active: %d, started: %d, "
1805 "success: %lu: reset: %d.\n",
1806 dev
->name
, r
, dev
->active
, dev
->started
,
1807 dev
->success
, reset
);
1809 if (++dev
->reset
>= 5) {
1810 dprintk("%s: really hard reset.\n", dev
->name
);
1811 hifn_reset_dma(dev
, 1);
1812 hifn_stop_device(dev
);
1813 hifn_start_device(dev
);
1817 spin_lock_irqsave(&dev
->lock
, flags
);
1818 hifn_check_for_completion(dev
, -EBUSY
);
1819 hifn_clear_rings(dev
);
1821 spin_unlock_irqrestore(&dev
->lock
, flags
);
1824 schedule_delayed_work(&dev
->work
, HZ
);
1827 static irqreturn_t
hifn_interrupt(int irq
, void *data
)
1829 struct hifn_device
*dev
= (struct hifn_device
*)data
;
1830 struct hifn_dma
*dma
= (struct hifn_dma
*)dev
->desc_virt
;
1831 u32 dmacsr
, restart
;
1833 dmacsr
= hifn_read_1(dev
, HIFN_1_DMA_CSR
);
1835 dprintk("%s: 1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
1836 "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
1837 dev
->name
, dmacsr
, dev
->dmareg
, dmacsr
& dev
->dmareg
, dma
->cmdi
,
1838 dma
->cmdu
, dma
->srcu
, dma
->dstu
, dma
->resu
,
1839 dma
->cmdi
, dma
->srci
, dma
->dsti
, dma
->resi
);
1841 if ((dmacsr
& dev
->dmareg
) == 0)
1844 hifn_write_1(dev
, HIFN_1_DMA_CSR
, dmacsr
& dev
->dmareg
);
1846 if (dmacsr
& HIFN_DMACSR_ENGINE
)
1847 hifn_write_0(dev
, HIFN_0_PUISR
, hifn_read_0(dev
, HIFN_0_PUISR
));
1848 if (dmacsr
& HIFN_DMACSR_PUBDONE
)
1849 hifn_write_1(dev
, HIFN_1_PUB_STATUS
,
1850 hifn_read_1(dev
, HIFN_1_PUB_STATUS
) | HIFN_PUBSTS_DONE
);
1852 restart
= dmacsr
& (HIFN_DMACSR_R_OVER
| HIFN_DMACSR_D_OVER
);
1854 u32 puisr
= hifn_read_0(dev
, HIFN_0_PUISR
);
1856 if (printk_ratelimit())
1857 printk("%s: overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
1858 dev
->name
, !!(dmacsr
& HIFN_DMACSR_R_OVER
),
1859 !!(dmacsr
& HIFN_DMACSR_D_OVER
),
1860 puisr
, !!(puisr
& HIFN_PUISR_DSTOVER
));
1861 if (!!(puisr
& HIFN_PUISR_DSTOVER
))
1862 hifn_write_0(dev
, HIFN_0_PUISR
, HIFN_PUISR_DSTOVER
);
1863 hifn_write_1(dev
, HIFN_1_DMA_CSR
, dmacsr
& (HIFN_DMACSR_R_OVER
|
1864 HIFN_DMACSR_D_OVER
));
1867 restart
= dmacsr
& (HIFN_DMACSR_C_ABORT
| HIFN_DMACSR_S_ABORT
|
1868 HIFN_DMACSR_D_ABORT
| HIFN_DMACSR_R_ABORT
);
1870 if (printk_ratelimit())
1871 printk("%s: abort: c: %d, s: %d, d: %d, r: %d.\n",
1872 dev
->name
, !!(dmacsr
& HIFN_DMACSR_C_ABORT
),
1873 !!(dmacsr
& HIFN_DMACSR_S_ABORT
),
1874 !!(dmacsr
& HIFN_DMACSR_D_ABORT
),
1875 !!(dmacsr
& HIFN_DMACSR_R_ABORT
));
1876 hifn_reset_dma(dev
, 1);
1878 hifn_init_registers(dev
);
1881 if ((dmacsr
& HIFN_DMACSR_C_WAIT
) && (dma
->cmdu
== 0)) {
1882 dprintk("%s: wait on command.\n", dev
->name
);
1883 dev
->dmareg
&= ~(HIFN_DMAIER_C_WAIT
);
1884 hifn_write_1(dev
, HIFN_1_DMA_IER
, dev
->dmareg
);
1887 tasklet_schedule(&dev
->tasklet
);
1888 hifn_clear_rings(dev
);
1893 static void hifn_flush(struct hifn_device
*dev
)
1895 unsigned long flags
;
1896 struct crypto_async_request
*async_req
;
1897 struct hifn_context
*ctx
;
1898 struct ablkcipher_request
*req
;
1899 struct hifn_dma
*dma
= (struct hifn_dma
*)dev
->desc_virt
;
1902 spin_lock_irqsave(&dev
->lock
, flags
);
1903 for (i
=0; i
<HIFN_D_RES_RSIZE
; ++i
) {
1904 struct hifn_desc
*d
= &dma
->resr
[i
];
1907 hifn_process_ready(dev
->sa
[i
],
1908 (d
->l
& __cpu_to_le32(HIFN_D_VALID
))?-ENODEV
:0);
1912 while ((async_req
= crypto_dequeue_request(&dev
->queue
))) {
1913 ctx
= crypto_tfm_ctx(async_req
->tfm
);
1914 req
= container_of(async_req
, struct ablkcipher_request
, base
);
1916 hifn_process_ready(req
, -ENODEV
);
1918 spin_unlock_irqrestore(&dev
->lock
, flags
);
1921 static int hifn_setkey(struct crypto_ablkcipher
*cipher
, const u8
*key
,
1924 struct crypto_tfm
*tfm
= crypto_ablkcipher_tfm(cipher
);
1925 struct hifn_context
*ctx
= crypto_tfm_ctx(tfm
);
1926 struct hifn_device
*dev
= ctx
->dev
;
1928 if (len
> HIFN_MAX_CRYPT_KEY_LENGTH
) {
1929 crypto_ablkcipher_set_flags(cipher
, CRYPTO_TFM_RES_BAD_KEY_LEN
);
1933 if (len
== HIFN_DES_KEY_LENGTH
) {
1934 u32 tmp
[DES_EXPKEY_WORDS
];
1935 int ret
= des_ekey(tmp
, key
);
1937 if (unlikely(ret
== 0) && (tfm
->crt_flags
& CRYPTO_TFM_REQ_WEAK_KEY
)) {
1938 tfm
->crt_flags
|= CRYPTO_TFM_RES_WEAK_KEY
;
1943 dev
->flags
&= ~HIFN_FLAG_OLD_KEY
;
1945 memcpy(ctx
->key
, key
, len
);
1951 static int hifn_handle_req(struct ablkcipher_request
*req
)
1953 struct hifn_context
*ctx
= crypto_tfm_ctx(req
->base
.tfm
);
1954 struct hifn_device
*dev
= ctx
->dev
;
1957 if (dev
->started
+ DIV_ROUND_UP(req
->nbytes
, PAGE_SIZE
) <= HIFN_QUEUE_LENGTH
)
1958 err
= hifn_setup_session(req
);
1960 if (err
== -EAGAIN
) {
1961 unsigned long flags
;
1963 spin_lock_irqsave(&dev
->lock
, flags
);
1964 err
= ablkcipher_enqueue_request(&dev
->queue
, req
);
1965 spin_unlock_irqrestore(&dev
->lock
, flags
);
1971 static int hifn_setup_crypto_req(struct ablkcipher_request
*req
, u8 op
,
1974 struct hifn_context
*ctx
= crypto_tfm_ctx(req
->base
.tfm
);
1977 ivsize
= crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req
));
1979 if (req
->info
&& mode
!= ACRYPTO_MODE_ECB
) {
1980 if (type
== ACRYPTO_TYPE_AES_128
)
1981 ivsize
= HIFN_AES_IV_LENGTH
;
1982 else if (type
== ACRYPTO_TYPE_DES
)
1983 ivsize
= HIFN_DES_KEY_LENGTH
;
1984 else if (type
== ACRYPTO_TYPE_3DES
)
1985 ivsize
= HIFN_3DES_KEY_LENGTH
;
1988 if (ctx
->keysize
!= 16 && type
== ACRYPTO_TYPE_AES_128
) {
1989 if (ctx
->keysize
== 24)
1990 type
= ACRYPTO_TYPE_AES_192
;
1991 else if (ctx
->keysize
== 32)
1992 type
= ACRYPTO_TYPE_AES_256
;
1998 ctx
->iv
= req
->info
;
1999 ctx
->ivsize
= ivsize
;
2002 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2003 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2004 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2007 return hifn_handle_req(req
);
2010 static int hifn_process_queue(struct hifn_device
*dev
)
2012 struct crypto_async_request
*async_req
;
2013 struct hifn_context
*ctx
;
2014 struct ablkcipher_request
*req
;
2015 unsigned long flags
;
2018 while (dev
->started
< HIFN_QUEUE_LENGTH
) {
2019 spin_lock_irqsave(&dev
->lock
, flags
);
2020 async_req
= crypto_dequeue_request(&dev
->queue
);
2021 spin_unlock_irqrestore(&dev
->lock
, flags
);
2026 ctx
= crypto_tfm_ctx(async_req
->tfm
);
2027 req
= container_of(async_req
, struct ablkcipher_request
, base
);
2029 err
= hifn_handle_req(req
);
2037 static int hifn_setup_crypto(struct ablkcipher_request
*req
, u8 op
,
2041 struct hifn_context
*ctx
= crypto_tfm_ctx(req
->base
.tfm
);
2042 struct hifn_device
*dev
= ctx
->dev
;
2044 err
= hifn_setup_crypto_req(req
, op
, type
, mode
);
2048 if (dev
->started
< HIFN_QUEUE_LENGTH
&& dev
->queue
.qlen
)
2049 err
= hifn_process_queue(dev
);
2055 * AES ecryption functions.
2057 static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request
*req
)
2059 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2060 ACRYPTO_TYPE_AES_128
, ACRYPTO_MODE_ECB
);
2062 static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request
*req
)
2064 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2065 ACRYPTO_TYPE_AES_128
, ACRYPTO_MODE_CBC
);
2067 static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request
*req
)
2069 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2070 ACRYPTO_TYPE_AES_128
, ACRYPTO_MODE_CFB
);
2072 static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request
*req
)
2074 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2075 ACRYPTO_TYPE_AES_128
, ACRYPTO_MODE_OFB
);
2079 * AES decryption functions.
2081 static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request
*req
)
2083 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2084 ACRYPTO_TYPE_AES_128
, ACRYPTO_MODE_ECB
);
2086 static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request
*req
)
2088 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2089 ACRYPTO_TYPE_AES_128
, ACRYPTO_MODE_CBC
);
2091 static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request
*req
)
2093 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2094 ACRYPTO_TYPE_AES_128
, ACRYPTO_MODE_CFB
);
2096 static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request
*req
)
2098 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2099 ACRYPTO_TYPE_AES_128
, ACRYPTO_MODE_OFB
);
2103 * DES ecryption functions.
2105 static inline int hifn_encrypt_des_ecb(struct ablkcipher_request
*req
)
2107 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2108 ACRYPTO_TYPE_DES
, ACRYPTO_MODE_ECB
);
2110 static inline int hifn_encrypt_des_cbc(struct ablkcipher_request
*req
)
2112 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2113 ACRYPTO_TYPE_DES
, ACRYPTO_MODE_CBC
);
2115 static inline int hifn_encrypt_des_cfb(struct ablkcipher_request
*req
)
2117 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2118 ACRYPTO_TYPE_DES
, ACRYPTO_MODE_CFB
);
2120 static inline int hifn_encrypt_des_ofb(struct ablkcipher_request
*req
)
2122 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2123 ACRYPTO_TYPE_DES
, ACRYPTO_MODE_OFB
);
2127 * DES decryption functions.
2129 static inline int hifn_decrypt_des_ecb(struct ablkcipher_request
*req
)
2131 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2132 ACRYPTO_TYPE_DES
, ACRYPTO_MODE_ECB
);
2134 static inline int hifn_decrypt_des_cbc(struct ablkcipher_request
*req
)
2136 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2137 ACRYPTO_TYPE_DES
, ACRYPTO_MODE_CBC
);
2139 static inline int hifn_decrypt_des_cfb(struct ablkcipher_request
*req
)
2141 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2142 ACRYPTO_TYPE_DES
, ACRYPTO_MODE_CFB
);
2144 static inline int hifn_decrypt_des_ofb(struct ablkcipher_request
*req
)
2146 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2147 ACRYPTO_TYPE_DES
, ACRYPTO_MODE_OFB
);
2151 * 3DES ecryption functions.
2153 static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request
*req
)
2155 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2156 ACRYPTO_TYPE_3DES
, ACRYPTO_MODE_ECB
);
2158 static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request
*req
)
2160 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2161 ACRYPTO_TYPE_3DES
, ACRYPTO_MODE_CBC
);
2163 static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request
*req
)
2165 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2166 ACRYPTO_TYPE_3DES
, ACRYPTO_MODE_CFB
);
2168 static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request
*req
)
2170 return hifn_setup_crypto(req
, ACRYPTO_OP_ENCRYPT
,
2171 ACRYPTO_TYPE_3DES
, ACRYPTO_MODE_OFB
);
2175 * 3DES decryption functions.
2177 static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request
*req
)
2179 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2180 ACRYPTO_TYPE_3DES
, ACRYPTO_MODE_ECB
);
2182 static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request
*req
)
2184 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2185 ACRYPTO_TYPE_3DES
, ACRYPTO_MODE_CBC
);
2187 static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request
*req
)
2189 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2190 ACRYPTO_TYPE_3DES
, ACRYPTO_MODE_CFB
);
2192 static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request
*req
)
2194 return hifn_setup_crypto(req
, ACRYPTO_OP_DECRYPT
,
2195 ACRYPTO_TYPE_3DES
, ACRYPTO_MODE_OFB
);
2198 struct hifn_alg_template
2200 char name
[CRYPTO_MAX_ALG_NAME
];
2201 char drv_name
[CRYPTO_MAX_ALG_NAME
];
2203 struct ablkcipher_alg ablkcipher
;
2206 static struct hifn_alg_template hifn_alg_templates
[] = {
2208 * 3DES ECB, CBC, CFB and OFB modes.
2211 .name
= "cfb(des3_ede)", .drv_name
= "hifn-3des", .bsize
= 8,
2213 .min_keysize
= HIFN_3DES_KEY_LENGTH
,
2214 .max_keysize
= HIFN_3DES_KEY_LENGTH
,
2215 .setkey
= hifn_setkey
,
2216 .encrypt
= hifn_encrypt_3des_cfb
,
2217 .decrypt
= hifn_decrypt_3des_cfb
,
2221 .name
= "ofb(des3_ede)", .drv_name
= "hifn-3des", .bsize
= 8,
2223 .min_keysize
= HIFN_3DES_KEY_LENGTH
,
2224 .max_keysize
= HIFN_3DES_KEY_LENGTH
,
2225 .setkey
= hifn_setkey
,
2226 .encrypt
= hifn_encrypt_3des_ofb
,
2227 .decrypt
= hifn_decrypt_3des_ofb
,
2231 .name
= "cbc(des3_ede)", .drv_name
= "hifn-3des", .bsize
= 8,
2233 .min_keysize
= HIFN_3DES_KEY_LENGTH
,
2234 .max_keysize
= HIFN_3DES_KEY_LENGTH
,
2235 .setkey
= hifn_setkey
,
2236 .encrypt
= hifn_encrypt_3des_cbc
,
2237 .decrypt
= hifn_decrypt_3des_cbc
,
2241 .name
= "ecb(des3_ede)", .drv_name
= "hifn-3des", .bsize
= 8,
2243 .min_keysize
= HIFN_3DES_KEY_LENGTH
,
2244 .max_keysize
= HIFN_3DES_KEY_LENGTH
,
2245 .setkey
= hifn_setkey
,
2246 .encrypt
= hifn_encrypt_3des_ecb
,
2247 .decrypt
= hifn_decrypt_3des_ecb
,
2252 * DES ECB, CBC, CFB and OFB modes.
2255 .name
= "cfb(des)", .drv_name
= "hifn-des", .bsize
= 8,
2257 .min_keysize
= HIFN_DES_KEY_LENGTH
,
2258 .max_keysize
= HIFN_DES_KEY_LENGTH
,
2259 .setkey
= hifn_setkey
,
2260 .encrypt
= hifn_encrypt_des_cfb
,
2261 .decrypt
= hifn_decrypt_des_cfb
,
2265 .name
= "ofb(des)", .drv_name
= "hifn-des", .bsize
= 8,
2267 .min_keysize
= HIFN_DES_KEY_LENGTH
,
2268 .max_keysize
= HIFN_DES_KEY_LENGTH
,
2269 .setkey
= hifn_setkey
,
2270 .encrypt
= hifn_encrypt_des_ofb
,
2271 .decrypt
= hifn_decrypt_des_ofb
,
2275 .name
= "cbc(des)", .drv_name
= "hifn-des", .bsize
= 8,
2277 .min_keysize
= HIFN_DES_KEY_LENGTH
,
2278 .max_keysize
= HIFN_DES_KEY_LENGTH
,
2279 .setkey
= hifn_setkey
,
2280 .encrypt
= hifn_encrypt_des_cbc
,
2281 .decrypt
= hifn_decrypt_des_cbc
,
2285 .name
= "ecb(des)", .drv_name
= "hifn-des", .bsize
= 8,
2287 .min_keysize
= HIFN_DES_KEY_LENGTH
,
2288 .max_keysize
= HIFN_DES_KEY_LENGTH
,
2289 .setkey
= hifn_setkey
,
2290 .encrypt
= hifn_encrypt_des_ecb
,
2291 .decrypt
= hifn_decrypt_des_ecb
,
2296 * AES ECB, CBC, CFB and OFB modes.
2299 .name
= "ecb(aes)", .drv_name
= "hifn-aes", .bsize
= 16,
2301 .min_keysize
= AES_MIN_KEY_SIZE
,
2302 .max_keysize
= AES_MAX_KEY_SIZE
,
2303 .setkey
= hifn_setkey
,
2304 .encrypt
= hifn_encrypt_aes_ecb
,
2305 .decrypt
= hifn_decrypt_aes_ecb
,
2309 .name
= "cbc(aes)", .drv_name
= "hifn-aes", .bsize
= 16,
2311 .min_keysize
= AES_MIN_KEY_SIZE
,
2312 .max_keysize
= AES_MAX_KEY_SIZE
,
2313 .setkey
= hifn_setkey
,
2314 .encrypt
= hifn_encrypt_aes_cbc
,
2315 .decrypt
= hifn_decrypt_aes_cbc
,
2319 .name
= "cfb(aes)", .drv_name
= "hifn-aes", .bsize
= 16,
2321 .min_keysize
= AES_MIN_KEY_SIZE
,
2322 .max_keysize
= AES_MAX_KEY_SIZE
,
2323 .setkey
= hifn_setkey
,
2324 .encrypt
= hifn_encrypt_aes_cfb
,
2325 .decrypt
= hifn_decrypt_aes_cfb
,
2329 .name
= "ofb(aes)", .drv_name
= "hifn-aes", .bsize
= 16,
2331 .min_keysize
= AES_MIN_KEY_SIZE
,
2332 .max_keysize
= AES_MAX_KEY_SIZE
,
2333 .setkey
= hifn_setkey
,
2334 .encrypt
= hifn_encrypt_aes_ofb
,
2335 .decrypt
= hifn_decrypt_aes_ofb
,
2340 static int hifn_cra_init(struct crypto_tfm
*tfm
)
2342 struct crypto_alg
*alg
= tfm
->__crt_alg
;
2343 struct hifn_crypto_alg
*ha
= crypto_alg_to_hifn(alg
);
2344 struct hifn_context
*ctx
= crypto_tfm_ctx(tfm
);
2351 static int hifn_alg_alloc(struct hifn_device
*dev
, struct hifn_alg_template
*t
)
2353 struct hifn_crypto_alg
*alg
;
2356 alg
= kzalloc(sizeof(struct hifn_crypto_alg
), GFP_KERNEL
);
2360 snprintf(alg
->alg
.cra_name
, CRYPTO_MAX_ALG_NAME
, "%s", t
->name
);
2361 snprintf(alg
->alg
.cra_driver_name
, CRYPTO_MAX_ALG_NAME
, "%s", t
->drv_name
);
2363 alg
->alg
.cra_priority
= 300;
2364 alg
->alg
.cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
| CRYPTO_ALG_ASYNC
;
2365 alg
->alg
.cra_blocksize
= t
->bsize
;
2366 alg
->alg
.cra_ctxsize
= sizeof(struct hifn_context
);
2367 alg
->alg
.cra_alignmask
= 15;
2369 alg
->alg
.cra_alignmask
= 3;
2370 alg
->alg
.cra_type
= &crypto_ablkcipher_type
;
2371 alg
->alg
.cra_module
= THIS_MODULE
;
2372 alg
->alg
.cra_u
.ablkcipher
= t
->ablkcipher
;
2373 alg
->alg
.cra_init
= hifn_cra_init
;
2377 list_add_tail(&alg
->entry
, &dev
->alg_list
);
2379 err
= crypto_register_alg(&alg
->alg
);
2381 list_del(&alg
->entry
);
2388 static void hifn_unregister_alg(struct hifn_device
*dev
)
2390 struct hifn_crypto_alg
*a
, *n
;
2392 list_for_each_entry_safe(a
, n
, &dev
->alg_list
, entry
) {
2393 list_del(&a
->entry
);
2394 crypto_unregister_alg(&a
->alg
);
2399 static int hifn_register_alg(struct hifn_device
*dev
)
2403 for (i
=0; i
<ARRAY_SIZE(hifn_alg_templates
); ++i
) {
2404 err
= hifn_alg_alloc(dev
, &hifn_alg_templates
[i
]);
2412 hifn_unregister_alg(dev
);
2416 static void hifn_tasklet_callback(unsigned long data
)
2418 struct hifn_device
*dev
= (struct hifn_device
*)data
;
2421 * This is ok to call this without lock being held,
2422 * althogh it modifies some parameters used in parallel,
2423 * (like dev->success), but they are used in process
2424 * context or update is atomic (like setting dev->sa[i] to NULL).
2426 hifn_check_for_completion(dev
, 0);
2429 static int hifn_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2432 struct hifn_device
*dev
;
2435 err
= pci_enable_device(pdev
);
2438 pci_set_master(pdev
);
2440 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
2442 goto err_out_disable_pci_device
;
2444 snprintf(name
, sizeof(name
), "hifn%d",
2445 atomic_inc_return(&hifn_dev_number
)-1);
2447 err
= pci_request_regions(pdev
, name
);
2449 goto err_out_disable_pci_device
;
2451 if (pci_resource_len(pdev
, 0) < HIFN_BAR0_SIZE
||
2452 pci_resource_len(pdev
, 1) < HIFN_BAR1_SIZE
||
2453 pci_resource_len(pdev
, 2) < HIFN_BAR2_SIZE
) {
2454 dprintk("%s: Broken hardware - I/O regions are too small.\n",
2457 goto err_out_free_regions
;
2460 dev
= kzalloc(sizeof(struct hifn_device
) + sizeof(struct crypto_alg
),
2464 goto err_out_free_regions
;
2467 INIT_LIST_HEAD(&dev
->alg_list
);
2469 snprintf(dev
->name
, sizeof(dev
->name
), "%s", name
);
2470 spin_lock_init(&dev
->lock
);
2472 for (i
=0; i
<3; ++i
) {
2473 unsigned long addr
, size
;
2475 addr
= pci_resource_start(pdev
, i
);
2476 size
= pci_resource_len(pdev
, i
);
2478 dev
->bar
[i
] = ioremap_nocache(addr
, size
);
2480 goto err_out_unmap_bars
;
2483 dev
->result_mem
= __get_free_pages(GFP_KERNEL
, HIFN_MAX_RESULT_ORDER
);
2484 if (!dev
->result_mem
) {
2485 dprintk("Failed to allocate %d pages for result_mem.\n",
2486 HIFN_MAX_RESULT_ORDER
);
2487 goto err_out_unmap_bars
;
2489 memset((void *)dev
->result_mem
, 0, PAGE_SIZE
*(1<<HIFN_MAX_RESULT_ORDER
));
2491 dev
->dst
= pci_map_single(pdev
, (void *)dev
->result_mem
,
2492 PAGE_SIZE
<< HIFN_MAX_RESULT_ORDER
, PCI_DMA_FROMDEVICE
);
2494 dev
->desc_virt
= pci_alloc_consistent(pdev
, sizeof(struct hifn_dma
),
2496 if (!dev
->desc_virt
) {
2497 dprintk("Failed to allocate descriptor rings.\n");
2498 goto err_out_free_result_pages
;
2500 memset(dev
->desc_virt
, 0, sizeof(struct hifn_dma
));
2503 dev
->irq
= pdev
->irq
;
2505 for (i
=0; i
<HIFN_D_RES_RSIZE
; ++i
)
2508 pci_set_drvdata(pdev
, dev
);
2510 tasklet_init(&dev
->tasklet
, hifn_tasklet_callback
, (unsigned long)dev
);
2512 crypto_init_queue(&dev
->queue
, 1);
2514 err
= request_irq(dev
->irq
, hifn_interrupt
, IRQF_SHARED
, dev
->name
, dev
);
2516 dprintk("Failed to request IRQ%d: err: %d.\n", dev
->irq
, err
);
2518 goto err_out_free_desc
;
2521 err
= hifn_start_device(dev
);
2523 goto err_out_free_irq
;
2525 err
= hifn_test(dev
, 1, 0);
2527 goto err_out_stop_device
;
2529 err
= hifn_register_alg(dev
);
2531 goto err_out_stop_device
;
2533 INIT_DELAYED_WORK(&dev
->work
, hifn_work
);
2534 schedule_delayed_work(&dev
->work
, HZ
);
2536 dprintk("HIFN crypto accelerator card at %s has been "
2537 "successfully registered as %s.\n",
2538 pci_name(pdev
), dev
->name
);
2542 err_out_stop_device
:
2543 hifn_reset_dma(dev
, 1);
2544 hifn_stop_device(dev
);
2546 free_irq(dev
->irq
, dev
->name
);
2547 tasklet_kill(&dev
->tasklet
);
2549 pci_free_consistent(pdev
, sizeof(struct hifn_dma
),
2550 dev
->desc_virt
, dev
->desc_dma
);
2552 err_out_free_result_pages
:
2553 pci_unmap_single(pdev
, dev
->dst
, PAGE_SIZE
<< HIFN_MAX_RESULT_ORDER
,
2554 PCI_DMA_FROMDEVICE
);
2555 free_pages(dev
->result_mem
, HIFN_MAX_RESULT_ORDER
);
2560 iounmap(dev
->bar
[i
]);
2562 err_out_free_regions
:
2563 pci_release_regions(pdev
);
2565 err_out_disable_pci_device
:
2566 pci_disable_device(pdev
);
2571 static void hifn_remove(struct pci_dev
*pdev
)
2574 struct hifn_device
*dev
;
2576 dev
= pci_get_drvdata(pdev
);
2579 cancel_delayed_work(&dev
->work
);
2580 flush_scheduled_work();
2582 hifn_unregister_alg(dev
);
2583 hifn_reset_dma(dev
, 1);
2584 hifn_stop_device(dev
);
2586 free_irq(dev
->irq
, dev
->name
);
2587 tasklet_kill(&dev
->tasklet
);
2591 pci_free_consistent(pdev
, sizeof(struct hifn_dma
),
2592 dev
->desc_virt
, dev
->desc_dma
);
2593 pci_unmap_single(pdev
, dev
->dst
,
2594 PAGE_SIZE
<< HIFN_MAX_RESULT_ORDER
,
2595 PCI_DMA_FROMDEVICE
);
2596 free_pages(dev
->result_mem
, HIFN_MAX_RESULT_ORDER
);
2599 iounmap(dev
->bar
[i
]);
2604 pci_release_regions(pdev
);
2605 pci_disable_device(pdev
);
2608 static struct pci_device_id hifn_pci_tbl
[] = {
2609 { PCI_DEVICE(PCI_VENDOR_ID_HIFN
, PCI_DEVICE_ID_HIFN_7955
) },
2610 { PCI_DEVICE(PCI_VENDOR_ID_HIFN
, PCI_DEVICE_ID_HIFN_7956
) },
2613 MODULE_DEVICE_TABLE(pci
, hifn_pci_tbl
);
2615 static struct pci_driver hifn_pci_driver
= {
2617 .id_table
= hifn_pci_tbl
,
2618 .probe
= hifn_probe
,
2619 .remove
= __devexit_p(hifn_remove
),
2622 static int __devinit
hifn_init(void)
2626 err
= pci_register_driver(&hifn_pci_driver
);
2628 dprintk("Failed to register PCI driver for %s device.\n",
2629 hifn_pci_driver
.name
);
2633 printk(KERN_INFO
"Driver for HIFN 795x crypto accelerator chip "
2634 "has been successfully registered.\n");
2639 static void __devexit
hifn_fini(void)
2641 pci_unregister_driver(&hifn_pci_driver
);
2643 printk(KERN_INFO
"Driver for HIFN 795x crypto accelerator chip "
2644 "has been successfully unregistered.\n");
2647 module_init(hifn_init
);
2648 module_exit(hifn_fini
);
2650 MODULE_LICENSE("GPL");
2651 MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
2652 MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip.");