2 * Intel IXP4xx NPE-C crypto driver
4 * Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmapool.h>
15 #include <linux/crypto.h>
16 #include <linux/kernel.h>
17 #include <linux/rtnetlink.h>
18 #include <linux/interrupt.h>
19 #include <linux/spinlock.h>
21 #include <crypto/ctr.h>
22 #include <crypto/des.h>
23 #include <crypto/aes.h>
24 #include <crypto/sha.h>
25 #include <crypto/algapi.h>
26 #include <crypto/aead.h>
27 #include <crypto/authenc.h>
28 #include <crypto/scatterwalk.h>
31 #include <mach/qmgr.h>
35 /* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */
36 #define NPE_CTX_LEN 80
37 #define AES_BLOCK128 16
39 #define NPE_OP_HASH_VERIFY 0x01
40 #define NPE_OP_CCM_ENABLE 0x04
41 #define NPE_OP_CRYPT_ENABLE 0x08
42 #define NPE_OP_HASH_ENABLE 0x10
43 #define NPE_OP_NOT_IN_PLACE 0x20
44 #define NPE_OP_HMAC_DISABLE 0x40
45 #define NPE_OP_CRYPT_ENCRYPT 0x80
47 #define NPE_OP_CCM_GEN_MIC 0xcc
48 #define NPE_OP_HASH_GEN_ICV 0x50
49 #define NPE_OP_ENC_GEN_KEY 0xc9
51 #define MOD_ECB 0x0000
52 #define MOD_CTR 0x1000
53 #define MOD_CBC_ENC 0x2000
54 #define MOD_CBC_DEC 0x3000
55 #define MOD_CCM_ENC 0x4000
56 #define MOD_CCM_DEC 0x5000
62 #define CIPH_DECR 0x0000
63 #define CIPH_ENCR 0x0400
65 #define MOD_DES 0x0000
66 #define MOD_TDEA2 0x0100
67 #define MOD_3DES 0x0200
68 #define MOD_AES 0x0800
69 #define MOD_AES128 (0x0800 | KEYLEN_128)
70 #define MOD_AES192 (0x0900 | KEYLEN_192)
71 #define MOD_AES256 (0x0a00 | KEYLEN_256)
74 #define NPE_ID 2 /* NPE C */
76 /* Space for registering when the first
77 * NPE_QLEN crypt_ctl are busy */
78 #define NPE_QLEN_TOTAL 64
83 #define CTL_FLAG_UNUSED 0x0000
84 #define CTL_FLAG_USED 0x1000
85 #define CTL_FLAG_PERFORM_ABLK 0x0001
86 #define CTL_FLAG_GEN_ICV 0x0002
87 #define CTL_FLAG_GEN_REVAES 0x0004
88 #define CTL_FLAG_PERFORM_AEAD 0x0008
89 #define CTL_FLAG_MASK 0x000f
91 #define HMAC_IPAD_VALUE 0x36
92 #define HMAC_OPAD_VALUE 0x5C
93 #define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE
95 #define MD5_DIGEST_SIZE 16
103 struct buffer_desc
*next
;
107 u8 mode
; /* NPE_OP_* operation mode */
110 u8 iv
[MAX_IVLEN
]; /* IV for CBC mode or CTR IV for CTR mode */
111 u32 icv_rev_aes
; /* icv or rev aes */
114 u16 auth_offs
; /* Authentication start offset */
115 u16 auth_len
; /* Authentication data length */
116 u16 crypt_offs
; /* Cryption start offset */
117 u16 crypt_len
; /* Cryption data length */
118 u32 aadAddr
; /* Additional Auth Data Addr for CCM mode */
119 u32 crypto_ctx
; /* NPE Crypto Param structure address */
121 /* Used by Host: 4*4 bytes*/
124 struct ablkcipher_request
*ablk_req
;
125 struct aead_request
*aead_req
;
126 struct crypto_tfm
*tfm
;
128 struct buffer_desc
*regist_buf
;
133 struct buffer_desc
*src
;
134 struct buffer_desc
*dst
;
140 struct buffer_desc
*buffer
;
141 unsigned short assoc_nents
;
142 unsigned short src_nents
;
143 struct scatterlist ivlist
;
144 /* used when the hmac is not on one sg entry */
149 struct ix_hash_algo
{
155 unsigned char *npe_ctx
;
156 dma_addr_t npe_ctx_phys
;
162 struct ix_sa_dir encrypt
;
163 struct ix_sa_dir decrypt
;
165 u8 authkey
[MAX_KEYLEN
];
167 u8 enckey
[MAX_KEYLEN
];
169 u8 nonce
[CTR_RFC3686_NONCE_SIZE
];
171 atomic_t configuring
;
172 struct completion completion
;
176 struct crypto_alg crypto
;
177 const struct ix_hash_algo
*hash
;
184 static const struct ix_hash_algo hash_alg_md5
= {
185 .cfgword
= 0xAA010004,
186 .icv
= "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
187 "\xFE\xDC\xBA\x98\x76\x54\x32\x10",
189 static const struct ix_hash_algo hash_alg_sha1
= {
190 .cfgword
= 0x00000005,
191 .icv
= "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
192 "\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
195 static struct npe
*npe_c
;
196 static struct dma_pool
*buffer_pool
= NULL
;
197 static struct dma_pool
*ctx_pool
= NULL
;
199 static struct crypt_ctl
*crypt_virt
= NULL
;
200 static dma_addr_t crypt_phys
;
202 static int support_aes
= 1;
204 static void dev_release(struct device
*dev
)
209 #define DRIVER_NAME "ixp4xx_crypto"
210 static struct platform_device pseudo_dev
= {
215 .coherent_dma_mask
= DMA_32BIT_MASK
,
216 .release
= dev_release
,
220 static struct device
*dev
= &pseudo_dev
.dev
;
222 static inline dma_addr_t
crypt_virt2phys(struct crypt_ctl
*virt
)
224 return crypt_phys
+ (virt
- crypt_virt
) * sizeof(struct crypt_ctl
);
227 static inline struct crypt_ctl
*crypt_phys2virt(dma_addr_t phys
)
229 return crypt_virt
+ (phys
- crypt_phys
) / sizeof(struct crypt_ctl
);
232 static inline u32
cipher_cfg_enc(struct crypto_tfm
*tfm
)
234 return container_of(tfm
->__crt_alg
, struct ixp_alg
,crypto
)->cfg_enc
;
237 static inline u32
cipher_cfg_dec(struct crypto_tfm
*tfm
)
239 return container_of(tfm
->__crt_alg
, struct ixp_alg
,crypto
)->cfg_dec
;
242 static inline const struct ix_hash_algo
*ix_hash(struct crypto_tfm
*tfm
)
244 return container_of(tfm
->__crt_alg
, struct ixp_alg
, crypto
)->hash
;
247 static int setup_crypt_desc(void)
249 BUILD_BUG_ON(sizeof(struct crypt_ctl
) != 64);
250 crypt_virt
= dma_alloc_coherent(dev
,
251 NPE_QLEN
* sizeof(struct crypt_ctl
),
252 &crypt_phys
, GFP_KERNEL
);
255 memset(crypt_virt
, 0, NPE_QLEN
* sizeof(struct crypt_ctl
));
259 static spinlock_t desc_lock
;
260 static struct crypt_ctl
*get_crypt_desc(void)
266 spin_lock_irqsave(&desc_lock
, flags
);
268 if (unlikely(!crypt_virt
))
270 if (unlikely(!crypt_virt
)) {
271 spin_unlock_irqrestore(&desc_lock
, flags
);
275 if (crypt_virt
[i
].ctl_flags
== CTL_FLAG_UNUSED
) {
276 if (++idx
>= NPE_QLEN
)
278 crypt_virt
[i
].ctl_flags
= CTL_FLAG_USED
;
279 spin_unlock_irqrestore(&desc_lock
, flags
);
280 return crypt_virt
+i
;
282 spin_unlock_irqrestore(&desc_lock
, flags
);
287 static spinlock_t emerg_lock
;
288 static struct crypt_ctl
*get_crypt_desc_emerg(void)
291 static int idx
= NPE_QLEN
;
292 struct crypt_ctl
*desc
;
295 desc
= get_crypt_desc();
298 if (unlikely(!crypt_virt
))
301 spin_lock_irqsave(&emerg_lock
, flags
);
303 if (crypt_virt
[i
].ctl_flags
== CTL_FLAG_UNUSED
) {
304 if (++idx
>= NPE_QLEN_TOTAL
)
306 crypt_virt
[i
].ctl_flags
= CTL_FLAG_USED
;
307 spin_unlock_irqrestore(&emerg_lock
, flags
);
308 return crypt_virt
+i
;
310 spin_unlock_irqrestore(&emerg_lock
, flags
);
315 static void free_buf_chain(struct buffer_desc
*buf
, u32 phys
)
318 struct buffer_desc
*buf1
;
322 phys1
= buf
->phys_next
;
323 dma_pool_free(buffer_pool
, buf
, phys
);
329 static struct tasklet_struct crypto_done_tasklet
;
331 static void finish_scattered_hmac(struct crypt_ctl
*crypt
)
333 struct aead_request
*req
= crypt
->data
.aead_req
;
334 struct aead_ctx
*req_ctx
= aead_request_ctx(req
);
335 struct crypto_aead
*tfm
= crypto_aead_reqtfm(req
);
336 int authsize
= crypto_aead_authsize(tfm
);
337 int decryptlen
= req
->cryptlen
- authsize
;
339 if (req_ctx
->encrypt
) {
340 scatterwalk_map_and_copy(req_ctx
->hmac_virt
,
341 req
->src
, decryptlen
, authsize
, 1);
343 dma_pool_free(buffer_pool
, req_ctx
->hmac_virt
, crypt
->icv_rev_aes
);
346 static void one_packet(dma_addr_t phys
)
348 struct crypt_ctl
*crypt
;
351 enum dma_data_direction src_direction
= DMA_BIDIRECTIONAL
;
353 failed
= phys
& 0x1 ? -EBADMSG
: 0;
355 crypt
= crypt_phys2virt(phys
);
357 switch (crypt
->ctl_flags
& CTL_FLAG_MASK
) {
358 case CTL_FLAG_PERFORM_AEAD
: {
359 struct aead_request
*req
= crypt
->data
.aead_req
;
360 struct aead_ctx
*req_ctx
= aead_request_ctx(req
);
361 dma_unmap_sg(dev
, req
->assoc
, req_ctx
->assoc_nents
,
363 dma_unmap_sg(dev
, &req_ctx
->ivlist
, 1, DMA_BIDIRECTIONAL
);
364 dma_unmap_sg(dev
, req
->src
, req_ctx
->src_nents
,
367 free_buf_chain(req_ctx
->buffer
, crypt
->src_buf
);
368 if (req_ctx
->hmac_virt
) {
369 finish_scattered_hmac(crypt
);
371 req
->base
.complete(&req
->base
, failed
);
374 case CTL_FLAG_PERFORM_ABLK
: {
375 struct ablkcipher_request
*req
= crypt
->data
.ablk_req
;
376 struct ablk_ctx
*req_ctx
= ablkcipher_request_ctx(req
);
379 nents
= req_ctx
->dst_nents
;
380 dma_unmap_sg(dev
, req
->dst
, nents
, DMA_FROM_DEVICE
);
381 free_buf_chain(req_ctx
->dst
, crypt
->dst_buf
);
382 src_direction
= DMA_TO_DEVICE
;
384 nents
= req_ctx
->src_nents
;
385 dma_unmap_sg(dev
, req
->src
, nents
, src_direction
);
386 free_buf_chain(req_ctx
->src
, crypt
->src_buf
);
387 req
->base
.complete(&req
->base
, failed
);
390 case CTL_FLAG_GEN_ICV
:
391 ctx
= crypto_tfm_ctx(crypt
->data
.tfm
);
392 dma_pool_free(ctx_pool
, crypt
->regist_ptr
,
393 crypt
->regist_buf
->phys_addr
);
394 dma_pool_free(buffer_pool
, crypt
->regist_buf
, crypt
->src_buf
);
395 if (atomic_dec_and_test(&ctx
->configuring
))
396 complete(&ctx
->completion
);
398 case CTL_FLAG_GEN_REVAES
:
399 ctx
= crypto_tfm_ctx(crypt
->data
.tfm
);
400 *(u32
*)ctx
->decrypt
.npe_ctx
&= cpu_to_be32(~CIPH_ENCR
);
401 if (atomic_dec_and_test(&ctx
->configuring
))
402 complete(&ctx
->completion
);
407 crypt
->ctl_flags
= CTL_FLAG_UNUSED
;
410 static void irqhandler(void *_unused
)
412 tasklet_schedule(&crypto_done_tasklet
);
415 static void crypto_done_action(unsigned long arg
)
420 dma_addr_t phys
= qmgr_get_entry(RECV_QID
);
425 tasklet_schedule(&crypto_done_tasklet
);
428 static int init_ixp_crypto(void)
432 if (! ( ~(*IXP4XX_EXP_CFG2
) & (IXP4XX_FEATURE_HASH
|
433 IXP4XX_FEATURE_AES
| IXP4XX_FEATURE_DES
))) {
434 printk(KERN_ERR
"ixp_crypto: No HW crypto available\n");
437 npe_c
= npe_request(NPE_ID
);
441 if (!npe_running(npe_c
)) {
442 npe_load_firmware(npe_c
, npe_name(npe_c
), dev
);
445 /* buffer_pool will also be used to sometimes store the hmac,
446 * so assure it is large enough
448 BUILD_BUG_ON(SHA1_DIGEST_SIZE
> sizeof(struct buffer_desc
));
449 buffer_pool
= dma_pool_create("buffer", dev
,
450 sizeof(struct buffer_desc
), 32, 0);
455 ctx_pool
= dma_pool_create("context", dev
,
460 ret
= qmgr_request_queue(SEND_QID
, NPE_QLEN_TOTAL
, 0, 0,
461 "ixp_crypto:out", NULL
);
464 ret
= qmgr_request_queue(RECV_QID
, NPE_QLEN
, 0, 0,
465 "ixp_crypto:in", NULL
);
467 qmgr_release_queue(SEND_QID
);
470 qmgr_set_irq(RECV_QID
, QUEUE_IRQ_SRC_NOT_EMPTY
, irqhandler
, NULL
);
471 tasklet_init(&crypto_done_tasklet
, crypto_done_action
, 0);
473 qmgr_enable_irq(RECV_QID
);
477 dma_pool_destroy(ctx_pool
);
479 dma_pool_destroy(buffer_pool
);
484 static void release_ixp_crypto(void)
486 qmgr_disable_irq(RECV_QID
);
487 tasklet_kill(&crypto_done_tasklet
);
489 qmgr_release_queue(SEND_QID
);
490 qmgr_release_queue(RECV_QID
);
492 dma_pool_destroy(ctx_pool
);
493 dma_pool_destroy(buffer_pool
);
498 dma_free_coherent(dev
,
499 NPE_QLEN_TOTAL
* sizeof( struct crypt_ctl
),
500 crypt_virt
, crypt_phys
);
505 static void reset_sa_dir(struct ix_sa_dir
*dir
)
507 memset(dir
->npe_ctx
, 0, NPE_CTX_LEN
);
508 dir
->npe_ctx_idx
= 0;
512 static int init_sa_dir(struct ix_sa_dir
*dir
)
514 dir
->npe_ctx
= dma_pool_alloc(ctx_pool
, GFP_KERNEL
, &dir
->npe_ctx_phys
);
522 static void free_sa_dir(struct ix_sa_dir
*dir
)
524 memset(dir
->npe_ctx
, 0, NPE_CTX_LEN
);
525 dma_pool_free(ctx_pool
, dir
->npe_ctx
, dir
->npe_ctx_phys
);
528 static int init_tfm(struct crypto_tfm
*tfm
)
530 struct ixp_ctx
*ctx
= crypto_tfm_ctx(tfm
);
533 atomic_set(&ctx
->configuring
, 0);
534 ret
= init_sa_dir(&ctx
->encrypt
);
537 ret
= init_sa_dir(&ctx
->decrypt
);
539 free_sa_dir(&ctx
->encrypt
);
544 static int init_tfm_ablk(struct crypto_tfm
*tfm
)
546 tfm
->crt_ablkcipher
.reqsize
= sizeof(struct ablk_ctx
);
547 return init_tfm(tfm
);
550 static int init_tfm_aead(struct crypto_tfm
*tfm
)
552 tfm
->crt_aead
.reqsize
= sizeof(struct aead_ctx
);
553 return init_tfm(tfm
);
556 static void exit_tfm(struct crypto_tfm
*tfm
)
558 struct ixp_ctx
*ctx
= crypto_tfm_ctx(tfm
);
559 free_sa_dir(&ctx
->encrypt
);
560 free_sa_dir(&ctx
->decrypt
);
563 static int register_chain_var(struct crypto_tfm
*tfm
, u8 xpad
, u32 target
,
564 int init_len
, u32 ctx_addr
, const u8
*key
, int key_len
)
566 struct ixp_ctx
*ctx
= crypto_tfm_ctx(tfm
);
567 struct crypt_ctl
*crypt
;
568 struct buffer_desc
*buf
;
571 u32 pad_phys
, buf_phys
;
573 BUILD_BUG_ON(NPE_CTX_LEN
< HMAC_PAD_BLOCKLEN
);
574 pad
= dma_pool_alloc(ctx_pool
, GFP_KERNEL
, &pad_phys
);
577 buf
= dma_pool_alloc(buffer_pool
, GFP_KERNEL
, &buf_phys
);
579 dma_pool_free(ctx_pool
, pad
, pad_phys
);
582 crypt
= get_crypt_desc_emerg();
584 dma_pool_free(ctx_pool
, pad
, pad_phys
);
585 dma_pool_free(buffer_pool
, buf
, buf_phys
);
589 memcpy(pad
, key
, key_len
);
590 memset(pad
+ key_len
, 0, HMAC_PAD_BLOCKLEN
- key_len
);
591 for (i
= 0; i
< HMAC_PAD_BLOCKLEN
; i
++) {
595 crypt
->data
.tfm
= tfm
;
596 crypt
->regist_ptr
= pad
;
597 crypt
->regist_buf
= buf
;
599 crypt
->auth_offs
= 0;
600 crypt
->auth_len
= HMAC_PAD_BLOCKLEN
;
601 crypt
->crypto_ctx
= ctx_addr
;
602 crypt
->src_buf
= buf_phys
;
603 crypt
->icv_rev_aes
= target
;
604 crypt
->mode
= NPE_OP_HASH_GEN_ICV
;
605 crypt
->init_len
= init_len
;
606 crypt
->ctl_flags
|= CTL_FLAG_GEN_ICV
;
609 buf
->buf_len
= HMAC_PAD_BLOCKLEN
;
611 buf
->phys_addr
= pad_phys
;
613 atomic_inc(&ctx
->configuring
);
614 qmgr_put_entry(SEND_QID
, crypt_virt2phys(crypt
));
615 BUG_ON(qmgr_stat_overflow(SEND_QID
));
619 static int setup_auth(struct crypto_tfm
*tfm
, int encrypt
, unsigned authsize
,
620 const u8
*key
, int key_len
, unsigned digest_len
)
622 u32 itarget
, otarget
, npe_ctx_addr
;
623 unsigned char *cinfo
;
624 int init_len
, ret
= 0;
626 struct ix_sa_dir
*dir
;
627 struct ixp_ctx
*ctx
= crypto_tfm_ctx(tfm
);
628 const struct ix_hash_algo
*algo
;
630 dir
= encrypt
? &ctx
->encrypt
: &ctx
->decrypt
;
631 cinfo
= dir
->npe_ctx
+ dir
->npe_ctx_idx
;
634 /* write cfg word to cryptinfo */
635 cfgword
= algo
->cfgword
| ( authsize
<< 6); /* (authsize/4) << 8 */
636 *(u32
*)cinfo
= cpu_to_be32(cfgword
);
637 cinfo
+= sizeof(cfgword
);
639 /* write ICV to cryptinfo */
640 memcpy(cinfo
, algo
->icv
, digest_len
);
643 itarget
= dir
->npe_ctx_phys
+ dir
->npe_ctx_idx
644 + sizeof(algo
->cfgword
);
645 otarget
= itarget
+ digest_len
;
646 init_len
= cinfo
- (dir
->npe_ctx
+ dir
->npe_ctx_idx
);
647 npe_ctx_addr
= dir
->npe_ctx_phys
+ dir
->npe_ctx_idx
;
649 dir
->npe_ctx_idx
+= init_len
;
650 dir
->npe_mode
|= NPE_OP_HASH_ENABLE
;
653 dir
->npe_mode
|= NPE_OP_HASH_VERIFY
;
655 ret
= register_chain_var(tfm
, HMAC_OPAD_VALUE
, otarget
,
656 init_len
, npe_ctx_addr
, key
, key_len
);
659 return register_chain_var(tfm
, HMAC_IPAD_VALUE
, itarget
,
660 init_len
, npe_ctx_addr
, key
, key_len
);
663 static int gen_rev_aes_key(struct crypto_tfm
*tfm
)
665 struct crypt_ctl
*crypt
;
666 struct ixp_ctx
*ctx
= crypto_tfm_ctx(tfm
);
667 struct ix_sa_dir
*dir
= &ctx
->decrypt
;
669 crypt
= get_crypt_desc_emerg();
673 *(u32
*)dir
->npe_ctx
|= cpu_to_be32(CIPH_ENCR
);
675 crypt
->data
.tfm
= tfm
;
676 crypt
->crypt_offs
= 0;
677 crypt
->crypt_len
= AES_BLOCK128
;
679 crypt
->crypto_ctx
= dir
->npe_ctx_phys
;
680 crypt
->icv_rev_aes
= dir
->npe_ctx_phys
+ sizeof(u32
);
681 crypt
->mode
= NPE_OP_ENC_GEN_KEY
;
682 crypt
->init_len
= dir
->npe_ctx_idx
;
683 crypt
->ctl_flags
|= CTL_FLAG_GEN_REVAES
;
685 atomic_inc(&ctx
->configuring
);
686 qmgr_put_entry(SEND_QID
, crypt_virt2phys(crypt
));
687 BUG_ON(qmgr_stat_overflow(SEND_QID
));
691 static int setup_cipher(struct crypto_tfm
*tfm
, int encrypt
,
692 const u8
*key
, int key_len
)
697 struct ix_sa_dir
*dir
;
698 struct ixp_ctx
*ctx
= crypto_tfm_ctx(tfm
);
699 u32
*flags
= &tfm
->crt_flags
;
701 dir
= encrypt
? &ctx
->encrypt
: &ctx
->decrypt
;
702 cinfo
= dir
->npe_ctx
;
705 cipher_cfg
= cipher_cfg_enc(tfm
);
706 dir
->npe_mode
|= NPE_OP_CRYPT_ENCRYPT
;
708 cipher_cfg
= cipher_cfg_dec(tfm
);
710 if (cipher_cfg
& MOD_AES
) {
712 case 16: keylen_cfg
= MOD_AES128
| KEYLEN_128
; break;
713 case 24: keylen_cfg
= MOD_AES192
| KEYLEN_192
; break;
714 case 32: keylen_cfg
= MOD_AES256
| KEYLEN_256
; break;
716 *flags
|= CRYPTO_TFM_RES_BAD_KEY_LEN
;
719 cipher_cfg
|= keylen_cfg
;
720 } else if (cipher_cfg
& MOD_3DES
) {
721 const u32
*K
= (const u32
*)key
;
722 if (unlikely(!((K
[0] ^ K
[2]) | (K
[1] ^ K
[3])) ||
723 !((K
[2] ^ K
[4]) | (K
[3] ^ K
[5]))))
725 *flags
|= CRYPTO_TFM_RES_BAD_KEY_SCHED
;
729 u32 tmp
[DES_EXPKEY_WORDS
];
730 if (des_ekey(tmp
, key
) == 0) {
731 *flags
|= CRYPTO_TFM_RES_WEAK_KEY
;
734 /* write cfg word to cryptinfo */
735 *(u32
*)cinfo
= cpu_to_be32(cipher_cfg
);
736 cinfo
+= sizeof(cipher_cfg
);
738 /* write cipher key to cryptinfo */
739 memcpy(cinfo
, key
, key_len
);
740 /* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */
741 if (key_len
< DES3_EDE_KEY_SIZE
&& !(cipher_cfg
& MOD_AES
)) {
742 memset(cinfo
+ key_len
, 0, DES3_EDE_KEY_SIZE
-key_len
);
743 key_len
= DES3_EDE_KEY_SIZE
;
745 dir
->npe_ctx_idx
= sizeof(cipher_cfg
) + key_len
;
746 dir
->npe_mode
|= NPE_OP_CRYPT_ENABLE
;
747 if ((cipher_cfg
& MOD_AES
) && !encrypt
) {
748 return gen_rev_aes_key(tfm
);
753 static int count_sg(struct scatterlist
*sg
, int nbytes
)
756 for (i
= 0; nbytes
> 0; i
++, sg
= sg_next(sg
))
757 nbytes
-= sg
->length
;
761 static struct buffer_desc
*chainup_buffers(struct scatterlist
*sg
,
762 unsigned nbytes
, struct buffer_desc
*buf
, gfp_t flags
)
767 struct buffer_desc
*next_buf
;
769 unsigned len
= min(nbytes
, sg_dma_len(sg
));
773 if (!buf
->phys_addr
) {
774 buf
->phys_addr
= sg_dma_address(sg
);
780 /* Two consecutive chunks on one page may be handled by the old
781 * buffer descriptor, increased by the length of the new one
783 if (sg_dma_address(sg
) == buf
->phys_addr
+ buf
->buf_len
) {
787 next_buf
= dma_pool_alloc(buffer_pool
, flags
, &next_buf_phys
);
790 buf
->next
= next_buf
;
791 buf
->phys_next
= next_buf_phys
;
796 buf
->phys_addr
= sg_dma_address(sg
);
806 static int ablk_setkey(struct crypto_ablkcipher
*tfm
, const u8
*key
,
807 unsigned int key_len
)
809 struct ixp_ctx
*ctx
= crypto_ablkcipher_ctx(tfm
);
810 u32
*flags
= &tfm
->base
.crt_flags
;
813 init_completion(&ctx
->completion
);
814 atomic_inc(&ctx
->configuring
);
816 reset_sa_dir(&ctx
->encrypt
);
817 reset_sa_dir(&ctx
->decrypt
);
819 ctx
->encrypt
.npe_mode
= NPE_OP_HMAC_DISABLE
;
820 ctx
->decrypt
.npe_mode
= NPE_OP_HMAC_DISABLE
;
822 ret
= setup_cipher(&tfm
->base
, 0, key
, key_len
);
825 ret
= setup_cipher(&tfm
->base
, 1, key
, key_len
);
829 if (*flags
& CRYPTO_TFM_RES_WEAK_KEY
) {
830 if (*flags
& CRYPTO_TFM_REQ_WEAK_KEY
) {
833 *flags
&= ~CRYPTO_TFM_RES_WEAK_KEY
;
837 if (!atomic_dec_and_test(&ctx
->configuring
))
838 wait_for_completion(&ctx
->completion
);
842 static int ablk_rfc3686_setkey(struct crypto_ablkcipher
*tfm
, const u8
*key
,
843 unsigned int key_len
)
845 struct ixp_ctx
*ctx
= crypto_ablkcipher_ctx(tfm
);
847 /* the nonce is stored in bytes at end of key */
848 if (key_len
< CTR_RFC3686_NONCE_SIZE
)
851 memcpy(ctx
->nonce
, key
+ (key_len
- CTR_RFC3686_NONCE_SIZE
),
852 CTR_RFC3686_NONCE_SIZE
);
854 key_len
-= CTR_RFC3686_NONCE_SIZE
;
855 return ablk_setkey(tfm
, key
, key_len
);
858 static int ablk_perform(struct ablkcipher_request
*req
, int encrypt
)
860 struct crypto_ablkcipher
*tfm
= crypto_ablkcipher_reqtfm(req
);
861 struct ixp_ctx
*ctx
= crypto_ablkcipher_ctx(tfm
);
862 unsigned ivsize
= crypto_ablkcipher_ivsize(tfm
);
864 struct ix_sa_dir
*dir
;
865 struct crypt_ctl
*crypt
;
866 unsigned int nbytes
= req
->nbytes
, nents
;
867 enum dma_data_direction src_direction
= DMA_BIDIRECTIONAL
;
868 struct ablk_ctx
*req_ctx
= ablkcipher_request_ctx(req
);
869 gfp_t flags
= req
->base
.flags
& CRYPTO_TFM_REQ_MAY_SLEEP
?
870 GFP_KERNEL
: GFP_ATOMIC
;
872 if (qmgr_stat_full(SEND_QID
))
874 if (atomic_read(&ctx
->configuring
))
877 dir
= encrypt
? &ctx
->encrypt
: &ctx
->decrypt
;
879 crypt
= get_crypt_desc();
883 crypt
->data
.ablk_req
= req
;
884 crypt
->crypto_ctx
= dir
->npe_ctx_phys
;
885 crypt
->mode
= dir
->npe_mode
;
886 crypt
->init_len
= dir
->npe_ctx_idx
;
888 crypt
->crypt_offs
= 0;
889 crypt
->crypt_len
= nbytes
;
891 BUG_ON(ivsize
&& !req
->info
);
892 memcpy(crypt
->iv
, req
->info
, ivsize
);
893 if (req
->src
!= req
->dst
) {
894 crypt
->mode
|= NPE_OP_NOT_IN_PLACE
;
895 nents
= count_sg(req
->dst
, nbytes
);
896 /* This was never tested by Intel
897 * for more than one dst buffer, I think. */
899 req_ctx
->dst_nents
= nents
;
900 dma_map_sg(dev
, req
->dst
, nents
, DMA_FROM_DEVICE
);
901 req_ctx
->dst
= dma_pool_alloc(buffer_pool
, flags
,&crypt
->dst_buf
);
904 req_ctx
->dst
->phys_addr
= 0;
905 if (!chainup_buffers(req
->dst
, nbytes
, req_ctx
->dst
, flags
))
907 src_direction
= DMA_TO_DEVICE
;
910 req_ctx
->dst_nents
= 0;
912 nents
= count_sg(req
->src
, nbytes
);
913 req_ctx
->src_nents
= nents
;
914 dma_map_sg(dev
, req
->src
, nents
, src_direction
);
916 req_ctx
->src
= dma_pool_alloc(buffer_pool
, flags
, &crypt
->src_buf
);
919 req_ctx
->src
->phys_addr
= 0;
920 if (!chainup_buffers(req
->src
, nbytes
, req_ctx
->src
, flags
))
923 crypt
->ctl_flags
|= CTL_FLAG_PERFORM_ABLK
;
924 qmgr_put_entry(SEND_QID
, crypt_virt2phys(crypt
));
925 BUG_ON(qmgr_stat_overflow(SEND_QID
));
929 free_buf_chain(req_ctx
->src
, crypt
->src_buf
);
931 dma_unmap_sg(dev
, req
->src
, req_ctx
->src_nents
, src_direction
);
933 if (req
->src
!= req
->dst
) {
934 free_buf_chain(req_ctx
->dst
, crypt
->dst_buf
);
936 dma_unmap_sg(dev
, req
->src
, req_ctx
->dst_nents
,
939 crypt
->ctl_flags
= CTL_FLAG_UNUSED
;
943 static int ablk_encrypt(struct ablkcipher_request
*req
)
945 return ablk_perform(req
, 1);
948 static int ablk_decrypt(struct ablkcipher_request
*req
)
950 return ablk_perform(req
, 0);
953 static int ablk_rfc3686_crypt(struct ablkcipher_request
*req
)
955 struct crypto_ablkcipher
*tfm
= crypto_ablkcipher_reqtfm(req
);
956 struct ixp_ctx
*ctx
= crypto_ablkcipher_ctx(tfm
);
957 u8 iv
[CTR_RFC3686_BLOCK_SIZE
];
958 u8
*info
= req
->info
;
961 /* set up counter block */
962 memcpy(iv
, ctx
->nonce
, CTR_RFC3686_NONCE_SIZE
);
963 memcpy(iv
+ CTR_RFC3686_NONCE_SIZE
, info
, CTR_RFC3686_IV_SIZE
);
965 /* initialize counter portion of counter block */
966 *(__be32
*)(iv
+ CTR_RFC3686_NONCE_SIZE
+ CTR_RFC3686_IV_SIZE
) =
970 ret
= ablk_perform(req
, 1);
975 static int hmac_inconsistent(struct scatterlist
*sg
, unsigned start
,
984 if (start
< offset
+ sg
->length
)
987 offset
+= sg
->length
;
990 return (start
+ nbytes
> offset
+ sg
->length
);
993 static int aead_perform(struct aead_request
*req
, int encrypt
,
994 int cryptoffset
, int eff_cryptlen
, u8
*iv
)
996 struct crypto_aead
*tfm
= crypto_aead_reqtfm(req
);
997 struct ixp_ctx
*ctx
= crypto_aead_ctx(tfm
);
998 unsigned ivsize
= crypto_aead_ivsize(tfm
);
999 unsigned authsize
= crypto_aead_authsize(tfm
);
1001 struct ix_sa_dir
*dir
;
1002 struct crypt_ctl
*crypt
;
1003 unsigned int cryptlen
, nents
;
1004 struct buffer_desc
*buf
;
1005 struct aead_ctx
*req_ctx
= aead_request_ctx(req
);
1006 gfp_t flags
= req
->base
.flags
& CRYPTO_TFM_REQ_MAY_SLEEP
?
1007 GFP_KERNEL
: GFP_ATOMIC
;
1009 if (qmgr_stat_full(SEND_QID
))
1011 if (atomic_read(&ctx
->configuring
))
1015 dir
= &ctx
->encrypt
;
1016 cryptlen
= req
->cryptlen
;
1018 dir
= &ctx
->decrypt
;
1019 /* req->cryptlen includes the authsize when decrypting */
1020 cryptlen
= req
->cryptlen
-authsize
;
1021 eff_cryptlen
-= authsize
;
1023 crypt
= get_crypt_desc();
1027 crypt
->data
.aead_req
= req
;
1028 crypt
->crypto_ctx
= dir
->npe_ctx_phys
;
1029 crypt
->mode
= dir
->npe_mode
;
1030 crypt
->init_len
= dir
->npe_ctx_idx
;
1032 crypt
->crypt_offs
= cryptoffset
;
1033 crypt
->crypt_len
= eff_cryptlen
;
1035 crypt
->auth_offs
= 0;
1036 crypt
->auth_len
= req
->assoclen
+ ivsize
+ cryptlen
;
1037 BUG_ON(ivsize
&& !req
->iv
);
1038 memcpy(crypt
->iv
, req
->iv
, ivsize
);
1040 if (req
->src
!= req
->dst
) {
1041 BUG(); /* -ENOTSUP because of my lazyness */
1044 req_ctx
->buffer
= dma_pool_alloc(buffer_pool
, flags
, &crypt
->src_buf
);
1045 if (!req_ctx
->buffer
)
1047 req_ctx
->buffer
->phys_addr
= 0;
1049 nents
= count_sg(req
->assoc
, req
->assoclen
);
1050 req_ctx
->assoc_nents
= nents
;
1051 dma_map_sg(dev
, req
->assoc
, nents
, DMA_TO_DEVICE
);
1052 buf
= chainup_buffers(req
->assoc
, req
->assoclen
, req_ctx
->buffer
,flags
);
1054 goto unmap_sg_assoc
;
1056 sg_init_table(&req_ctx
->ivlist
, 1);
1057 sg_set_buf(&req_ctx
->ivlist
, iv
, ivsize
);
1058 dma_map_sg(dev
, &req_ctx
->ivlist
, 1, DMA_BIDIRECTIONAL
);
1059 buf
= chainup_buffers(&req_ctx
->ivlist
, ivsize
, buf
, flags
);
1062 if (unlikely(hmac_inconsistent(req
->src
, cryptlen
, authsize
))) {
1063 /* The 12 hmac bytes are scattered,
1064 * we need to copy them into a safe buffer */
1065 req_ctx
->hmac_virt
= dma_pool_alloc(buffer_pool
, flags
,
1066 &crypt
->icv_rev_aes
);
1067 if (unlikely(!req_ctx
->hmac_virt
))
1070 scatterwalk_map_and_copy(req_ctx
->hmac_virt
,
1071 req
->src
, cryptlen
, authsize
, 0);
1073 req_ctx
->encrypt
= encrypt
;
1075 req_ctx
->hmac_virt
= NULL
;
1078 nents
= count_sg(req
->src
, cryptlen
+ authsize
);
1079 req_ctx
->src_nents
= nents
;
1080 dma_map_sg(dev
, req
->src
, nents
, DMA_BIDIRECTIONAL
);
1081 buf
= chainup_buffers(req
->src
, cryptlen
+ authsize
, buf
, flags
);
1084 if (!req_ctx
->hmac_virt
) {
1085 crypt
->icv_rev_aes
= buf
->phys_addr
+ buf
->buf_len
- authsize
;
1087 crypt
->ctl_flags
|= CTL_FLAG_PERFORM_AEAD
;
1088 qmgr_put_entry(SEND_QID
, crypt_virt2phys(crypt
));
1089 BUG_ON(qmgr_stat_overflow(SEND_QID
));
1090 return -EINPROGRESS
;
1092 dma_unmap_sg(dev
, req
->src
, req_ctx
->src_nents
, DMA_BIDIRECTIONAL
);
1093 if (req_ctx
->hmac_virt
) {
1094 dma_pool_free(buffer_pool
, req_ctx
->hmac_virt
,
1095 crypt
->icv_rev_aes
);
1098 dma_unmap_sg(dev
, &req_ctx
->ivlist
, 1, DMA_BIDIRECTIONAL
);
1100 dma_unmap_sg(dev
, req
->assoc
, req_ctx
->assoc_nents
, DMA_TO_DEVICE
);
1101 free_buf_chain(req_ctx
->buffer
, crypt
->src_buf
);
1103 crypt
->ctl_flags
= CTL_FLAG_UNUSED
;
1107 static int aead_setup(struct crypto_aead
*tfm
, unsigned int authsize
)
1109 struct ixp_ctx
*ctx
= crypto_aead_ctx(tfm
);
1110 u32
*flags
= &tfm
->base
.crt_flags
;
1111 unsigned digest_len
= crypto_aead_alg(tfm
)->maxauthsize
;
1114 if (!ctx
->enckey_len
&& !ctx
->authkey_len
)
1116 init_completion(&ctx
->completion
);
1117 atomic_inc(&ctx
->configuring
);
1119 reset_sa_dir(&ctx
->encrypt
);
1120 reset_sa_dir(&ctx
->decrypt
);
1122 ret
= setup_cipher(&tfm
->base
, 0, ctx
->enckey
, ctx
->enckey_len
);
1125 ret
= setup_cipher(&tfm
->base
, 1, ctx
->enckey
, ctx
->enckey_len
);
1128 ret
= setup_auth(&tfm
->base
, 0, authsize
, ctx
->authkey
,
1129 ctx
->authkey_len
, digest_len
);
1132 ret
= setup_auth(&tfm
->base
, 1, authsize
, ctx
->authkey
,
1133 ctx
->authkey_len
, digest_len
);
1137 if (*flags
& CRYPTO_TFM_RES_WEAK_KEY
) {
1138 if (*flags
& CRYPTO_TFM_REQ_WEAK_KEY
) {
1142 *flags
&= ~CRYPTO_TFM_RES_WEAK_KEY
;
1146 if (!atomic_dec_and_test(&ctx
->configuring
))
1147 wait_for_completion(&ctx
->completion
);
1151 static int aead_setauthsize(struct crypto_aead
*tfm
, unsigned int authsize
)
1153 int max
= crypto_aead_alg(tfm
)->maxauthsize
>> 2;
1155 if ((authsize
>>2) < 1 || (authsize
>>2) > max
|| (authsize
& 3))
1157 return aead_setup(tfm
, authsize
);
1160 static int aead_setkey(struct crypto_aead
*tfm
, const u8
*key
,
1161 unsigned int keylen
)
1163 struct ixp_ctx
*ctx
= crypto_aead_ctx(tfm
);
1164 struct rtattr
*rta
= (struct rtattr
*)key
;
1165 struct crypto_authenc_key_param
*param
;
1167 if (!RTA_OK(rta
, keylen
))
1169 if (rta
->rta_type
!= CRYPTO_AUTHENC_KEYA_PARAM
)
1171 if (RTA_PAYLOAD(rta
) < sizeof(*param
))
1174 param
= RTA_DATA(rta
);
1175 ctx
->enckey_len
= be32_to_cpu(param
->enckeylen
);
1177 key
+= RTA_ALIGN(rta
->rta_len
);
1178 keylen
-= RTA_ALIGN(rta
->rta_len
);
1180 if (keylen
< ctx
->enckey_len
)
1183 ctx
->authkey_len
= keylen
- ctx
->enckey_len
;
1184 memcpy(ctx
->enckey
, key
+ ctx
->authkey_len
, ctx
->enckey_len
);
1185 memcpy(ctx
->authkey
, key
, ctx
->authkey_len
);
1187 return aead_setup(tfm
, crypto_aead_authsize(tfm
));
1189 ctx
->enckey_len
= 0;
1190 crypto_aead_set_flags(tfm
, CRYPTO_TFM_RES_BAD_KEY_LEN
);
1194 static int aead_encrypt(struct aead_request
*req
)
1196 unsigned ivsize
= crypto_aead_ivsize(crypto_aead_reqtfm(req
));
1197 return aead_perform(req
, 1, req
->assoclen
+ ivsize
,
1198 req
->cryptlen
, req
->iv
);
1201 static int aead_decrypt(struct aead_request
*req
)
1203 unsigned ivsize
= crypto_aead_ivsize(crypto_aead_reqtfm(req
));
1204 return aead_perform(req
, 0, req
->assoclen
+ ivsize
,
1205 req
->cryptlen
, req
->iv
);
1208 static int aead_givencrypt(struct aead_givcrypt_request
*req
)
1210 struct crypto_aead
*tfm
= aead_givcrypt_reqtfm(req
);
1211 struct ixp_ctx
*ctx
= crypto_aead_ctx(tfm
);
1212 unsigned len
, ivsize
= crypto_aead_ivsize(tfm
);
1215 /* copied from eseqiv.c */
1217 get_random_bytes(ctx
->salt
, ivsize
);
1220 memcpy(req
->areq
.iv
, ctx
->salt
, ivsize
);
1222 if (ivsize
> sizeof(u64
)) {
1223 memset(req
->giv
, 0, ivsize
- sizeof(u64
));
1226 seq
= cpu_to_be64(req
->seq
);
1227 memcpy(req
->giv
+ ivsize
- len
, &seq
, len
);
1228 return aead_perform(&req
->areq
, 1, req
->areq
.assoclen
,
1229 req
->areq
.cryptlen
+ivsize
, req
->giv
);
1232 static struct ixp_alg ixp4xx_algos
[] = {
1235 .cra_name
= "cbc(des)",
1236 .cra_blocksize
= DES_BLOCK_SIZE
,
1237 .cra_u
= { .ablkcipher
= {
1238 .min_keysize
= DES_KEY_SIZE
,
1239 .max_keysize
= DES_KEY_SIZE
,
1240 .ivsize
= DES_BLOCK_SIZE
,
1245 .cfg_enc
= CIPH_ENCR
| MOD_DES
| MOD_CBC_ENC
| KEYLEN_192
,
1246 .cfg_dec
= CIPH_DECR
| MOD_DES
| MOD_CBC_DEC
| KEYLEN_192
,
1250 .cra_name
= "ecb(des)",
1251 .cra_blocksize
= DES_BLOCK_SIZE
,
1252 .cra_u
= { .ablkcipher
= {
1253 .min_keysize
= DES_KEY_SIZE
,
1254 .max_keysize
= DES_KEY_SIZE
,
1258 .cfg_enc
= CIPH_ENCR
| MOD_DES
| MOD_ECB
| KEYLEN_192
,
1259 .cfg_dec
= CIPH_DECR
| MOD_DES
| MOD_ECB
| KEYLEN_192
,
1262 .cra_name
= "cbc(des3_ede)",
1263 .cra_blocksize
= DES3_EDE_BLOCK_SIZE
,
1264 .cra_u
= { .ablkcipher
= {
1265 .min_keysize
= DES3_EDE_KEY_SIZE
,
1266 .max_keysize
= DES3_EDE_KEY_SIZE
,
1267 .ivsize
= DES3_EDE_BLOCK_SIZE
,
1272 .cfg_enc
= CIPH_ENCR
| MOD_3DES
| MOD_CBC_ENC
| KEYLEN_192
,
1273 .cfg_dec
= CIPH_DECR
| MOD_3DES
| MOD_CBC_DEC
| KEYLEN_192
,
1276 .cra_name
= "ecb(des3_ede)",
1277 .cra_blocksize
= DES3_EDE_BLOCK_SIZE
,
1278 .cra_u
= { .ablkcipher
= {
1279 .min_keysize
= DES3_EDE_KEY_SIZE
,
1280 .max_keysize
= DES3_EDE_KEY_SIZE
,
1284 .cfg_enc
= CIPH_ENCR
| MOD_3DES
| MOD_ECB
| KEYLEN_192
,
1285 .cfg_dec
= CIPH_DECR
| MOD_3DES
| MOD_ECB
| KEYLEN_192
,
1288 .cra_name
= "cbc(aes)",
1289 .cra_blocksize
= AES_BLOCK_SIZE
,
1290 .cra_u
= { .ablkcipher
= {
1291 .min_keysize
= AES_MIN_KEY_SIZE
,
1292 .max_keysize
= AES_MAX_KEY_SIZE
,
1293 .ivsize
= AES_BLOCK_SIZE
,
1298 .cfg_enc
= CIPH_ENCR
| MOD_AES
| MOD_CBC_ENC
,
1299 .cfg_dec
= CIPH_DECR
| MOD_AES
| MOD_CBC_DEC
,
1302 .cra_name
= "ecb(aes)",
1303 .cra_blocksize
= AES_BLOCK_SIZE
,
1304 .cra_u
= { .ablkcipher
= {
1305 .min_keysize
= AES_MIN_KEY_SIZE
,
1306 .max_keysize
= AES_MAX_KEY_SIZE
,
1310 .cfg_enc
= CIPH_ENCR
| MOD_AES
| MOD_ECB
,
1311 .cfg_dec
= CIPH_DECR
| MOD_AES
| MOD_ECB
,
1314 .cra_name
= "ctr(aes)",
1315 .cra_blocksize
= AES_BLOCK_SIZE
,
1316 .cra_u
= { .ablkcipher
= {
1317 .min_keysize
= AES_MIN_KEY_SIZE
,
1318 .max_keysize
= AES_MAX_KEY_SIZE
,
1319 .ivsize
= AES_BLOCK_SIZE
,
1324 .cfg_enc
= CIPH_ENCR
| MOD_AES
| MOD_CTR
,
1325 .cfg_dec
= CIPH_ENCR
| MOD_AES
| MOD_CTR
,
1328 .cra_name
= "rfc3686(ctr(aes))",
1329 .cra_blocksize
= AES_BLOCK_SIZE
,
1330 .cra_u
= { .ablkcipher
= {
1331 .min_keysize
= AES_MIN_KEY_SIZE
,
1332 .max_keysize
= AES_MAX_KEY_SIZE
,
1333 .ivsize
= AES_BLOCK_SIZE
,
1335 .setkey
= ablk_rfc3686_setkey
,
1336 .encrypt
= ablk_rfc3686_crypt
,
1337 .decrypt
= ablk_rfc3686_crypt
}
1340 .cfg_enc
= CIPH_ENCR
| MOD_AES
| MOD_CTR
,
1341 .cfg_dec
= CIPH_ENCR
| MOD_AES
| MOD_CTR
,
1344 .cra_name
= "authenc(hmac(md5),cbc(des))",
1345 .cra_blocksize
= DES_BLOCK_SIZE
,
1346 .cra_u
= { .aead
= {
1347 .ivsize
= DES_BLOCK_SIZE
,
1348 .maxauthsize
= MD5_DIGEST_SIZE
,
1352 .hash
= &hash_alg_md5
,
1353 .cfg_enc
= CIPH_ENCR
| MOD_DES
| MOD_CBC_ENC
| KEYLEN_192
,
1354 .cfg_dec
= CIPH_DECR
| MOD_DES
| MOD_CBC_DEC
| KEYLEN_192
,
1357 .cra_name
= "authenc(hmac(md5),cbc(des3_ede))",
1358 .cra_blocksize
= DES3_EDE_BLOCK_SIZE
,
1359 .cra_u
= { .aead
= {
1360 .ivsize
= DES3_EDE_BLOCK_SIZE
,
1361 .maxauthsize
= MD5_DIGEST_SIZE
,
1365 .hash
= &hash_alg_md5
,
1366 .cfg_enc
= CIPH_ENCR
| MOD_3DES
| MOD_CBC_ENC
| KEYLEN_192
,
1367 .cfg_dec
= CIPH_DECR
| MOD_3DES
| MOD_CBC_DEC
| KEYLEN_192
,
1370 .cra_name
= "authenc(hmac(sha1),cbc(des))",
1371 .cra_blocksize
= DES_BLOCK_SIZE
,
1372 .cra_u
= { .aead
= {
1373 .ivsize
= DES_BLOCK_SIZE
,
1374 .maxauthsize
= SHA1_DIGEST_SIZE
,
1378 .hash
= &hash_alg_sha1
,
1379 .cfg_enc
= CIPH_ENCR
| MOD_DES
| MOD_CBC_ENC
| KEYLEN_192
,
1380 .cfg_dec
= CIPH_DECR
| MOD_DES
| MOD_CBC_DEC
| KEYLEN_192
,
1383 .cra_name
= "authenc(hmac(sha1),cbc(des3_ede))",
1384 .cra_blocksize
= DES3_EDE_BLOCK_SIZE
,
1385 .cra_u
= { .aead
= {
1386 .ivsize
= DES3_EDE_BLOCK_SIZE
,
1387 .maxauthsize
= SHA1_DIGEST_SIZE
,
1391 .hash
= &hash_alg_sha1
,
1392 .cfg_enc
= CIPH_ENCR
| MOD_3DES
| MOD_CBC_ENC
| KEYLEN_192
,
1393 .cfg_dec
= CIPH_DECR
| MOD_3DES
| MOD_CBC_DEC
| KEYLEN_192
,
1396 .cra_name
= "authenc(hmac(md5),cbc(aes))",
1397 .cra_blocksize
= AES_BLOCK_SIZE
,
1398 .cra_u
= { .aead
= {
1399 .ivsize
= AES_BLOCK_SIZE
,
1400 .maxauthsize
= MD5_DIGEST_SIZE
,
1404 .hash
= &hash_alg_md5
,
1405 .cfg_enc
= CIPH_ENCR
| MOD_AES
| MOD_CBC_ENC
,
1406 .cfg_dec
= CIPH_DECR
| MOD_AES
| MOD_CBC_DEC
,
1409 .cra_name
= "authenc(hmac(sha1),cbc(aes))",
1410 .cra_blocksize
= AES_BLOCK_SIZE
,
1411 .cra_u
= { .aead
= {
1412 .ivsize
= AES_BLOCK_SIZE
,
1413 .maxauthsize
= SHA1_DIGEST_SIZE
,
1417 .hash
= &hash_alg_sha1
,
1418 .cfg_enc
= CIPH_ENCR
| MOD_AES
| MOD_CBC_ENC
,
1419 .cfg_dec
= CIPH_DECR
| MOD_AES
| MOD_CBC_DEC
,
1422 #define IXP_POSTFIX "-ixp4xx"
1423 static int __init
ixp_module_init(void)
1425 int num
= ARRAY_SIZE(ixp4xx_algos
);
1428 if (platform_device_register(&pseudo_dev
))
1431 spin_lock_init(&desc_lock
);
1432 spin_lock_init(&emerg_lock
);
1434 err
= init_ixp_crypto();
1436 platform_device_unregister(&pseudo_dev
);
1439 for (i
=0; i
< num
; i
++) {
1440 struct crypto_alg
*cra
= &ixp4xx_algos
[i
].crypto
;
1442 if (snprintf(cra
->cra_driver_name
, CRYPTO_MAX_ALG_NAME
,
1443 "%s"IXP_POSTFIX
, cra
->cra_name
) >=
1444 CRYPTO_MAX_ALG_NAME
)
1448 if (!support_aes
&& (ixp4xx_algos
[i
].cfg_enc
& MOD_AES
)) {
1451 if (!ixp4xx_algos
[i
].hash
) {
1453 cra
->cra_type
= &crypto_ablkcipher_type
;
1454 cra
->cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
|
1456 if (!cra
->cra_ablkcipher
.setkey
)
1457 cra
->cra_ablkcipher
.setkey
= ablk_setkey
;
1458 if (!cra
->cra_ablkcipher
.encrypt
)
1459 cra
->cra_ablkcipher
.encrypt
= ablk_encrypt
;
1460 if (!cra
->cra_ablkcipher
.decrypt
)
1461 cra
->cra_ablkcipher
.decrypt
= ablk_decrypt
;
1462 cra
->cra_init
= init_tfm_ablk
;
1465 cra
->cra_type
= &crypto_aead_type
;
1466 cra
->cra_flags
= CRYPTO_ALG_TYPE_AEAD
|
1468 cra
->cra_aead
.setkey
= aead_setkey
;
1469 cra
->cra_aead
.setauthsize
= aead_setauthsize
;
1470 cra
->cra_aead
.encrypt
= aead_encrypt
;
1471 cra
->cra_aead
.decrypt
= aead_decrypt
;
1472 cra
->cra_aead
.givencrypt
= aead_givencrypt
;
1473 cra
->cra_init
= init_tfm_aead
;
1475 cra
->cra_ctxsize
= sizeof(struct ixp_ctx
);
1476 cra
->cra_module
= THIS_MODULE
;
1477 cra
->cra_alignmask
= 3;
1478 cra
->cra_priority
= 300;
1479 cra
->cra_exit
= exit_tfm
;
1480 if (crypto_register_alg(cra
))
1481 printk(KERN_ERR
"Failed to register '%s'\n",
1484 ixp4xx_algos
[i
].registered
= 1;
1489 static void __exit
ixp_module_exit(void)
1491 int num
= ARRAY_SIZE(ixp4xx_algos
);
1494 for (i
=0; i
< num
; i
++) {
1495 if (ixp4xx_algos
[i
].registered
)
1496 crypto_unregister_alg(&ixp4xx_algos
[i
].crypto
);
1498 release_ixp_crypto();
1499 platform_device_unregister(&pseudo_dev
);
1502 module_init(ixp_module_init
);
1503 module_exit(ixp_module_exit
);
1505 MODULE_LICENSE("GPL");
1506 MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
1507 MODULE_DESCRIPTION("IXP4xx hardware crypto");