drivers/crypto/marvell/cesa.c

   1 /*
   2  * Support for Marvell's Cryptographic Engine and Security Accelerator (CESA)
   3  * that can be found on the following platform: Orion, Kirkwood, Armada. This
   4  * driver supports the TDMA engine on platforms on which it is available.
   5  *
   6  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   7  * Author: Arnaud Ebalard <arno@natisbad.org>
   8  *
   9  * This work is based on an initial version written by
  10  * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms of the GNU General Public License version 2 as published
  14  * by the Free Software Foundation.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/genalloc.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/kthread.h>
  22 #include <linux/mbus.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/scatterlist.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/of_irq.h>
  31
  32 #include "cesa.h"
  33
  34 struct mv_cesa_dev *cesa_dev;
  35
  36 static void mv_cesa_dequeue_req_unlocked(struct mv_cesa_engine *engine)
  37 {
  38         struct crypto_async_request *req, *backlog;
  39         struct mv_cesa_ctx *ctx;
  40
  41         spin_lock_bh(&cesa_dev->lock);
  42         backlog = crypto_get_backlog(&cesa_dev->queue);
  43         req = crypto_dequeue_request(&cesa_dev->queue);
  44         engine->req = req;
  45         spin_unlock_bh(&cesa_dev->lock);
  46
  47         if (!req)
  48                 return;
  49
  50         if (backlog)
  51                 backlog->complete(backlog, -EINPROGRESS);
  52
  53         ctx = crypto_tfm_ctx(req->tfm);
  54         ctx->ops->prepare(req, engine);
  55         ctx->ops->step(req);
  56 }
  57
  58 static irqreturn_t mv_cesa_int(int irq, void *priv)
  59 {
  60         struct mv_cesa_engine *engine = priv;
  61         struct crypto_async_request *req;
  62         struct mv_cesa_ctx *ctx;
  63         u32 status, mask;
  64         irqreturn_t ret = IRQ_NONE;
  65
  66         while (true) {
  67                 int res;
  68
  69                 mask = mv_cesa_get_int_mask(engine);
  70                 status = readl(engine->regs + CESA_SA_INT_STATUS);
  71
  72                 if (!(status & mask))
  73                         break;
  74
  75                 /*
  76                  * TODO: avoid clearing the FPGA_INT_STATUS if this not
  77                  * relevant on some platforms.
  78                  */
  79                 writel(~status, engine->regs + CESA_SA_FPGA_INT_STATUS);
  80                 writel(~status, engine->regs + CESA_SA_INT_STATUS);
  81
  82                 ret = IRQ_HANDLED;
  83                 spin_lock_bh(&engine->lock);
  84                 req = engine->req;
  85                 spin_unlock_bh(&engine->lock);
  86                 if (req) {
  87                         ctx = crypto_tfm_ctx(req->tfm);
  88                         res = ctx->ops->process(req, status & mask);
  89                         if (res != -EINPROGRESS) {
  90                                 spin_lock_bh(&engine->lock);
  91                                 engine->req = NULL;
  92                                 mv_cesa_dequeue_req_unlocked(engine);
  93                                 spin_unlock_bh(&engine->lock);
  94                                 ctx->ops->cleanup(req);
  95                                 local_bh_disable();
  96                                 req->complete(req, res);
  97                                 local_bh_enable();
  98                         } else {
  99                                 ctx->ops->step(req);
 100                         }
 101                 }
 102         }
 103
 104         return ret;
 105 }
 106
 107 int mv_cesa_queue_req(struct crypto_async_request *req)
 108 {
 109         int ret;
 110         int i;
 111
 112         spin_lock_bh(&cesa_dev->lock);
 113         ret = crypto_enqueue_request(&cesa_dev->queue, req);
 114         spin_unlock_bh(&cesa_dev->lock);
 115
 116         if (ret != -EINPROGRESS)
 117                 return ret;
 118
 119         for (i = 0; i < cesa_dev->caps->nengines; i++) {
 120                 spin_lock_bh(&cesa_dev->engines[i].lock);
 121                 if (!cesa_dev->engines[i].req)
 122                         mv_cesa_dequeue_req_unlocked(&cesa_dev->engines[i]);
 123                 spin_unlock_bh(&cesa_dev->engines[i].lock);
 124         }
 125
 126         return -EINPROGRESS;
 127 }
 128
 129 static int mv_cesa_add_algs(struct mv_cesa_dev *cesa)
 130 {
 131         int ret;
 132         int i, j;
 133
 134         for (i = 0; i < cesa->caps->ncipher_algs; i++) {
 135                 ret = crypto_register_alg(cesa->caps->cipher_algs[i]);
 136                 if (ret)
 137                         goto err_unregister_crypto;
 138         }
 139
 140         for (i = 0; i < cesa->caps->nahash_algs; i++) {
 141                 ret = crypto_register_ahash(cesa->caps->ahash_algs[i]);
 142                 if (ret)
 143                         goto err_unregister_ahash;
 144         }
 145
 146         return 0;
 147
 148 err_unregister_ahash:
 149         for (j = 0; j < i; j++)
 150                 crypto_unregister_ahash(cesa->caps->ahash_algs[j]);
 151         i = cesa->caps->ncipher_algs;
 152
 153 err_unregister_crypto:
 154         for (j = 0; j < i; j++)
 155                 crypto_unregister_alg(cesa->caps->cipher_algs[j]);
 156
 157         return ret;
 158 }
 159
 160 static void mv_cesa_remove_algs(struct mv_cesa_dev *cesa)
 161 {
 162         int i;
 163
 164         for (i = 0; i < cesa->caps->nahash_algs; i++)
 165                 crypto_unregister_ahash(cesa->caps->ahash_algs[i]);
 166
 167         for (i = 0; i < cesa->caps->ncipher_algs; i++)
 168                 crypto_unregister_alg(cesa->caps->cipher_algs[i]);
 169 }
 170
 171 static struct crypto_alg *armada_370_cipher_algs[] = {
 172         &mv_cesa_ecb_des_alg,
 173         &mv_cesa_cbc_des_alg,
 174         &mv_cesa_ecb_aes_alg,
 175         &mv_cesa_cbc_aes_alg,
 176 };
 177
 178 static struct ahash_alg *armada_370_ahash_algs[] = {
 179         &mv_sha1_alg,
 180         &mv_ahmac_sha1_alg,
 181 };
 182
 183 static const struct mv_cesa_caps armada_370_caps = {
 184         .nengines = 1,
 185         .cipher_algs = armada_370_cipher_algs,
 186         .ncipher_algs = ARRAY_SIZE(armada_370_cipher_algs),
 187         .ahash_algs = armada_370_ahash_algs,
 188         .nahash_algs = ARRAY_SIZE(armada_370_ahash_algs),
 189         .has_tdma = true,
 190 };
 191
 192 static const struct of_device_id mv_cesa_of_match_table[] = {
 193         { .compatible = "marvell,armada-370-crypto", .data = &armada_370_caps },
 194         {}
 195 };
 196 MODULE_DEVICE_TABLE(of, mv_cesa_of_match_table);
 197
 198 static void
 199 mv_cesa_conf_mbus_windows(struct mv_cesa_engine *engine,
 200                           const struct mbus_dram_target_info *dram)
 201 {
 202         void __iomem *iobase = engine->regs;
 203         int i;
 204
 205         for (i = 0; i < 4; i++) {
 206                 writel(0, iobase + CESA_TDMA_WINDOW_CTRL(i));
 207                 writel(0, iobase + CESA_TDMA_WINDOW_BASE(i));
 208         }
 209
 210         for (i = 0; i < dram->num_cs; i++) {
 211                 const struct mbus_dram_window *cs = dram->cs + i;
 212
 213                 writel(((cs->size - 1) & 0xffff0000) |
 214                        (cs->mbus_attr << 8) |
 215                        (dram->mbus_dram_target_id << 4) | 1,
 216                        iobase + CESA_TDMA_WINDOW_CTRL(i));
 217                 writel(cs->base, iobase + CESA_TDMA_WINDOW_BASE(i));
 218         }
 219 }
 220
 221 static int mv_cesa_dev_dma_init(struct mv_cesa_dev *cesa)
 222 {
 223         struct device *dev = cesa->dev;
 224         struct mv_cesa_dev_dma *dma;
 225
 226         if (!cesa->caps->has_tdma)
 227                 return 0;
 228
 229         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 230         if (!dma)
 231                 return -ENOMEM;
 232
 233         dma->tdma_desc_pool = dmam_pool_create("tdma_desc", dev,
 234                                         sizeof(struct mv_cesa_tdma_desc),
 235                                         16, 0);
 236         if (!dma->tdma_desc_pool)
 237                 return -ENOMEM;
 238
 239         dma->op_pool = dmam_pool_create("cesa_op", dev,
 240                                         sizeof(struct mv_cesa_op_ctx), 16, 0);
 241         if (!dma->op_pool)
 242                 return -ENOMEM;
 243
 244         dma->cache_pool = dmam_pool_create("cesa_cache", dev,
 245                                            CESA_MAX_HASH_BLOCK_SIZE, 1, 0);
 246         if (!dma->cache_pool)
 247                 return -ENOMEM;
 248
 249         dma->padding_pool = dmam_pool_create("cesa_padding", dev, 72, 1, 0);
 250         if (!dma->cache_pool)
 251                 return -ENOMEM;
 252
 253         cesa->dma = dma;
 254
 255         return 0;
 256 }
 257
 258 static int mv_cesa_get_sram(struct platform_device *pdev, int idx)
 259 {
 260         struct mv_cesa_dev *cesa = platform_get_drvdata(pdev);
 261         struct mv_cesa_engine *engine = &cesa->engines[idx];
 262         const char *res_name = "sram";
 263         struct resource *res;
 264
 265         engine->pool = of_get_named_gen_pool(cesa->dev->of_node,
 266                                              "marvell,crypto-srams",
 267                                              idx);
 268         if (engine->pool) {
 269                 engine->sram = gen_pool_dma_alloc(engine->pool,
 270                                                   cesa->sram_size,
 271                                                   &engine->sram_dma);
 272                 if (engine->sram)
 273                         return 0;
 274
 275                 engine->pool = NULL;
 276                 return -ENOMEM;
 277         }
 278
 279         if (cesa->caps->nengines > 1) {
 280                 if (!idx)
 281                         res_name = "sram0";
 282                 else
 283                         res_name = "sram1";
 284         }
 285
 286         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 287                                            res_name);
 288         if (!res || resource_size(res) < cesa->sram_size)
 289                 return -EINVAL;
 290
 291         engine->sram = devm_ioremap_resource(cesa->dev, res);
 292         if (IS_ERR(engine->sram))
 293                 return PTR_ERR(engine->sram);
 294
 295         engine->sram_dma = phys_to_dma(cesa->dev,
 296                                        (phys_addr_t)res->start);
 297
 298         return 0;
 299 }
 300
 301 static void mv_cesa_put_sram(struct platform_device *pdev, int idx)
 302 {
 303         struct mv_cesa_dev *cesa = platform_get_drvdata(pdev);
 304         struct mv_cesa_engine *engine = &cesa->engines[idx];
 305
 306         if (!engine->pool)
 307                 return;
 308
 309         gen_pool_free(engine->pool, (unsigned long)engine->sram,
 310                       cesa->sram_size);
 311 }
 312
 313 static int mv_cesa_probe(struct platform_device *pdev)
 314 {
 315         const struct mv_cesa_caps *caps = NULL;
 316         const struct mbus_dram_target_info *dram;
 317         const struct of_device_id *match;
 318         struct device *dev = &pdev->dev;
 319         struct mv_cesa_dev *cesa;
 320         struct mv_cesa_engine *engines;
 321         struct resource *res;
 322         int irq, ret, i;
 323         u32 sram_size;
 324
 325         if (cesa_dev) {
 326                 dev_err(&pdev->dev, "Only one CESA device authorized\n");
 327                 return -EEXIST;
 328         }
 329
 330         if (!dev->of_node)
 331                 return -ENOTSUPP;
 332
 333         match = of_match_node(mv_cesa_of_match_table, dev->of_node);
 334         if (!match || !match->data)
 335                 return -ENOTSUPP;
 336
 337         caps = match->data;
 338
 339         cesa = devm_kzalloc(dev, sizeof(*cesa), GFP_KERNEL);
 340         if (!cesa)
 341                 return -ENOMEM;
 342
 343         cesa->caps = caps;
 344         cesa->dev = dev;
 345
 346         sram_size = CESA_SA_DEFAULT_SRAM_SIZE;
 347         of_property_read_u32(cesa->dev->of_node, "marvell,crypto-sram-size",
 348                              &sram_size);
 349         if (sram_size < CESA_SA_MIN_SRAM_SIZE)
 350                 sram_size = CESA_SA_MIN_SRAM_SIZE;
 351
 352         cesa->sram_size = sram_size;
 353         cesa->engines = devm_kzalloc(dev, caps->nengines * sizeof(*engines),
 354                                      GFP_KERNEL);
 355         if (!cesa->engines)
 356                 return -ENOMEM;
 357
 358         spin_lock_init(&cesa->lock);
 359         crypto_init_queue(&cesa->queue, 50);
 360         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 361         cesa->regs = devm_ioremap_resource(dev, res);
 362         if (IS_ERR(cesa->regs))
 363                 return -ENOMEM;
 364
 365         ret = mv_cesa_dev_dma_init(cesa);
 366         if (ret)
 367                 return ret;
 368
 369         dram = mv_mbus_dram_info_nooverlap();
 370
 371         platform_set_drvdata(pdev, cesa);
 372
 373         for (i = 0; i < caps->nengines; i++) {
 374                 struct mv_cesa_engine *engine = &cesa->engines[i];
 375                 char res_name[7];
 376
 377                 engine->id = i;
 378                 spin_lock_init(&engine->lock);
 379
 380                 ret = mv_cesa_get_sram(pdev, i);
 381                 if (ret)
 382                         goto err_cleanup;
 383
 384                 irq = platform_get_irq(pdev, i);
 385                 if (irq < 0) {
 386                         ret = irq;
 387                         goto err_cleanup;
 388                 }
 389
 390                 /*
 391                  * Not all platforms can gate the CESA clocks: do not complain
 392                  * if the clock does not exist.
 393                  */
 394                 snprintf(res_name, sizeof(res_name), "cesa%d", i);
 395                 engine->clk = devm_clk_get(dev, res_name);
 396                 if (IS_ERR(engine->clk)) {
 397                         engine->clk = devm_clk_get(dev, NULL);
 398                         if (IS_ERR(engine->clk))
 399                                 engine->clk = NULL;
 400                 }
 401
 402                 snprintf(res_name, sizeof(res_name), "cesaz%d", i);
 403                 engine->zclk = devm_clk_get(dev, res_name);
 404                 if (IS_ERR(engine->zclk))
 405                         engine->zclk = NULL;
 406
 407                 ret = clk_prepare_enable(engine->clk);
 408                 if (ret)
 409                         goto err_cleanup;
 410
 411                 ret = clk_prepare_enable(engine->zclk);
 412                 if (ret)
 413                         goto err_cleanup;
 414
 415                 engine->regs = cesa->regs + CESA_ENGINE_OFF(i);
 416
 417                 if (dram && cesa->caps->has_tdma)
 418                         mv_cesa_conf_mbus_windows(&cesa->engines[i], dram);
 419
 420                 writel(0, cesa->engines[i].regs + CESA_SA_INT_STATUS);
 421                 writel(CESA_SA_CFG_STOP_DIG_ERR,
 422                        cesa->engines[i].regs + CESA_SA_CFG);
 423                 writel(engine->sram_dma & CESA_SA_SRAM_MSK,
 424                        cesa->engines[i].regs + CESA_SA_DESC_P0);
 425
 426                 ret = devm_request_threaded_irq(dev, irq, NULL, mv_cesa_int,
 427                                                 IRQF_ONESHOT,
 428                                                 dev_name(&pdev->dev),
 429                                                 &cesa->engines[i]);
 430                 if (ret)
 431                         goto err_cleanup;
 432         }
 433
 434         cesa_dev = cesa;
 435
 436         ret = mv_cesa_add_algs(cesa);
 437         if (ret) {
 438                 cesa_dev = NULL;
 439                 goto err_cleanup;
 440         }
 441
 442         dev_info(dev, "CESA device successfully registered\n");
 443
 444         return 0;
 445
 446 err_cleanup:
 447         for (i = 0; i < caps->nengines; i++) {
 448                 clk_disable_unprepare(cesa->engines[i].zclk);
 449                 clk_disable_unprepare(cesa->engines[i].clk);
 450                 mv_cesa_put_sram(pdev, i);
 451         }
 452
 453         return ret;
 454 }
 455
 456 static int mv_cesa_remove(struct platform_device *pdev)
 457 {
 458         struct mv_cesa_dev *cesa = platform_get_drvdata(pdev);
 459         int i;
 460
 461         mv_cesa_remove_algs(cesa);
 462
 463         for (i = 0; i < cesa->caps->nengines; i++) {
 464                 clk_disable_unprepare(cesa->engines[i].zclk);
 465                 clk_disable_unprepare(cesa->engines[i].clk);
 466                 mv_cesa_put_sram(pdev, i);
 467         }
 468
 469         return 0;
 470 }
 471
 472 static struct platform_driver marvell_cesa = {
 473         .probe          = mv_cesa_probe,
 474         .remove         = mv_cesa_remove,
 475         .driver         = {
 476                 .owner  = THIS_MODULE,
 477                 .name   = "marvell-cesa",
 478                 .of_match_table = mv_cesa_of_match_table,
 479         },
 480 };
 481 module_platform_driver(marvell_cesa);
 482
 483 MODULE_ALIAS("platform:mv_crypto");
 484 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
 485 MODULE_AUTHOR("Arnaud Ebalard <arno@natisbad.org>");
 486 MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
 487 MODULE_LICENSE("GPL v2");