2 * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256.
4 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
5 * Author: Arnaud Ebalard <arno@natisbad.org>
7 * This work is based on an initial version written by
8 * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #include <crypto/md5.h>
16 #include <crypto/sha.h>
20 struct mv_cesa_ahash_dma_iter
{
21 struct mv_cesa_dma_iter base
;
22 struct mv_cesa_sg_dma_iter src
;
26 mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter
*iter
,
27 struct ahash_request
*req
)
29 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
30 unsigned int len
= req
->nbytes
;
33 len
= (len
+ creq
->cache_ptr
) & ~CESA_HASH_BLOCK_SIZE_MSK
;
35 mv_cesa_req_dma_iter_init(&iter
->base
, len
);
36 mv_cesa_sg_dma_iter_init(&iter
->src
, req
->src
, DMA_TO_DEVICE
);
37 iter
->src
.op_offset
= creq
->cache_ptr
;
41 mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter
*iter
)
43 iter
->src
.op_offset
= 0;
45 return mv_cesa_req_dma_iter_next_op(&iter
->base
);
48 static inline int mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_req
*creq
,
51 struct mv_cesa_ahash_dma_req
*dreq
= &creq
->req
.dma
;
53 creq
->cache
= dma_pool_alloc(cesa_dev
->dma
->cache_pool
, flags
,
61 static inline int mv_cesa_ahash_std_alloc_cache(struct mv_cesa_ahash_req
*creq
,
64 creq
->cache
= kzalloc(CESA_MAX_HASH_BLOCK_SIZE
, flags
);
71 static int mv_cesa_ahash_alloc_cache(struct ahash_request
*req
)
73 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
74 gfp_t flags
= (req
->base
.flags
& CRYPTO_TFM_REQ_MAY_SLEEP
) ?
75 GFP_KERNEL
: GFP_ATOMIC
;
81 if (creq
->req
.base
.type
== CESA_DMA_REQ
)
82 ret
= mv_cesa_ahash_dma_alloc_cache(creq
, flags
);
84 ret
= mv_cesa_ahash_std_alloc_cache(creq
, flags
);
89 static inline void mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_req
*creq
)
91 dma_pool_free(cesa_dev
->dma
->cache_pool
, creq
->cache
,
92 creq
->req
.dma
.cache_dma
);
95 static inline void mv_cesa_ahash_std_free_cache(struct mv_cesa_ahash_req
*creq
)
100 static void mv_cesa_ahash_free_cache(struct mv_cesa_ahash_req
*creq
)
105 if (creq
->req
.base
.type
== CESA_DMA_REQ
)
106 mv_cesa_ahash_dma_free_cache(creq
);
108 mv_cesa_ahash_std_free_cache(creq
);
113 static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req
*req
,
119 req
->padding
= dma_pool_alloc(cesa_dev
->dma
->padding_pool
, flags
,
127 static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req
*req
)
132 dma_pool_free(cesa_dev
->dma
->padding_pool
, req
->padding
,
137 static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request
*req
)
139 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
141 mv_cesa_ahash_dma_free_padding(&creq
->req
.dma
);
144 static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request
*req
)
146 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
148 dma_unmap_sg(cesa_dev
->dev
, req
->src
, creq
->src_nents
, DMA_TO_DEVICE
);
149 mv_cesa_dma_cleanup(&creq
->req
.dma
.base
);
152 static inline void mv_cesa_ahash_cleanup(struct ahash_request
*req
)
154 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
156 if (creq
->req
.base
.type
== CESA_DMA_REQ
)
157 mv_cesa_ahash_dma_cleanup(req
);
160 static void mv_cesa_ahash_last_cleanup(struct ahash_request
*req
)
162 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
164 mv_cesa_ahash_free_cache(creq
);
166 if (creq
->req
.base
.type
== CESA_DMA_REQ
)
167 mv_cesa_ahash_dma_last_cleanup(req
);
170 static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req
*creq
)
172 unsigned int index
, padlen
;
174 index
= creq
->len
& CESA_HASH_BLOCK_SIZE_MSK
;
175 padlen
= (index
< 56) ? (56 - index
) : (64 + 56 - index
);
180 static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req
*creq
, u8
*buf
)
182 __be64 bits
= cpu_to_be64(creq
->len
<< 3);
183 unsigned int index
, padlen
;
186 /* Pad out to 56 mod 64 */
187 index
= creq
->len
& CESA_HASH_BLOCK_SIZE_MSK
;
188 padlen
= mv_cesa_ahash_pad_len(creq
);
189 memset(buf
+ 1, 0, padlen
- 1);
190 memcpy(buf
+ padlen
, &bits
, sizeof(bits
));
195 static void mv_cesa_ahash_std_step(struct ahash_request
*req
)
197 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
198 struct mv_cesa_ahash_std_req
*sreq
= &creq
->req
.std
;
199 struct mv_cesa_engine
*engine
= sreq
->base
.engine
;
200 struct mv_cesa_op_ctx
*op
;
201 unsigned int new_cache_ptr
= 0;
206 memcpy(engine
->sram
+ CESA_SA_DATA_SRAM_OFFSET
, creq
->cache
,
209 len
= min_t(size_t, req
->nbytes
+ creq
->cache_ptr
- sreq
->offset
,
210 CESA_SA_SRAM_PAYLOAD_SIZE
);
212 if (!creq
->last_req
) {
213 new_cache_ptr
= len
& CESA_HASH_BLOCK_SIZE_MSK
;
214 len
&= ~CESA_HASH_BLOCK_SIZE_MSK
;
217 if (len
- creq
->cache_ptr
)
218 sreq
->offset
+= sg_pcopy_to_buffer(req
->src
, creq
->src_nents
,
220 CESA_SA_DATA_SRAM_OFFSET
+
222 len
- creq
->cache_ptr
,
227 frag_mode
= mv_cesa_get_op_cfg(op
) & CESA_SA_DESC_CFG_FRAG_MSK
;
229 if (creq
->last_req
&& sreq
->offset
== req
->nbytes
&&
230 creq
->len
<= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX
) {
231 if (frag_mode
== CESA_SA_DESC_CFG_FIRST_FRAG
)
232 frag_mode
= CESA_SA_DESC_CFG_NOT_FRAG
;
233 else if (frag_mode
== CESA_SA_DESC_CFG_MID_FRAG
)
234 frag_mode
= CESA_SA_DESC_CFG_LAST_FRAG
;
237 if (frag_mode
== CESA_SA_DESC_CFG_NOT_FRAG
||
238 frag_mode
== CESA_SA_DESC_CFG_LAST_FRAG
) {
240 creq
->len
<= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX
) {
241 mv_cesa_set_mac_op_total_len(op
, creq
->len
);
243 int trailerlen
= mv_cesa_ahash_pad_len(creq
) + 8;
245 if (len
+ trailerlen
> CESA_SA_SRAM_PAYLOAD_SIZE
) {
246 len
&= CESA_HASH_BLOCK_SIZE_MSK
;
247 new_cache_ptr
= 64 - trailerlen
;
250 CESA_SA_DATA_SRAM_OFFSET
+ len
,
253 len
+= mv_cesa_ahash_pad_req(creq
,
255 CESA_SA_DATA_SRAM_OFFSET
);
258 if (frag_mode
== CESA_SA_DESC_CFG_LAST_FRAG
)
259 frag_mode
= CESA_SA_DESC_CFG_MID_FRAG
;
261 frag_mode
= CESA_SA_DESC_CFG_FIRST_FRAG
;
265 mv_cesa_set_mac_op_frag_len(op
, len
);
266 mv_cesa_update_op_cfg(op
, frag_mode
, CESA_SA_DESC_CFG_FRAG_MSK
);
268 /* FIXME: only update enc_len field */
269 memcpy(engine
->sram
, op
, sizeof(*op
));
271 if (frag_mode
== CESA_SA_DESC_CFG_FIRST_FRAG
)
272 mv_cesa_update_op_cfg(op
, CESA_SA_DESC_CFG_MID_FRAG
,
273 CESA_SA_DESC_CFG_FRAG_MSK
);
275 creq
->cache_ptr
= new_cache_ptr
;
277 mv_cesa_set_int_mask(engine
, CESA_SA_INT_ACCEL0_DONE
);
278 writel(CESA_SA_CFG_PARA_DIS
, engine
->regs
+ CESA_SA_CFG
);
279 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0
, engine
->regs
+ CESA_SA_CMD
);
282 static int mv_cesa_ahash_std_process(struct ahash_request
*req
, u32 status
)
284 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
285 struct mv_cesa_ahash_std_req
*sreq
= &creq
->req
.std
;
287 if (sreq
->offset
< (req
->nbytes
- creq
->cache_ptr
))
293 static inline void mv_cesa_ahash_dma_prepare(struct ahash_request
*req
)
295 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
296 struct mv_cesa_tdma_req
*dreq
= &creq
->req
.dma
.base
;
298 mv_cesa_dma_prepare(dreq
, dreq
->base
.engine
);
301 static void mv_cesa_ahash_std_prepare(struct ahash_request
*req
)
303 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
304 struct mv_cesa_ahash_std_req
*sreq
= &creq
->req
.std
;
305 struct mv_cesa_engine
*engine
= sreq
->base
.engine
;
308 mv_cesa_adjust_op(engine
, &creq
->op_tmpl
);
309 memcpy(engine
->sram
, &creq
->op_tmpl
, sizeof(creq
->op_tmpl
));
312 static void mv_cesa_ahash_step(struct crypto_async_request
*req
)
314 struct ahash_request
*ahashreq
= ahash_request_cast(req
);
315 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(ahashreq
);
317 if (creq
->req
.base
.type
== CESA_DMA_REQ
)
318 mv_cesa_dma_step(&creq
->req
.dma
.base
);
320 mv_cesa_ahash_std_step(ahashreq
);
323 static int mv_cesa_ahash_process(struct crypto_async_request
*req
, u32 status
)
325 struct ahash_request
*ahashreq
= ahash_request_cast(req
);
326 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(ahashreq
);
327 struct mv_cesa_engine
*engine
= creq
->req
.base
.engine
;
328 unsigned int digsize
;
331 if (creq
->req
.base
.type
== CESA_DMA_REQ
)
332 ret
= mv_cesa_dma_process(&creq
->req
.dma
.base
, status
);
334 ret
= mv_cesa_ahash_std_process(ahashreq
, status
);
336 if (ret
== -EINPROGRESS
)
339 digsize
= crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq
));
340 for (i
= 0; i
< digsize
/ 4; i
++)
341 creq
->state
[i
] = readl(engine
->regs
+ CESA_IVDIG(i
));
344 sg_pcopy_to_buffer(ahashreq
->src
, creq
->src_nents
,
347 ahashreq
->nbytes
- creq
->cache_ptr
);
349 if (creq
->last_req
) {
350 for (i
= 0; i
< digsize
/ 4; i
++) {
352 * Hardware provides MD5 digest in a different
353 * endianness than SHA-1 and SHA-256 ones.
355 if (digsize
== MD5_DIGEST_SIZE
)
356 creq
->state
[i
] = cpu_to_le32(creq
->state
[i
]);
358 creq
->state
[i
] = cpu_to_be32(creq
->state
[i
]);
361 memcpy(ahashreq
->result
, creq
->state
, digsize
);
367 static void mv_cesa_ahash_prepare(struct crypto_async_request
*req
,
368 struct mv_cesa_engine
*engine
)
370 struct ahash_request
*ahashreq
= ahash_request_cast(req
);
371 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(ahashreq
);
372 unsigned int digsize
;
375 creq
->req
.base
.engine
= engine
;
377 if (creq
->req
.base
.type
== CESA_DMA_REQ
)
378 mv_cesa_ahash_dma_prepare(ahashreq
);
380 mv_cesa_ahash_std_prepare(ahashreq
);
382 digsize
= crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq
));
383 for (i
= 0; i
< digsize
/ 4; i
++)
384 writel(creq
->state
[i
],
385 engine
->regs
+ CESA_IVDIG(i
));
388 static void mv_cesa_ahash_req_cleanup(struct crypto_async_request
*req
)
390 struct ahash_request
*ahashreq
= ahash_request_cast(req
);
391 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(ahashreq
);
394 mv_cesa_ahash_last_cleanup(ahashreq
);
396 mv_cesa_ahash_cleanup(ahashreq
);
399 static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops
= {
400 .step
= mv_cesa_ahash_step
,
401 .process
= mv_cesa_ahash_process
,
402 .prepare
= mv_cesa_ahash_prepare
,
403 .cleanup
= mv_cesa_ahash_req_cleanup
,
406 static int mv_cesa_ahash_init(struct ahash_request
*req
,
407 struct mv_cesa_op_ctx
*tmpl
)
409 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
411 memset(creq
, 0, sizeof(*creq
));
412 mv_cesa_update_op_cfg(tmpl
,
413 CESA_SA_DESC_CFG_OP_MAC_ONLY
|
414 CESA_SA_DESC_CFG_FIRST_FRAG
,
415 CESA_SA_DESC_CFG_OP_MSK
|
416 CESA_SA_DESC_CFG_FRAG_MSK
);
417 mv_cesa_set_mac_op_total_len(tmpl
, 0);
418 mv_cesa_set_mac_op_frag_len(tmpl
, 0);
419 creq
->op_tmpl
= *tmpl
;
425 static inline int mv_cesa_ahash_cra_init(struct crypto_tfm
*tfm
)
427 struct mv_cesa_hash_ctx
*ctx
= crypto_tfm_ctx(tfm
);
429 ctx
->base
.ops
= &mv_cesa_ahash_req_ops
;
431 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm
),
432 sizeof(struct mv_cesa_ahash_req
));
436 static int mv_cesa_ahash_cache_req(struct ahash_request
*req
, bool *cached
)
438 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
441 if (((creq
->cache_ptr
+ req
->nbytes
) & CESA_HASH_BLOCK_SIZE_MSK
) &&
443 ret
= mv_cesa_ahash_alloc_cache(req
);
448 if (creq
->cache_ptr
+ req
->nbytes
< 64 && !creq
->last_req
) {
454 sg_pcopy_to_buffer(req
->src
, creq
->src_nents
,
455 creq
->cache
+ creq
->cache_ptr
,
458 creq
->cache_ptr
+= req
->nbytes
;
464 static struct mv_cesa_op_ctx
*
465 mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain
*chain
,
466 struct mv_cesa_ahash_dma_iter
*dma_iter
,
467 struct mv_cesa_ahash_req
*creq
,
470 struct mv_cesa_ahash_dma_req
*ahashdreq
= &creq
->req
.dma
;
471 struct mv_cesa_op_ctx
*op
= NULL
;
474 if (!creq
->cache_ptr
)
477 ret
= mv_cesa_dma_add_data_transfer(chain
,
478 CESA_SA_DATA_SRAM_OFFSET
,
479 ahashdreq
->cache_dma
,
481 CESA_TDMA_DST_IN_SRAM
,
486 if (!dma_iter
->base
.op_len
) {
487 op
= mv_cesa_dma_add_op(chain
, &creq
->op_tmpl
, false, flags
);
491 mv_cesa_set_mac_op_frag_len(op
, creq
->cache_ptr
);
493 /* Add dummy desc to launch crypto operation */
494 ret
= mv_cesa_dma_add_dummy_launch(chain
, flags
);
502 static struct mv_cesa_op_ctx
*
503 mv_cesa_ahash_dma_add_data(struct mv_cesa_tdma_chain
*chain
,
504 struct mv_cesa_ahash_dma_iter
*dma_iter
,
505 struct mv_cesa_ahash_req
*creq
,
508 struct mv_cesa_op_ctx
*op
;
511 op
= mv_cesa_dma_add_op(chain
, &creq
->op_tmpl
, false, flags
);
515 mv_cesa_set_mac_op_frag_len(op
, dma_iter
->base
.op_len
);
517 if ((mv_cesa_get_op_cfg(&creq
->op_tmpl
) & CESA_SA_DESC_CFG_FRAG_MSK
) ==
518 CESA_SA_DESC_CFG_FIRST_FRAG
)
519 mv_cesa_update_op_cfg(&creq
->op_tmpl
,
520 CESA_SA_DESC_CFG_MID_FRAG
,
521 CESA_SA_DESC_CFG_FRAG_MSK
);
523 /* Add input transfers */
524 ret
= mv_cesa_dma_add_op_transfers(chain
, &dma_iter
->base
,
525 &dma_iter
->src
, flags
);
529 /* Add dummy desc to launch crypto operation */
530 ret
= mv_cesa_dma_add_dummy_launch(chain
, flags
);
537 static struct mv_cesa_op_ctx
*
538 mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain
*chain
,
539 struct mv_cesa_ahash_dma_iter
*dma_iter
,
540 struct mv_cesa_ahash_req
*creq
,
541 struct mv_cesa_op_ctx
*op
,
544 struct mv_cesa_ahash_dma_req
*ahashdreq
= &creq
->req
.dma
;
545 unsigned int len
, trailerlen
, padoff
= 0;
551 if (op
&& creq
->len
<= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX
) {
552 u32 frag
= CESA_SA_DESC_CFG_NOT_FRAG
;
554 if ((mv_cesa_get_op_cfg(op
) & CESA_SA_DESC_CFG_FRAG_MSK
) !=
555 CESA_SA_DESC_CFG_FIRST_FRAG
)
556 frag
= CESA_SA_DESC_CFG_LAST_FRAG
;
558 mv_cesa_update_op_cfg(op
, frag
, CESA_SA_DESC_CFG_FRAG_MSK
);
563 ret
= mv_cesa_ahash_dma_alloc_padding(ahashdreq
, flags
);
567 trailerlen
= mv_cesa_ahash_pad_req(creq
, ahashdreq
->padding
);
570 len
= min(CESA_SA_SRAM_PAYLOAD_SIZE
- dma_iter
->base
.op_len
,
573 ret
= mv_cesa_dma_add_data_transfer(chain
,
574 CESA_SA_DATA_SRAM_OFFSET
+
575 dma_iter
->base
.op_len
,
576 ahashdreq
->padding_dma
,
577 len
, CESA_TDMA_DST_IN_SRAM
,
582 mv_cesa_update_op_cfg(op
, CESA_SA_DESC_CFG_MID_FRAG
,
583 CESA_SA_DESC_CFG_FRAG_MSK
);
584 mv_cesa_set_mac_op_frag_len(op
,
585 dma_iter
->base
.op_len
+ len
);
590 if (padoff
>= trailerlen
)
593 if ((mv_cesa_get_op_cfg(&creq
->op_tmpl
) & CESA_SA_DESC_CFG_FRAG_MSK
) !=
594 CESA_SA_DESC_CFG_FIRST_FRAG
)
595 mv_cesa_update_op_cfg(&creq
->op_tmpl
,
596 CESA_SA_DESC_CFG_MID_FRAG
,
597 CESA_SA_DESC_CFG_FRAG_MSK
);
599 op
= mv_cesa_dma_add_op(chain
, &creq
->op_tmpl
, false, flags
);
603 mv_cesa_set_mac_op_frag_len(op
, trailerlen
- padoff
);
605 ret
= mv_cesa_dma_add_data_transfer(chain
,
606 CESA_SA_DATA_SRAM_OFFSET
,
607 ahashdreq
->padding_dma
+
610 CESA_TDMA_DST_IN_SRAM
,
615 /* Add dummy desc to launch crypto operation */
616 ret
= mv_cesa_dma_add_dummy_launch(chain
, flags
);
623 static int mv_cesa_ahash_dma_req_init(struct ahash_request
*req
)
625 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
626 gfp_t flags
= (req
->base
.flags
& CRYPTO_TFM_REQ_MAY_SLEEP
) ?
627 GFP_KERNEL
: GFP_ATOMIC
;
628 struct mv_cesa_ahash_dma_req
*ahashdreq
= &creq
->req
.dma
;
629 struct mv_cesa_tdma_req
*dreq
= &ahashdreq
->base
;
630 struct mv_cesa_tdma_chain chain
;
631 struct mv_cesa_ahash_dma_iter iter
;
632 struct mv_cesa_op_ctx
*op
= NULL
;
635 dreq
->chain
.first
= NULL
;
636 dreq
->chain
.last
= NULL
;
638 if (creq
->src_nents
) {
639 ret
= dma_map_sg(cesa_dev
->dev
, req
->src
, creq
->src_nents
,
647 mv_cesa_tdma_desc_iter_init(&chain
);
648 mv_cesa_ahash_req_iter_init(&iter
, req
);
650 op
= mv_cesa_ahash_dma_add_cache(&chain
, &iter
,
658 if (!iter
.base
.op_len
)
661 op
= mv_cesa_ahash_dma_add_data(&chain
, &iter
,
667 } while (mv_cesa_ahash_req_iter_next_op(&iter
));
669 op
= mv_cesa_ahash_dma_last_req(&chain
, &iter
, creq
, op
, flags
);
676 /* Add dummy desc to wait for crypto operation end */
677 ret
= mv_cesa_dma_add_dummy_end(&chain
, flags
);
683 creq
->cache_ptr
= req
->nbytes
+ creq
->cache_ptr
-
693 mv_cesa_dma_cleanup(dreq
);
694 dma_unmap_sg(cesa_dev
->dev
, req
->src
, creq
->src_nents
, DMA_TO_DEVICE
);
697 mv_cesa_ahash_last_cleanup(req
);
702 static int mv_cesa_ahash_req_init(struct ahash_request
*req
, bool *cached
)
704 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
707 if (cesa_dev
->caps
->has_tdma
)
708 creq
->req
.base
.type
= CESA_DMA_REQ
;
710 creq
->req
.base
.type
= CESA_STD_REQ
;
712 creq
->src_nents
= sg_nents_for_len(req
->src
, req
->nbytes
);
714 ret
= mv_cesa_ahash_cache_req(req
, cached
);
721 if (creq
->req
.base
.type
== CESA_DMA_REQ
)
722 ret
= mv_cesa_ahash_dma_req_init(req
);
727 static int mv_cesa_ahash_update(struct ahash_request
*req
)
729 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
733 creq
->len
+= req
->nbytes
;
734 ret
= mv_cesa_ahash_req_init(req
, &cached
);
741 ret
= mv_cesa_queue_req(&req
->base
);
742 if (ret
&& ret
!= -EINPROGRESS
) {
743 mv_cesa_ahash_cleanup(req
);
750 static int mv_cesa_ahash_final(struct ahash_request
*req
)
752 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
753 struct mv_cesa_op_ctx
*tmpl
= &creq
->op_tmpl
;
757 mv_cesa_set_mac_op_total_len(tmpl
, creq
->len
);
758 creq
->last_req
= true;
761 ret
= mv_cesa_ahash_req_init(req
, &cached
);
768 ret
= mv_cesa_queue_req(&req
->base
);
769 if (ret
&& ret
!= -EINPROGRESS
)
770 mv_cesa_ahash_cleanup(req
);
775 static int mv_cesa_ahash_finup(struct ahash_request
*req
)
777 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
778 struct mv_cesa_op_ctx
*tmpl
= &creq
->op_tmpl
;
782 creq
->len
+= req
->nbytes
;
783 mv_cesa_set_mac_op_total_len(tmpl
, creq
->len
);
784 creq
->last_req
= true;
786 ret
= mv_cesa_ahash_req_init(req
, &cached
);
793 ret
= mv_cesa_queue_req(&req
->base
);
794 if (ret
&& ret
!= -EINPROGRESS
)
795 mv_cesa_ahash_cleanup(req
);
800 static int mv_cesa_md5_init(struct ahash_request
*req
)
802 struct mv_cesa_op_ctx tmpl
;
804 mv_cesa_set_op_cfg(&tmpl
, CESA_SA_DESC_CFG_MACM_MD5
);
806 mv_cesa_ahash_init(req
, &tmpl
);
811 static int mv_cesa_md5_export(struct ahash_request
*req
, void *out
)
813 struct md5_state
*out_state
= out
;
814 struct crypto_ahash
*ahash
= crypto_ahash_reqtfm(req
);
815 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
816 unsigned int digsize
= crypto_ahash_digestsize(ahash
);
818 out_state
->byte_count
= creq
->len
;
819 memcpy(out_state
->hash
, creq
->state
, digsize
);
820 memset(out_state
->block
, 0, sizeof(out_state
->block
));
822 memcpy(out_state
->block
, creq
->cache
, creq
->cache_ptr
);
827 static int mv_cesa_md5_import(struct ahash_request
*req
, const void *in
)
829 const struct md5_state
*in_state
= in
;
830 struct crypto_ahash
*ahash
= crypto_ahash_reqtfm(req
);
831 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
832 unsigned int digsize
= crypto_ahash_digestsize(ahash
);
833 unsigned int cache_ptr
;
836 creq
->len
= in_state
->byte_count
;
837 memcpy(creq
->state
, in_state
->hash
, digsize
);
840 cache_ptr
= creq
->len
% sizeof(in_state
->block
);
844 ret
= mv_cesa_ahash_alloc_cache(req
);
848 memcpy(creq
->cache
, in_state
->block
, cache_ptr
);
849 creq
->cache_ptr
= cache_ptr
;
854 static int mv_cesa_md5_digest(struct ahash_request
*req
)
858 ret
= mv_cesa_md5_init(req
);
862 return mv_cesa_ahash_finup(req
);
865 struct ahash_alg mv_md5_alg
= {
866 .init
= mv_cesa_md5_init
,
867 .update
= mv_cesa_ahash_update
,
868 .final
= mv_cesa_ahash_final
,
869 .finup
= mv_cesa_ahash_finup
,
870 .digest
= mv_cesa_md5_digest
,
871 .export
= mv_cesa_md5_export
,
872 .import
= mv_cesa_md5_import
,
874 .digestsize
= MD5_DIGEST_SIZE
,
877 .cra_driver_name
= "mv-md5",
879 .cra_flags
= CRYPTO_ALG_ASYNC
|
880 CRYPTO_ALG_KERN_DRIVER_ONLY
,
881 .cra_blocksize
= MD5_HMAC_BLOCK_SIZE
,
882 .cra_ctxsize
= sizeof(struct mv_cesa_hash_ctx
),
883 .cra_init
= mv_cesa_ahash_cra_init
,
884 .cra_module
= THIS_MODULE
,
889 static int mv_cesa_sha1_init(struct ahash_request
*req
)
891 struct mv_cesa_op_ctx tmpl
;
893 mv_cesa_set_op_cfg(&tmpl
, CESA_SA_DESC_CFG_MACM_SHA1
);
895 mv_cesa_ahash_init(req
, &tmpl
);
900 static int mv_cesa_sha1_export(struct ahash_request
*req
, void *out
)
902 struct sha1_state
*out_state
= out
;
903 struct crypto_ahash
*ahash
= crypto_ahash_reqtfm(req
);
904 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
905 unsigned int digsize
= crypto_ahash_digestsize(ahash
);
907 out_state
->count
= creq
->len
;
908 memcpy(out_state
->state
, creq
->state
, digsize
);
909 memset(out_state
->buffer
, 0, sizeof(out_state
->buffer
));
911 memcpy(out_state
->buffer
, creq
->cache
, creq
->cache_ptr
);
916 static int mv_cesa_sha1_import(struct ahash_request
*req
, const void *in
)
918 const struct sha1_state
*in_state
= in
;
919 struct crypto_ahash
*ahash
= crypto_ahash_reqtfm(req
);
920 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
921 unsigned int digsize
= crypto_ahash_digestsize(ahash
);
922 unsigned int cache_ptr
;
925 creq
->len
= in_state
->count
;
926 memcpy(creq
->state
, in_state
->state
, digsize
);
929 cache_ptr
= creq
->len
% SHA1_BLOCK_SIZE
;
933 ret
= mv_cesa_ahash_alloc_cache(req
);
937 memcpy(creq
->cache
, in_state
->buffer
, cache_ptr
);
938 creq
->cache_ptr
= cache_ptr
;
943 static int mv_cesa_sha1_digest(struct ahash_request
*req
)
947 ret
= mv_cesa_sha1_init(req
);
951 return mv_cesa_ahash_finup(req
);
954 struct ahash_alg mv_sha1_alg
= {
955 .init
= mv_cesa_sha1_init
,
956 .update
= mv_cesa_ahash_update
,
957 .final
= mv_cesa_ahash_final
,
958 .finup
= mv_cesa_ahash_finup
,
959 .digest
= mv_cesa_sha1_digest
,
960 .export
= mv_cesa_sha1_export
,
961 .import
= mv_cesa_sha1_import
,
963 .digestsize
= SHA1_DIGEST_SIZE
,
966 .cra_driver_name
= "mv-sha1",
968 .cra_flags
= CRYPTO_ALG_ASYNC
|
969 CRYPTO_ALG_KERN_DRIVER_ONLY
,
970 .cra_blocksize
= SHA1_BLOCK_SIZE
,
971 .cra_ctxsize
= sizeof(struct mv_cesa_hash_ctx
),
972 .cra_init
= mv_cesa_ahash_cra_init
,
973 .cra_module
= THIS_MODULE
,
978 static int mv_cesa_sha256_init(struct ahash_request
*req
)
980 struct mv_cesa_op_ctx tmpl
;
982 mv_cesa_set_op_cfg(&tmpl
, CESA_SA_DESC_CFG_MACM_SHA256
);
984 mv_cesa_ahash_init(req
, &tmpl
);
989 static int mv_cesa_sha256_digest(struct ahash_request
*req
)
993 ret
= mv_cesa_sha256_init(req
);
997 return mv_cesa_ahash_finup(req
);
1000 static int mv_cesa_sha256_export(struct ahash_request
*req
, void *out
)
1002 struct sha256_state
*out_state
= out
;
1003 struct crypto_ahash
*ahash
= crypto_ahash_reqtfm(req
);
1004 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
1005 unsigned int ds
= crypto_ahash_digestsize(ahash
);
1007 out_state
->count
= creq
->len
;
1008 memcpy(out_state
->state
, creq
->state
, ds
);
1009 memset(out_state
->buf
, 0, sizeof(out_state
->buf
));
1011 memcpy(out_state
->buf
, creq
->cache
, creq
->cache_ptr
);
1016 static int mv_cesa_sha256_import(struct ahash_request
*req
, const void *in
)
1018 const struct sha256_state
*in_state
= in
;
1019 struct crypto_ahash
*ahash
= crypto_ahash_reqtfm(req
);
1020 struct mv_cesa_ahash_req
*creq
= ahash_request_ctx(req
);
1021 unsigned int digsize
= crypto_ahash_digestsize(ahash
);
1022 unsigned int cache_ptr
;
1025 creq
->len
= in_state
->count
;
1026 memcpy(creq
->state
, in_state
->state
, digsize
);
1027 creq
->cache_ptr
= 0;
1029 cache_ptr
= creq
->len
% SHA256_BLOCK_SIZE
;
1033 ret
= mv_cesa_ahash_alloc_cache(req
);
1037 memcpy(creq
->cache
, in_state
->buf
, cache_ptr
);
1038 creq
->cache_ptr
= cache_ptr
;
1043 struct ahash_alg mv_sha256_alg
= {
1044 .init
= mv_cesa_sha256_init
,
1045 .update
= mv_cesa_ahash_update
,
1046 .final
= mv_cesa_ahash_final
,
1047 .finup
= mv_cesa_ahash_finup
,
1048 .digest
= mv_cesa_sha256_digest
,
1049 .export
= mv_cesa_sha256_export
,
1050 .import
= mv_cesa_sha256_import
,
1052 .digestsize
= SHA256_DIGEST_SIZE
,
1054 .cra_name
= "sha256",
1055 .cra_driver_name
= "mv-sha256",
1056 .cra_priority
= 300,
1057 .cra_flags
= CRYPTO_ALG_ASYNC
|
1058 CRYPTO_ALG_KERN_DRIVER_ONLY
,
1059 .cra_blocksize
= SHA256_BLOCK_SIZE
,
1060 .cra_ctxsize
= sizeof(struct mv_cesa_hash_ctx
),
1061 .cra_init
= mv_cesa_ahash_cra_init
,
1062 .cra_module
= THIS_MODULE
,
1067 struct mv_cesa_ahash_result
{
1068 struct completion completion
;
1072 static void mv_cesa_hmac_ahash_complete(struct crypto_async_request
*req
,
1075 struct mv_cesa_ahash_result
*result
= req
->data
;
1077 if (error
== -EINPROGRESS
)
1080 result
->error
= error
;
1081 complete(&result
->completion
);
1084 static int mv_cesa_ahmac_iv_state_init(struct ahash_request
*req
, u8
*pad
,
1085 void *state
, unsigned int blocksize
)
1087 struct mv_cesa_ahash_result result
;
1088 struct scatterlist sg
;
1091 ahash_request_set_callback(req
, CRYPTO_TFM_REQ_MAY_BACKLOG
,
1092 mv_cesa_hmac_ahash_complete
, &result
);
1093 sg_init_one(&sg
, pad
, blocksize
);
1094 ahash_request_set_crypt(req
, &sg
, pad
, blocksize
);
1095 init_completion(&result
.completion
);
1097 ret
= crypto_ahash_init(req
);
1101 ret
= crypto_ahash_update(req
);
1102 if (ret
&& ret
!= -EINPROGRESS
)
1105 wait_for_completion_interruptible(&result
.completion
);
1107 return result
.error
;
1109 ret
= crypto_ahash_export(req
, state
);
1116 static int mv_cesa_ahmac_pad_init(struct ahash_request
*req
,
1117 const u8
*key
, unsigned int keylen
,
1119 unsigned int blocksize
)
1121 struct mv_cesa_ahash_result result
;
1122 struct scatterlist sg
;
1126 if (keylen
<= blocksize
) {
1127 memcpy(ipad
, key
, keylen
);
1129 u8
*keydup
= kmemdup(key
, keylen
, GFP_KERNEL
);
1134 ahash_request_set_callback(req
, CRYPTO_TFM_REQ_MAY_BACKLOG
,
1135 mv_cesa_hmac_ahash_complete
,
1137 sg_init_one(&sg
, keydup
, keylen
);
1138 ahash_request_set_crypt(req
, &sg
, ipad
, keylen
);
1139 init_completion(&result
.completion
);
1141 ret
= crypto_ahash_digest(req
);
1142 if (ret
== -EINPROGRESS
) {
1143 wait_for_completion_interruptible(&result
.completion
);
1147 /* Set the memory region to 0 to avoid any leak. */
1148 memset(keydup
, 0, keylen
);
1154 keylen
= crypto_ahash_digestsize(crypto_ahash_reqtfm(req
));
1157 memset(ipad
+ keylen
, 0, blocksize
- keylen
);
1158 memcpy(opad
, ipad
, blocksize
);
1160 for (i
= 0; i
< blocksize
; i
++) {
1168 static int mv_cesa_ahmac_setkey(const char *hash_alg_name
,
1169 const u8
*key
, unsigned int keylen
,
1170 void *istate
, void *ostate
)
1172 struct ahash_request
*req
;
1173 struct crypto_ahash
*tfm
;
1174 unsigned int blocksize
;
1179 tfm
= crypto_alloc_ahash(hash_alg_name
, CRYPTO_ALG_TYPE_AHASH
,
1180 CRYPTO_ALG_TYPE_AHASH_MASK
);
1182 return PTR_ERR(tfm
);
1184 req
= ahash_request_alloc(tfm
, GFP_KERNEL
);
1190 crypto_ahash_clear_flags(tfm
, ~0);
1192 blocksize
= crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm
));
1194 ipad
= kzalloc(2 * blocksize
, GFP_KERNEL
);
1200 opad
= ipad
+ blocksize
;
1202 ret
= mv_cesa_ahmac_pad_init(req
, key
, keylen
, ipad
, opad
, blocksize
);
1206 ret
= mv_cesa_ahmac_iv_state_init(req
, ipad
, istate
, blocksize
);
1210 ret
= mv_cesa_ahmac_iv_state_init(req
, opad
, ostate
, blocksize
);
1215 ahash_request_free(req
);
1217 crypto_free_ahash(tfm
);
1222 static int mv_cesa_ahmac_cra_init(struct crypto_tfm
*tfm
)
1224 struct mv_cesa_hmac_ctx
*ctx
= crypto_tfm_ctx(tfm
);
1226 ctx
->base
.ops
= &mv_cesa_ahash_req_ops
;
1228 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm
),
1229 sizeof(struct mv_cesa_ahash_req
));
1233 static int mv_cesa_ahmac_md5_init(struct ahash_request
*req
)
1235 struct mv_cesa_hmac_ctx
*ctx
= crypto_tfm_ctx(req
->base
.tfm
);
1236 struct mv_cesa_op_ctx tmpl
;
1238 mv_cesa_set_op_cfg(&tmpl
, CESA_SA_DESC_CFG_MACM_HMAC_MD5
);
1239 memcpy(tmpl
.ctx
.hash
.iv
, ctx
->iv
, sizeof(ctx
->iv
));
1241 mv_cesa_ahash_init(req
, &tmpl
);
1246 static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash
*tfm
, const u8
*key
,
1247 unsigned int keylen
)
1249 struct mv_cesa_hmac_ctx
*ctx
= crypto_tfm_ctx(crypto_ahash_tfm(tfm
));
1250 struct md5_state istate
, ostate
;
1253 ret
= mv_cesa_ahmac_setkey("mv-md5", key
, keylen
, &istate
, &ostate
);
1257 for (i
= 0; i
< ARRAY_SIZE(istate
.hash
); i
++)
1258 ctx
->iv
[i
] = be32_to_cpu(istate
.hash
[i
]);
1260 for (i
= 0; i
< ARRAY_SIZE(ostate
.hash
); i
++)
1261 ctx
->iv
[i
+ 8] = be32_to_cpu(ostate
.hash
[i
]);
1266 static int mv_cesa_ahmac_md5_digest(struct ahash_request
*req
)
1270 ret
= mv_cesa_ahmac_md5_init(req
);
1274 return mv_cesa_ahash_finup(req
);
1277 struct ahash_alg mv_ahmac_md5_alg
= {
1278 .init
= mv_cesa_ahmac_md5_init
,
1279 .update
= mv_cesa_ahash_update
,
1280 .final
= mv_cesa_ahash_final
,
1281 .finup
= mv_cesa_ahash_finup
,
1282 .digest
= mv_cesa_ahmac_md5_digest
,
1283 .setkey
= mv_cesa_ahmac_md5_setkey
,
1284 .export
= mv_cesa_md5_export
,
1285 .import
= mv_cesa_md5_import
,
1287 .digestsize
= MD5_DIGEST_SIZE
,
1288 .statesize
= sizeof(struct md5_state
),
1290 .cra_name
= "hmac(md5)",
1291 .cra_driver_name
= "mv-hmac-md5",
1292 .cra_priority
= 300,
1293 .cra_flags
= CRYPTO_ALG_ASYNC
|
1294 CRYPTO_ALG_KERN_DRIVER_ONLY
,
1295 .cra_blocksize
= MD5_HMAC_BLOCK_SIZE
,
1296 .cra_ctxsize
= sizeof(struct mv_cesa_hmac_ctx
),
1297 .cra_init
= mv_cesa_ahmac_cra_init
,
1298 .cra_module
= THIS_MODULE
,
1303 static int mv_cesa_ahmac_sha1_init(struct ahash_request
*req
)
1305 struct mv_cesa_hmac_ctx
*ctx
= crypto_tfm_ctx(req
->base
.tfm
);
1306 struct mv_cesa_op_ctx tmpl
;
1308 mv_cesa_set_op_cfg(&tmpl
, CESA_SA_DESC_CFG_MACM_HMAC_SHA1
);
1309 memcpy(tmpl
.ctx
.hash
.iv
, ctx
->iv
, sizeof(ctx
->iv
));
1311 mv_cesa_ahash_init(req
, &tmpl
);
1316 static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash
*tfm
, const u8
*key
,
1317 unsigned int keylen
)
1319 struct mv_cesa_hmac_ctx
*ctx
= crypto_tfm_ctx(crypto_ahash_tfm(tfm
));
1320 struct sha1_state istate
, ostate
;
1323 ret
= mv_cesa_ahmac_setkey("mv-sha1", key
, keylen
, &istate
, &ostate
);
1327 for (i
= 0; i
< ARRAY_SIZE(istate
.state
); i
++)
1328 ctx
->iv
[i
] = be32_to_cpu(istate
.state
[i
]);
1330 for (i
= 0; i
< ARRAY_SIZE(ostate
.state
); i
++)
1331 ctx
->iv
[i
+ 8] = be32_to_cpu(ostate
.state
[i
]);
1336 static int mv_cesa_ahmac_sha1_digest(struct ahash_request
*req
)
1340 ret
= mv_cesa_ahmac_sha1_init(req
);
1344 return mv_cesa_ahash_finup(req
);
1347 struct ahash_alg mv_ahmac_sha1_alg
= {
1348 .init
= mv_cesa_ahmac_sha1_init
,
1349 .update
= mv_cesa_ahash_update
,
1350 .final
= mv_cesa_ahash_final
,
1351 .finup
= mv_cesa_ahash_finup
,
1352 .digest
= mv_cesa_ahmac_sha1_digest
,
1353 .setkey
= mv_cesa_ahmac_sha1_setkey
,
1354 .export
= mv_cesa_sha1_export
,
1355 .import
= mv_cesa_sha1_import
,
1357 .digestsize
= SHA1_DIGEST_SIZE
,
1358 .statesize
= sizeof(struct sha1_state
),
1360 .cra_name
= "hmac(sha1)",
1361 .cra_driver_name
= "mv-hmac-sha1",
1362 .cra_priority
= 300,
1363 .cra_flags
= CRYPTO_ALG_ASYNC
|
1364 CRYPTO_ALG_KERN_DRIVER_ONLY
,
1365 .cra_blocksize
= SHA1_BLOCK_SIZE
,
1366 .cra_ctxsize
= sizeof(struct mv_cesa_hmac_ctx
),
1367 .cra_init
= mv_cesa_ahmac_cra_init
,
1368 .cra_module
= THIS_MODULE
,
1373 static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash
*tfm
, const u8
*key
,
1374 unsigned int keylen
)
1376 struct mv_cesa_hmac_ctx
*ctx
= crypto_tfm_ctx(crypto_ahash_tfm(tfm
));
1377 struct sha256_state istate
, ostate
;
1380 ret
= mv_cesa_ahmac_setkey("mv-sha256", key
, keylen
, &istate
, &ostate
);
1384 for (i
= 0; i
< ARRAY_SIZE(istate
.state
); i
++)
1385 ctx
->iv
[i
] = be32_to_cpu(istate
.state
[i
]);
1387 for (i
= 0; i
< ARRAY_SIZE(ostate
.state
); i
++)
1388 ctx
->iv
[i
+ 8] = be32_to_cpu(ostate
.state
[i
]);
1393 static int mv_cesa_ahmac_sha256_init(struct ahash_request
*req
)
1395 struct mv_cesa_hmac_ctx
*ctx
= crypto_tfm_ctx(req
->base
.tfm
);
1396 struct mv_cesa_op_ctx tmpl
;
1398 mv_cesa_set_op_cfg(&tmpl
, CESA_SA_DESC_CFG_MACM_HMAC_SHA256
);
1399 memcpy(tmpl
.ctx
.hash
.iv
, ctx
->iv
, sizeof(ctx
->iv
));
1401 mv_cesa_ahash_init(req
, &tmpl
);
1406 static int mv_cesa_ahmac_sha256_digest(struct ahash_request
*req
)
1410 ret
= mv_cesa_ahmac_sha256_init(req
);
1414 return mv_cesa_ahash_finup(req
);
1417 struct ahash_alg mv_ahmac_sha256_alg
= {
1418 .init
= mv_cesa_ahmac_sha256_init
,
1419 .update
= mv_cesa_ahash_update
,
1420 .final
= mv_cesa_ahash_final
,
1421 .finup
= mv_cesa_ahash_finup
,
1422 .digest
= mv_cesa_ahmac_sha256_digest
,
1423 .setkey
= mv_cesa_ahmac_sha256_setkey
,
1424 .export
= mv_cesa_sha256_export
,
1425 .import
= mv_cesa_sha256_import
,
1427 .digestsize
= SHA256_DIGEST_SIZE
,
1428 .statesize
= sizeof(struct sha256_state
),
1430 .cra_name
= "hmac(sha256)",
1431 .cra_driver_name
= "mv-hmac-sha256",
1432 .cra_priority
= 300,
1433 .cra_flags
= CRYPTO_ALG_ASYNC
|
1434 CRYPTO_ALG_KERN_DRIVER_ONLY
,
1435 .cra_blocksize
= SHA256_BLOCK_SIZE
,
1436 .cra_ctxsize
= sizeof(struct mv_cesa_hmac_ctx
),
1437 .cra_init
= mv_cesa_ahmac_cra_init
,
1438 .cra_module
= THIS_MODULE
,