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crypto: omap - do not call dmaengine_terminate_all
[deliverable/linux.git] / drivers / crypto / omap-aes.c
1 /*
2 * Cryptographic API.
3 *
4 * Support for OMAP AES HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 * Copyright (c) 2011 Texas Instruments Incorporated
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 */
15
16 #define pr_fmt(fmt) "%20s: " fmt, __func__
17 #define prn(num) pr_debug(#num "=%d\n", num)
18 #define prx(num) pr_debug(#num "=%x\n", num)
19
20 #include <linux/err.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/kernel.h>
25 #include <linux/platform_device.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmaengine.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/of_address.h>
33 #include <linux/io.h>
34 #include <linux/crypto.h>
35 #include <linux/interrupt.h>
36 #include <crypto/scatterwalk.h>
37 #include <crypto/aes.h>
38 #include <crypto/algapi.h>
39
40 #define DST_MAXBURST 4
41 #define DMA_MIN (DST_MAXBURST * sizeof(u32))
42
43 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
44
45 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
46 number. For example 7:0 */
47 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
48 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
49
50 #define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
51 ((x ^ 0x01) * 0x04))
52 #define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
53
54 #define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
55 #define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7)
56 #define AES_REG_CTRL_CTR_WIDTH_32 0
57 #define AES_REG_CTRL_CTR_WIDTH_64 BIT(7)
58 #define AES_REG_CTRL_CTR_WIDTH_96 BIT(8)
59 #define AES_REG_CTRL_CTR_WIDTH_128 GENMASK(8, 7)
60 #define AES_REG_CTRL_CTR BIT(6)
61 #define AES_REG_CTRL_CBC BIT(5)
62 #define AES_REG_CTRL_KEY_SIZE GENMASK(4, 3)
63 #define AES_REG_CTRL_DIRECTION BIT(2)
64 #define AES_REG_CTRL_INPUT_READY BIT(1)
65 #define AES_REG_CTRL_OUTPUT_READY BIT(0)
66 #define AES_REG_CTRL_MASK GENMASK(24, 2)
67
68 #define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
69
70 #define AES_REG_REV(dd) ((dd)->pdata->rev_ofs)
71
72 #define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
73 #define AES_REG_MASK_SIDLE BIT(6)
74 #define AES_REG_MASK_START BIT(5)
75 #define AES_REG_MASK_DMA_OUT_EN BIT(3)
76 #define AES_REG_MASK_DMA_IN_EN BIT(2)
77 #define AES_REG_MASK_SOFTRESET BIT(1)
78 #define AES_REG_AUTOIDLE BIT(0)
79
80 #define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04))
81
82 #define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
83 #define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
84 #define AES_REG_IRQ_DATA_IN BIT(1)
85 #define AES_REG_IRQ_DATA_OUT BIT(2)
86 #define DEFAULT_TIMEOUT (5*HZ)
87
88 #define FLAGS_MODE_MASK 0x000f
89 #define FLAGS_ENCRYPT BIT(0)
90 #define FLAGS_CBC BIT(1)
91 #define FLAGS_GIV BIT(2)
92 #define FLAGS_CTR BIT(3)
93
94 #define FLAGS_INIT BIT(4)
95 #define FLAGS_FAST BIT(5)
96 #define FLAGS_BUSY BIT(6)
97
98 #define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2)
99
100 struct omap_aes_ctx {
101 struct omap_aes_dev *dd;
102
103 int keylen;
104 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
105 unsigned long flags;
106 };
107
108 struct omap_aes_reqctx {
109 unsigned long mode;
110 };
111
112 #define OMAP_AES_QUEUE_LENGTH 1
113 #define OMAP_AES_CACHE_SIZE 0
114
115 struct omap_aes_algs_info {
116 struct crypto_alg *algs_list;
117 unsigned int size;
118 unsigned int registered;
119 };
120
121 struct omap_aes_pdata {
122 struct omap_aes_algs_info *algs_info;
123 unsigned int algs_info_size;
124
125 void (*trigger)(struct omap_aes_dev *dd, int length);
126
127 u32 key_ofs;
128 u32 iv_ofs;
129 u32 ctrl_ofs;
130 u32 data_ofs;
131 u32 rev_ofs;
132 u32 mask_ofs;
133 u32 irq_enable_ofs;
134 u32 irq_status_ofs;
135
136 u32 dma_enable_in;
137 u32 dma_enable_out;
138 u32 dma_start;
139
140 u32 major_mask;
141 u32 major_shift;
142 u32 minor_mask;
143 u32 minor_shift;
144 };
145
146 struct omap_aes_dev {
147 struct list_head list;
148 unsigned long phys_base;
149 void __iomem *io_base;
150 struct omap_aes_ctx *ctx;
151 struct device *dev;
152 unsigned long flags;
153 int err;
154
155 struct tasklet_struct done_task;
156
157 struct ablkcipher_request *req;
158 struct crypto_engine *engine;
159
160 /*
161 * total is used by PIO mode for book keeping so introduce
162 * variable total_save as need it to calc page_order
163 */
164 size_t total;
165 size_t total_save;
166
167 struct scatterlist *in_sg;
168 struct scatterlist *out_sg;
169
170 /* Buffers for copying for unaligned cases */
171 struct scatterlist in_sgl;
172 struct scatterlist out_sgl;
173 struct scatterlist *orig_out;
174 int sgs_copied;
175
176 struct scatter_walk in_walk;
177 struct scatter_walk out_walk;
178 struct dma_chan *dma_lch_in;
179 struct dma_chan *dma_lch_out;
180 int in_sg_len;
181 int out_sg_len;
182 int pio_only;
183 const struct omap_aes_pdata *pdata;
184 };
185
186 /* keep registered devices data here */
187 static LIST_HEAD(dev_list);
188 static DEFINE_SPINLOCK(list_lock);
189
190 #ifdef DEBUG
191 #define omap_aes_read(dd, offset) \
192 ({ \
193 int _read_ret; \
194 _read_ret = __raw_readl(dd->io_base + offset); \
195 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
196 offset, _read_ret); \
197 _read_ret; \
198 })
199 #else
200 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
201 {
202 return __raw_readl(dd->io_base + offset);
203 }
204 #endif
205
206 #ifdef DEBUG
207 #define omap_aes_write(dd, offset, value) \
208 do { \
209 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
210 offset, value); \
211 __raw_writel(value, dd->io_base + offset); \
212 } while (0)
213 #else
214 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
215 u32 value)
216 {
217 __raw_writel(value, dd->io_base + offset);
218 }
219 #endif
220
221 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
222 u32 value, u32 mask)
223 {
224 u32 val;
225
226 val = omap_aes_read(dd, offset);
227 val &= ~mask;
228 val |= value;
229 omap_aes_write(dd, offset, val);
230 }
231
232 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
233 u32 *value, int count)
234 {
235 for (; count--; value++, offset += 4)
236 omap_aes_write(dd, offset, *value);
237 }
238
239 static int omap_aes_hw_init(struct omap_aes_dev *dd)
240 {
241 if (!(dd->flags & FLAGS_INIT)) {
242 dd->flags |= FLAGS_INIT;
243 dd->err = 0;
244 }
245
246 return 0;
247 }
248
249 static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
250 {
251 unsigned int key32;
252 int i, err;
253 u32 val;
254
255 err = omap_aes_hw_init(dd);
256 if (err)
257 return err;
258
259 key32 = dd->ctx->keylen / sizeof(u32);
260
261 /* it seems a key should always be set even if it has not changed */
262 for (i = 0; i < key32; i++) {
263 omap_aes_write(dd, AES_REG_KEY(dd, i),
264 __le32_to_cpu(dd->ctx->key[i]));
265 }
266
267 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
268 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
269
270 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
271 if (dd->flags & FLAGS_CBC)
272 val |= AES_REG_CTRL_CBC;
273 if (dd->flags & FLAGS_CTR)
274 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
275
276 if (dd->flags & FLAGS_ENCRYPT)
277 val |= AES_REG_CTRL_DIRECTION;
278
279 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
280
281 return 0;
282 }
283
284 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
285 {
286 u32 mask, val;
287
288 val = dd->pdata->dma_start;
289
290 if (dd->dma_lch_out != NULL)
291 val |= dd->pdata->dma_enable_out;
292 if (dd->dma_lch_in != NULL)
293 val |= dd->pdata->dma_enable_in;
294
295 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
296 dd->pdata->dma_start;
297
298 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
299
300 }
301
302 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
303 {
304 omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
305 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
306
307 omap_aes_dma_trigger_omap2(dd, length);
308 }
309
310 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
311 {
312 u32 mask;
313
314 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
315 dd->pdata->dma_start;
316
317 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
318 }
319
320 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
321 {
322 struct omap_aes_dev *dd = NULL, *tmp;
323
324 spin_lock_bh(&list_lock);
325 if (!ctx->dd) {
326 list_for_each_entry(tmp, &dev_list, list) {
327 /* FIXME: take fist available aes core */
328 dd = tmp;
329 break;
330 }
331 ctx->dd = dd;
332 } else {
333 /* already found before */
334 dd = ctx->dd;
335 }
336 spin_unlock_bh(&list_lock);
337
338 return dd;
339 }
340
341 static void omap_aes_dma_out_callback(void *data)
342 {
343 struct omap_aes_dev *dd = data;
344
345 /* dma_lch_out - completed */
346 tasklet_schedule(&dd->done_task);
347 }
348
349 static int omap_aes_dma_init(struct omap_aes_dev *dd)
350 {
351 int err;
352
353 dd->dma_lch_out = NULL;
354 dd->dma_lch_in = NULL;
355
356 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
357 if (IS_ERR(dd->dma_lch_in)) {
358 dev_err(dd->dev, "Unable to request in DMA channel\n");
359 return PTR_ERR(dd->dma_lch_in);
360 }
361
362 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
363 if (IS_ERR(dd->dma_lch_out)) {
364 dev_err(dd->dev, "Unable to request out DMA channel\n");
365 err = PTR_ERR(dd->dma_lch_out);
366 goto err_dma_out;
367 }
368
369 return 0;
370
371 err_dma_out:
372 dma_release_channel(dd->dma_lch_in);
373
374 return err;
375 }
376
377 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
378 {
379 if (dd->pio_only)
380 return;
381
382 dma_release_channel(dd->dma_lch_out);
383 dma_release_channel(dd->dma_lch_in);
384 }
385
386 static void sg_copy_buf(void *buf, struct scatterlist *sg,
387 unsigned int start, unsigned int nbytes, int out)
388 {
389 struct scatter_walk walk;
390
391 if (!nbytes)
392 return;
393
394 scatterwalk_start(&walk, sg);
395 scatterwalk_advance(&walk, start);
396 scatterwalk_copychunks(buf, &walk, nbytes, out);
397 scatterwalk_done(&walk, out, 0);
398 }
399
400 static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
401 struct scatterlist *in_sg, struct scatterlist *out_sg,
402 int in_sg_len, int out_sg_len)
403 {
404 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
405 struct omap_aes_dev *dd = ctx->dd;
406 struct dma_async_tx_descriptor *tx_in, *tx_out;
407 struct dma_slave_config cfg;
408 int ret;
409
410 if (dd->pio_only) {
411 scatterwalk_start(&dd->in_walk, dd->in_sg);
412 scatterwalk_start(&dd->out_walk, dd->out_sg);
413
414 /* Enable DATAIN interrupt and let it take
415 care of the rest */
416 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
417 return 0;
418 }
419
420 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
421
422 memset(&cfg, 0, sizeof(cfg));
423
424 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
425 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
426 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
427 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
428 cfg.src_maxburst = DST_MAXBURST;
429 cfg.dst_maxburst = DST_MAXBURST;
430
431 /* IN */
432 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
433 if (ret) {
434 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
435 ret);
436 return ret;
437 }
438
439 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
440 DMA_MEM_TO_DEV,
441 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
442 if (!tx_in) {
443 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
444 return -EINVAL;
445 }
446
447 /* No callback necessary */
448 tx_in->callback_param = dd;
449
450 /* OUT */
451 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
452 if (ret) {
453 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
454 ret);
455 return ret;
456 }
457
458 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
459 DMA_DEV_TO_MEM,
460 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
461 if (!tx_out) {
462 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
463 return -EINVAL;
464 }
465
466 tx_out->callback = omap_aes_dma_out_callback;
467 tx_out->callback_param = dd;
468
469 dmaengine_submit(tx_in);
470 dmaengine_submit(tx_out);
471
472 dma_async_issue_pending(dd->dma_lch_in);
473 dma_async_issue_pending(dd->dma_lch_out);
474
475 /* start DMA */
476 dd->pdata->trigger(dd, dd->total);
477
478 return 0;
479 }
480
481 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
482 {
483 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
484 crypto_ablkcipher_reqtfm(dd->req));
485 int err;
486
487 pr_debug("total: %d\n", dd->total);
488
489 if (!dd->pio_only) {
490 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
491 DMA_TO_DEVICE);
492 if (!err) {
493 dev_err(dd->dev, "dma_map_sg() error\n");
494 return -EINVAL;
495 }
496
497 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
498 DMA_FROM_DEVICE);
499 if (!err) {
500 dev_err(dd->dev, "dma_map_sg() error\n");
501 return -EINVAL;
502 }
503 }
504
505 err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
506 dd->out_sg_len);
507 if (err && !dd->pio_only) {
508 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
509 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
510 DMA_FROM_DEVICE);
511 }
512
513 return err;
514 }
515
516 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
517 {
518 struct ablkcipher_request *req = dd->req;
519
520 pr_debug("err: %d\n", err);
521
522 crypto_finalize_request(dd->engine, req, err);
523 }
524
525 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
526 {
527 pr_debug("total: %d\n", dd->total);
528
529 omap_aes_dma_stop(dd);
530
531
532 return 0;
533 }
534
535 static int omap_aes_check_aligned(struct scatterlist *sg, int total)
536 {
537 int len = 0;
538
539 if (!IS_ALIGNED(total, AES_BLOCK_SIZE))
540 return -EINVAL;
541
542 while (sg) {
543 if (!IS_ALIGNED(sg->offset, 4))
544 return -1;
545 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
546 return -1;
547
548 len += sg->length;
549 sg = sg_next(sg);
550 }
551
552 if (len != total)
553 return -1;
554
555 return 0;
556 }
557
558 static int omap_aes_copy_sgs(struct omap_aes_dev *dd)
559 {
560 void *buf_in, *buf_out;
561 int pages, total;
562
563 total = ALIGN(dd->total, AES_BLOCK_SIZE);
564 pages = get_order(total);
565
566 buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages);
567 buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages);
568
569 if (!buf_in || !buf_out) {
570 pr_err("Couldn't allocated pages for unaligned cases.\n");
571 return -1;
572 }
573
574 dd->orig_out = dd->out_sg;
575
576 sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0);
577
578 sg_init_table(&dd->in_sgl, 1);
579 sg_set_buf(&dd->in_sgl, buf_in, total);
580 dd->in_sg = &dd->in_sgl;
581
582 sg_init_table(&dd->out_sgl, 1);
583 sg_set_buf(&dd->out_sgl, buf_out, total);
584 dd->out_sg = &dd->out_sgl;
585
586 return 0;
587 }
588
589 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
590 struct ablkcipher_request *req)
591 {
592 if (req)
593 return crypto_transfer_request_to_engine(dd->engine, req);
594
595 return 0;
596 }
597
598 static int omap_aes_prepare_req(struct crypto_engine *engine,
599 struct ablkcipher_request *req)
600 {
601 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
602 crypto_ablkcipher_reqtfm(req));
603 struct omap_aes_dev *dd = omap_aes_find_dev(ctx);
604 struct omap_aes_reqctx *rctx;
605 int len;
606
607 if (!dd)
608 return -ENODEV;
609
610 /* assign new request to device */
611 dd->req = req;
612 dd->total = req->nbytes;
613 dd->total_save = req->nbytes;
614 dd->in_sg = req->src;
615 dd->out_sg = req->dst;
616
617 if (omap_aes_check_aligned(dd->in_sg, dd->total) ||
618 omap_aes_check_aligned(dd->out_sg, dd->total)) {
619 if (omap_aes_copy_sgs(dd))
620 pr_err("Failed to copy SGs for unaligned cases\n");
621 dd->sgs_copied = 1;
622 } else {
623 dd->sgs_copied = 0;
624 }
625
626 len = ALIGN(dd->total, AES_BLOCK_SIZE);
627 dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, len);
628 dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, len);
629 BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0);
630
631 rctx = ablkcipher_request_ctx(req);
632 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
633 rctx->mode &= FLAGS_MODE_MASK;
634 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
635
636 dd->ctx = ctx;
637 ctx->dd = dd;
638
639 return omap_aes_write_ctrl(dd);
640 }
641
642 static int omap_aes_crypt_req(struct crypto_engine *engine,
643 struct ablkcipher_request *req)
644 {
645 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
646 crypto_ablkcipher_reqtfm(req));
647 struct omap_aes_dev *dd = omap_aes_find_dev(ctx);
648
649 if (!dd)
650 return -ENODEV;
651
652 return omap_aes_crypt_dma_start(dd);
653 }
654
655 static void omap_aes_done_task(unsigned long data)
656 {
657 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
658 void *buf_in, *buf_out;
659 int pages, len;
660
661 pr_debug("enter done_task\n");
662
663 if (!dd->pio_only) {
664 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
665 DMA_FROM_DEVICE);
666 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
667 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
668 DMA_FROM_DEVICE);
669 omap_aes_crypt_dma_stop(dd);
670 }
671
672 if (dd->sgs_copied) {
673 buf_in = sg_virt(&dd->in_sgl);
674 buf_out = sg_virt(&dd->out_sgl);
675
676 sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1);
677
678 len = ALIGN(dd->total_save, AES_BLOCK_SIZE);
679 pages = get_order(len);
680 free_pages((unsigned long)buf_in, pages);
681 free_pages((unsigned long)buf_out, pages);
682 }
683
684 omap_aes_finish_req(dd, 0);
685
686 pr_debug("exit\n");
687 }
688
689 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
690 {
691 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
692 crypto_ablkcipher_reqtfm(req));
693 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
694 struct omap_aes_dev *dd;
695
696 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
697 !!(mode & FLAGS_ENCRYPT),
698 !!(mode & FLAGS_CBC));
699
700 dd = omap_aes_find_dev(ctx);
701 if (!dd)
702 return -ENODEV;
703
704 rctx->mode = mode;
705
706 return omap_aes_handle_queue(dd, req);
707 }
708
709 /* ********************** ALG API ************************************ */
710
711 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
712 unsigned int keylen)
713 {
714 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
715
716 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
717 keylen != AES_KEYSIZE_256)
718 return -EINVAL;
719
720 pr_debug("enter, keylen: %d\n", keylen);
721
722 memcpy(ctx->key, key, keylen);
723 ctx->keylen = keylen;
724
725 return 0;
726 }
727
728 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
729 {
730 return omap_aes_crypt(req, FLAGS_ENCRYPT);
731 }
732
733 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
734 {
735 return omap_aes_crypt(req, 0);
736 }
737
738 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
739 {
740 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
741 }
742
743 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
744 {
745 return omap_aes_crypt(req, FLAGS_CBC);
746 }
747
748 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
749 {
750 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
751 }
752
753 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
754 {
755 return omap_aes_crypt(req, FLAGS_CTR);
756 }
757
758 static int omap_aes_cra_init(struct crypto_tfm *tfm)
759 {
760 struct omap_aes_dev *dd = NULL;
761 int err;
762
763 /* Find AES device, currently picks the first device */
764 spin_lock_bh(&list_lock);
765 list_for_each_entry(dd, &dev_list, list) {
766 break;
767 }
768 spin_unlock_bh(&list_lock);
769
770 err = pm_runtime_get_sync(dd->dev);
771 if (err < 0) {
772 dev_err(dd->dev, "%s: failed to get_sync(%d)\n",
773 __func__, err);
774 return err;
775 }
776
777 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
778
779 return 0;
780 }
781
782 static void omap_aes_cra_exit(struct crypto_tfm *tfm)
783 {
784 struct omap_aes_dev *dd = NULL;
785
786 /* Find AES device, currently picks the first device */
787 spin_lock_bh(&list_lock);
788 list_for_each_entry(dd, &dev_list, list) {
789 break;
790 }
791 spin_unlock_bh(&list_lock);
792
793 pm_runtime_put_sync(dd->dev);
794 }
795
796 /* ********************** ALGS ************************************ */
797
798 static struct crypto_alg algs_ecb_cbc[] = {
799 {
800 .cra_name = "ecb(aes)",
801 .cra_driver_name = "ecb-aes-omap",
802 .cra_priority = 300,
803 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
804 CRYPTO_ALG_KERN_DRIVER_ONLY |
805 CRYPTO_ALG_ASYNC,
806 .cra_blocksize = AES_BLOCK_SIZE,
807 .cra_ctxsize = sizeof(struct omap_aes_ctx),
808 .cra_alignmask = 0,
809 .cra_type = &crypto_ablkcipher_type,
810 .cra_module = THIS_MODULE,
811 .cra_init = omap_aes_cra_init,
812 .cra_exit = omap_aes_cra_exit,
813 .cra_u.ablkcipher = {
814 .min_keysize = AES_MIN_KEY_SIZE,
815 .max_keysize = AES_MAX_KEY_SIZE,
816 .setkey = omap_aes_setkey,
817 .encrypt = omap_aes_ecb_encrypt,
818 .decrypt = omap_aes_ecb_decrypt,
819 }
820 },
821 {
822 .cra_name = "cbc(aes)",
823 .cra_driver_name = "cbc-aes-omap",
824 .cra_priority = 300,
825 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
826 CRYPTO_ALG_KERN_DRIVER_ONLY |
827 CRYPTO_ALG_ASYNC,
828 .cra_blocksize = AES_BLOCK_SIZE,
829 .cra_ctxsize = sizeof(struct omap_aes_ctx),
830 .cra_alignmask = 0,
831 .cra_type = &crypto_ablkcipher_type,
832 .cra_module = THIS_MODULE,
833 .cra_init = omap_aes_cra_init,
834 .cra_exit = omap_aes_cra_exit,
835 .cra_u.ablkcipher = {
836 .min_keysize = AES_MIN_KEY_SIZE,
837 .max_keysize = AES_MAX_KEY_SIZE,
838 .ivsize = AES_BLOCK_SIZE,
839 .setkey = omap_aes_setkey,
840 .encrypt = omap_aes_cbc_encrypt,
841 .decrypt = omap_aes_cbc_decrypt,
842 }
843 }
844 };
845
846 static struct crypto_alg algs_ctr[] = {
847 {
848 .cra_name = "ctr(aes)",
849 .cra_driver_name = "ctr-aes-omap",
850 .cra_priority = 300,
851 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
852 CRYPTO_ALG_KERN_DRIVER_ONLY |
853 CRYPTO_ALG_ASYNC,
854 .cra_blocksize = AES_BLOCK_SIZE,
855 .cra_ctxsize = sizeof(struct omap_aes_ctx),
856 .cra_alignmask = 0,
857 .cra_type = &crypto_ablkcipher_type,
858 .cra_module = THIS_MODULE,
859 .cra_init = omap_aes_cra_init,
860 .cra_exit = omap_aes_cra_exit,
861 .cra_u.ablkcipher = {
862 .min_keysize = AES_MIN_KEY_SIZE,
863 .max_keysize = AES_MAX_KEY_SIZE,
864 .geniv = "eseqiv",
865 .ivsize = AES_BLOCK_SIZE,
866 .setkey = omap_aes_setkey,
867 .encrypt = omap_aes_ctr_encrypt,
868 .decrypt = omap_aes_ctr_decrypt,
869 }
870 } ,
871 };
872
873 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
874 {
875 .algs_list = algs_ecb_cbc,
876 .size = ARRAY_SIZE(algs_ecb_cbc),
877 },
878 };
879
880 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
881 .algs_info = omap_aes_algs_info_ecb_cbc,
882 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
883 .trigger = omap_aes_dma_trigger_omap2,
884 .key_ofs = 0x1c,
885 .iv_ofs = 0x20,
886 .ctrl_ofs = 0x30,
887 .data_ofs = 0x34,
888 .rev_ofs = 0x44,
889 .mask_ofs = 0x48,
890 .dma_enable_in = BIT(2),
891 .dma_enable_out = BIT(3),
892 .dma_start = BIT(5),
893 .major_mask = 0xf0,
894 .major_shift = 4,
895 .minor_mask = 0x0f,
896 .minor_shift = 0,
897 };
898
899 #ifdef CONFIG_OF
900 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
901 {
902 .algs_list = algs_ecb_cbc,
903 .size = ARRAY_SIZE(algs_ecb_cbc),
904 },
905 {
906 .algs_list = algs_ctr,
907 .size = ARRAY_SIZE(algs_ctr),
908 },
909 };
910
911 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
912 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
913 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
914 .trigger = omap_aes_dma_trigger_omap2,
915 .key_ofs = 0x1c,
916 .iv_ofs = 0x20,
917 .ctrl_ofs = 0x30,
918 .data_ofs = 0x34,
919 .rev_ofs = 0x44,
920 .mask_ofs = 0x48,
921 .dma_enable_in = BIT(2),
922 .dma_enable_out = BIT(3),
923 .dma_start = BIT(5),
924 .major_mask = 0xf0,
925 .major_shift = 4,
926 .minor_mask = 0x0f,
927 .minor_shift = 0,
928 };
929
930 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
931 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
932 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
933 .trigger = omap_aes_dma_trigger_omap4,
934 .key_ofs = 0x3c,
935 .iv_ofs = 0x40,
936 .ctrl_ofs = 0x50,
937 .data_ofs = 0x60,
938 .rev_ofs = 0x80,
939 .mask_ofs = 0x84,
940 .irq_status_ofs = 0x8c,
941 .irq_enable_ofs = 0x90,
942 .dma_enable_in = BIT(5),
943 .dma_enable_out = BIT(6),
944 .major_mask = 0x0700,
945 .major_shift = 8,
946 .minor_mask = 0x003f,
947 .minor_shift = 0,
948 };
949
950 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
951 {
952 struct omap_aes_dev *dd = dev_id;
953 u32 status, i;
954 u32 *src, *dst;
955
956 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
957 if (status & AES_REG_IRQ_DATA_IN) {
958 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
959
960 BUG_ON(!dd->in_sg);
961
962 BUG_ON(_calc_walked(in) > dd->in_sg->length);
963
964 src = sg_virt(dd->in_sg) + _calc_walked(in);
965
966 for (i = 0; i < AES_BLOCK_WORDS; i++) {
967 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
968
969 scatterwalk_advance(&dd->in_walk, 4);
970 if (dd->in_sg->length == _calc_walked(in)) {
971 dd->in_sg = sg_next(dd->in_sg);
972 if (dd->in_sg) {
973 scatterwalk_start(&dd->in_walk,
974 dd->in_sg);
975 src = sg_virt(dd->in_sg) +
976 _calc_walked(in);
977 }
978 } else {
979 src++;
980 }
981 }
982
983 /* Clear IRQ status */
984 status &= ~AES_REG_IRQ_DATA_IN;
985 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
986
987 /* Enable DATA_OUT interrupt */
988 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
989
990 } else if (status & AES_REG_IRQ_DATA_OUT) {
991 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
992
993 BUG_ON(!dd->out_sg);
994
995 BUG_ON(_calc_walked(out) > dd->out_sg->length);
996
997 dst = sg_virt(dd->out_sg) + _calc_walked(out);
998
999 for (i = 0; i < AES_BLOCK_WORDS; i++) {
1000 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
1001 scatterwalk_advance(&dd->out_walk, 4);
1002 if (dd->out_sg->length == _calc_walked(out)) {
1003 dd->out_sg = sg_next(dd->out_sg);
1004 if (dd->out_sg) {
1005 scatterwalk_start(&dd->out_walk,
1006 dd->out_sg);
1007 dst = sg_virt(dd->out_sg) +
1008 _calc_walked(out);
1009 }
1010 } else {
1011 dst++;
1012 }
1013 }
1014
1015 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
1016
1017 /* Clear IRQ status */
1018 status &= ~AES_REG_IRQ_DATA_OUT;
1019 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
1020
1021 if (!dd->total)
1022 /* All bytes read! */
1023 tasklet_schedule(&dd->done_task);
1024 else
1025 /* Enable DATA_IN interrupt for next block */
1026 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
1027 }
1028
1029 return IRQ_HANDLED;
1030 }
1031
1032 static const struct of_device_id omap_aes_of_match[] = {
1033 {
1034 .compatible = "ti,omap2-aes",
1035 .data = &omap_aes_pdata_omap2,
1036 },
1037 {
1038 .compatible = "ti,omap3-aes",
1039 .data = &omap_aes_pdata_omap3,
1040 },
1041 {
1042 .compatible = "ti,omap4-aes",
1043 .data = &omap_aes_pdata_omap4,
1044 },
1045 {},
1046 };
1047 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
1048
1049 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1050 struct device *dev, struct resource *res)
1051 {
1052 struct device_node *node = dev->of_node;
1053 const struct of_device_id *match;
1054 int err = 0;
1055
1056 match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
1057 if (!match) {
1058 dev_err(dev, "no compatible OF match\n");
1059 err = -EINVAL;
1060 goto err;
1061 }
1062
1063 err = of_address_to_resource(node, 0, res);
1064 if (err < 0) {
1065 dev_err(dev, "can't translate OF node address\n");
1066 err = -EINVAL;
1067 goto err;
1068 }
1069
1070 dd->pdata = match->data;
1071
1072 err:
1073 return err;
1074 }
1075 #else
1076 static const struct of_device_id omap_aes_of_match[] = {
1077 {},
1078 };
1079
1080 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1081 struct device *dev, struct resource *res)
1082 {
1083 return -EINVAL;
1084 }
1085 #endif
1086
1087 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1088 struct platform_device *pdev, struct resource *res)
1089 {
1090 struct device *dev = &pdev->dev;
1091 struct resource *r;
1092 int err = 0;
1093
1094 /* Get the base address */
1095 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1096 if (!r) {
1097 dev_err(dev, "no MEM resource info\n");
1098 err = -ENODEV;
1099 goto err;
1100 }
1101 memcpy(res, r, sizeof(*res));
1102
1103 /* Only OMAP2/3 can be non-DT */
1104 dd->pdata = &omap_aes_pdata_omap2;
1105
1106 err:
1107 return err;
1108 }
1109
1110 static int omap_aes_probe(struct platform_device *pdev)
1111 {
1112 struct device *dev = &pdev->dev;
1113 struct omap_aes_dev *dd;
1114 struct crypto_alg *algp;
1115 struct resource res;
1116 int err = -ENOMEM, i, j, irq = -1;
1117 u32 reg;
1118
1119 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1120 if (dd == NULL) {
1121 dev_err(dev, "unable to alloc data struct.\n");
1122 goto err_data;
1123 }
1124 dd->dev = dev;
1125 platform_set_drvdata(pdev, dd);
1126
1127 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1128 omap_aes_get_res_pdev(dd, pdev, &res);
1129 if (err)
1130 goto err_res;
1131
1132 dd->io_base = devm_ioremap_resource(dev, &res);
1133 if (IS_ERR(dd->io_base)) {
1134 err = PTR_ERR(dd->io_base);
1135 goto err_res;
1136 }
1137 dd->phys_base = res.start;
1138
1139 pm_runtime_enable(dev);
1140 err = pm_runtime_get_sync(dev);
1141 if (err < 0) {
1142 dev_err(dev, "%s: failed to get_sync(%d)\n",
1143 __func__, err);
1144 goto err_res;
1145 }
1146
1147 omap_aes_dma_stop(dd);
1148
1149 reg = omap_aes_read(dd, AES_REG_REV(dd));
1150
1151 pm_runtime_put_sync(dev);
1152
1153 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1154 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1155 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1156
1157 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1158
1159 err = omap_aes_dma_init(dd);
1160 if (err == -EPROBE_DEFER) {
1161 goto err_irq;
1162 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1163 dd->pio_only = 1;
1164
1165 irq = platform_get_irq(pdev, 0);
1166 if (irq < 0) {
1167 dev_err(dev, "can't get IRQ resource\n");
1168 goto err_irq;
1169 }
1170
1171 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1172 dev_name(dev), dd);
1173 if (err) {
1174 dev_err(dev, "Unable to grab omap-aes IRQ\n");
1175 goto err_irq;
1176 }
1177 }
1178
1179
1180 INIT_LIST_HEAD(&dd->list);
1181 spin_lock(&list_lock);
1182 list_add_tail(&dd->list, &dev_list);
1183 spin_unlock(&list_lock);
1184
1185 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1186 if (!dd->pdata->algs_info[i].registered) {
1187 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1188 algp = &dd->pdata->algs_info[i].algs_list[j];
1189
1190 pr_debug("reg alg: %s\n", algp->cra_name);
1191 INIT_LIST_HEAD(&algp->cra_list);
1192
1193 err = crypto_register_alg(algp);
1194 if (err)
1195 goto err_algs;
1196
1197 dd->pdata->algs_info[i].registered++;
1198 }
1199 }
1200 }
1201
1202 /* Initialize crypto engine */
1203 dd->engine = crypto_engine_alloc_init(dev, 1);
1204 if (!dd->engine)
1205 goto err_algs;
1206
1207 dd->engine->prepare_request = omap_aes_prepare_req;
1208 dd->engine->crypt_one_request = omap_aes_crypt_req;
1209 err = crypto_engine_start(dd->engine);
1210 if (err)
1211 goto err_engine;
1212
1213 return 0;
1214 err_engine:
1215 crypto_engine_exit(dd->engine);
1216 err_algs:
1217 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1218 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1219 crypto_unregister_alg(
1220 &dd->pdata->algs_info[i].algs_list[j]);
1221
1222 omap_aes_dma_cleanup(dd);
1223 err_irq:
1224 tasklet_kill(&dd->done_task);
1225 pm_runtime_disable(dev);
1226 err_res:
1227 dd = NULL;
1228 err_data:
1229 dev_err(dev, "initialization failed.\n");
1230 return err;
1231 }
1232
1233 static int omap_aes_remove(struct platform_device *pdev)
1234 {
1235 struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1236 int i, j;
1237
1238 if (!dd)
1239 return -ENODEV;
1240
1241 spin_lock(&list_lock);
1242 list_del(&dd->list);
1243 spin_unlock(&list_lock);
1244
1245 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1246 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1247 crypto_unregister_alg(
1248 &dd->pdata->algs_info[i].algs_list[j]);
1249
1250 crypto_engine_exit(dd->engine);
1251 tasklet_kill(&dd->done_task);
1252 omap_aes_dma_cleanup(dd);
1253 pm_runtime_disable(dd->dev);
1254 dd = NULL;
1255
1256 return 0;
1257 }
1258
1259 #ifdef CONFIG_PM_SLEEP
1260 static int omap_aes_suspend(struct device *dev)
1261 {
1262 pm_runtime_put_sync(dev);
1263 return 0;
1264 }
1265
1266 static int omap_aes_resume(struct device *dev)
1267 {
1268 pm_runtime_get_sync(dev);
1269 return 0;
1270 }
1271 #endif
1272
1273 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1274
1275 static struct platform_driver omap_aes_driver = {
1276 .probe = omap_aes_probe,
1277 .remove = omap_aes_remove,
1278 .driver = {
1279 .name = "omap-aes",
1280 .pm = &omap_aes_pm_ops,
1281 .of_match_table = omap_aes_of_match,
1282 },
1283 };
1284
1285 module_platform_driver(omap_aes_driver);
1286
1287 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1288 MODULE_LICENSE("GPL v2");
1289 MODULE_AUTHOR("Dmitry Kasatkin");
1290
Linux kernel - Deliverables
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