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228c658c0e8ce8e04df156e5a5daccffaa113a71
[deliverable/linux.git] / drivers / devfreq / exynos / exynos4_bus.c
1 /* drivers/devfreq/exynos4210_memorybus.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 * MyungJoo Ham <myungjoo.ham@samsung.com>
6 *
7 * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
8 * This version supports EXYNOS4210 only. This changes bus frequencies
9 * and vddint voltages. Exynos4412/4212 should be able to be supported
10 * with minor modifications.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/io.h>
19 #include <linux/slab.h>
20 #include <linux/mutex.h>
21 #include <linux/suspend.h>
22 #include <linux/pm_opp.h>
23 #include <linux/devfreq.h>
24 #include <linux/platform_device.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/module.h>
27
28 #include <mach/map.h>
29
30 #include "exynos_ppmu.h"
31 #include "exynos4_bus.h"
32
33 /* Exynos4 ASV has been in the mailing list, but not upstreamed, yet. */
34 #ifdef CONFIG_EXYNOS_ASV
35 extern unsigned int exynos_result_of_asv;
36 #endif
37
38 #define MAX_SAFEVOLT 1200000 /* 1.2V */
39
40 enum exynos4_busf_type {
41 TYPE_BUSF_EXYNOS4210,
42 TYPE_BUSF_EXYNOS4x12,
43 };
44
45 /* Assume that the bus is saturated if the utilization is 40% */
46 #define BUS_SATURATION_RATIO 40
47
48 enum busclk_level_idx {
49 LV_0 = 0,
50 LV_1,
51 LV_2,
52 LV_3,
53 LV_4,
54 _LV_END
55 };
56
57 enum exynos_ppmu_idx {
58 PPMU_DMC0,
59 PPMU_DMC1,
60 PPMU_END,
61 };
62
63 #define EX4210_LV_MAX LV_2
64 #define EX4x12_LV_MAX LV_4
65 #define EX4210_LV_NUM (LV_2 + 1)
66 #define EX4x12_LV_NUM (LV_4 + 1)
67
68 /**
69 * struct busfreq_opp_info - opp information for bus
70 * @rate: Frequency in hertz
71 * @volt: Voltage in microvolts corresponding to this OPP
72 */
73 struct busfreq_opp_info {
74 unsigned long rate;
75 unsigned long volt;
76 };
77
78 struct busfreq_data {
79 enum exynos4_busf_type type;
80 struct device *dev;
81 struct devfreq *devfreq;
82 bool disabled;
83 struct regulator *vdd_int;
84 struct regulator *vdd_mif; /* Exynos4412/4212 only */
85 struct busfreq_opp_info curr_oppinfo;
86 struct exynos_ppmu ppmu[PPMU_END];
87
88 struct notifier_block pm_notifier;
89 struct mutex lock;
90
91 /* Dividers calculated at boot/probe-time */
92 unsigned int dmc_divtable[_LV_END]; /* DMC0 */
93 unsigned int top_divtable[_LV_END];
94 };
95
96 /* 4210 controls clock of mif and voltage of int */
97 static struct bus_opp_table exynos4210_busclk_table[] = {
98 {LV_0, 400000, 1150000},
99 {LV_1, 267000, 1050000},
100 {LV_2, 133000, 1025000},
101 {0, 0, 0},
102 };
103
104 /*
105 * MIF is the main control knob clock for Exynos4x12 MIF/INT
106 * clock and voltage of both mif/int are controlled.
107 */
108 static struct bus_opp_table exynos4x12_mifclk_table[] = {
109 {LV_0, 400000, 1100000},
110 {LV_1, 267000, 1000000},
111 {LV_2, 160000, 950000},
112 {LV_3, 133000, 950000},
113 {LV_4, 100000, 950000},
114 {0, 0, 0},
115 };
116
117 /*
118 * INT is not the control knob of 4x12. LV_x is not meant to represent
119 * the current performance. (MIF does)
120 */
121 static struct bus_opp_table exynos4x12_intclk_table[] = {
122 {LV_0, 200000, 1000000},
123 {LV_1, 160000, 950000},
124 {LV_2, 133000, 925000},
125 {LV_3, 100000, 900000},
126 {0, 0, 0},
127 };
128
129 /* TODO: asv volt definitions are "__initdata"? */
130 /* Some chips have different operating voltages */
131 static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = {
132 {1150000, 1050000, 1050000},
133 {1125000, 1025000, 1025000},
134 {1100000, 1000000, 1000000},
135 {1075000, 975000, 975000},
136 {1050000, 950000, 950000},
137 };
138
139 static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = {
140 /* 400 267 160 133 100 */
141 {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */
142 {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */
143 {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */
144 {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */
145 {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */
146 {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */
147 {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */
148 {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */
149 {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */
150 };
151
152 static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = {
153 /* 200 160 133 100 */
154 {1000000, 950000, 925000, 900000}, /* ASV0 */
155 {975000, 925000, 925000, 900000}, /* ASV1 */
156 {950000, 925000, 900000, 875000}, /* ASV2 */
157 {950000, 900000, 900000, 875000}, /* ASV3 */
158 {925000, 875000, 875000, 875000}, /* ASV4 */
159 {900000, 850000, 850000, 850000}, /* ASV5 */
160 {900000, 850000, 850000, 850000}, /* ASV6 */
161 {900000, 850000, 850000, 850000}, /* ASV7 */
162 {900000, 850000, 850000, 850000}, /* ASV8 */
163 };
164
165 /*** Clock Divider Data for Exynos4210 ***/
166 static unsigned int exynos4210_clkdiv_dmc0[][8] = {
167 /*
168 * Clock divider value for following
169 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
170 * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
171 */
172
173 /* DMC L0: 400MHz */
174 { 3, 1, 1, 1, 1, 1, 3, 1 },
175 /* DMC L1: 266.7MHz */
176 { 4, 1, 1, 2, 1, 1, 3, 1 },
177 /* DMC L2: 133MHz */
178 { 5, 1, 1, 5, 1, 1, 3, 1 },
179 };
180 static unsigned int exynos4210_clkdiv_top[][5] = {
181 /*
182 * Clock divider value for following
183 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
184 */
185 /* ACLK200 L0: 200MHz */
186 { 3, 7, 4, 5, 1 },
187 /* ACLK200 L1: 160MHz */
188 { 4, 7, 5, 6, 1 },
189 /* ACLK200 L2: 133MHz */
190 { 5, 7, 7, 7, 1 },
191 };
192 static unsigned int exynos4210_clkdiv_lr_bus[][2] = {
193 /*
194 * Clock divider value for following
195 * { DIVGDL/R, DIVGPL/R }
196 */
197 /* ACLK_GDL/R L1: 200MHz */
198 { 3, 1 },
199 /* ACLK_GDL/R L2: 160MHz */
200 { 4, 1 },
201 /* ACLK_GDL/R L3: 133MHz */
202 { 5, 1 },
203 };
204
205 /*** Clock Divider Data for Exynos4212/4412 ***/
206 static unsigned int exynos4x12_clkdiv_dmc0[][6] = {
207 /*
208 * Clock divider value for following
209 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
210 * DIVDMCP}
211 */
212
213 /* DMC L0: 400MHz */
214 {3, 1, 1, 1, 1, 1},
215 /* DMC L1: 266.7MHz */
216 {4, 1, 1, 2, 1, 1},
217 /* DMC L2: 160MHz */
218 {5, 1, 1, 4, 1, 1},
219 /* DMC L3: 133MHz */
220 {5, 1, 1, 5, 1, 1},
221 /* DMC L4: 100MHz */
222 {7, 1, 1, 7, 1, 1},
223 };
224 static unsigned int exynos4x12_clkdiv_dmc1[][6] = {
225 /*
226 * Clock divider value for following
227 * { G2DACP, DIVC2C, DIVC2C_ACLK }
228 */
229
230 /* DMC L0: 400MHz */
231 {3, 1, 1},
232 /* DMC L1: 266.7MHz */
233 {4, 2, 1},
234 /* DMC L2: 160MHz */
235 {5, 4, 1},
236 /* DMC L3: 133MHz */
237 {5, 5, 1},
238 /* DMC L4: 100MHz */
239 {7, 7, 1},
240 };
241 static unsigned int exynos4x12_clkdiv_top[][5] = {
242 /*
243 * Clock divider value for following
244 * { DIVACLK266_GPS, DIVACLK100, DIVACLK160,
245 DIVACLK133, DIVONENAND }
246 */
247
248 /* ACLK_GDL/R L0: 200MHz */
249 {2, 7, 4, 5, 1},
250 /* ACLK_GDL/R L1: 200MHz */
251 {2, 7, 4, 5, 1},
252 /* ACLK_GDL/R L2: 160MHz */
253 {4, 7, 5, 7, 1},
254 /* ACLK_GDL/R L3: 133MHz */
255 {4, 7, 5, 7, 1},
256 /* ACLK_GDL/R L4: 100MHz */
257 {7, 7, 7, 7, 1},
258 };
259 static unsigned int exynos4x12_clkdiv_lr_bus[][2] = {
260 /*
261 * Clock divider value for following
262 * { DIVGDL/R, DIVGPL/R }
263 */
264
265 /* ACLK_GDL/R L0: 200MHz */
266 {3, 1},
267 /* ACLK_GDL/R L1: 200MHz */
268 {3, 1},
269 /* ACLK_GDL/R L2: 160MHz */
270 {4, 1},
271 /* ACLK_GDL/R L3: 133MHz */
272 {5, 1},
273 /* ACLK_GDL/R L4: 100MHz */
274 {7, 1},
275 };
276 static unsigned int exynos4x12_clkdiv_sclkip[][3] = {
277 /*
278 * Clock divider value for following
279 * { DIVMFC, DIVJPEG, DIVFIMC0~3}
280 */
281
282 /* SCLK_MFC: 200MHz */
283 {3, 3, 4},
284 /* SCLK_MFC: 200MHz */
285 {3, 3, 4},
286 /* SCLK_MFC: 160MHz */
287 {4, 4, 5},
288 /* SCLK_MFC: 133MHz */
289 {5, 5, 5},
290 /* SCLK_MFC: 100MHz */
291 {7, 7, 7},
292 };
293
294
295 static int exynos4210_set_busclk(struct busfreq_data *data,
296 struct busfreq_opp_info *oppi)
297 {
298 unsigned int index;
299 unsigned int tmp;
300
301 for (index = LV_0; index < EX4210_LV_NUM; index++)
302 if (oppi->rate == exynos4210_busclk_table[index].clk)
303 break;
304
305 if (index == EX4210_LV_NUM)
306 return -EINVAL;
307
308 /* Change Divider - DMC0 */
309 tmp = data->dmc_divtable[index];
310
311 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
312
313 do {
314 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
315 } while (tmp & 0x11111111);
316
317 /* Change Divider - TOP */
318 tmp = data->top_divtable[index];
319
320 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
321
322 do {
323 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
324 } while (tmp & 0x11111);
325
326 /* Change Divider - LEFTBUS */
327 tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
328
329 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
330
331 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
332 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
333 (exynos4210_clkdiv_lr_bus[index][1] <<
334 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
335
336 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
337
338 do {
339 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
340 } while (tmp & 0x11);
341
342 /* Change Divider - RIGHTBUS */
343 tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
344
345 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
346
347 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
348 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
349 (exynos4210_clkdiv_lr_bus[index][1] <<
350 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
351
352 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
353
354 do {
355 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
356 } while (tmp & 0x11);
357
358 return 0;
359 }
360
361 static int exynos4x12_set_busclk(struct busfreq_data *data,
362 struct busfreq_opp_info *oppi)
363 {
364 unsigned int index;
365 unsigned int tmp;
366
367 for (index = LV_0; index < EX4x12_LV_NUM; index++)
368 if (oppi->rate == exynos4x12_mifclk_table[index].clk)
369 break;
370
371 if (index == EX4x12_LV_NUM)
372 return -EINVAL;
373
374 /* Change Divider - DMC0 */
375 tmp = data->dmc_divtable[index];
376
377 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
378
379 do {
380 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
381 } while (tmp & 0x11111111);
382
383 /* Change Divider - DMC1 */
384 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
385
386 tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK |
387 EXYNOS4_CLKDIV_DMC1_C2C_MASK |
388 EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK);
389
390 tmp |= ((exynos4x12_clkdiv_dmc1[index][0] <<
391 EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) |
392 (exynos4x12_clkdiv_dmc1[index][1] <<
393 EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) |
394 (exynos4x12_clkdiv_dmc1[index][2] <<
395 EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT));
396
397 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
398
399 do {
400 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1);
401 } while (tmp & 0x111111);
402
403 /* Change Divider - TOP */
404 tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
405
406 tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK |
407 EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
408 EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
409 EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
410 EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
411
412 tmp |= ((exynos4x12_clkdiv_top[index][0] <<
413 EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
414 (exynos4x12_clkdiv_top[index][1] <<
415 EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
416 (exynos4x12_clkdiv_top[index][2] <<
417 EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
418 (exynos4x12_clkdiv_top[index][3] <<
419 EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
420 (exynos4x12_clkdiv_top[index][4] <<
421 EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
422
423 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
424
425 do {
426 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
427 } while (tmp & 0x11111);
428
429 /* Change Divider - LEFTBUS */
430 tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
431
432 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
433
434 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
435 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
436 (exynos4x12_clkdiv_lr_bus[index][1] <<
437 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
438
439 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
440
441 do {
442 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
443 } while (tmp & 0x11);
444
445 /* Change Divider - RIGHTBUS */
446 tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
447
448 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
449
450 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
451 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
452 (exynos4x12_clkdiv_lr_bus[index][1] <<
453 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
454
455 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
456
457 do {
458 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
459 } while (tmp & 0x11);
460
461 /* Change Divider - MFC */
462 tmp = __raw_readl(EXYNOS4_CLKDIV_MFC);
463
464 tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK);
465
466 tmp |= ((exynos4x12_clkdiv_sclkip[index][0] <<
467 EXYNOS4_CLKDIV_MFC_SHIFT));
468
469 __raw_writel(tmp, EXYNOS4_CLKDIV_MFC);
470
471 do {
472 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC);
473 } while (tmp & 0x1);
474
475 /* Change Divider - JPEG */
476 tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1);
477
478 tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK);
479
480 tmp |= ((exynos4x12_clkdiv_sclkip[index][1] <<
481 EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT));
482
483 __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1);
484
485 do {
486 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
487 } while (tmp & 0x1);
488
489 /* Change Divider - FIMC0~3 */
490 tmp = __raw_readl(EXYNOS4_CLKDIV_CAM);
491
492 tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK |
493 EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK);
494
495 tmp |= ((exynos4x12_clkdiv_sclkip[index][2] <<
496 EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) |
497 (exynos4x12_clkdiv_sclkip[index][2] <<
498 EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) |
499 (exynos4x12_clkdiv_sclkip[index][2] <<
500 EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) |
501 (exynos4x12_clkdiv_sclkip[index][2] <<
502 EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT));
503
504 __raw_writel(tmp, EXYNOS4_CLKDIV_CAM);
505
506 do {
507 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
508 } while (tmp & 0x1111);
509
510 return 0;
511 }
512
513 static void busfreq_mon_reset(struct busfreq_data *data)
514 {
515 unsigned int i;
516
517 for (i = 0; i < PPMU_END; i++) {
518 void __iomem *ppmu_base = data->ppmu[i].hw_base;
519
520 /* Reset the performance and cycle counters */
521 exynos_ppmu_reset(ppmu_base);
522
523 /* Setup count registers to monitor read/write transactions */
524 data->ppmu[i].event[PPMU_PMNCNT3] = RDWR_DATA_COUNT;
525 exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3,
526 data->ppmu[i].event[PPMU_PMNCNT3]);
527
528 exynos_ppmu_start(ppmu_base);
529 }
530 }
531
532 static void exynos4_read_ppmu(struct busfreq_data *data)
533 {
534 int i, j;
535
536 for (i = 0; i < PPMU_END; i++) {
537 void __iomem *ppmu_base = data->ppmu[i].hw_base;
538
539 exynos_ppmu_stop(ppmu_base);
540
541 /* Update local data from PPMU */
542 data->ppmu[i].ccnt = __raw_readl(ppmu_base + PPMU_CCNT);
543
544 for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
545 if (data->ppmu[i].event[j] == 0)
546 data->ppmu[i].count[j] = 0;
547 else
548 data->ppmu[i].count[j] =
549 exynos_ppmu_read(ppmu_base, j);
550 }
551 }
552
553 busfreq_mon_reset(data);
554 }
555
556 static int exynos4x12_get_intspec(unsigned long mifclk)
557 {
558 int i = 0;
559
560 while (exynos4x12_intclk_table[i].clk) {
561 if (exynos4x12_intclk_table[i].clk <= mifclk)
562 return i;
563 i++;
564 }
565
566 return -EINVAL;
567 }
568
569 static int exynos4_bus_setvolt(struct busfreq_data *data,
570 struct busfreq_opp_info *oppi,
571 struct busfreq_opp_info *oldoppi)
572 {
573 int err = 0, tmp;
574 unsigned long volt = oppi->volt;
575
576 switch (data->type) {
577 case TYPE_BUSF_EXYNOS4210:
578 /* OPP represents DMC clock + INT voltage */
579 err = regulator_set_voltage(data->vdd_int, volt,
580 MAX_SAFEVOLT);
581 break;
582 case TYPE_BUSF_EXYNOS4x12:
583 /* OPP represents MIF clock + MIF voltage */
584 err = regulator_set_voltage(data->vdd_mif, volt,
585 MAX_SAFEVOLT);
586 if (err)
587 break;
588
589 tmp = exynos4x12_get_intspec(oppi->rate);
590 if (tmp < 0) {
591 err = tmp;
592 regulator_set_voltage(data->vdd_mif,
593 oldoppi->volt,
594 MAX_SAFEVOLT);
595 break;
596 }
597 err = regulator_set_voltage(data->vdd_int,
598 exynos4x12_intclk_table[tmp].volt,
599 MAX_SAFEVOLT);
600 /* Try to recover */
601 if (err)
602 regulator_set_voltage(data->vdd_mif,
603 oldoppi->volt,
604 MAX_SAFEVOLT);
605 break;
606 default:
607 err = -EINVAL;
608 }
609
610 return err;
611 }
612
613 static int exynos4_bus_target(struct device *dev, unsigned long *_freq,
614 u32 flags)
615 {
616 int err = 0;
617 struct platform_device *pdev = container_of(dev, struct platform_device,
618 dev);
619 struct busfreq_data *data = platform_get_drvdata(pdev);
620 struct dev_pm_opp *opp;
621 unsigned long freq;
622 unsigned long old_freq = data->curr_oppinfo.rate;
623 struct busfreq_opp_info new_oppinfo;
624
625 rcu_read_lock();
626 opp = devfreq_recommended_opp(dev, _freq, flags);
627 if (IS_ERR(opp)) {
628 rcu_read_unlock();
629 return PTR_ERR(opp);
630 }
631 new_oppinfo.rate = dev_pm_opp_get_freq(opp);
632 new_oppinfo.volt = dev_pm_opp_get_voltage(opp);
633 rcu_read_unlock();
634 freq = new_oppinfo.rate;
635
636 if (old_freq == freq)
637 return 0;
638
639 dev_dbg(dev, "targeting %lukHz %luuV\n", freq, new_oppinfo.volt);
640
641 mutex_lock(&data->lock);
642
643 if (data->disabled)
644 goto out;
645
646 if (old_freq < freq)
647 err = exynos4_bus_setvolt(data, &new_oppinfo,
648 &data->curr_oppinfo);
649 if (err)
650 goto out;
651
652 if (old_freq != freq) {
653 switch (data->type) {
654 case TYPE_BUSF_EXYNOS4210:
655 err = exynos4210_set_busclk(data, &new_oppinfo);
656 break;
657 case TYPE_BUSF_EXYNOS4x12:
658 err = exynos4x12_set_busclk(data, &new_oppinfo);
659 break;
660 default:
661 err = -EINVAL;
662 }
663 }
664 if (err)
665 goto out;
666
667 if (old_freq > freq)
668 err = exynos4_bus_setvolt(data, &new_oppinfo,
669 &data->curr_oppinfo);
670 if (err)
671 goto out;
672
673 data->curr_oppinfo = new_oppinfo;
674 out:
675 mutex_unlock(&data->lock);
676 return err;
677 }
678
679 static int exynos4_get_busier_ppmu(struct busfreq_data *data)
680 {
681 int i, j;
682 int busy = 0;
683 unsigned int temp = 0;
684
685 for (i = 0; i < PPMU_END; i++) {
686 for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
687 if (data->ppmu[i].count[j] > temp) {
688 temp = data->ppmu[i].count[j];
689 busy = i;
690 }
691 }
692 }
693
694 return busy;
695 }
696
697 static int exynos4_bus_get_dev_status(struct device *dev,
698 struct devfreq_dev_status *stat)
699 {
700 struct busfreq_data *data = dev_get_drvdata(dev);
701 int busier;
702
703 exynos4_read_ppmu(data);
704 busier = exynos4_get_busier_ppmu(data);
705 stat->current_frequency = data->curr_oppinfo.rate;
706
707 /* Number of cycles spent on memory access */
708 stat->busy_time = data->ppmu[busier].count[PPMU_PMNCNT3];
709 stat->busy_time *= 100 / BUS_SATURATION_RATIO;
710 stat->total_time = data->ppmu[busier].ccnt;
711
712 /* If the counters have overflown, retry */
713 if (data->ppmu[busier].ccnt_overflow ||
714 data->ppmu[busier].count_overflow[0])
715 return -EAGAIN;
716
717 return 0;
718 }
719
720 static struct devfreq_dev_profile exynos4_devfreq_profile = {
721 .initial_freq = 400000,
722 .polling_ms = 50,
723 .target = exynos4_bus_target,
724 .get_dev_status = exynos4_bus_get_dev_status,
725 };
726
727 static int exynos4210_init_tables(struct busfreq_data *data)
728 {
729 u32 tmp;
730 int mgrp;
731 int i, err = 0;
732
733 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
734 for (i = LV_0; i < EX4210_LV_NUM; i++) {
735 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
736 EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
737 EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
738 EXYNOS4_CLKDIV_DMC0_DMC_MASK |
739 EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
740 EXYNOS4_CLKDIV_DMC0_DMCP_MASK |
741 EXYNOS4_CLKDIV_DMC0_COPY2_MASK |
742 EXYNOS4_CLKDIV_DMC0_CORETI_MASK);
743
744 tmp |= ((exynos4210_clkdiv_dmc0[i][0] <<
745 EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
746 (exynos4210_clkdiv_dmc0[i][1] <<
747 EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
748 (exynos4210_clkdiv_dmc0[i][2] <<
749 EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
750 (exynos4210_clkdiv_dmc0[i][3] <<
751 EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
752 (exynos4210_clkdiv_dmc0[i][4] <<
753 EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
754 (exynos4210_clkdiv_dmc0[i][5] <<
755 EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
756 (exynos4210_clkdiv_dmc0[i][6] <<
757 EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
758 (exynos4210_clkdiv_dmc0[i][7] <<
759 EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT));
760
761 data->dmc_divtable[i] = tmp;
762 }
763
764 tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
765 for (i = LV_0; i < EX4210_LV_NUM; i++) {
766 tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK |
767 EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
768 EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
769 EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
770 EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
771
772 tmp |= ((exynos4210_clkdiv_top[i][0] <<
773 EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
774 (exynos4210_clkdiv_top[i][1] <<
775 EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
776 (exynos4210_clkdiv_top[i][2] <<
777 EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
778 (exynos4210_clkdiv_top[i][3] <<
779 EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
780 (exynos4210_clkdiv_top[i][4] <<
781 EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
782
783 data->top_divtable[i] = tmp;
784 }
785
786 #ifdef CONFIG_EXYNOS_ASV
787 tmp = exynos4_result_of_asv;
788 #else
789 tmp = 0; /* Max voltages for the reliability of the unknown */
790 #endif
791
792 pr_debug("ASV Group of Exynos4 is %d\n", tmp);
793 /* Use merged grouping for voltage */
794 switch (tmp) {
795 case 0:
796 mgrp = 0;
797 break;
798 case 1:
799 case 2:
800 mgrp = 1;
801 break;
802 case 3:
803 case 4:
804 mgrp = 2;
805 break;
806 case 5:
807 case 6:
808 mgrp = 3;
809 break;
810 case 7:
811 mgrp = 4;
812 break;
813 default:
814 pr_warn("Unknown ASV Group. Use max voltage.\n");
815 mgrp = 0;
816 }
817
818 for (i = LV_0; i < EX4210_LV_NUM; i++)
819 exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i];
820
821 for (i = LV_0; i < EX4210_LV_NUM; i++) {
822 err = dev_pm_opp_add(data->dev, exynos4210_busclk_table[i].clk,
823 exynos4210_busclk_table[i].volt);
824 if (err) {
825 dev_err(data->dev, "Cannot add opp entries.\n");
826 return err;
827 }
828 }
829
830
831 return 0;
832 }
833
834 static int exynos4x12_init_tables(struct busfreq_data *data)
835 {
836 unsigned int i;
837 unsigned int tmp;
838 int ret;
839
840 /* Enable pause function for DREX2 DVFS */
841 tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL);
842 tmp |= EXYNOS4_DMC_PAUSE_ENABLE;
843 __raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL);
844
845 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
846
847 for (i = 0; i < EX4x12_LV_NUM; i++) {
848 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
849 EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
850 EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
851 EXYNOS4_CLKDIV_DMC0_DMC_MASK |
852 EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
853 EXYNOS4_CLKDIV_DMC0_DMCP_MASK);
854
855 tmp |= ((exynos4x12_clkdiv_dmc0[i][0] <<
856 EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
857 (exynos4x12_clkdiv_dmc0[i][1] <<
858 EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
859 (exynos4x12_clkdiv_dmc0[i][2] <<
860 EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
861 (exynos4x12_clkdiv_dmc0[i][3] <<
862 EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
863 (exynos4x12_clkdiv_dmc0[i][4] <<
864 EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
865 (exynos4x12_clkdiv_dmc0[i][5] <<
866 EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT));
867
868 data->dmc_divtable[i] = tmp;
869 }
870
871 #ifdef CONFIG_EXYNOS_ASV
872 tmp = exynos4_result_of_asv;
873 #else
874 tmp = 0; /* Max voltages for the reliability of the unknown */
875 #endif
876
877 if (tmp > 8)
878 tmp = 0;
879 pr_debug("ASV Group of Exynos4x12 is %d\n", tmp);
880
881 for (i = 0; i < EX4x12_LV_NUM; i++) {
882 exynos4x12_mifclk_table[i].volt =
883 exynos4x12_mif_step_50[tmp][i];
884 exynos4x12_intclk_table[i].volt =
885 exynos4x12_int_volt[tmp][i];
886 }
887
888 for (i = 0; i < EX4x12_LV_NUM; i++) {
889 ret = dev_pm_opp_add(data->dev, exynos4x12_mifclk_table[i].clk,
890 exynos4x12_mifclk_table[i].volt);
891 if (ret) {
892 dev_err(data->dev, "Fail to add opp entries.\n");
893 return ret;
894 }
895 }
896
897 return 0;
898 }
899
900 static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this,
901 unsigned long event, void *ptr)
902 {
903 struct busfreq_data *data = container_of(this, struct busfreq_data,
904 pm_notifier);
905 struct dev_pm_opp *opp;
906 struct busfreq_opp_info new_oppinfo;
907 unsigned long maxfreq = ULONG_MAX;
908 int err = 0;
909
910 switch (event) {
911 case PM_SUSPEND_PREPARE:
912 /* Set Fastest and Deactivate DVFS */
913 mutex_lock(&data->lock);
914
915 data->disabled = true;
916
917 rcu_read_lock();
918 opp = dev_pm_opp_find_freq_floor(data->dev, &maxfreq);
919 if (IS_ERR(opp)) {
920 rcu_read_unlock();
921 dev_err(data->dev, "%s: unable to find a min freq\n",
922 __func__);
923 mutex_unlock(&data->lock);
924 return PTR_ERR(opp);
925 }
926 new_oppinfo.rate = dev_pm_opp_get_freq(opp);
927 new_oppinfo.volt = dev_pm_opp_get_voltage(opp);
928 rcu_read_unlock();
929
930 err = exynos4_bus_setvolt(data, &new_oppinfo,
931 &data->curr_oppinfo);
932 if (err)
933 goto unlock;
934
935 switch (data->type) {
936 case TYPE_BUSF_EXYNOS4210:
937 err = exynos4210_set_busclk(data, &new_oppinfo);
938 break;
939 case TYPE_BUSF_EXYNOS4x12:
940 err = exynos4x12_set_busclk(data, &new_oppinfo);
941 break;
942 default:
943 err = -EINVAL;
944 }
945 if (err)
946 goto unlock;
947
948 data->curr_oppinfo = new_oppinfo;
949 unlock:
950 mutex_unlock(&data->lock);
951 if (err)
952 return err;
953 return NOTIFY_OK;
954 case PM_POST_RESTORE:
955 case PM_POST_SUSPEND:
956 /* Reactivate */
957 mutex_lock(&data->lock);
958 data->disabled = false;
959 mutex_unlock(&data->lock);
960 return NOTIFY_OK;
961 }
962
963 return NOTIFY_DONE;
964 }
965
966 static int exynos4_busfreq_probe(struct platform_device *pdev)
967 {
968 struct busfreq_data *data;
969 struct dev_pm_opp *opp;
970 struct device *dev = &pdev->dev;
971 int err = 0;
972
973 data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data), GFP_KERNEL);
974 if (data == NULL) {
975 dev_err(dev, "Cannot allocate memory.\n");
976 return -ENOMEM;
977 }
978
979 data->type = pdev->id_entry->driver_data;
980 data->ppmu[PPMU_DMC0].hw_base = S5P_VA_DMC0;
981 data->ppmu[PPMU_DMC1].hw_base = S5P_VA_DMC1;
982 data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event;
983 data->dev = dev;
984 mutex_init(&data->lock);
985
986 switch (data->type) {
987 case TYPE_BUSF_EXYNOS4210:
988 err = exynos4210_init_tables(data);
989 break;
990 case TYPE_BUSF_EXYNOS4x12:
991 err = exynos4x12_init_tables(data);
992 break;
993 default:
994 dev_err(dev, "Cannot determine the device id %d\n", data->type);
995 err = -EINVAL;
996 }
997 if (err) {
998 dev_err(dev, "Cannot initialize busfreq table %d\n",
999 data->type);
1000 return err;
1001 }
1002
1003 data->vdd_int = devm_regulator_get(dev, "vdd_int");
1004 if (IS_ERR(data->vdd_int)) {
1005 dev_err(dev, "Cannot get the regulator \"vdd_int\"\n");
1006 return PTR_ERR(data->vdd_int);
1007 }
1008 if (data->type == TYPE_BUSF_EXYNOS4x12) {
1009 data->vdd_mif = devm_regulator_get(dev, "vdd_mif");
1010 if (IS_ERR(data->vdd_mif)) {
1011 dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n");
1012 return PTR_ERR(data->vdd_mif);
1013 }
1014 }
1015
1016 rcu_read_lock();
1017 opp = dev_pm_opp_find_freq_floor(dev,
1018 &exynos4_devfreq_profile.initial_freq);
1019 if (IS_ERR(opp)) {
1020 rcu_read_unlock();
1021 dev_err(dev, "Invalid initial frequency %lu kHz.\n",
1022 exynos4_devfreq_profile.initial_freq);
1023 return PTR_ERR(opp);
1024 }
1025 data->curr_oppinfo.rate = dev_pm_opp_get_freq(opp);
1026 data->curr_oppinfo.volt = dev_pm_opp_get_voltage(opp);
1027 rcu_read_unlock();
1028
1029 platform_set_drvdata(pdev, data);
1030
1031 data->devfreq = devfreq_add_device(dev, &exynos4_devfreq_profile,
1032 "simple_ondemand", NULL);
1033 if (IS_ERR(data->devfreq))
1034 return PTR_ERR(data->devfreq);
1035
1036 /*
1037 * Start PPMU (Performance Profiling Monitoring Unit) to check
1038 * utilization of each IP in the Exynos4 SoC.
1039 */
1040 busfreq_mon_reset(data);
1041
1042 /* Register opp_notifier for Exynos4 busfreq */
1043 err = devfreq_register_opp_notifier(dev, data->devfreq);
1044 if (err < 0) {
1045 dev_err(dev, "Failed to register opp notifier\n");
1046 goto err_notifier_opp;
1047 }
1048
1049 /* Register pm_notifier for Exynos4 busfreq */
1050 err = register_pm_notifier(&data->pm_notifier);
1051 if (err) {
1052 dev_err(dev, "Failed to setup pm notifier\n");
1053 goto err_notifier_pm;
1054 }
1055
1056 return 0;
1057
1058 err_notifier_pm:
1059 devfreq_unregister_opp_notifier(dev, data->devfreq);
1060 err_notifier_opp:
1061 devfreq_remove_device(data->devfreq);
1062
1063 return err;
1064 }
1065
1066 static int exynos4_busfreq_remove(struct platform_device *pdev)
1067 {
1068 struct busfreq_data *data = platform_get_drvdata(pdev);
1069
1070 /* Unregister all of notifier chain */
1071 unregister_pm_notifier(&data->pm_notifier);
1072 devfreq_unregister_opp_notifier(data->dev, data->devfreq);
1073
1074 /* Remove devfreq instance */
1075 devfreq_remove_device(data->devfreq);
1076
1077 return 0;
1078 }
1079
1080 #ifdef CONFIG_PM_SLEEP
1081 static int exynos4_busfreq_resume(struct device *dev)
1082 {
1083 struct busfreq_data *data = dev_get_drvdata(dev);
1084
1085 busfreq_mon_reset(data);
1086 return 0;
1087 }
1088 #endif
1089
1090 static SIMPLE_DEV_PM_OPS(exynos4_busfreq_pm_ops, NULL, exynos4_busfreq_resume);
1091
1092 static const struct platform_device_id exynos4_busfreq_id[] = {
1093 { "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 },
1094 { "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 },
1095 { "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 },
1096 { },
1097 };
1098
1099 static struct platform_driver exynos4_busfreq_driver = {
1100 .probe = exynos4_busfreq_probe,
1101 .remove = exynos4_busfreq_remove,
1102 .id_table = exynos4_busfreq_id,
1103 .driver = {
1104 .name = "exynos4-busfreq",
1105 .owner = THIS_MODULE,
1106 .pm = &exynos4_busfreq_pm_ops,
1107 },
1108 };
1109
1110 static int __init exynos4_busfreq_init(void)
1111 {
1112 return platform_driver_register(&exynos4_busfreq_driver);
1113 }
1114 late_initcall(exynos4_busfreq_init);
1115
1116 static void __exit exynos4_busfreq_exit(void)
1117 {
1118 platform_driver_unregister(&exynos4_busfreq_driver);
1119 }
1120 module_exit(exynos4_busfreq_exit);
1121
1122 MODULE_LICENSE("GPL");
1123 MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework");
1124 MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>");
Linux kernel - Deliverables
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