2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <asm/hardware/pl080.h>
88 #include "dmaengine.h"
90 #define DRIVER_NAME "pl08xdmac"
92 static struct amba_driver pl08x_amba_driver
;
95 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
96 * @channels: the number of channels available in this variant
97 * @dualmaster: whether this version supports dual AHB masters or not.
105 * PL08X private data structures
106 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
107 * start & end do not - their bus bit info is in cctl. Also note that these
108 * are fixed 32-bit quantities.
118 * struct pl08x_driver_data - the local state holder for the PL08x
119 * @slave: slave engine for this instance
120 * @memcpy: memcpy engine for this instance
121 * @base: virtual memory base (remapped) for the PL08x
122 * @adev: the corresponding AMBA (PrimeCell) bus entry
123 * @vd: vendor data for this PL08x variant
124 * @pd: platform data passed in from the platform/machine
125 * @phy_chans: array of data for the physical channels
126 * @pool: a pool for the LLI descriptors
127 * @pool_ctr: counter of LLIs in the pool
128 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
130 * @mem_buses: set to indicate memory transfers on AHB2.
131 * @lock: a spinlock for this struct
133 struct pl08x_driver_data
{
134 struct dma_device slave
;
135 struct dma_device memcpy
;
137 struct amba_device
*adev
;
138 const struct vendor_data
*vd
;
139 struct pl08x_platform_data
*pd
;
140 struct pl08x_phy_chan
*phy_chans
;
141 struct dma_pool
*pool
;
149 * PL08X specific defines
152 /* Size (bytes) of each LLI buffer allocated for one transfer */
153 # define PL08X_LLI_TSFR_SIZE 0x2000
155 /* Maximum times we call dma_pool_alloc on this pool without freeing */
156 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
157 #define PL08X_ALIGN 8
159 static inline struct pl08x_dma_chan
*to_pl08x_chan(struct dma_chan
*chan
)
161 return container_of(chan
, struct pl08x_dma_chan
, chan
);
164 static inline struct pl08x_txd
*to_pl08x_txd(struct dma_async_tx_descriptor
*tx
)
166 return container_of(tx
, struct pl08x_txd
, tx
);
170 * Physical channel handling
173 /* Whether a certain channel is busy or not */
174 static int pl08x_phy_channel_busy(struct pl08x_phy_chan
*ch
)
178 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
179 return val
& PL080_CONFIG_ACTIVE
;
183 * Set the initial DMA register values i.e. those for the first LLI
184 * The next LLI pointer and the configuration interrupt bit have
185 * been set when the LLIs were constructed. Poke them into the hardware
186 * and start the transfer.
188 static void pl08x_start_txd(struct pl08x_dma_chan
*plchan
,
189 struct pl08x_txd
*txd
)
191 struct pl08x_driver_data
*pl08x
= plchan
->host
;
192 struct pl08x_phy_chan
*phychan
= plchan
->phychan
;
193 struct pl08x_lli
*lli
= &txd
->llis_va
[0];
198 /* Wait for channel inactive */
199 while (pl08x_phy_channel_busy(phychan
))
202 dev_vdbg(&pl08x
->adev
->dev
,
203 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
204 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
205 phychan
->id
, lli
->src
, lli
->dst
, lli
->lli
, lli
->cctl
,
208 writel(lli
->src
, phychan
->base
+ PL080_CH_SRC_ADDR
);
209 writel(lli
->dst
, phychan
->base
+ PL080_CH_DST_ADDR
);
210 writel(lli
->lli
, phychan
->base
+ PL080_CH_LLI
);
211 writel(lli
->cctl
, phychan
->base
+ PL080_CH_CONTROL
);
212 writel(txd
->ccfg
, phychan
->base
+ PL080_CH_CONFIG
);
214 /* Enable the DMA channel */
215 /* Do not access config register until channel shows as disabled */
216 while (readl(pl08x
->base
+ PL080_EN_CHAN
) & (1 << phychan
->id
))
219 /* Do not access config register until channel shows as inactive */
220 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
221 while ((val
& PL080_CONFIG_ACTIVE
) || (val
& PL080_CONFIG_ENABLE
))
222 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
224 writel(val
| PL080_CONFIG_ENABLE
, phychan
->base
+ PL080_CH_CONFIG
);
228 * Pause the channel by setting the HALT bit.
230 * For M->P transfers, pause the DMAC first and then stop the peripheral -
231 * the FIFO can only drain if the peripheral is still requesting data.
232 * (note: this can still timeout if the DMAC FIFO never drains of data.)
234 * For P->M transfers, disable the peripheral first to stop it filling
235 * the DMAC FIFO, and then pause the DMAC.
237 static void pl08x_pause_phy_chan(struct pl08x_phy_chan
*ch
)
242 /* Set the HALT bit and wait for the FIFO to drain */
243 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
244 val
|= PL080_CONFIG_HALT
;
245 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
247 /* Wait for channel inactive */
248 for (timeout
= 1000; timeout
; timeout
--) {
249 if (!pl08x_phy_channel_busy(ch
))
253 if (pl08x_phy_channel_busy(ch
))
254 pr_err("pl08x: channel%u timeout waiting for pause\n", ch
->id
);
257 static void pl08x_resume_phy_chan(struct pl08x_phy_chan
*ch
)
261 /* Clear the HALT bit */
262 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
263 val
&= ~PL080_CONFIG_HALT
;
264 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
268 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
269 * clears any pending interrupt status. This should not be used for
270 * an on-going transfer, but as a method of shutting down a channel
271 * (eg, when it's no longer used) or terminating a transfer.
273 static void pl08x_terminate_phy_chan(struct pl08x_driver_data
*pl08x
,
274 struct pl08x_phy_chan
*ch
)
276 u32 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
278 val
&= ~(PL080_CONFIG_ENABLE
| PL080_CONFIG_ERR_IRQ_MASK
|
279 PL080_CONFIG_TC_IRQ_MASK
);
281 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
283 writel(1 << ch
->id
, pl08x
->base
+ PL080_ERR_CLEAR
);
284 writel(1 << ch
->id
, pl08x
->base
+ PL080_TC_CLEAR
);
287 static inline u32
get_bytes_in_cctl(u32 cctl
)
289 /* The source width defines the number of bytes */
290 u32 bytes
= cctl
& PL080_CONTROL_TRANSFER_SIZE_MASK
;
292 switch (cctl
>> PL080_CONTROL_SWIDTH_SHIFT
) {
293 case PL080_WIDTH_8BIT
:
295 case PL080_WIDTH_16BIT
:
298 case PL080_WIDTH_32BIT
:
305 /* The channel should be paused when calling this */
306 static u32
pl08x_getbytes_chan(struct pl08x_dma_chan
*plchan
)
308 struct pl08x_phy_chan
*ch
;
309 struct pl08x_txd
*txd
;
313 spin_lock_irqsave(&plchan
->lock
, flags
);
314 ch
= plchan
->phychan
;
318 * Follow the LLIs to get the number of remaining
319 * bytes in the currently active transaction.
322 u32 clli
= readl(ch
->base
+ PL080_CH_LLI
) & ~PL080_LLI_LM_AHB2
;
324 /* First get the remaining bytes in the active transfer */
325 bytes
= get_bytes_in_cctl(readl(ch
->base
+ PL080_CH_CONTROL
));
328 struct pl08x_lli
*llis_va
= txd
->llis_va
;
329 dma_addr_t llis_bus
= txd
->llis_bus
;
332 BUG_ON(clli
< llis_bus
|| clli
>= llis_bus
+
333 sizeof(struct pl08x_lli
) * MAX_NUM_TSFR_LLIS
);
336 * Locate the next LLI - as this is an array,
337 * it's simple maths to find.
339 index
= (clli
- llis_bus
) / sizeof(struct pl08x_lli
);
341 for (; index
< MAX_NUM_TSFR_LLIS
; index
++) {
342 bytes
+= get_bytes_in_cctl(llis_va
[index
].cctl
);
345 * A LLI pointer of 0 terminates the LLI list
347 if (!llis_va
[index
].lli
)
353 /* Sum up all queued transactions */
354 if (!list_empty(&plchan
->pend_list
)) {
355 struct pl08x_txd
*txdi
;
356 list_for_each_entry(txdi
, &plchan
->pend_list
, node
) {
357 struct pl08x_sg
*dsg
;
358 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
363 spin_unlock_irqrestore(&plchan
->lock
, flags
);
369 * Allocate a physical channel for a virtual channel
371 * Try to locate a physical channel to be used for this transfer. If all
372 * are taken return NULL and the requester will have to cope by using
373 * some fallback PIO mode or retrying later.
375 static struct pl08x_phy_chan
*
376 pl08x_get_phy_channel(struct pl08x_driver_data
*pl08x
,
377 struct pl08x_dma_chan
*virt_chan
)
379 struct pl08x_phy_chan
*ch
= NULL
;
383 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
384 ch
= &pl08x
->phy_chans
[i
];
386 spin_lock_irqsave(&ch
->lock
, flags
);
389 ch
->serving
= virt_chan
;
391 spin_unlock_irqrestore(&ch
->lock
, flags
);
395 spin_unlock_irqrestore(&ch
->lock
, flags
);
398 if (i
== pl08x
->vd
->channels
) {
399 /* No physical channel available, cope with it */
403 pm_runtime_get_sync(&pl08x
->adev
->dev
);
407 static inline void pl08x_put_phy_channel(struct pl08x_driver_data
*pl08x
,
408 struct pl08x_phy_chan
*ch
)
412 spin_lock_irqsave(&ch
->lock
, flags
);
414 /* Stop the channel and clear its interrupts */
415 pl08x_terminate_phy_chan(pl08x
, ch
);
417 pm_runtime_put(&pl08x
->adev
->dev
);
419 /* Mark it as free */
421 spin_unlock_irqrestore(&ch
->lock
, flags
);
428 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded
)
431 case PL080_WIDTH_8BIT
:
433 case PL080_WIDTH_16BIT
:
435 case PL080_WIDTH_32BIT
:
444 static inline u32
pl08x_cctl_bits(u32 cctl
, u8 srcwidth
, u8 dstwidth
,
449 /* Remove all src, dst and transfer size bits */
450 retbits
&= ~PL080_CONTROL_DWIDTH_MASK
;
451 retbits
&= ~PL080_CONTROL_SWIDTH_MASK
;
452 retbits
&= ~PL080_CONTROL_TRANSFER_SIZE_MASK
;
454 /* Then set the bits according to the parameters */
457 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
460 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
463 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
472 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
475 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
478 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
485 retbits
|= tsize
<< PL080_CONTROL_TRANSFER_SIZE_SHIFT
;
489 struct pl08x_lli_build_data
{
490 struct pl08x_txd
*txd
;
491 struct pl08x_bus_data srcbus
;
492 struct pl08x_bus_data dstbus
;
498 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
499 * victim in case src & dest are not similarly aligned. i.e. If after aligning
500 * masters address with width requirements of transfer (by sending few byte by
501 * byte data), slave is still not aligned, then its width will be reduced to
503 * - prefers the destination bus if both available
504 * - prefers bus with fixed address (i.e. peripheral)
506 static void pl08x_choose_master_bus(struct pl08x_lli_build_data
*bd
,
507 struct pl08x_bus_data
**mbus
, struct pl08x_bus_data
**sbus
, u32 cctl
)
509 if (!(cctl
& PL080_CONTROL_DST_INCR
)) {
512 } else if (!(cctl
& PL080_CONTROL_SRC_INCR
)) {
516 if (bd
->dstbus
.buswidth
>= bd
->srcbus
.buswidth
) {
527 * Fills in one LLI for a certain transfer descriptor and advance the counter
529 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data
*bd
,
530 int num_llis
, int len
, u32 cctl
)
532 struct pl08x_lli
*llis_va
= bd
->txd
->llis_va
;
533 dma_addr_t llis_bus
= bd
->txd
->llis_bus
;
535 BUG_ON(num_llis
>= MAX_NUM_TSFR_LLIS
);
537 llis_va
[num_llis
].cctl
= cctl
;
538 llis_va
[num_llis
].src
= bd
->srcbus
.addr
;
539 llis_va
[num_llis
].dst
= bd
->dstbus
.addr
;
540 llis_va
[num_llis
].lli
= llis_bus
+ (num_llis
+ 1) *
541 sizeof(struct pl08x_lli
);
542 llis_va
[num_llis
].lli
|= bd
->lli_bus
;
544 if (cctl
& PL080_CONTROL_SRC_INCR
)
545 bd
->srcbus
.addr
+= len
;
546 if (cctl
& PL080_CONTROL_DST_INCR
)
547 bd
->dstbus
.addr
+= len
;
549 BUG_ON(bd
->remainder
< len
);
551 bd
->remainder
-= len
;
554 static inline void prep_byte_width_lli(struct pl08x_lli_build_data
*bd
,
555 u32
*cctl
, u32 len
, int num_llis
, size_t *total_bytes
)
557 *cctl
= pl08x_cctl_bits(*cctl
, 1, 1, len
);
558 pl08x_fill_lli_for_desc(bd
, num_llis
, len
, *cctl
);
559 (*total_bytes
) += len
;
563 * This fills in the table of LLIs for the transfer descriptor
564 * Note that we assume we never have to change the burst sizes
567 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data
*pl08x
,
568 struct pl08x_txd
*txd
)
570 struct pl08x_bus_data
*mbus
, *sbus
;
571 struct pl08x_lli_build_data bd
;
573 u32 cctl
, early_bytes
= 0;
574 size_t max_bytes_per_lli
, total_bytes
;
575 struct pl08x_lli
*llis_va
;
576 struct pl08x_sg
*dsg
;
578 txd
->llis_va
= dma_pool_alloc(pl08x
->pool
, GFP_NOWAIT
, &txd
->llis_bus
);
580 dev_err(&pl08x
->adev
->dev
, "%s no memory for llis\n", __func__
);
587 bd
.lli_bus
= (pl08x
->lli_buses
& PL08X_AHB2
) ? PL080_LLI_LM_AHB2
: 0;
590 /* Find maximum width of the source bus */
592 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_SWIDTH_MASK
) >>
593 PL080_CONTROL_SWIDTH_SHIFT
);
595 /* Find maximum width of the destination bus */
597 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_DWIDTH_MASK
) >>
598 PL080_CONTROL_DWIDTH_SHIFT
);
600 list_for_each_entry(dsg
, &txd
->dsg_list
, node
) {
604 bd
.srcbus
.addr
= dsg
->src_addr
;
605 bd
.dstbus
.addr
= dsg
->dst_addr
;
606 bd
.remainder
= dsg
->len
;
607 bd
.srcbus
.buswidth
= bd
.srcbus
.maxwidth
;
608 bd
.dstbus
.buswidth
= bd
.dstbus
.maxwidth
;
610 pl08x_choose_master_bus(&bd
, &mbus
, &sbus
, cctl
);
612 dev_vdbg(&pl08x
->adev
->dev
, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
613 bd
.srcbus
.addr
, cctl
& PL080_CONTROL_SRC_INCR
? "+" : "",
615 bd
.dstbus
.addr
, cctl
& PL080_CONTROL_DST_INCR
? "+" : "",
618 dev_vdbg(&pl08x
->adev
->dev
, "mbus=%s sbus=%s\n",
619 mbus
== &bd
.srcbus
? "src" : "dst",
620 sbus
== &bd
.srcbus
? "src" : "dst");
623 * Zero length is only allowed if all these requirements are
625 * - flow controller is peripheral.
626 * - src.addr is aligned to src.width
627 * - dst.addr is aligned to dst.width
629 * sg_len == 1 should be true, as there can be two cases here:
631 * - Memory addresses are contiguous and are not scattered.
632 * Here, Only one sg will be passed by user driver, with
633 * memory address and zero length. We pass this to controller
634 * and after the transfer it will receive the last burst
635 * request from peripheral and so transfer finishes.
637 * - Memory addresses are scattered and are not contiguous.
638 * Here, Obviously as DMA controller doesn't know when a lli's
639 * transfer gets over, it can't load next lli. So in this
640 * case, there has to be an assumption that only one lli is
641 * supported. Thus, we can't have scattered addresses.
644 u32 fc
= (txd
->ccfg
& PL080_CONFIG_FLOW_CONTROL_MASK
) >>
645 PL080_CONFIG_FLOW_CONTROL_SHIFT
;
646 if (!((fc
>= PL080_FLOW_SRC2DST_DST
) &&
647 (fc
<= PL080_FLOW_SRC2DST_SRC
))) {
648 dev_err(&pl08x
->adev
->dev
, "%s sg len can't be zero",
653 if ((bd
.srcbus
.addr
% bd
.srcbus
.buswidth
) ||
654 (bd
.dstbus
.addr
% bd
.dstbus
.buswidth
)) {
655 dev_err(&pl08x
->adev
->dev
,
656 "%s src & dst address must be aligned to src"
657 " & dst width if peripheral is flow controller",
662 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
663 bd
.dstbus
.buswidth
, 0);
664 pl08x_fill_lli_for_desc(&bd
, num_llis
++, 0, cctl
);
669 * Send byte by byte for following cases
670 * - Less than a bus width available
671 * - until master bus is aligned
673 if (bd
.remainder
< mbus
->buswidth
)
674 early_bytes
= bd
.remainder
;
675 else if ((mbus
->addr
) % (mbus
->buswidth
)) {
676 early_bytes
= mbus
->buswidth
- (mbus
->addr
) %
678 if ((bd
.remainder
- early_bytes
) < mbus
->buswidth
)
679 early_bytes
= bd
.remainder
;
683 dev_vdbg(&pl08x
->adev
->dev
,
684 "%s byte width LLIs (remain 0x%08x)\n",
685 __func__
, bd
.remainder
);
686 prep_byte_width_lli(&bd
, &cctl
, early_bytes
, num_llis
++,
693 * - if slave is not then we must set its width down
695 if (sbus
->addr
% sbus
->buswidth
) {
696 dev_dbg(&pl08x
->adev
->dev
,
697 "%s set down bus width to one byte\n",
704 * Bytes transferred = tsize * src width, not
707 max_bytes_per_lli
= bd
.srcbus
.buswidth
*
708 PL080_CONTROL_TRANSFER_SIZE_MASK
;
709 dev_vdbg(&pl08x
->adev
->dev
,
710 "%s max bytes per lli = %zu\n",
711 __func__
, max_bytes_per_lli
);
714 * Make largest possible LLIs until less than one bus
717 while (bd
.remainder
> (mbus
->buswidth
- 1)) {
718 size_t lli_len
, tsize
, width
;
721 * If enough left try to send max possible,
722 * otherwise try to send the remainder
724 lli_len
= min(bd
.remainder
, max_bytes_per_lli
);
727 * Check against maximum bus alignment:
728 * Calculate actual transfer size in relation to
729 * bus width an get a maximum remainder of the
730 * highest bus width - 1
732 width
= max(mbus
->buswidth
, sbus
->buswidth
);
733 lli_len
= (lli_len
/ width
) * width
;
734 tsize
= lli_len
/ bd
.srcbus
.buswidth
;
736 dev_vdbg(&pl08x
->adev
->dev
,
737 "%s fill lli with single lli chunk of "
738 "size 0x%08zx (remainder 0x%08zx)\n",
739 __func__
, lli_len
, bd
.remainder
);
741 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
742 bd
.dstbus
.buswidth
, tsize
);
743 pl08x_fill_lli_for_desc(&bd
, num_llis
++,
745 total_bytes
+= lli_len
;
752 dev_vdbg(&pl08x
->adev
->dev
,
753 "%s align with boundary, send odd bytes (remain %zu)\n",
754 __func__
, bd
.remainder
);
755 prep_byte_width_lli(&bd
, &cctl
, bd
.remainder
,
756 num_llis
++, &total_bytes
);
760 if (total_bytes
!= dsg
->len
) {
761 dev_err(&pl08x
->adev
->dev
,
762 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
763 __func__
, total_bytes
, dsg
->len
);
767 if (num_llis
>= MAX_NUM_TSFR_LLIS
) {
768 dev_err(&pl08x
->adev
->dev
,
769 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
770 __func__
, (u32
) MAX_NUM_TSFR_LLIS
);
775 llis_va
= txd
->llis_va
;
776 /* The final LLI terminates the LLI. */
777 llis_va
[num_llis
- 1].lli
= 0;
778 /* The final LLI element shall also fire an interrupt. */
779 llis_va
[num_llis
- 1].cctl
|= PL080_CONTROL_TC_IRQ_EN
;
785 dev_vdbg(&pl08x
->adev
->dev
,
786 "%-3s %-9s %-10s %-10s %-10s %s\n",
787 "lli", "", "csrc", "cdst", "clli", "cctl");
788 for (i
= 0; i
< num_llis
; i
++) {
789 dev_vdbg(&pl08x
->adev
->dev
,
790 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
791 i
, &llis_va
[i
], llis_va
[i
].src
,
792 llis_va
[i
].dst
, llis_va
[i
].lli
, llis_va
[i
].cctl
801 /* You should call this with the struct pl08x lock held */
802 static void pl08x_free_txd(struct pl08x_driver_data
*pl08x
,
803 struct pl08x_txd
*txd
)
805 struct pl08x_sg
*dsg
, *_dsg
;
809 dma_pool_free(pl08x
->pool
, txd
->llis_va
, txd
->llis_bus
);
813 list_for_each_entry_safe(dsg
, _dsg
, &txd
->dsg_list
, node
) {
814 list_del(&dsg
->node
);
821 static void pl08x_free_txd_list(struct pl08x_driver_data
*pl08x
,
822 struct pl08x_dma_chan
*plchan
)
824 struct pl08x_txd
*txdi
= NULL
;
825 struct pl08x_txd
*next
;
827 if (!list_empty(&plchan
->pend_list
)) {
828 list_for_each_entry_safe(txdi
,
829 next
, &plchan
->pend_list
, node
) {
830 list_del(&txdi
->node
);
831 pl08x_free_txd(pl08x
, txdi
);
839 static int pl08x_alloc_chan_resources(struct dma_chan
*chan
)
844 static void pl08x_free_chan_resources(struct dma_chan
*chan
)
849 * This should be called with the channel plchan->lock held
851 static int prep_phy_channel(struct pl08x_dma_chan
*plchan
,
852 struct pl08x_txd
*txd
)
854 struct pl08x_driver_data
*pl08x
= plchan
->host
;
855 struct pl08x_phy_chan
*ch
;
858 /* Check if we already have a channel */
859 if (plchan
->phychan
) {
860 ch
= plchan
->phychan
;
864 ch
= pl08x_get_phy_channel(pl08x
, plchan
);
866 /* No physical channel available, cope with it */
867 dev_dbg(&pl08x
->adev
->dev
, "no physical channel available for xfer on %s\n", plchan
->name
);
872 * OK we have a physical channel: for memcpy() this is all we
873 * need, but for slaves the physical signals may be muxed!
874 * Can the platform allow us to use this channel?
876 if (plchan
->slave
&& pl08x
->pd
->get_signal
) {
877 ret
= pl08x
->pd
->get_signal(plchan
);
879 dev_dbg(&pl08x
->adev
->dev
,
880 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
881 ch
->id
, plchan
->name
);
882 /* Release physical channel & return */
883 pl08x_put_phy_channel(pl08x
, ch
);
889 plchan
->phychan
= ch
;
890 dev_dbg(&pl08x
->adev
->dev
, "allocated physical channel %d and signal %d for xfer on %s\n",
896 /* Assign the flow control signal to this channel */
897 if (txd
->direction
== DMA_MEM_TO_DEV
)
898 txd
->ccfg
|= ch
->signal
<< PL080_CONFIG_DST_SEL_SHIFT
;
899 else if (txd
->direction
== DMA_DEV_TO_MEM
)
900 txd
->ccfg
|= ch
->signal
<< PL080_CONFIG_SRC_SEL_SHIFT
;
902 plchan
->phychan_hold
++;
907 static void release_phy_channel(struct pl08x_dma_chan
*plchan
)
909 struct pl08x_driver_data
*pl08x
= plchan
->host
;
911 if ((plchan
->phychan
->signal
>= 0) && pl08x
->pd
->put_signal
) {
912 pl08x
->pd
->put_signal(plchan
);
913 plchan
->phychan
->signal
= -1;
915 pl08x_put_phy_channel(pl08x
, plchan
->phychan
);
916 plchan
->phychan
= NULL
;
919 static dma_cookie_t
pl08x_tx_submit(struct dma_async_tx_descriptor
*tx
)
921 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(tx
->chan
);
922 struct pl08x_txd
*txd
= to_pl08x_txd(tx
);
926 spin_lock_irqsave(&plchan
->lock
, flags
);
927 cookie
= dma_cookie_assign(tx
);
929 /* Put this onto the pending list */
930 list_add_tail(&txd
->node
, &plchan
->pend_list
);
933 * If there was no physical channel available for this memcpy,
934 * stack the request up and indicate that the channel is waiting
935 * for a free physical channel.
937 if (!plchan
->slave
&& !plchan
->phychan
) {
938 /* Do this memcpy whenever there is a channel ready */
939 plchan
->state
= PL08X_CHAN_WAITING
;
940 plchan
->waiting
= txd
;
942 plchan
->phychan_hold
--;
945 spin_unlock_irqrestore(&plchan
->lock
, flags
);
950 static struct dma_async_tx_descriptor
*pl08x_prep_dma_interrupt(
951 struct dma_chan
*chan
, unsigned long flags
)
953 struct dma_async_tx_descriptor
*retval
= NULL
;
959 * Code accessing dma_async_is_complete() in a tight loop may give problems.
960 * If slaves are relying on interrupts to signal completion this function
961 * must not be called with interrupts disabled.
963 static enum dma_status
pl08x_dma_tx_status(struct dma_chan
*chan
,
964 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
966 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
967 dma_cookie_t last_used
;
968 dma_cookie_t last_complete
;
972 last_used
= plchan
->chan
.cookie
;
973 last_complete
= plchan
->chan
.completed_cookie
;
975 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
976 if (ret
== DMA_SUCCESS
) {
977 dma_set_tx_state(txstate
, last_complete
, last_used
, 0);
982 * This cookie not complete yet
984 last_used
= plchan
->chan
.cookie
;
985 last_complete
= plchan
->chan
.completed_cookie
;
987 /* Get number of bytes left in the active transactions and queue */
988 bytesleft
= pl08x_getbytes_chan(plchan
);
990 dma_set_tx_state(txstate
, last_complete
, last_used
,
993 if (plchan
->state
== PL08X_CHAN_PAUSED
)
996 /* Whether waiting or running, we're in progress */
997 return DMA_IN_PROGRESS
;
1000 /* PrimeCell DMA extension */
1001 struct burst_table
{
1006 static const struct burst_table burst_sizes
[] = {
1009 .reg
= PL080_BSIZE_256
,
1013 .reg
= PL080_BSIZE_128
,
1017 .reg
= PL080_BSIZE_64
,
1021 .reg
= PL080_BSIZE_32
,
1025 .reg
= PL080_BSIZE_16
,
1029 .reg
= PL080_BSIZE_8
,
1033 .reg
= PL080_BSIZE_4
,
1037 .reg
= PL080_BSIZE_1
,
1042 * Given the source and destination available bus masks, select which
1043 * will be routed to each port. We try to have source and destination
1044 * on separate ports, but always respect the allowable settings.
1046 static u32
pl08x_select_bus(u8 src
, u8 dst
)
1050 if (!(dst
& PL08X_AHB1
) || ((dst
& PL08X_AHB2
) && (src
& PL08X_AHB1
)))
1051 cctl
|= PL080_CONTROL_DST_AHB2
;
1052 if (!(src
& PL08X_AHB1
) || ((src
& PL08X_AHB2
) && !(dst
& PL08X_AHB2
)))
1053 cctl
|= PL080_CONTROL_SRC_AHB2
;
1058 static u32
pl08x_cctl(u32 cctl
)
1060 cctl
&= ~(PL080_CONTROL_SRC_AHB2
| PL080_CONTROL_DST_AHB2
|
1061 PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
|
1062 PL080_CONTROL_PROT_MASK
);
1064 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1065 return cctl
| PL080_CONTROL_PROT_SYS
;
1068 static u32
pl08x_width(enum dma_slave_buswidth width
)
1071 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
1072 return PL080_WIDTH_8BIT
;
1073 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
1074 return PL080_WIDTH_16BIT
;
1075 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
1076 return PL080_WIDTH_32BIT
;
1082 static u32
pl08x_burst(u32 maxburst
)
1086 for (i
= 0; i
< ARRAY_SIZE(burst_sizes
); i
++)
1087 if (burst_sizes
[i
].burstwords
<= maxburst
)
1090 return burst_sizes
[i
].reg
;
1093 static int dma_set_runtime_config(struct dma_chan
*chan
,
1094 struct dma_slave_config
*config
)
1096 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1097 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1098 enum dma_slave_buswidth addr_width
;
1099 u32 width
, burst
, maxburst
;
1105 /* Transfer direction */
1106 plchan
->runtime_direction
= config
->direction
;
1107 if (config
->direction
== DMA_MEM_TO_DEV
) {
1108 addr_width
= config
->dst_addr_width
;
1109 maxburst
= config
->dst_maxburst
;
1110 } else if (config
->direction
== DMA_DEV_TO_MEM
) {
1111 addr_width
= config
->src_addr_width
;
1112 maxburst
= config
->src_maxburst
;
1114 dev_err(&pl08x
->adev
->dev
,
1115 "bad runtime_config: alien transfer direction\n");
1119 width
= pl08x_width(addr_width
);
1121 dev_err(&pl08x
->adev
->dev
,
1122 "bad runtime_config: alien address width\n");
1126 cctl
|= width
<< PL080_CONTROL_SWIDTH_SHIFT
;
1127 cctl
|= width
<< PL080_CONTROL_DWIDTH_SHIFT
;
1130 * If this channel will only request single transfers, set this
1131 * down to ONE element. Also select one element if no maxburst
1134 if (plchan
->cd
->single
)
1137 burst
= pl08x_burst(maxburst
);
1138 cctl
|= burst
<< PL080_CONTROL_SB_SIZE_SHIFT
;
1139 cctl
|= burst
<< PL080_CONTROL_DB_SIZE_SHIFT
;
1141 plchan
->device_fc
= config
->device_fc
;
1143 if (plchan
->runtime_direction
== DMA_DEV_TO_MEM
) {
1144 plchan
->src_addr
= config
->src_addr
;
1145 plchan
->src_cctl
= pl08x_cctl(cctl
) | PL080_CONTROL_DST_INCR
|
1146 pl08x_select_bus(plchan
->cd
->periph_buses
,
1149 plchan
->dst_addr
= config
->dst_addr
;
1150 plchan
->dst_cctl
= pl08x_cctl(cctl
) | PL080_CONTROL_SRC_INCR
|
1151 pl08x_select_bus(pl08x
->mem_buses
,
1152 plchan
->cd
->periph_buses
);
1155 dev_dbg(&pl08x
->adev
->dev
,
1156 "configured channel %s (%s) for %s, data width %d, "
1157 "maxburst %d words, LE, CCTL=0x%08x\n",
1158 dma_chan_name(chan
), plchan
->name
,
1159 (config
->direction
== DMA_DEV_TO_MEM
) ? "RX" : "TX",
1168 * Slave transactions callback to the slave device to allow
1169 * synchronization of slave DMA signals with the DMAC enable
1171 static void pl08x_issue_pending(struct dma_chan
*chan
)
1173 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1174 unsigned long flags
;
1176 spin_lock_irqsave(&plchan
->lock
, flags
);
1177 /* Something is already active, or we're waiting for a channel... */
1178 if (plchan
->at
|| plchan
->state
== PL08X_CHAN_WAITING
) {
1179 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1183 /* Take the first element in the queue and execute it */
1184 if (!list_empty(&plchan
->pend_list
)) {
1185 struct pl08x_txd
*next
;
1187 next
= list_first_entry(&plchan
->pend_list
,
1190 list_del(&next
->node
);
1191 plchan
->state
= PL08X_CHAN_RUNNING
;
1193 pl08x_start_txd(plchan
, next
);
1196 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1199 static int pl08x_prep_channel_resources(struct pl08x_dma_chan
*plchan
,
1200 struct pl08x_txd
*txd
)
1202 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1203 unsigned long flags
;
1206 num_llis
= pl08x_fill_llis_for_desc(pl08x
, txd
);
1208 spin_lock_irqsave(&plchan
->lock
, flags
);
1209 pl08x_free_txd(pl08x
, txd
);
1210 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1214 spin_lock_irqsave(&plchan
->lock
, flags
);
1217 * See if we already have a physical channel allocated,
1218 * else this is the time to try to get one.
1220 ret
= prep_phy_channel(plchan
, txd
);
1223 * No physical channel was available.
1225 * memcpy transfers can be sorted out at submission time.
1227 * Slave transfers may have been denied due to platform
1228 * channel muxing restrictions. Since there is no guarantee
1229 * that this will ever be resolved, and the signal must be
1230 * acquired AFTER acquiring the physical channel, we will let
1231 * them be NACK:ed with -EBUSY here. The drivers can retry
1232 * the prep() call if they are eager on doing this using DMA.
1234 if (plchan
->slave
) {
1235 pl08x_free_txd_list(pl08x
, plchan
);
1236 pl08x_free_txd(pl08x
, txd
);
1237 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1242 * Else we're all set, paused and ready to roll, status
1243 * will switch to PL08X_CHAN_RUNNING when we call
1244 * issue_pending(). If there is something running on the
1245 * channel already we don't change its state.
1247 if (plchan
->state
== PL08X_CHAN_IDLE
)
1248 plchan
->state
= PL08X_CHAN_PAUSED
;
1250 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1255 static struct pl08x_txd
*pl08x_get_txd(struct pl08x_dma_chan
*plchan
,
1256 unsigned long flags
)
1258 struct pl08x_txd
*txd
= kzalloc(sizeof(*txd
), GFP_NOWAIT
);
1261 dma_async_tx_descriptor_init(&txd
->tx
, &plchan
->chan
);
1262 txd
->tx
.flags
= flags
;
1263 txd
->tx
.tx_submit
= pl08x_tx_submit
;
1264 INIT_LIST_HEAD(&txd
->node
);
1265 INIT_LIST_HEAD(&txd
->dsg_list
);
1267 /* Always enable error and terminal interrupts */
1268 txd
->ccfg
= PL080_CONFIG_ERR_IRQ_MASK
|
1269 PL080_CONFIG_TC_IRQ_MASK
;
1275 * Initialize a descriptor to be used by memcpy submit
1277 static struct dma_async_tx_descriptor
*pl08x_prep_dma_memcpy(
1278 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1279 size_t len
, unsigned long flags
)
1281 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1282 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1283 struct pl08x_txd
*txd
;
1284 struct pl08x_sg
*dsg
;
1287 txd
= pl08x_get_txd(plchan
, flags
);
1289 dev_err(&pl08x
->adev
->dev
,
1290 "%s no memory for descriptor\n", __func__
);
1294 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1296 pl08x_free_txd(pl08x
, txd
);
1297 dev_err(&pl08x
->adev
->dev
, "%s no memory for pl080 sg\n",
1301 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1303 txd
->direction
= DMA_NONE
;
1304 dsg
->src_addr
= src
;
1305 dsg
->dst_addr
= dest
;
1308 /* Set platform data for m2m */
1309 txd
->ccfg
|= PL080_FLOW_MEM2MEM
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1310 txd
->cctl
= pl08x
->pd
->memcpy_channel
.cctl
&
1311 ~(PL080_CONTROL_DST_AHB2
| PL080_CONTROL_SRC_AHB2
);
1313 /* Both to be incremented or the code will break */
1314 txd
->cctl
|= PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
;
1316 if (pl08x
->vd
->dualmaster
)
1317 txd
->cctl
|= pl08x_select_bus(pl08x
->mem_buses
,
1320 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1327 static struct dma_async_tx_descriptor
*pl08x_prep_slave_sg(
1328 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1329 unsigned int sg_len
, enum dma_transfer_direction direction
,
1330 unsigned long flags
)
1332 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1333 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1334 struct pl08x_txd
*txd
;
1335 struct pl08x_sg
*dsg
;
1336 struct scatterlist
*sg
;
1337 dma_addr_t slave_addr
;
1340 dev_dbg(&pl08x
->adev
->dev
, "%s prepare transaction of %d bytes from %s\n",
1341 __func__
, sgl
->length
, plchan
->name
);
1343 txd
= pl08x_get_txd(plchan
, flags
);
1345 dev_err(&pl08x
->adev
->dev
, "%s no txd\n", __func__
);
1349 if (direction
!= plchan
->runtime_direction
)
1350 dev_err(&pl08x
->adev
->dev
, "%s DMA setup does not match "
1351 "the direction configured for the PrimeCell\n",
1355 * Set up addresses, the PrimeCell configured address
1356 * will take precedence since this may configure the
1357 * channel target address dynamically at runtime.
1359 txd
->direction
= direction
;
1361 if (direction
== DMA_MEM_TO_DEV
) {
1362 txd
->cctl
= plchan
->dst_cctl
;
1363 slave_addr
= plchan
->dst_addr
;
1364 } else if (direction
== DMA_DEV_TO_MEM
) {
1365 txd
->cctl
= plchan
->src_cctl
;
1366 slave_addr
= plchan
->src_addr
;
1368 pl08x_free_txd(pl08x
, txd
);
1369 dev_err(&pl08x
->adev
->dev
,
1370 "%s direction unsupported\n", __func__
);
1374 if (plchan
->device_fc
)
1375 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER_PER
:
1376 PL080_FLOW_PER2MEM_PER
;
1378 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER
:
1381 txd
->ccfg
|= tmp
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1383 for_each_sg(sgl
, sg
, sg_len
, tmp
) {
1384 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1386 pl08x_free_txd(pl08x
, txd
);
1387 dev_err(&pl08x
->adev
->dev
, "%s no mem for pl080 sg\n",
1391 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1393 dsg
->len
= sg_dma_len(sg
);
1394 if (direction
== DMA_MEM_TO_DEV
) {
1395 dsg
->src_addr
= sg_phys(sg
);
1396 dsg
->dst_addr
= slave_addr
;
1398 dsg
->src_addr
= slave_addr
;
1399 dsg
->dst_addr
= sg_phys(sg
);
1403 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1410 static int pl08x_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1413 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1414 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1415 unsigned long flags
;
1418 /* Controls applicable to inactive channels */
1419 if (cmd
== DMA_SLAVE_CONFIG
) {
1420 return dma_set_runtime_config(chan
,
1421 (struct dma_slave_config
*)arg
);
1425 * Anything succeeds on channels with no physical allocation and
1426 * no queued transfers.
1428 spin_lock_irqsave(&plchan
->lock
, flags
);
1429 if (!plchan
->phychan
&& !plchan
->at
) {
1430 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1435 case DMA_TERMINATE_ALL
:
1436 plchan
->state
= PL08X_CHAN_IDLE
;
1438 if (plchan
->phychan
) {
1439 pl08x_terminate_phy_chan(pl08x
, plchan
->phychan
);
1442 * Mark physical channel as free and free any slave
1445 release_phy_channel(plchan
);
1447 /* Dequeue jobs and free LLIs */
1449 pl08x_free_txd(pl08x
, plchan
->at
);
1452 /* Dequeue jobs not yet fired as well */
1453 pl08x_free_txd_list(pl08x
, plchan
);
1456 pl08x_pause_phy_chan(plchan
->phychan
);
1457 plchan
->state
= PL08X_CHAN_PAUSED
;
1460 pl08x_resume_phy_chan(plchan
->phychan
);
1461 plchan
->state
= PL08X_CHAN_RUNNING
;
1464 /* Unknown command */
1469 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1474 bool pl08x_filter_id(struct dma_chan
*chan
, void *chan_id
)
1476 struct pl08x_dma_chan
*plchan
;
1477 char *name
= chan_id
;
1479 /* Reject channels for devices not bound to this driver */
1480 if (chan
->device
->dev
->driver
!= &pl08x_amba_driver
.drv
)
1483 plchan
= to_pl08x_chan(chan
);
1485 /* Check that the channel is not taken! */
1486 if (!strcmp(plchan
->name
, name
))
1493 * Just check that the device is there and active
1494 * TODO: turn this bit on/off depending on the number of physical channels
1495 * actually used, if it is zero... well shut it off. That will save some
1496 * power. Cut the clock at the same time.
1498 static void pl08x_ensure_on(struct pl08x_driver_data
*pl08x
)
1500 writel(PL080_CONFIG_ENABLE
, pl08x
->base
+ PL080_CONFIG
);
1503 static void pl08x_unmap_buffers(struct pl08x_txd
*txd
)
1505 struct device
*dev
= txd
->tx
.chan
->device
->dev
;
1506 struct pl08x_sg
*dsg
;
1508 if (!(txd
->tx
.flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
1509 if (txd
->tx
.flags
& DMA_COMPL_SRC_UNMAP_SINGLE
)
1510 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1511 dma_unmap_single(dev
, dsg
->src_addr
, dsg
->len
,
1514 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1515 dma_unmap_page(dev
, dsg
->src_addr
, dsg
->len
,
1519 if (!(txd
->tx
.flags
& DMA_COMPL_SKIP_DEST_UNMAP
)) {
1520 if (txd
->tx
.flags
& DMA_COMPL_DEST_UNMAP_SINGLE
)
1521 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1522 dma_unmap_single(dev
, dsg
->dst_addr
, dsg
->len
,
1525 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1526 dma_unmap_page(dev
, dsg
->dst_addr
, dsg
->len
,
1531 static void pl08x_tasklet(unsigned long data
)
1533 struct pl08x_dma_chan
*plchan
= (struct pl08x_dma_chan
*) data
;
1534 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1535 struct pl08x_txd
*txd
;
1536 unsigned long flags
;
1538 spin_lock_irqsave(&plchan
->lock
, flags
);
1544 /* Update last completed */
1545 plchan
->chan
.completed_cookie
= txd
->tx
.cookie
;
1548 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1549 if (!list_empty(&plchan
->pend_list
)) {
1550 struct pl08x_txd
*next
;
1552 next
= list_first_entry(&plchan
->pend_list
,
1555 list_del(&next
->node
);
1557 pl08x_start_txd(plchan
, next
);
1558 } else if (plchan
->phychan_hold
) {
1560 * This channel is still in use - we have a new txd being
1561 * prepared and will soon be queued. Don't give up the
1565 struct pl08x_dma_chan
*waiting
= NULL
;
1568 * No more jobs, so free up the physical channel
1569 * Free any allocated signal on slave transfers too
1571 release_phy_channel(plchan
);
1572 plchan
->state
= PL08X_CHAN_IDLE
;
1575 * And NOW before anyone else can grab that free:d up
1576 * physical channel, see if there is some memcpy pending
1577 * that seriously needs to start because of being stacked
1578 * up while we were choking the physical channels with data.
1580 list_for_each_entry(waiting
, &pl08x
->memcpy
.channels
,
1582 if (waiting
->state
== PL08X_CHAN_WAITING
&&
1583 waiting
->waiting
!= NULL
) {
1586 /* This should REALLY not fail now */
1587 ret
= prep_phy_channel(waiting
,
1590 waiting
->phychan_hold
--;
1591 waiting
->state
= PL08X_CHAN_RUNNING
;
1592 waiting
->waiting
= NULL
;
1593 pl08x_issue_pending(&waiting
->chan
);
1599 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1602 dma_async_tx_callback callback
= txd
->tx
.callback
;
1603 void *callback_param
= txd
->tx
.callback_param
;
1605 /* Don't try to unmap buffers on slave channels */
1607 pl08x_unmap_buffers(txd
);
1609 /* Free the descriptor */
1610 spin_lock_irqsave(&plchan
->lock
, flags
);
1611 pl08x_free_txd(pl08x
, txd
);
1612 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1614 /* Callback to signal completion */
1616 callback(callback_param
);
1620 static irqreturn_t
pl08x_irq(int irq
, void *dev
)
1622 struct pl08x_driver_data
*pl08x
= dev
;
1623 u32 mask
= 0, err
, tc
, i
;
1625 /* check & clear - ERR & TC interrupts */
1626 err
= readl(pl08x
->base
+ PL080_ERR_STATUS
);
1628 dev_err(&pl08x
->adev
->dev
, "%s error interrupt, register value 0x%08x\n",
1630 writel(err
, pl08x
->base
+ PL080_ERR_CLEAR
);
1632 tc
= readl(pl08x
->base
+ PL080_INT_STATUS
);
1634 writel(tc
, pl08x
->base
+ PL080_TC_CLEAR
);
1639 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1640 if (((1 << i
) & err
) || ((1 << i
) & tc
)) {
1641 /* Locate physical channel */
1642 struct pl08x_phy_chan
*phychan
= &pl08x
->phy_chans
[i
];
1643 struct pl08x_dma_chan
*plchan
= phychan
->serving
;
1646 dev_err(&pl08x
->adev
->dev
,
1647 "%s Error TC interrupt on unused channel: 0x%08x\n",
1652 /* Schedule tasklet on this channel */
1653 tasklet_schedule(&plchan
->tasklet
);
1658 return mask
? IRQ_HANDLED
: IRQ_NONE
;
1661 static void pl08x_dma_slave_init(struct pl08x_dma_chan
*chan
)
1663 u32 cctl
= pl08x_cctl(chan
->cd
->cctl
);
1666 chan
->name
= chan
->cd
->bus_id
;
1667 chan
->src_addr
= chan
->cd
->addr
;
1668 chan
->dst_addr
= chan
->cd
->addr
;
1669 chan
->src_cctl
= cctl
| PL080_CONTROL_DST_INCR
|
1670 pl08x_select_bus(chan
->cd
->periph_buses
, chan
->host
->mem_buses
);
1671 chan
->dst_cctl
= cctl
| PL080_CONTROL_SRC_INCR
|
1672 pl08x_select_bus(chan
->host
->mem_buses
, chan
->cd
->periph_buses
);
1676 * Initialise the DMAC memcpy/slave channels.
1677 * Make a local wrapper to hold required data
1679 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data
*pl08x
,
1680 struct dma_device
*dmadev
, unsigned int channels
, bool slave
)
1682 struct pl08x_dma_chan
*chan
;
1685 INIT_LIST_HEAD(&dmadev
->channels
);
1688 * Register as many many memcpy as we have physical channels,
1689 * we won't always be able to use all but the code will have
1690 * to cope with that situation.
1692 for (i
= 0; i
< channels
; i
++) {
1693 chan
= kzalloc(sizeof(*chan
), GFP_KERNEL
);
1695 dev_err(&pl08x
->adev
->dev
,
1696 "%s no memory for channel\n", __func__
);
1701 chan
->state
= PL08X_CHAN_IDLE
;
1704 chan
->cd
= &pl08x
->pd
->slave_channels
[i
];
1705 pl08x_dma_slave_init(chan
);
1707 chan
->cd
= &pl08x
->pd
->memcpy_channel
;
1708 chan
->name
= kasprintf(GFP_KERNEL
, "memcpy%d", i
);
1714 if (chan
->cd
->circular_buffer
) {
1715 dev_err(&pl08x
->adev
->dev
,
1716 "channel %s: circular buffers not supported\n",
1721 dev_dbg(&pl08x
->adev
->dev
,
1722 "initialize virtual channel \"%s\"\n",
1725 chan
->chan
.device
= dmadev
;
1726 chan
->chan
.cookie
= 0;
1727 chan
->chan
.completed_cookie
= 0;
1729 spin_lock_init(&chan
->lock
);
1730 INIT_LIST_HEAD(&chan
->pend_list
);
1731 tasklet_init(&chan
->tasklet
, pl08x_tasklet
,
1732 (unsigned long) chan
);
1734 list_add_tail(&chan
->chan
.device_node
, &dmadev
->channels
);
1736 dev_info(&pl08x
->adev
->dev
, "initialized %d virtual %s channels\n",
1737 i
, slave
? "slave" : "memcpy");
1741 static void pl08x_free_virtual_channels(struct dma_device
*dmadev
)
1743 struct pl08x_dma_chan
*chan
= NULL
;
1744 struct pl08x_dma_chan
*next
;
1746 list_for_each_entry_safe(chan
,
1747 next
, &dmadev
->channels
, chan
.device_node
) {
1748 list_del(&chan
->chan
.device_node
);
1753 #ifdef CONFIG_DEBUG_FS
1754 static const char *pl08x_state_str(enum pl08x_dma_chan_state state
)
1757 case PL08X_CHAN_IDLE
:
1759 case PL08X_CHAN_RUNNING
:
1761 case PL08X_CHAN_PAUSED
:
1763 case PL08X_CHAN_WAITING
:
1768 return "UNKNOWN STATE";
1771 static int pl08x_debugfs_show(struct seq_file
*s
, void *data
)
1773 struct pl08x_driver_data
*pl08x
= s
->private;
1774 struct pl08x_dma_chan
*chan
;
1775 struct pl08x_phy_chan
*ch
;
1776 unsigned long flags
;
1779 seq_printf(s
, "PL08x physical channels:\n");
1780 seq_printf(s
, "CHANNEL:\tUSER:\n");
1781 seq_printf(s
, "--------\t-----\n");
1782 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1783 struct pl08x_dma_chan
*virt_chan
;
1785 ch
= &pl08x
->phy_chans
[i
];
1787 spin_lock_irqsave(&ch
->lock
, flags
);
1788 virt_chan
= ch
->serving
;
1790 seq_printf(s
, "%d\t\t%s\n",
1791 ch
->id
, virt_chan
? virt_chan
->name
: "(none)");
1793 spin_unlock_irqrestore(&ch
->lock
, flags
);
1796 seq_printf(s
, "\nPL08x virtual memcpy channels:\n");
1797 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1798 seq_printf(s
, "--------\t------\n");
1799 list_for_each_entry(chan
, &pl08x
->memcpy
.channels
, chan
.device_node
) {
1800 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1801 pl08x_state_str(chan
->state
));
1804 seq_printf(s
, "\nPL08x virtual slave channels:\n");
1805 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1806 seq_printf(s
, "--------\t------\n");
1807 list_for_each_entry(chan
, &pl08x
->slave
.channels
, chan
.device_node
) {
1808 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1809 pl08x_state_str(chan
->state
));
1815 static int pl08x_debugfs_open(struct inode
*inode
, struct file
*file
)
1817 return single_open(file
, pl08x_debugfs_show
, inode
->i_private
);
1820 static const struct file_operations pl08x_debugfs_operations
= {
1821 .open
= pl08x_debugfs_open
,
1823 .llseek
= seq_lseek
,
1824 .release
= single_release
,
1827 static void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1829 /* Expose a simple debugfs interface to view all clocks */
1830 (void) debugfs_create_file(dev_name(&pl08x
->adev
->dev
),
1831 S_IFREG
| S_IRUGO
, NULL
, pl08x
,
1832 &pl08x_debugfs_operations
);
1836 static inline void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1841 static int pl08x_probe(struct amba_device
*adev
, const struct amba_id
*id
)
1843 struct pl08x_driver_data
*pl08x
;
1844 const struct vendor_data
*vd
= id
->data
;
1848 ret
= amba_request_regions(adev
, NULL
);
1852 /* Create the driver state holder */
1853 pl08x
= kzalloc(sizeof(*pl08x
), GFP_KERNEL
);
1859 pm_runtime_set_active(&adev
->dev
);
1860 pm_runtime_enable(&adev
->dev
);
1862 /* Initialize memcpy engine */
1863 dma_cap_set(DMA_MEMCPY
, pl08x
->memcpy
.cap_mask
);
1864 pl08x
->memcpy
.dev
= &adev
->dev
;
1865 pl08x
->memcpy
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1866 pl08x
->memcpy
.device_free_chan_resources
= pl08x_free_chan_resources
;
1867 pl08x
->memcpy
.device_prep_dma_memcpy
= pl08x_prep_dma_memcpy
;
1868 pl08x
->memcpy
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1869 pl08x
->memcpy
.device_tx_status
= pl08x_dma_tx_status
;
1870 pl08x
->memcpy
.device_issue_pending
= pl08x_issue_pending
;
1871 pl08x
->memcpy
.device_control
= pl08x_control
;
1873 /* Initialize slave engine */
1874 dma_cap_set(DMA_SLAVE
, pl08x
->slave
.cap_mask
);
1875 pl08x
->slave
.dev
= &adev
->dev
;
1876 pl08x
->slave
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1877 pl08x
->slave
.device_free_chan_resources
= pl08x_free_chan_resources
;
1878 pl08x
->slave
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1879 pl08x
->slave
.device_tx_status
= pl08x_dma_tx_status
;
1880 pl08x
->slave
.device_issue_pending
= pl08x_issue_pending
;
1881 pl08x
->slave
.device_prep_slave_sg
= pl08x_prep_slave_sg
;
1882 pl08x
->slave
.device_control
= pl08x_control
;
1884 /* Get the platform data */
1885 pl08x
->pd
= dev_get_platdata(&adev
->dev
);
1887 dev_err(&adev
->dev
, "no platform data supplied\n");
1888 goto out_no_platdata
;
1891 /* Assign useful pointers to the driver state */
1895 /* By default, AHB1 only. If dualmaster, from platform */
1896 pl08x
->lli_buses
= PL08X_AHB1
;
1897 pl08x
->mem_buses
= PL08X_AHB1
;
1898 if (pl08x
->vd
->dualmaster
) {
1899 pl08x
->lli_buses
= pl08x
->pd
->lli_buses
;
1900 pl08x
->mem_buses
= pl08x
->pd
->mem_buses
;
1903 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1904 pl08x
->pool
= dma_pool_create(DRIVER_NAME
, &pl08x
->adev
->dev
,
1905 PL08X_LLI_TSFR_SIZE
, PL08X_ALIGN
, 0);
1908 goto out_no_lli_pool
;
1911 spin_lock_init(&pl08x
->lock
);
1913 pl08x
->base
= ioremap(adev
->res
.start
, resource_size(&adev
->res
));
1916 goto out_no_ioremap
;
1919 /* Turn on the PL08x */
1920 pl08x_ensure_on(pl08x
);
1922 /* Attach the interrupt handler */
1923 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
1924 writel(0x000000FF, pl08x
->base
+ PL080_TC_CLEAR
);
1926 ret
= request_irq(adev
->irq
[0], pl08x_irq
, IRQF_DISABLED
,
1927 DRIVER_NAME
, pl08x
);
1929 dev_err(&adev
->dev
, "%s failed to request interrupt %d\n",
1930 __func__
, adev
->irq
[0]);
1934 /* Initialize physical channels */
1935 pl08x
->phy_chans
= kmalloc((vd
->channels
* sizeof(*pl08x
->phy_chans
)),
1937 if (!pl08x
->phy_chans
) {
1938 dev_err(&adev
->dev
, "%s failed to allocate "
1939 "physical channel holders\n",
1941 goto out_no_phychans
;
1944 for (i
= 0; i
< vd
->channels
; i
++) {
1945 struct pl08x_phy_chan
*ch
= &pl08x
->phy_chans
[i
];
1948 ch
->base
= pl08x
->base
+ PL080_Cx_BASE(i
);
1949 spin_lock_init(&ch
->lock
);
1952 dev_dbg(&adev
->dev
, "physical channel %d is %s\n",
1953 i
, pl08x_phy_channel_busy(ch
) ? "BUSY" : "FREE");
1956 /* Register as many memcpy channels as there are physical channels */
1957 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->memcpy
,
1958 pl08x
->vd
->channels
, false);
1960 dev_warn(&pl08x
->adev
->dev
,
1961 "%s failed to enumerate memcpy channels - %d\n",
1965 pl08x
->memcpy
.chancnt
= ret
;
1967 /* Register slave channels */
1968 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->slave
,
1969 pl08x
->pd
->num_slave_channels
, true);
1971 dev_warn(&pl08x
->adev
->dev
,
1972 "%s failed to enumerate slave channels - %d\n",
1976 pl08x
->slave
.chancnt
= ret
;
1978 ret
= dma_async_device_register(&pl08x
->memcpy
);
1980 dev_warn(&pl08x
->adev
->dev
,
1981 "%s failed to register memcpy as an async device - %d\n",
1983 goto out_no_memcpy_reg
;
1986 ret
= dma_async_device_register(&pl08x
->slave
);
1988 dev_warn(&pl08x
->adev
->dev
,
1989 "%s failed to register slave as an async device - %d\n",
1991 goto out_no_slave_reg
;
1994 amba_set_drvdata(adev
, pl08x
);
1995 init_pl08x_debugfs(pl08x
);
1996 dev_info(&pl08x
->adev
->dev
, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1997 amba_part(adev
), amba_rev(adev
),
1998 (unsigned long long)adev
->res
.start
, adev
->irq
[0]);
2000 pm_runtime_put(&adev
->dev
);
2004 dma_async_device_unregister(&pl08x
->memcpy
);
2006 pl08x_free_virtual_channels(&pl08x
->slave
);
2008 pl08x_free_virtual_channels(&pl08x
->memcpy
);
2010 kfree(pl08x
->phy_chans
);
2012 free_irq(adev
->irq
[0], pl08x
);
2014 iounmap(pl08x
->base
);
2016 dma_pool_destroy(pl08x
->pool
);
2019 pm_runtime_put(&adev
->dev
);
2020 pm_runtime_disable(&adev
->dev
);
2024 amba_release_regions(adev
);
2028 /* PL080 has 8 channels and the PL080 have just 2 */
2029 static struct vendor_data vendor_pl080
= {
2034 static struct vendor_data vendor_pl081
= {
2036 .dualmaster
= false,
2039 static struct amba_id pl08x_ids
[] = {
2044 .data
= &vendor_pl080
,
2050 .data
= &vendor_pl081
,
2052 /* Nomadik 8815 PL080 variant */
2056 .data
= &vendor_pl080
,
2061 MODULE_DEVICE_TABLE(amba
, pl08x_ids
);
2063 static struct amba_driver pl08x_amba_driver
= {
2064 .drv
.name
= DRIVER_NAME
,
2065 .id_table
= pl08x_ids
,
2066 .probe
= pl08x_probe
,
2069 static int __init
pl08x_init(void)
2072 retval
= amba_driver_register(&pl08x_amba_driver
);
2074 printk(KERN_WARNING DRIVER_NAME
2075 "failed to register as an AMBA device (%d)\n",
2079 subsys_initcall(pl08x_init
);