2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <asm/hardware/pl080.h>
88 #include "dmaengine.h"
91 #define DRIVER_NAME "pl08xdmac"
93 static struct amba_driver pl08x_amba_driver
;
94 struct pl08x_driver_data
;
97 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
98 * @channels: the number of channels available in this variant
99 * @dualmaster: whether this version supports dual AHB masters or not.
100 * @nomadik: whether the channels have Nomadik security extension bits
101 * that need to be checked for permission before use and some registers are
111 * PL08X private data structures
112 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
113 * start & end do not - their bus bit info is in cctl. Also note that these
114 * are fixed 32-bit quantities.
124 * struct pl08x_bus_data - information of source or destination
125 * busses for a transfer
126 * @addr: current address
127 * @maxwidth: the maximum width of a transfer on this bus
128 * @buswidth: the width of this bus in bytes: 1, 2 or 4
130 struct pl08x_bus_data
{
137 * struct pl08x_phy_chan - holder for the physical channels
138 * @id: physical index to this channel
139 * @lock: a lock to use when altering an instance of this struct
140 * @serving: the virtual channel currently being served by this physical
142 * @locked: channel unavailable for the system, e.g. dedicated to secure
145 struct pl08x_phy_chan
{
149 struct pl08x_dma_chan
*serving
;
154 * struct pl08x_sg - structure containing data per sg
155 * @src_addr: src address of sg
156 * @dst_addr: dst address of sg
157 * @len: transfer len in bytes
158 * @node: node for txd's dsg_list
164 struct list_head node
;
168 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
169 * @vd: virtual DMA descriptor
170 * @dsg_list: list of children sg's
171 * @llis_bus: DMA memory address (physical) start for the LLIs
172 * @llis_va: virtual memory address start for the LLIs
173 * @cctl: control reg values for current txd
174 * @ccfg: config reg values for current txd
175 * @done: this marks completed descriptors, which should not have their
179 struct virt_dma_desc vd
;
180 struct list_head dsg_list
;
182 struct pl08x_lli
*llis_va
;
183 /* Default cctl value for LLIs */
186 * Settings to be put into the physical channel when we
187 * trigger this txd. Other registers are in llis_va[0].
194 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
196 * @PL08X_CHAN_IDLE: the channel is idle
197 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
198 * channel and is running a transfer on it
199 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
200 * channel, but the transfer is currently paused
201 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
202 * channel to become available (only pertains to memcpy channels)
204 enum pl08x_dma_chan_state
{
212 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
213 * @vc: wrappped virtual channel
214 * @phychan: the physical channel utilized by this channel, if there is one
215 * @name: name of channel
216 * @cd: channel platform data
217 * @runtime_addr: address for RX/TX according to the runtime config
218 * @at: active transaction on this channel
219 * @lock: a lock for this channel data
220 * @host: a pointer to the host (internal use)
221 * @state: whether the channel is idle, paused, running etc
222 * @slave: whether this channel is a device (slave) or for memcpy
223 * @signal: the physical DMA request signal which this channel is using
224 * @mux_use: count of descriptors using this DMA request signal setting
226 struct pl08x_dma_chan
{
227 struct virt_dma_chan vc
;
228 struct pl08x_phy_chan
*phychan
;
230 const struct pl08x_channel_data
*cd
;
231 struct dma_slave_config cfg
;
232 struct pl08x_txd
*at
;
233 struct pl08x_driver_data
*host
;
234 enum pl08x_dma_chan_state state
;
241 * struct pl08x_driver_data - the local state holder for the PL08x
242 * @slave: slave engine for this instance
243 * @memcpy: memcpy engine for this instance
244 * @base: virtual memory base (remapped) for the PL08x
245 * @adev: the corresponding AMBA (PrimeCell) bus entry
246 * @vd: vendor data for this PL08x variant
247 * @pd: platform data passed in from the platform/machine
248 * @phy_chans: array of data for the physical channels
249 * @pool: a pool for the LLI descriptors
250 * @pool_ctr: counter of LLIs in the pool
251 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
253 * @mem_buses: set to indicate memory transfers on AHB2.
254 * @lock: a spinlock for this struct
256 struct pl08x_driver_data
{
257 struct dma_device slave
;
258 struct dma_device memcpy
;
260 struct amba_device
*adev
;
261 const struct vendor_data
*vd
;
262 struct pl08x_platform_data
*pd
;
263 struct pl08x_phy_chan
*phy_chans
;
264 struct dma_pool
*pool
;
271 * PL08X specific defines
274 /* Size (bytes) of each LLI buffer allocated for one transfer */
275 # define PL08X_LLI_TSFR_SIZE 0x2000
277 /* Maximum times we call dma_pool_alloc on this pool without freeing */
278 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
279 #define PL08X_ALIGN 8
281 static inline struct pl08x_dma_chan
*to_pl08x_chan(struct dma_chan
*chan
)
283 return container_of(chan
, struct pl08x_dma_chan
, vc
.chan
);
286 static inline struct pl08x_txd
*to_pl08x_txd(struct dma_async_tx_descriptor
*tx
)
288 return container_of(tx
, struct pl08x_txd
, vd
.tx
);
294 * This gives us the DMA request input to the PL08x primecell which the
295 * peripheral described by the channel data will be routed to, possibly
296 * via a board/SoC specific external MUX. One important point to note
297 * here is that this does not depend on the physical channel.
299 static int pl08x_request_mux(struct pl08x_dma_chan
*plchan
)
301 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
304 if (plchan
->mux_use
++ == 0 && pd
->get_signal
) {
305 ret
= pd
->get_signal(plchan
->cd
);
311 plchan
->signal
= ret
;
316 static void pl08x_release_mux(struct pl08x_dma_chan
*plchan
)
318 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
320 if (plchan
->signal
>= 0) {
321 WARN_ON(plchan
->mux_use
== 0);
323 if (--plchan
->mux_use
== 0 && pd
->put_signal
) {
324 pd
->put_signal(plchan
->cd
, plchan
->signal
);
331 * Physical channel handling
334 /* Whether a certain channel is busy or not */
335 static int pl08x_phy_channel_busy(struct pl08x_phy_chan
*ch
)
339 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
340 return val
& PL080_CONFIG_ACTIVE
;
344 * Set the initial DMA register values i.e. those for the first LLI
345 * The next LLI pointer and the configuration interrupt bit have
346 * been set when the LLIs were constructed. Poke them into the hardware
347 * and start the transfer.
349 static void pl08x_start_next_txd(struct pl08x_dma_chan
*plchan
)
351 struct pl08x_driver_data
*pl08x
= plchan
->host
;
352 struct pl08x_phy_chan
*phychan
= plchan
->phychan
;
353 struct virt_dma_desc
*vd
= vchan_next_desc(&plchan
->vc
);
354 struct pl08x_txd
*txd
= to_pl08x_txd(&vd
->tx
);
355 struct pl08x_lli
*lli
;
358 list_del(&txd
->vd
.node
);
362 /* Wait for channel inactive */
363 while (pl08x_phy_channel_busy(phychan
))
366 lli
= &txd
->llis_va
[0];
368 dev_vdbg(&pl08x
->adev
->dev
,
369 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
370 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
371 phychan
->id
, lli
->src
, lli
->dst
, lli
->lli
, lli
->cctl
,
374 writel(lli
->src
, phychan
->base
+ PL080_CH_SRC_ADDR
);
375 writel(lli
->dst
, phychan
->base
+ PL080_CH_DST_ADDR
);
376 writel(lli
->lli
, phychan
->base
+ PL080_CH_LLI
);
377 writel(lli
->cctl
, phychan
->base
+ PL080_CH_CONTROL
);
378 writel(txd
->ccfg
, phychan
->base
+ PL080_CH_CONFIG
);
380 /* Enable the DMA channel */
381 /* Do not access config register until channel shows as disabled */
382 while (readl(pl08x
->base
+ PL080_EN_CHAN
) & (1 << phychan
->id
))
385 /* Do not access config register until channel shows as inactive */
386 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
387 while ((val
& PL080_CONFIG_ACTIVE
) || (val
& PL080_CONFIG_ENABLE
))
388 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
390 writel(val
| PL080_CONFIG_ENABLE
, phychan
->base
+ PL080_CH_CONFIG
);
394 * Pause the channel by setting the HALT bit.
396 * For M->P transfers, pause the DMAC first and then stop the peripheral -
397 * the FIFO can only drain if the peripheral is still requesting data.
398 * (note: this can still timeout if the DMAC FIFO never drains of data.)
400 * For P->M transfers, disable the peripheral first to stop it filling
401 * the DMAC FIFO, and then pause the DMAC.
403 static void pl08x_pause_phy_chan(struct pl08x_phy_chan
*ch
)
408 /* Set the HALT bit and wait for the FIFO to drain */
409 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
410 val
|= PL080_CONFIG_HALT
;
411 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
413 /* Wait for channel inactive */
414 for (timeout
= 1000; timeout
; timeout
--) {
415 if (!pl08x_phy_channel_busy(ch
))
419 if (pl08x_phy_channel_busy(ch
))
420 pr_err("pl08x: channel%u timeout waiting for pause\n", ch
->id
);
423 static void pl08x_resume_phy_chan(struct pl08x_phy_chan
*ch
)
427 /* Clear the HALT bit */
428 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
429 val
&= ~PL080_CONFIG_HALT
;
430 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
434 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
435 * clears any pending interrupt status. This should not be used for
436 * an on-going transfer, but as a method of shutting down a channel
437 * (eg, when it's no longer used) or terminating a transfer.
439 static void pl08x_terminate_phy_chan(struct pl08x_driver_data
*pl08x
,
440 struct pl08x_phy_chan
*ch
)
442 u32 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
444 val
&= ~(PL080_CONFIG_ENABLE
| PL080_CONFIG_ERR_IRQ_MASK
|
445 PL080_CONFIG_TC_IRQ_MASK
);
447 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
449 writel(1 << ch
->id
, pl08x
->base
+ PL080_ERR_CLEAR
);
450 writel(1 << ch
->id
, pl08x
->base
+ PL080_TC_CLEAR
);
453 static inline u32
get_bytes_in_cctl(u32 cctl
)
455 /* The source width defines the number of bytes */
456 u32 bytes
= cctl
& PL080_CONTROL_TRANSFER_SIZE_MASK
;
458 switch (cctl
>> PL080_CONTROL_SWIDTH_SHIFT
) {
459 case PL080_WIDTH_8BIT
:
461 case PL080_WIDTH_16BIT
:
464 case PL080_WIDTH_32BIT
:
471 /* The channel should be paused when calling this */
472 static u32
pl08x_getbytes_chan(struct pl08x_dma_chan
*plchan
)
474 struct pl08x_phy_chan
*ch
;
475 struct pl08x_txd
*txd
;
479 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
480 ch
= plchan
->phychan
;
484 * Follow the LLIs to get the number of remaining
485 * bytes in the currently active transaction.
488 u32 clli
= readl(ch
->base
+ PL080_CH_LLI
) & ~PL080_LLI_LM_AHB2
;
490 /* First get the remaining bytes in the active transfer */
491 bytes
= get_bytes_in_cctl(readl(ch
->base
+ PL080_CH_CONTROL
));
494 struct pl08x_lli
*llis_va
= txd
->llis_va
;
495 dma_addr_t llis_bus
= txd
->llis_bus
;
498 BUG_ON(clli
< llis_bus
|| clli
>= llis_bus
+
499 sizeof(struct pl08x_lli
) * MAX_NUM_TSFR_LLIS
);
502 * Locate the next LLI - as this is an array,
503 * it's simple maths to find.
505 index
= (clli
- llis_bus
) / sizeof(struct pl08x_lli
);
507 for (; index
< MAX_NUM_TSFR_LLIS
; index
++) {
508 bytes
+= get_bytes_in_cctl(llis_va
[index
].cctl
);
511 * A LLI pointer of 0 terminates the LLI list
513 if (!llis_va
[index
].lli
)
519 /* Sum up all queued transactions */
520 if (!list_empty(&plchan
->vc
.desc_issued
)) {
521 struct pl08x_txd
*txdi
;
522 list_for_each_entry(txdi
, &plchan
->vc
.desc_issued
, vd
.node
) {
523 struct pl08x_sg
*dsg
;
524 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
529 if (!list_empty(&plchan
->vc
.desc_submitted
)) {
530 struct pl08x_txd
*txdi
;
531 list_for_each_entry(txdi
, &plchan
->vc
.desc_submitted
, vd
.node
) {
532 struct pl08x_sg
*dsg
;
533 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
538 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
544 * Allocate a physical channel for a virtual channel
546 * Try to locate a physical channel to be used for this transfer. If all
547 * are taken return NULL and the requester will have to cope by using
548 * some fallback PIO mode or retrying later.
550 static struct pl08x_phy_chan
*
551 pl08x_get_phy_channel(struct pl08x_driver_data
*pl08x
,
552 struct pl08x_dma_chan
*virt_chan
)
554 struct pl08x_phy_chan
*ch
= NULL
;
558 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
559 ch
= &pl08x
->phy_chans
[i
];
561 spin_lock_irqsave(&ch
->lock
, flags
);
563 if (!ch
->locked
&& !ch
->serving
) {
564 ch
->serving
= virt_chan
;
565 spin_unlock_irqrestore(&ch
->lock
, flags
);
569 spin_unlock_irqrestore(&ch
->lock
, flags
);
572 if (i
== pl08x
->vd
->channels
) {
573 /* No physical channel available, cope with it */
580 /* Mark the physical channel as free. Note, this write is atomic. */
581 static inline void pl08x_put_phy_channel(struct pl08x_driver_data
*pl08x
,
582 struct pl08x_phy_chan
*ch
)
588 * Try to allocate a physical channel. When successful, assign it to
589 * this virtual channel, and initiate the next descriptor. The
590 * virtual channel lock must be held at this point.
592 static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan
*plchan
)
594 struct pl08x_driver_data
*pl08x
= plchan
->host
;
595 struct pl08x_phy_chan
*ch
;
597 ch
= pl08x_get_phy_channel(pl08x
, plchan
);
599 dev_dbg(&pl08x
->adev
->dev
, "no physical channel available for xfer on %s\n", plchan
->name
);
600 plchan
->state
= PL08X_CHAN_WAITING
;
604 dev_dbg(&pl08x
->adev
->dev
, "allocated physical channel %d for xfer on %s\n",
605 ch
->id
, plchan
->name
);
607 plchan
->phychan
= ch
;
608 plchan
->state
= PL08X_CHAN_RUNNING
;
609 pl08x_start_next_txd(plchan
);
612 static void pl08x_phy_reassign_start(struct pl08x_phy_chan
*ch
,
613 struct pl08x_dma_chan
*plchan
)
615 struct pl08x_driver_data
*pl08x
= plchan
->host
;
617 dev_dbg(&pl08x
->adev
->dev
, "reassigned physical channel %d for xfer on %s\n",
618 ch
->id
, plchan
->name
);
621 * We do this without taking the lock; we're really only concerned
622 * about whether this pointer is NULL or not, and we're guaranteed
623 * that this will only be called when it _already_ is non-NULL.
625 ch
->serving
= plchan
;
626 plchan
->phychan
= ch
;
627 plchan
->state
= PL08X_CHAN_RUNNING
;
628 pl08x_start_next_txd(plchan
);
632 * Free a physical DMA channel, potentially reallocating it to another
633 * virtual channel if we have any pending.
635 static void pl08x_phy_free(struct pl08x_dma_chan
*plchan
)
637 struct pl08x_driver_data
*pl08x
= plchan
->host
;
638 struct pl08x_dma_chan
*p
, *next
;
643 /* Find a waiting virtual channel for the next transfer. */
644 list_for_each_entry(p
, &pl08x
->memcpy
.channels
, vc
.chan
.device_node
)
645 if (p
->state
== PL08X_CHAN_WAITING
) {
651 list_for_each_entry(p
, &pl08x
->slave
.channels
, vc
.chan
.device_node
)
652 if (p
->state
== PL08X_CHAN_WAITING
) {
658 /* Ensure that the physical channel is stopped */
659 pl08x_terminate_phy_chan(pl08x
, plchan
->phychan
);
665 * Eww. We know this isn't going to deadlock
666 * but lockdep probably doesn't.
668 spin_lock(&next
->vc
.lock
);
669 /* Re-check the state now that we have the lock */
670 success
= next
->state
== PL08X_CHAN_WAITING
;
672 pl08x_phy_reassign_start(plchan
->phychan
, next
);
673 spin_unlock(&next
->vc
.lock
);
675 /* If the state changed, try to find another channel */
679 /* No more jobs, so free up the physical channel */
680 pl08x_put_phy_channel(pl08x
, plchan
->phychan
);
683 plchan
->phychan
= NULL
;
684 plchan
->state
= PL08X_CHAN_IDLE
;
691 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded
)
694 case PL080_WIDTH_8BIT
:
696 case PL080_WIDTH_16BIT
:
698 case PL080_WIDTH_32BIT
:
707 static inline u32
pl08x_cctl_bits(u32 cctl
, u8 srcwidth
, u8 dstwidth
,
712 /* Remove all src, dst and transfer size bits */
713 retbits
&= ~PL080_CONTROL_DWIDTH_MASK
;
714 retbits
&= ~PL080_CONTROL_SWIDTH_MASK
;
715 retbits
&= ~PL080_CONTROL_TRANSFER_SIZE_MASK
;
717 /* Then set the bits according to the parameters */
720 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
723 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
726 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
735 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
738 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
741 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
748 retbits
|= tsize
<< PL080_CONTROL_TRANSFER_SIZE_SHIFT
;
752 struct pl08x_lli_build_data
{
753 struct pl08x_txd
*txd
;
754 struct pl08x_bus_data srcbus
;
755 struct pl08x_bus_data dstbus
;
761 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
762 * victim in case src & dest are not similarly aligned. i.e. If after aligning
763 * masters address with width requirements of transfer (by sending few byte by
764 * byte data), slave is still not aligned, then its width will be reduced to
766 * - prefers the destination bus if both available
767 * - prefers bus with fixed address (i.e. peripheral)
769 static void pl08x_choose_master_bus(struct pl08x_lli_build_data
*bd
,
770 struct pl08x_bus_data
**mbus
, struct pl08x_bus_data
**sbus
, u32 cctl
)
772 if (!(cctl
& PL080_CONTROL_DST_INCR
)) {
775 } else if (!(cctl
& PL080_CONTROL_SRC_INCR
)) {
779 if (bd
->dstbus
.buswidth
>= bd
->srcbus
.buswidth
) {
790 * Fills in one LLI for a certain transfer descriptor and advance the counter
792 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data
*bd
,
793 int num_llis
, int len
, u32 cctl
)
795 struct pl08x_lli
*llis_va
= bd
->txd
->llis_va
;
796 dma_addr_t llis_bus
= bd
->txd
->llis_bus
;
798 BUG_ON(num_llis
>= MAX_NUM_TSFR_LLIS
);
800 llis_va
[num_llis
].cctl
= cctl
;
801 llis_va
[num_llis
].src
= bd
->srcbus
.addr
;
802 llis_va
[num_llis
].dst
= bd
->dstbus
.addr
;
803 llis_va
[num_llis
].lli
= llis_bus
+ (num_llis
+ 1) *
804 sizeof(struct pl08x_lli
);
805 llis_va
[num_llis
].lli
|= bd
->lli_bus
;
807 if (cctl
& PL080_CONTROL_SRC_INCR
)
808 bd
->srcbus
.addr
+= len
;
809 if (cctl
& PL080_CONTROL_DST_INCR
)
810 bd
->dstbus
.addr
+= len
;
812 BUG_ON(bd
->remainder
< len
);
814 bd
->remainder
-= len
;
817 static inline void prep_byte_width_lli(struct pl08x_lli_build_data
*bd
,
818 u32
*cctl
, u32 len
, int num_llis
, size_t *total_bytes
)
820 *cctl
= pl08x_cctl_bits(*cctl
, 1, 1, len
);
821 pl08x_fill_lli_for_desc(bd
, num_llis
, len
, *cctl
);
822 (*total_bytes
) += len
;
826 * This fills in the table of LLIs for the transfer descriptor
827 * Note that we assume we never have to change the burst sizes
830 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data
*pl08x
,
831 struct pl08x_txd
*txd
)
833 struct pl08x_bus_data
*mbus
, *sbus
;
834 struct pl08x_lli_build_data bd
;
836 u32 cctl
, early_bytes
= 0;
837 size_t max_bytes_per_lli
, total_bytes
;
838 struct pl08x_lli
*llis_va
;
839 struct pl08x_sg
*dsg
;
841 txd
->llis_va
= dma_pool_alloc(pl08x
->pool
, GFP_NOWAIT
, &txd
->llis_bus
);
843 dev_err(&pl08x
->adev
->dev
, "%s no memory for llis\n", __func__
);
850 bd
.lli_bus
= (pl08x
->lli_buses
& PL08X_AHB2
) ? PL080_LLI_LM_AHB2
: 0;
853 /* Find maximum width of the source bus */
855 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_SWIDTH_MASK
) >>
856 PL080_CONTROL_SWIDTH_SHIFT
);
858 /* Find maximum width of the destination bus */
860 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_DWIDTH_MASK
) >>
861 PL080_CONTROL_DWIDTH_SHIFT
);
863 list_for_each_entry(dsg
, &txd
->dsg_list
, node
) {
867 bd
.srcbus
.addr
= dsg
->src_addr
;
868 bd
.dstbus
.addr
= dsg
->dst_addr
;
869 bd
.remainder
= dsg
->len
;
870 bd
.srcbus
.buswidth
= bd
.srcbus
.maxwidth
;
871 bd
.dstbus
.buswidth
= bd
.dstbus
.maxwidth
;
873 pl08x_choose_master_bus(&bd
, &mbus
, &sbus
, cctl
);
875 dev_vdbg(&pl08x
->adev
->dev
, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
876 bd
.srcbus
.addr
, cctl
& PL080_CONTROL_SRC_INCR
? "+" : "",
878 bd
.dstbus
.addr
, cctl
& PL080_CONTROL_DST_INCR
? "+" : "",
881 dev_vdbg(&pl08x
->adev
->dev
, "mbus=%s sbus=%s\n",
882 mbus
== &bd
.srcbus
? "src" : "dst",
883 sbus
== &bd
.srcbus
? "src" : "dst");
886 * Zero length is only allowed if all these requirements are
888 * - flow controller is peripheral.
889 * - src.addr is aligned to src.width
890 * - dst.addr is aligned to dst.width
892 * sg_len == 1 should be true, as there can be two cases here:
894 * - Memory addresses are contiguous and are not scattered.
895 * Here, Only one sg will be passed by user driver, with
896 * memory address and zero length. We pass this to controller
897 * and after the transfer it will receive the last burst
898 * request from peripheral and so transfer finishes.
900 * - Memory addresses are scattered and are not contiguous.
901 * Here, Obviously as DMA controller doesn't know when a lli's
902 * transfer gets over, it can't load next lli. So in this
903 * case, there has to be an assumption that only one lli is
904 * supported. Thus, we can't have scattered addresses.
907 u32 fc
= (txd
->ccfg
& PL080_CONFIG_FLOW_CONTROL_MASK
) >>
908 PL080_CONFIG_FLOW_CONTROL_SHIFT
;
909 if (!((fc
>= PL080_FLOW_SRC2DST_DST
) &&
910 (fc
<= PL080_FLOW_SRC2DST_SRC
))) {
911 dev_err(&pl08x
->adev
->dev
, "%s sg len can't be zero",
916 if ((bd
.srcbus
.addr
% bd
.srcbus
.buswidth
) ||
917 (bd
.dstbus
.addr
% bd
.dstbus
.buswidth
)) {
918 dev_err(&pl08x
->adev
->dev
,
919 "%s src & dst address must be aligned to src"
920 " & dst width if peripheral is flow controller",
925 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
926 bd
.dstbus
.buswidth
, 0);
927 pl08x_fill_lli_for_desc(&bd
, num_llis
++, 0, cctl
);
932 * Send byte by byte for following cases
933 * - Less than a bus width available
934 * - until master bus is aligned
936 if (bd
.remainder
< mbus
->buswidth
)
937 early_bytes
= bd
.remainder
;
938 else if ((mbus
->addr
) % (mbus
->buswidth
)) {
939 early_bytes
= mbus
->buswidth
- (mbus
->addr
) %
941 if ((bd
.remainder
- early_bytes
) < mbus
->buswidth
)
942 early_bytes
= bd
.remainder
;
946 dev_vdbg(&pl08x
->adev
->dev
,
947 "%s byte width LLIs (remain 0x%08x)\n",
948 __func__
, bd
.remainder
);
949 prep_byte_width_lli(&bd
, &cctl
, early_bytes
, num_llis
++,
956 * - if slave is not then we must set its width down
958 if (sbus
->addr
% sbus
->buswidth
) {
959 dev_dbg(&pl08x
->adev
->dev
,
960 "%s set down bus width to one byte\n",
967 * Bytes transferred = tsize * src width, not
970 max_bytes_per_lli
= bd
.srcbus
.buswidth
*
971 PL080_CONTROL_TRANSFER_SIZE_MASK
;
972 dev_vdbg(&pl08x
->adev
->dev
,
973 "%s max bytes per lli = %zu\n",
974 __func__
, max_bytes_per_lli
);
977 * Make largest possible LLIs until less than one bus
980 while (bd
.remainder
> (mbus
->buswidth
- 1)) {
981 size_t lli_len
, tsize
, width
;
984 * If enough left try to send max possible,
985 * otherwise try to send the remainder
987 lli_len
= min(bd
.remainder
, max_bytes_per_lli
);
990 * Check against maximum bus alignment:
991 * Calculate actual transfer size in relation to
992 * bus width an get a maximum remainder of the
993 * highest bus width - 1
995 width
= max(mbus
->buswidth
, sbus
->buswidth
);
996 lli_len
= (lli_len
/ width
) * width
;
997 tsize
= lli_len
/ bd
.srcbus
.buswidth
;
999 dev_vdbg(&pl08x
->adev
->dev
,
1000 "%s fill lli with single lli chunk of "
1001 "size 0x%08zx (remainder 0x%08zx)\n",
1002 __func__
, lli_len
, bd
.remainder
);
1004 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
1005 bd
.dstbus
.buswidth
, tsize
);
1006 pl08x_fill_lli_for_desc(&bd
, num_llis
++,
1008 total_bytes
+= lli_len
;
1012 * Send any odd bytes
1015 dev_vdbg(&pl08x
->adev
->dev
,
1016 "%s align with boundary, send odd bytes (remain %zu)\n",
1017 __func__
, bd
.remainder
);
1018 prep_byte_width_lli(&bd
, &cctl
, bd
.remainder
,
1019 num_llis
++, &total_bytes
);
1023 if (total_bytes
!= dsg
->len
) {
1024 dev_err(&pl08x
->adev
->dev
,
1025 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
1026 __func__
, total_bytes
, dsg
->len
);
1030 if (num_llis
>= MAX_NUM_TSFR_LLIS
) {
1031 dev_err(&pl08x
->adev
->dev
,
1032 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
1033 __func__
, (u32
) MAX_NUM_TSFR_LLIS
);
1038 llis_va
= txd
->llis_va
;
1039 /* The final LLI terminates the LLI. */
1040 llis_va
[num_llis
- 1].lli
= 0;
1041 /* The final LLI element shall also fire an interrupt. */
1042 llis_va
[num_llis
- 1].cctl
|= PL080_CONTROL_TC_IRQ_EN
;
1044 #ifdef VERBOSE_DEBUG
1048 dev_vdbg(&pl08x
->adev
->dev
,
1049 "%-3s %-9s %-10s %-10s %-10s %s\n",
1050 "lli", "", "csrc", "cdst", "clli", "cctl");
1051 for (i
= 0; i
< num_llis
; i
++) {
1052 dev_vdbg(&pl08x
->adev
->dev
,
1053 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1054 i
, &llis_va
[i
], llis_va
[i
].src
,
1055 llis_va
[i
].dst
, llis_va
[i
].lli
, llis_va
[i
].cctl
1064 /* You should call this with the struct pl08x lock held */
1065 static void pl08x_free_txd(struct pl08x_driver_data
*pl08x
,
1066 struct pl08x_txd
*txd
)
1068 struct pl08x_sg
*dsg
, *_dsg
;
1072 dma_pool_free(pl08x
->pool
, txd
->llis_va
, txd
->llis_bus
);
1076 list_for_each_entry_safe(dsg
, _dsg
, &txd
->dsg_list
, node
) {
1077 list_del(&dsg
->node
);
1084 static void pl08x_unmap_buffers(struct pl08x_txd
*txd
)
1086 struct device
*dev
= txd
->vd
.tx
.chan
->device
->dev
;
1087 struct pl08x_sg
*dsg
;
1089 if (!(txd
->vd
.tx
.flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
1090 if (txd
->vd
.tx
.flags
& DMA_COMPL_SRC_UNMAP_SINGLE
)
1091 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1092 dma_unmap_single(dev
, dsg
->src_addr
, dsg
->len
,
1095 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1096 dma_unmap_page(dev
, dsg
->src_addr
, dsg
->len
,
1100 if (!(txd
->vd
.tx
.flags
& DMA_COMPL_SKIP_DEST_UNMAP
)) {
1101 if (txd
->vd
.tx
.flags
& DMA_COMPL_DEST_UNMAP_SINGLE
)
1102 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1103 dma_unmap_single(dev
, dsg
->dst_addr
, dsg
->len
,
1106 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1107 dma_unmap_page(dev
, dsg
->dst_addr
, dsg
->len
,
1112 static void pl08x_desc_free(struct virt_dma_desc
*vd
)
1114 struct pl08x_txd
*txd
= to_pl08x_txd(&vd
->tx
);
1115 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(vd
->tx
.chan
);
1116 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1117 unsigned long flags
;
1120 pl08x_unmap_buffers(txd
);
1123 pl08x_release_mux(plchan
);
1125 spin_lock_irqsave(&pl08x
->lock
, flags
);
1126 pl08x_free_txd(plchan
->host
, txd
);
1127 spin_unlock_irqrestore(&pl08x
->lock
, flags
);
1130 static void pl08x_free_txd_list(struct pl08x_driver_data
*pl08x
,
1131 struct pl08x_dma_chan
*plchan
)
1134 struct pl08x_txd
*txd
;
1136 vchan_get_all_descriptors(&plchan
->vc
, &head
);
1138 while (!list_empty(&head
)) {
1139 txd
= list_first_entry(&head
, struct pl08x_txd
, vd
.node
);
1140 list_del(&txd
->vd
.node
);
1141 pl08x_desc_free(&txd
->vd
);
1146 * The DMA ENGINE API
1148 static int pl08x_alloc_chan_resources(struct dma_chan
*chan
)
1153 static void pl08x_free_chan_resources(struct dma_chan
*chan
)
1157 static struct dma_async_tx_descriptor
*pl08x_prep_dma_interrupt(
1158 struct dma_chan
*chan
, unsigned long flags
)
1160 struct dma_async_tx_descriptor
*retval
= NULL
;
1166 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1167 * If slaves are relying on interrupts to signal completion this function
1168 * must not be called with interrupts disabled.
1170 static enum dma_status
pl08x_dma_tx_status(struct dma_chan
*chan
,
1171 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
1173 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1174 enum dma_status ret
;
1176 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1177 if (ret
== DMA_SUCCESS
)
1181 * This cookie not complete yet
1182 * Get number of bytes left in the active transactions and queue
1184 dma_set_residue(txstate
, pl08x_getbytes_chan(plchan
));
1186 if (plchan
->state
== PL08X_CHAN_PAUSED
)
1189 /* Whether waiting or running, we're in progress */
1190 return DMA_IN_PROGRESS
;
1193 /* PrimeCell DMA extension */
1194 struct burst_table
{
1199 static const struct burst_table burst_sizes
[] = {
1202 .reg
= PL080_BSIZE_256
,
1206 .reg
= PL080_BSIZE_128
,
1210 .reg
= PL080_BSIZE_64
,
1214 .reg
= PL080_BSIZE_32
,
1218 .reg
= PL080_BSIZE_16
,
1222 .reg
= PL080_BSIZE_8
,
1226 .reg
= PL080_BSIZE_4
,
1230 .reg
= PL080_BSIZE_1
,
1235 * Given the source and destination available bus masks, select which
1236 * will be routed to each port. We try to have source and destination
1237 * on separate ports, but always respect the allowable settings.
1239 static u32
pl08x_select_bus(u8 src
, u8 dst
)
1243 if (!(dst
& PL08X_AHB1
) || ((dst
& PL08X_AHB2
) && (src
& PL08X_AHB1
)))
1244 cctl
|= PL080_CONTROL_DST_AHB2
;
1245 if (!(src
& PL08X_AHB1
) || ((src
& PL08X_AHB2
) && !(dst
& PL08X_AHB2
)))
1246 cctl
|= PL080_CONTROL_SRC_AHB2
;
1251 static u32
pl08x_cctl(u32 cctl
)
1253 cctl
&= ~(PL080_CONTROL_SRC_AHB2
| PL080_CONTROL_DST_AHB2
|
1254 PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
|
1255 PL080_CONTROL_PROT_MASK
);
1257 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1258 return cctl
| PL080_CONTROL_PROT_SYS
;
1261 static u32
pl08x_width(enum dma_slave_buswidth width
)
1264 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
1265 return PL080_WIDTH_8BIT
;
1266 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
1267 return PL080_WIDTH_16BIT
;
1268 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
1269 return PL080_WIDTH_32BIT
;
1275 static u32
pl08x_burst(u32 maxburst
)
1279 for (i
= 0; i
< ARRAY_SIZE(burst_sizes
); i
++)
1280 if (burst_sizes
[i
].burstwords
<= maxburst
)
1283 return burst_sizes
[i
].reg
;
1286 static u32
pl08x_get_cctl(struct pl08x_dma_chan
*plchan
,
1287 enum dma_slave_buswidth addr_width
, u32 maxburst
)
1289 u32 width
, burst
, cctl
= 0;
1291 width
= pl08x_width(addr_width
);
1295 cctl
|= width
<< PL080_CONTROL_SWIDTH_SHIFT
;
1296 cctl
|= width
<< PL080_CONTROL_DWIDTH_SHIFT
;
1299 * If this channel will only request single transfers, set this
1300 * down to ONE element. Also select one element if no maxburst
1303 if (plchan
->cd
->single
)
1306 burst
= pl08x_burst(maxburst
);
1307 cctl
|= burst
<< PL080_CONTROL_SB_SIZE_SHIFT
;
1308 cctl
|= burst
<< PL080_CONTROL_DB_SIZE_SHIFT
;
1310 return pl08x_cctl(cctl
);
1313 static int dma_set_runtime_config(struct dma_chan
*chan
,
1314 struct dma_slave_config
*config
)
1316 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1321 /* Reject definitely invalid configurations */
1322 if (config
->src_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
||
1323 config
->dst_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
)
1326 plchan
->cfg
= *config
;
1332 * Slave transactions callback to the slave device to allow
1333 * synchronization of slave DMA signals with the DMAC enable
1335 static void pl08x_issue_pending(struct dma_chan
*chan
)
1337 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1338 unsigned long flags
;
1340 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1341 if (vchan_issue_pending(&plchan
->vc
)) {
1342 if (!plchan
->phychan
&& plchan
->state
!= PL08X_CHAN_WAITING
)
1343 pl08x_phy_alloc_and_start(plchan
);
1345 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1348 static int pl08x_prep_channel_resources(struct pl08x_dma_chan
*plchan
,
1349 struct pl08x_txd
*txd
)
1351 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1354 num_llis
= pl08x_fill_llis_for_desc(pl08x
, txd
);
1356 unsigned long flags
;
1358 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1359 pl08x_free_txd(pl08x
, txd
);
1360 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1367 static struct pl08x_txd
*pl08x_get_txd(struct pl08x_dma_chan
*plchan
)
1369 struct pl08x_txd
*txd
= kzalloc(sizeof(*txd
), GFP_NOWAIT
);
1372 INIT_LIST_HEAD(&txd
->dsg_list
);
1374 /* Always enable error and terminal interrupts */
1375 txd
->ccfg
= PL080_CONFIG_ERR_IRQ_MASK
|
1376 PL080_CONFIG_TC_IRQ_MASK
;
1382 * Initialize a descriptor to be used by memcpy submit
1384 static struct dma_async_tx_descriptor
*pl08x_prep_dma_memcpy(
1385 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1386 size_t len
, unsigned long flags
)
1388 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1389 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1390 struct pl08x_txd
*txd
;
1391 struct pl08x_sg
*dsg
;
1394 txd
= pl08x_get_txd(plchan
);
1396 dev_err(&pl08x
->adev
->dev
,
1397 "%s no memory for descriptor\n", __func__
);
1401 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1403 pl08x_free_txd(pl08x
, txd
);
1404 dev_err(&pl08x
->adev
->dev
, "%s no memory for pl080 sg\n",
1408 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1410 dsg
->src_addr
= src
;
1411 dsg
->dst_addr
= dest
;
1414 /* Set platform data for m2m */
1415 txd
->ccfg
|= PL080_FLOW_MEM2MEM
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1416 txd
->cctl
= pl08x
->pd
->memcpy_channel
.cctl_memcpy
&
1417 ~(PL080_CONTROL_DST_AHB2
| PL080_CONTROL_SRC_AHB2
);
1419 /* Both to be incremented or the code will break */
1420 txd
->cctl
|= PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
;
1422 if (pl08x
->vd
->dualmaster
)
1423 txd
->cctl
|= pl08x_select_bus(pl08x
->mem_buses
,
1426 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1430 return vchan_tx_prep(&plchan
->vc
, &txd
->vd
, flags
);
1433 static struct dma_async_tx_descriptor
*pl08x_prep_slave_sg(
1434 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1435 unsigned int sg_len
, enum dma_transfer_direction direction
,
1436 unsigned long flags
, void *context
)
1438 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1439 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1440 struct pl08x_txd
*txd
;
1441 struct pl08x_sg
*dsg
;
1442 struct scatterlist
*sg
;
1443 enum dma_slave_buswidth addr_width
;
1444 dma_addr_t slave_addr
;
1446 u8 src_buses
, dst_buses
;
1449 dev_dbg(&pl08x
->adev
->dev
, "%s prepare transaction of %d bytes from %s\n",
1450 __func__
, sg_dma_len(sgl
), plchan
->name
);
1452 txd
= pl08x_get_txd(plchan
);
1454 dev_err(&pl08x
->adev
->dev
, "%s no txd\n", __func__
);
1459 * Set up addresses, the PrimeCell configured address
1460 * will take precedence since this may configure the
1461 * channel target address dynamically at runtime.
1463 if (direction
== DMA_MEM_TO_DEV
) {
1464 cctl
= PL080_CONTROL_SRC_INCR
;
1465 slave_addr
= plchan
->cfg
.dst_addr
;
1466 addr_width
= plchan
->cfg
.dst_addr_width
;
1467 maxburst
= plchan
->cfg
.dst_maxburst
;
1468 src_buses
= pl08x
->mem_buses
;
1469 dst_buses
= plchan
->cd
->periph_buses
;
1470 } else if (direction
== DMA_DEV_TO_MEM
) {
1471 cctl
= PL080_CONTROL_DST_INCR
;
1472 slave_addr
= plchan
->cfg
.src_addr
;
1473 addr_width
= plchan
->cfg
.src_addr_width
;
1474 maxburst
= plchan
->cfg
.src_maxburst
;
1475 src_buses
= plchan
->cd
->periph_buses
;
1476 dst_buses
= pl08x
->mem_buses
;
1478 pl08x_free_txd(pl08x
, txd
);
1479 dev_err(&pl08x
->adev
->dev
,
1480 "%s direction unsupported\n", __func__
);
1484 cctl
|= pl08x_get_cctl(plchan
, addr_width
, maxburst
);
1486 pl08x_free_txd(pl08x
, txd
);
1487 dev_err(&pl08x
->adev
->dev
,
1488 "DMA slave configuration botched?\n");
1492 txd
->cctl
= cctl
| pl08x_select_bus(src_buses
, dst_buses
);
1494 if (plchan
->cfg
.device_fc
)
1495 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER_PER
:
1496 PL080_FLOW_PER2MEM_PER
;
1498 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER
:
1501 txd
->ccfg
|= tmp
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1503 ret
= pl08x_request_mux(plchan
);
1505 pl08x_free_txd(pl08x
, txd
);
1506 dev_dbg(&pl08x
->adev
->dev
,
1507 "unable to mux for transfer on %s due to platform restrictions\n",
1512 dev_dbg(&pl08x
->adev
->dev
, "allocated DMA request signal %d for xfer on %s\n",
1513 plchan
->signal
, plchan
->name
);
1515 /* Assign the flow control signal to this channel */
1516 if (direction
== DMA_MEM_TO_DEV
)
1517 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_DST_SEL_SHIFT
;
1519 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_SRC_SEL_SHIFT
;
1521 for_each_sg(sgl
, sg
, sg_len
, tmp
) {
1522 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1524 pl08x_release_mux(plchan
);
1525 pl08x_free_txd(pl08x
, txd
);
1526 dev_err(&pl08x
->adev
->dev
, "%s no mem for pl080 sg\n",
1530 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1532 dsg
->len
= sg_dma_len(sg
);
1533 if (direction
== DMA_MEM_TO_DEV
) {
1534 dsg
->src_addr
= sg_dma_address(sg
);
1535 dsg
->dst_addr
= slave_addr
;
1537 dsg
->src_addr
= slave_addr
;
1538 dsg
->dst_addr
= sg_dma_address(sg
);
1542 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1546 return vchan_tx_prep(&plchan
->vc
, &txd
->vd
, flags
);
1549 static int pl08x_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1552 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1553 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1554 unsigned long flags
;
1557 /* Controls applicable to inactive channels */
1558 if (cmd
== DMA_SLAVE_CONFIG
) {
1559 return dma_set_runtime_config(chan
,
1560 (struct dma_slave_config
*)arg
);
1564 * Anything succeeds on channels with no physical allocation and
1565 * no queued transfers.
1567 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1568 if (!plchan
->phychan
&& !plchan
->at
) {
1569 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1574 case DMA_TERMINATE_ALL
:
1575 plchan
->state
= PL08X_CHAN_IDLE
;
1577 if (plchan
->phychan
) {
1579 * Mark physical channel as free and free any slave
1582 pl08x_phy_free(plchan
);
1584 /* Dequeue jobs and free LLIs */
1586 pl08x_desc_free(&plchan
->at
->vd
);
1589 /* Dequeue jobs not yet fired as well */
1590 pl08x_free_txd_list(pl08x
, plchan
);
1593 pl08x_pause_phy_chan(plchan
->phychan
);
1594 plchan
->state
= PL08X_CHAN_PAUSED
;
1597 pl08x_resume_phy_chan(plchan
->phychan
);
1598 plchan
->state
= PL08X_CHAN_RUNNING
;
1601 /* Unknown command */
1606 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1611 bool pl08x_filter_id(struct dma_chan
*chan
, void *chan_id
)
1613 struct pl08x_dma_chan
*plchan
;
1614 char *name
= chan_id
;
1616 /* Reject channels for devices not bound to this driver */
1617 if (chan
->device
->dev
->driver
!= &pl08x_amba_driver
.drv
)
1620 plchan
= to_pl08x_chan(chan
);
1622 /* Check that the channel is not taken! */
1623 if (!strcmp(plchan
->name
, name
))
1630 * Just check that the device is there and active
1631 * TODO: turn this bit on/off depending on the number of physical channels
1632 * actually used, if it is zero... well shut it off. That will save some
1633 * power. Cut the clock at the same time.
1635 static void pl08x_ensure_on(struct pl08x_driver_data
*pl08x
)
1637 /* The Nomadik variant does not have the config register */
1638 if (pl08x
->vd
->nomadik
)
1640 writel(PL080_CONFIG_ENABLE
, pl08x
->base
+ PL080_CONFIG
);
1643 static irqreturn_t
pl08x_irq(int irq
, void *dev
)
1645 struct pl08x_driver_data
*pl08x
= dev
;
1646 u32 mask
= 0, err
, tc
, i
;
1648 /* check & clear - ERR & TC interrupts */
1649 err
= readl(pl08x
->base
+ PL080_ERR_STATUS
);
1651 dev_err(&pl08x
->adev
->dev
, "%s error interrupt, register value 0x%08x\n",
1653 writel(err
, pl08x
->base
+ PL080_ERR_CLEAR
);
1655 tc
= readl(pl08x
->base
+ PL080_TC_STATUS
);
1657 writel(tc
, pl08x
->base
+ PL080_TC_CLEAR
);
1662 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1663 if (((1 << i
) & err
) || ((1 << i
) & tc
)) {
1664 /* Locate physical channel */
1665 struct pl08x_phy_chan
*phychan
= &pl08x
->phy_chans
[i
];
1666 struct pl08x_dma_chan
*plchan
= phychan
->serving
;
1667 struct pl08x_txd
*tx
;
1670 dev_err(&pl08x
->adev
->dev
,
1671 "%s Error TC interrupt on unused channel: 0x%08x\n",
1676 spin_lock(&plchan
->vc
.lock
);
1681 * This descriptor is done, release its mux
1684 pl08x_release_mux(plchan
);
1686 vchan_cookie_complete(&tx
->vd
);
1689 * And start the next descriptor (if any),
1690 * otherwise free this channel.
1692 if (vchan_next_desc(&plchan
->vc
))
1693 pl08x_start_next_txd(plchan
);
1695 pl08x_phy_free(plchan
);
1697 spin_unlock(&plchan
->vc
.lock
);
1703 return mask
? IRQ_HANDLED
: IRQ_NONE
;
1706 static void pl08x_dma_slave_init(struct pl08x_dma_chan
*chan
)
1709 chan
->name
= chan
->cd
->bus_id
;
1710 chan
->cfg
.src_addr
= chan
->cd
->addr
;
1711 chan
->cfg
.dst_addr
= chan
->cd
->addr
;
1715 * Initialise the DMAC memcpy/slave channels.
1716 * Make a local wrapper to hold required data
1718 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data
*pl08x
,
1719 struct dma_device
*dmadev
, unsigned int channels
, bool slave
)
1721 struct pl08x_dma_chan
*chan
;
1724 INIT_LIST_HEAD(&dmadev
->channels
);
1727 * Register as many many memcpy as we have physical channels,
1728 * we won't always be able to use all but the code will have
1729 * to cope with that situation.
1731 for (i
= 0; i
< channels
; i
++) {
1732 chan
= kzalloc(sizeof(*chan
), GFP_KERNEL
);
1734 dev_err(&pl08x
->adev
->dev
,
1735 "%s no memory for channel\n", __func__
);
1740 chan
->state
= PL08X_CHAN_IDLE
;
1744 chan
->cd
= &pl08x
->pd
->slave_channels
[i
];
1745 pl08x_dma_slave_init(chan
);
1747 chan
->cd
= &pl08x
->pd
->memcpy_channel
;
1748 chan
->name
= kasprintf(GFP_KERNEL
, "memcpy%d", i
);
1754 dev_dbg(&pl08x
->adev
->dev
,
1755 "initialize virtual channel \"%s\"\n",
1758 chan
->vc
.desc_free
= pl08x_desc_free
;
1759 vchan_init(&chan
->vc
, dmadev
);
1761 dev_info(&pl08x
->adev
->dev
, "initialized %d virtual %s channels\n",
1762 i
, slave
? "slave" : "memcpy");
1766 static void pl08x_free_virtual_channels(struct dma_device
*dmadev
)
1768 struct pl08x_dma_chan
*chan
= NULL
;
1769 struct pl08x_dma_chan
*next
;
1771 list_for_each_entry_safe(chan
,
1772 next
, &dmadev
->channels
, vc
.chan
.device_node
) {
1773 list_del(&chan
->vc
.chan
.device_node
);
1778 #ifdef CONFIG_DEBUG_FS
1779 static const char *pl08x_state_str(enum pl08x_dma_chan_state state
)
1782 case PL08X_CHAN_IDLE
:
1784 case PL08X_CHAN_RUNNING
:
1786 case PL08X_CHAN_PAUSED
:
1788 case PL08X_CHAN_WAITING
:
1793 return "UNKNOWN STATE";
1796 static int pl08x_debugfs_show(struct seq_file
*s
, void *data
)
1798 struct pl08x_driver_data
*pl08x
= s
->private;
1799 struct pl08x_dma_chan
*chan
;
1800 struct pl08x_phy_chan
*ch
;
1801 unsigned long flags
;
1804 seq_printf(s
, "PL08x physical channels:\n");
1805 seq_printf(s
, "CHANNEL:\tUSER:\n");
1806 seq_printf(s
, "--------\t-----\n");
1807 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1808 struct pl08x_dma_chan
*virt_chan
;
1810 ch
= &pl08x
->phy_chans
[i
];
1812 spin_lock_irqsave(&ch
->lock
, flags
);
1813 virt_chan
= ch
->serving
;
1815 seq_printf(s
, "%d\t\t%s%s\n",
1817 virt_chan
? virt_chan
->name
: "(none)",
1818 ch
->locked
? " LOCKED" : "");
1820 spin_unlock_irqrestore(&ch
->lock
, flags
);
1823 seq_printf(s
, "\nPL08x virtual memcpy channels:\n");
1824 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1825 seq_printf(s
, "--------\t------\n");
1826 list_for_each_entry(chan
, &pl08x
->memcpy
.channels
, vc
.chan
.device_node
) {
1827 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1828 pl08x_state_str(chan
->state
));
1831 seq_printf(s
, "\nPL08x virtual slave channels:\n");
1832 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1833 seq_printf(s
, "--------\t------\n");
1834 list_for_each_entry(chan
, &pl08x
->slave
.channels
, vc
.chan
.device_node
) {
1835 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1836 pl08x_state_str(chan
->state
));
1842 static int pl08x_debugfs_open(struct inode
*inode
, struct file
*file
)
1844 return single_open(file
, pl08x_debugfs_show
, inode
->i_private
);
1847 static const struct file_operations pl08x_debugfs_operations
= {
1848 .open
= pl08x_debugfs_open
,
1850 .llseek
= seq_lseek
,
1851 .release
= single_release
,
1854 static void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1856 /* Expose a simple debugfs interface to view all clocks */
1857 (void) debugfs_create_file(dev_name(&pl08x
->adev
->dev
),
1858 S_IFREG
| S_IRUGO
, NULL
, pl08x
,
1859 &pl08x_debugfs_operations
);
1863 static inline void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1868 static int pl08x_probe(struct amba_device
*adev
, const struct amba_id
*id
)
1870 struct pl08x_driver_data
*pl08x
;
1871 const struct vendor_data
*vd
= id
->data
;
1875 ret
= amba_request_regions(adev
, NULL
);
1879 /* Create the driver state holder */
1880 pl08x
= kzalloc(sizeof(*pl08x
), GFP_KERNEL
);
1886 /* Initialize memcpy engine */
1887 dma_cap_set(DMA_MEMCPY
, pl08x
->memcpy
.cap_mask
);
1888 pl08x
->memcpy
.dev
= &adev
->dev
;
1889 pl08x
->memcpy
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1890 pl08x
->memcpy
.device_free_chan_resources
= pl08x_free_chan_resources
;
1891 pl08x
->memcpy
.device_prep_dma_memcpy
= pl08x_prep_dma_memcpy
;
1892 pl08x
->memcpy
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1893 pl08x
->memcpy
.device_tx_status
= pl08x_dma_tx_status
;
1894 pl08x
->memcpy
.device_issue_pending
= pl08x_issue_pending
;
1895 pl08x
->memcpy
.device_control
= pl08x_control
;
1897 /* Initialize slave engine */
1898 dma_cap_set(DMA_SLAVE
, pl08x
->slave
.cap_mask
);
1899 pl08x
->slave
.dev
= &adev
->dev
;
1900 pl08x
->slave
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1901 pl08x
->slave
.device_free_chan_resources
= pl08x_free_chan_resources
;
1902 pl08x
->slave
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1903 pl08x
->slave
.device_tx_status
= pl08x_dma_tx_status
;
1904 pl08x
->slave
.device_issue_pending
= pl08x_issue_pending
;
1905 pl08x
->slave
.device_prep_slave_sg
= pl08x_prep_slave_sg
;
1906 pl08x
->slave
.device_control
= pl08x_control
;
1908 /* Get the platform data */
1909 pl08x
->pd
= dev_get_platdata(&adev
->dev
);
1911 dev_err(&adev
->dev
, "no platform data supplied\n");
1912 goto out_no_platdata
;
1915 /* Assign useful pointers to the driver state */
1919 /* By default, AHB1 only. If dualmaster, from platform */
1920 pl08x
->lli_buses
= PL08X_AHB1
;
1921 pl08x
->mem_buses
= PL08X_AHB1
;
1922 if (pl08x
->vd
->dualmaster
) {
1923 pl08x
->lli_buses
= pl08x
->pd
->lli_buses
;
1924 pl08x
->mem_buses
= pl08x
->pd
->mem_buses
;
1927 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1928 pl08x
->pool
= dma_pool_create(DRIVER_NAME
, &pl08x
->adev
->dev
,
1929 PL08X_LLI_TSFR_SIZE
, PL08X_ALIGN
, 0);
1932 goto out_no_lli_pool
;
1935 pl08x
->base
= ioremap(adev
->res
.start
, resource_size(&adev
->res
));
1938 goto out_no_ioremap
;
1941 /* Turn on the PL08x */
1942 pl08x_ensure_on(pl08x
);
1944 /* Attach the interrupt handler */
1945 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
1946 writel(0x000000FF, pl08x
->base
+ PL080_TC_CLEAR
);
1948 ret
= request_irq(adev
->irq
[0], pl08x_irq
, IRQF_DISABLED
,
1949 DRIVER_NAME
, pl08x
);
1951 dev_err(&adev
->dev
, "%s failed to request interrupt %d\n",
1952 __func__
, adev
->irq
[0]);
1956 /* Initialize physical channels */
1957 pl08x
->phy_chans
= kzalloc((vd
->channels
* sizeof(*pl08x
->phy_chans
)),
1959 if (!pl08x
->phy_chans
) {
1960 dev_err(&adev
->dev
, "%s failed to allocate "
1961 "physical channel holders\n",
1963 goto out_no_phychans
;
1966 for (i
= 0; i
< vd
->channels
; i
++) {
1967 struct pl08x_phy_chan
*ch
= &pl08x
->phy_chans
[i
];
1970 ch
->base
= pl08x
->base
+ PL080_Cx_BASE(i
);
1971 spin_lock_init(&ch
->lock
);
1974 * Nomadik variants can have channels that are locked
1975 * down for the secure world only. Lock up these channels
1976 * by perpetually serving a dummy virtual channel.
1981 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
1982 if (val
& (PL080N_CONFIG_ITPROT
| PL080N_CONFIG_SECPROT
)) {
1983 dev_info(&adev
->dev
, "physical channel %d reserved for secure access only\n", i
);
1988 dev_dbg(&adev
->dev
, "physical channel %d is %s\n",
1989 i
, pl08x_phy_channel_busy(ch
) ? "BUSY" : "FREE");
1992 /* Register as many memcpy channels as there are physical channels */
1993 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->memcpy
,
1994 pl08x
->vd
->channels
, false);
1996 dev_warn(&pl08x
->adev
->dev
,
1997 "%s failed to enumerate memcpy channels - %d\n",
2001 pl08x
->memcpy
.chancnt
= ret
;
2003 /* Register slave channels */
2004 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->slave
,
2005 pl08x
->pd
->num_slave_channels
, true);
2007 dev_warn(&pl08x
->adev
->dev
,
2008 "%s failed to enumerate slave channels - %d\n",
2012 pl08x
->slave
.chancnt
= ret
;
2014 ret
= dma_async_device_register(&pl08x
->memcpy
);
2016 dev_warn(&pl08x
->adev
->dev
,
2017 "%s failed to register memcpy as an async device - %d\n",
2019 goto out_no_memcpy_reg
;
2022 ret
= dma_async_device_register(&pl08x
->slave
);
2024 dev_warn(&pl08x
->adev
->dev
,
2025 "%s failed to register slave as an async device - %d\n",
2027 goto out_no_slave_reg
;
2030 amba_set_drvdata(adev
, pl08x
);
2031 init_pl08x_debugfs(pl08x
);
2032 dev_info(&pl08x
->adev
->dev
, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2033 amba_part(adev
), amba_rev(adev
),
2034 (unsigned long long)adev
->res
.start
, adev
->irq
[0]);
2039 dma_async_device_unregister(&pl08x
->memcpy
);
2041 pl08x_free_virtual_channels(&pl08x
->slave
);
2043 pl08x_free_virtual_channels(&pl08x
->memcpy
);
2045 kfree(pl08x
->phy_chans
);
2047 free_irq(adev
->irq
[0], pl08x
);
2049 iounmap(pl08x
->base
);
2051 dma_pool_destroy(pl08x
->pool
);
2056 amba_release_regions(adev
);
2060 /* PL080 has 8 channels and the PL080 have just 2 */
2061 static struct vendor_data vendor_pl080
= {
2066 static struct vendor_data vendor_nomadik
= {
2072 static struct vendor_data vendor_pl081
= {
2074 .dualmaster
= false,
2077 static struct amba_id pl08x_ids
[] = {
2082 .data
= &vendor_pl080
,
2088 .data
= &vendor_pl081
,
2090 /* Nomadik 8815 PL080 variant */
2094 .data
= &vendor_nomadik
,
2099 MODULE_DEVICE_TABLE(amba
, pl08x_ids
);
2101 static struct amba_driver pl08x_amba_driver
= {
2102 .drv
.name
= DRIVER_NAME
,
2103 .id_table
= pl08x_ids
,
2104 .probe
= pl08x_probe
,
2107 static int __init
pl08x_init(void)
2110 retval
= amba_driver_register(&pl08x_amba_driver
);
2112 printk(KERN_WARNING DRIVER_NAME
2113 "failed to register as an AMBA device (%d)\n",
2117 subsys_initcall(pl08x_init
);