2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <asm/hardware/pl080.h>
88 #include "dmaengine.h"
90 #define DRIVER_NAME "pl08xdmac"
92 static struct amba_driver pl08x_amba_driver
;
93 struct pl08x_driver_data
;
96 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
97 * @channels: the number of channels available in this variant
98 * @dualmaster: whether this version supports dual AHB masters or not.
99 * @nomadik: whether the channels have Nomadik security extension bits
100 * that need to be checked for permission before use and some registers are
110 * PL08X private data structures
111 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
112 * start & end do not - their bus bit info is in cctl. Also note that these
113 * are fixed 32-bit quantities.
123 * struct pl08x_bus_data - information of source or destination
124 * busses for a transfer
125 * @addr: current address
126 * @maxwidth: the maximum width of a transfer on this bus
127 * @buswidth: the width of this bus in bytes: 1, 2 or 4
129 struct pl08x_bus_data
{
136 * struct pl08x_phy_chan - holder for the physical channels
137 * @id: physical index to this channel
138 * @lock: a lock to use when altering an instance of this struct
139 * @signal: the physical signal (aka channel) serving this physical channel
141 * @serving: the virtual channel currently being served by this physical
144 struct pl08x_phy_chan
{
149 struct pl08x_dma_chan
*serving
;
153 * struct pl08x_sg - structure containing data per sg
154 * @src_addr: src address of sg
155 * @dst_addr: dst address of sg
156 * @len: transfer len in bytes
157 * @node: node for txd's dsg_list
163 struct list_head node
;
167 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
168 * @tx: async tx descriptor
169 * @node: node for txd list for channels
170 * @dsg_list: list of children sg's
171 * @direction: direction of transfer
172 * @llis_bus: DMA memory address (physical) start for the LLIs
173 * @llis_va: virtual memory address start for the LLIs
174 * @cctl: control reg values for current txd
175 * @ccfg: config reg values for current txd
178 struct dma_async_tx_descriptor tx
;
179 struct list_head node
;
180 struct list_head dsg_list
;
181 enum dma_transfer_direction direction
;
183 struct pl08x_lli
*llis_va
;
184 /* Default cctl value for LLIs */
187 * Settings to be put into the physical channel when we
188 * trigger this txd. Other registers are in llis_va[0].
194 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
196 * @PL08X_CHAN_IDLE: the channel is idle
197 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
198 * channel and is running a transfer on it
199 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
200 * channel, but the transfer is currently paused
201 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
202 * channel to become available (only pertains to memcpy channels)
204 enum pl08x_dma_chan_state
{
212 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
213 * @chan: wrappped abstract channel
214 * @phychan: the physical channel utilized by this channel, if there is one
215 * @phychan_hold: if non-zero, hold on to the physical channel even if we
216 * have no pending entries
217 * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
218 * @name: name of channel
219 * @cd: channel platform data
220 * @runtime_addr: address for RX/TX according to the runtime config
221 * @pend_list: queued transactions pending on this channel
222 * @at: active transaction on this channel
223 * @lock: a lock for this channel data
224 * @host: a pointer to the host (internal use)
225 * @state: whether the channel is idle, paused, running etc
226 * @slave: whether this channel is a device (slave) or for memcpy
227 * @waiting: a TX descriptor on this channel which is waiting for a physical
228 * channel to become available
230 struct pl08x_dma_chan
{
231 struct dma_chan chan
;
232 struct pl08x_phy_chan
*phychan
;
234 struct tasklet_struct tasklet
;
236 const struct pl08x_channel_data
*cd
;
237 struct dma_slave_config cfg
;
238 struct list_head pend_list
;
239 struct pl08x_txd
*at
;
241 struct pl08x_driver_data
*host
;
242 enum pl08x_dma_chan_state state
;
244 struct pl08x_txd
*waiting
;
248 * struct pl08x_driver_data - the local state holder for the PL08x
249 * @slave: slave engine for this instance
250 * @memcpy: memcpy engine for this instance
251 * @base: virtual memory base (remapped) for the PL08x
252 * @adev: the corresponding AMBA (PrimeCell) bus entry
253 * @vd: vendor data for this PL08x variant
254 * @pd: platform data passed in from the platform/machine
255 * @phy_chans: array of data for the physical channels
256 * @pool: a pool for the LLI descriptors
257 * @pool_ctr: counter of LLIs in the pool
258 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
260 * @mem_buses: set to indicate memory transfers on AHB2.
261 * @lock: a spinlock for this struct
263 struct pl08x_driver_data
{
264 struct dma_device slave
;
265 struct dma_device memcpy
;
267 struct amba_device
*adev
;
268 const struct vendor_data
*vd
;
269 struct pl08x_platform_data
*pd
;
270 struct pl08x_phy_chan
*phy_chans
;
271 struct dma_pool
*pool
;
278 * PL08X specific defines
281 /* Size (bytes) of each LLI buffer allocated for one transfer */
282 # define PL08X_LLI_TSFR_SIZE 0x2000
284 /* Maximum times we call dma_pool_alloc on this pool without freeing */
285 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
286 #define PL08X_ALIGN 8
288 static inline struct pl08x_dma_chan
*to_pl08x_chan(struct dma_chan
*chan
)
290 return container_of(chan
, struct pl08x_dma_chan
, chan
);
293 static inline struct pl08x_txd
*to_pl08x_txd(struct dma_async_tx_descriptor
*tx
)
295 return container_of(tx
, struct pl08x_txd
, tx
);
301 * This gives us the DMA request input to the PL08x primecell which the
302 * peripheral described by the channel data will be routed to, possibly
303 * via a board/SoC specific external MUX. One important point to note
304 * here is that this does not depend on the physical channel.
306 static int pl08x_request_mux(struct pl08x_dma_chan
*plchan
, struct pl08x_phy_chan
*ch
)
308 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
311 if (pd
->get_signal
) {
312 ret
= pd
->get_signal(plchan
->cd
);
321 static void pl08x_release_mux(struct pl08x_dma_chan
*plchan
)
323 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
325 if (plchan
->phychan
->signal
>= 0 && pd
->put_signal
) {
326 pd
->put_signal(plchan
->cd
, plchan
->phychan
->signal
);
327 plchan
->phychan
->signal
= -1;
332 * Physical channel handling
335 /* Whether a certain channel is busy or not */
336 static int pl08x_phy_channel_busy(struct pl08x_phy_chan
*ch
)
340 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
341 return val
& PL080_CONFIG_ACTIVE
;
345 * Set the initial DMA register values i.e. those for the first LLI
346 * The next LLI pointer and the configuration interrupt bit have
347 * been set when the LLIs were constructed. Poke them into the hardware
348 * and start the transfer.
350 static void pl08x_start_txd(struct pl08x_dma_chan
*plchan
,
351 struct pl08x_txd
*txd
)
353 struct pl08x_driver_data
*pl08x
= plchan
->host
;
354 struct pl08x_phy_chan
*phychan
= plchan
->phychan
;
355 struct pl08x_lli
*lli
= &txd
->llis_va
[0];
360 /* Wait for channel inactive */
361 while (pl08x_phy_channel_busy(phychan
))
364 dev_vdbg(&pl08x
->adev
->dev
,
365 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
366 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
367 phychan
->id
, lli
->src
, lli
->dst
, lli
->lli
, lli
->cctl
,
370 writel(lli
->src
, phychan
->base
+ PL080_CH_SRC_ADDR
);
371 writel(lli
->dst
, phychan
->base
+ PL080_CH_DST_ADDR
);
372 writel(lli
->lli
, phychan
->base
+ PL080_CH_LLI
);
373 writel(lli
->cctl
, phychan
->base
+ PL080_CH_CONTROL
);
374 writel(txd
->ccfg
, phychan
->base
+ PL080_CH_CONFIG
);
376 /* Enable the DMA channel */
377 /* Do not access config register until channel shows as disabled */
378 while (readl(pl08x
->base
+ PL080_EN_CHAN
) & (1 << phychan
->id
))
381 /* Do not access config register until channel shows as inactive */
382 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
383 while ((val
& PL080_CONFIG_ACTIVE
) || (val
& PL080_CONFIG_ENABLE
))
384 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
386 writel(val
| PL080_CONFIG_ENABLE
, phychan
->base
+ PL080_CH_CONFIG
);
390 * Pause the channel by setting the HALT bit.
392 * For M->P transfers, pause the DMAC first and then stop the peripheral -
393 * the FIFO can only drain if the peripheral is still requesting data.
394 * (note: this can still timeout if the DMAC FIFO never drains of data.)
396 * For P->M transfers, disable the peripheral first to stop it filling
397 * the DMAC FIFO, and then pause the DMAC.
399 static void pl08x_pause_phy_chan(struct pl08x_phy_chan
*ch
)
404 /* Set the HALT bit and wait for the FIFO to drain */
405 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
406 val
|= PL080_CONFIG_HALT
;
407 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
409 /* Wait for channel inactive */
410 for (timeout
= 1000; timeout
; timeout
--) {
411 if (!pl08x_phy_channel_busy(ch
))
415 if (pl08x_phy_channel_busy(ch
))
416 pr_err("pl08x: channel%u timeout waiting for pause\n", ch
->id
);
419 static void pl08x_resume_phy_chan(struct pl08x_phy_chan
*ch
)
423 /* Clear the HALT bit */
424 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
425 val
&= ~PL080_CONFIG_HALT
;
426 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
430 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
431 * clears any pending interrupt status. This should not be used for
432 * an on-going transfer, but as a method of shutting down a channel
433 * (eg, when it's no longer used) or terminating a transfer.
435 static void pl08x_terminate_phy_chan(struct pl08x_driver_data
*pl08x
,
436 struct pl08x_phy_chan
*ch
)
438 u32 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
440 val
&= ~(PL080_CONFIG_ENABLE
| PL080_CONFIG_ERR_IRQ_MASK
|
441 PL080_CONFIG_TC_IRQ_MASK
);
443 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
445 writel(1 << ch
->id
, pl08x
->base
+ PL080_ERR_CLEAR
);
446 writel(1 << ch
->id
, pl08x
->base
+ PL080_TC_CLEAR
);
449 static inline u32
get_bytes_in_cctl(u32 cctl
)
451 /* The source width defines the number of bytes */
452 u32 bytes
= cctl
& PL080_CONTROL_TRANSFER_SIZE_MASK
;
454 switch (cctl
>> PL080_CONTROL_SWIDTH_SHIFT
) {
455 case PL080_WIDTH_8BIT
:
457 case PL080_WIDTH_16BIT
:
460 case PL080_WIDTH_32BIT
:
467 /* The channel should be paused when calling this */
468 static u32
pl08x_getbytes_chan(struct pl08x_dma_chan
*plchan
)
470 struct pl08x_phy_chan
*ch
;
471 struct pl08x_txd
*txd
;
475 spin_lock_irqsave(&plchan
->lock
, flags
);
476 ch
= plchan
->phychan
;
480 * Follow the LLIs to get the number of remaining
481 * bytes in the currently active transaction.
484 u32 clli
= readl(ch
->base
+ PL080_CH_LLI
) & ~PL080_LLI_LM_AHB2
;
486 /* First get the remaining bytes in the active transfer */
487 bytes
= get_bytes_in_cctl(readl(ch
->base
+ PL080_CH_CONTROL
));
490 struct pl08x_lli
*llis_va
= txd
->llis_va
;
491 dma_addr_t llis_bus
= txd
->llis_bus
;
494 BUG_ON(clli
< llis_bus
|| clli
>= llis_bus
+
495 sizeof(struct pl08x_lli
) * MAX_NUM_TSFR_LLIS
);
498 * Locate the next LLI - as this is an array,
499 * it's simple maths to find.
501 index
= (clli
- llis_bus
) / sizeof(struct pl08x_lli
);
503 for (; index
< MAX_NUM_TSFR_LLIS
; index
++) {
504 bytes
+= get_bytes_in_cctl(llis_va
[index
].cctl
);
507 * A LLI pointer of 0 terminates the LLI list
509 if (!llis_va
[index
].lli
)
515 /* Sum up all queued transactions */
516 if (!list_empty(&plchan
->pend_list
)) {
517 struct pl08x_txd
*txdi
;
518 list_for_each_entry(txdi
, &plchan
->pend_list
, node
) {
519 struct pl08x_sg
*dsg
;
520 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
525 spin_unlock_irqrestore(&plchan
->lock
, flags
);
531 * Allocate a physical channel for a virtual channel
533 * Try to locate a physical channel to be used for this transfer. If all
534 * are taken return NULL and the requester will have to cope by using
535 * some fallback PIO mode or retrying later.
537 static struct pl08x_phy_chan
*
538 pl08x_get_phy_channel(struct pl08x_driver_data
*pl08x
,
539 struct pl08x_dma_chan
*virt_chan
)
541 struct pl08x_phy_chan
*ch
= NULL
;
545 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
546 ch
= &pl08x
->phy_chans
[i
];
548 spin_lock_irqsave(&ch
->lock
, flags
);
550 if (!ch
->locked
&& !ch
->serving
) {
551 ch
->serving
= virt_chan
;
553 spin_unlock_irqrestore(&ch
->lock
, flags
);
557 spin_unlock_irqrestore(&ch
->lock
, flags
);
560 if (i
== pl08x
->vd
->channels
) {
561 /* No physical channel available, cope with it */
568 static inline void pl08x_put_phy_channel(struct pl08x_driver_data
*pl08x
,
569 struct pl08x_phy_chan
*ch
)
573 spin_lock_irqsave(&ch
->lock
, flags
);
575 /* Stop the channel and clear its interrupts */
576 pl08x_terminate_phy_chan(pl08x
, ch
);
578 /* Mark it as free */
580 spin_unlock_irqrestore(&ch
->lock
, flags
);
587 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded
)
590 case PL080_WIDTH_8BIT
:
592 case PL080_WIDTH_16BIT
:
594 case PL080_WIDTH_32BIT
:
603 static inline u32
pl08x_cctl_bits(u32 cctl
, u8 srcwidth
, u8 dstwidth
,
608 /* Remove all src, dst and transfer size bits */
609 retbits
&= ~PL080_CONTROL_DWIDTH_MASK
;
610 retbits
&= ~PL080_CONTROL_SWIDTH_MASK
;
611 retbits
&= ~PL080_CONTROL_TRANSFER_SIZE_MASK
;
613 /* Then set the bits according to the parameters */
616 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
619 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
622 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
631 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
634 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
637 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
644 retbits
|= tsize
<< PL080_CONTROL_TRANSFER_SIZE_SHIFT
;
648 struct pl08x_lli_build_data
{
649 struct pl08x_txd
*txd
;
650 struct pl08x_bus_data srcbus
;
651 struct pl08x_bus_data dstbus
;
657 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
658 * victim in case src & dest are not similarly aligned. i.e. If after aligning
659 * masters address with width requirements of transfer (by sending few byte by
660 * byte data), slave is still not aligned, then its width will be reduced to
662 * - prefers the destination bus if both available
663 * - prefers bus with fixed address (i.e. peripheral)
665 static void pl08x_choose_master_bus(struct pl08x_lli_build_data
*bd
,
666 struct pl08x_bus_data
**mbus
, struct pl08x_bus_data
**sbus
, u32 cctl
)
668 if (!(cctl
& PL080_CONTROL_DST_INCR
)) {
671 } else if (!(cctl
& PL080_CONTROL_SRC_INCR
)) {
675 if (bd
->dstbus
.buswidth
>= bd
->srcbus
.buswidth
) {
686 * Fills in one LLI for a certain transfer descriptor and advance the counter
688 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data
*bd
,
689 int num_llis
, int len
, u32 cctl
)
691 struct pl08x_lli
*llis_va
= bd
->txd
->llis_va
;
692 dma_addr_t llis_bus
= bd
->txd
->llis_bus
;
694 BUG_ON(num_llis
>= MAX_NUM_TSFR_LLIS
);
696 llis_va
[num_llis
].cctl
= cctl
;
697 llis_va
[num_llis
].src
= bd
->srcbus
.addr
;
698 llis_va
[num_llis
].dst
= bd
->dstbus
.addr
;
699 llis_va
[num_llis
].lli
= llis_bus
+ (num_llis
+ 1) *
700 sizeof(struct pl08x_lli
);
701 llis_va
[num_llis
].lli
|= bd
->lli_bus
;
703 if (cctl
& PL080_CONTROL_SRC_INCR
)
704 bd
->srcbus
.addr
+= len
;
705 if (cctl
& PL080_CONTROL_DST_INCR
)
706 bd
->dstbus
.addr
+= len
;
708 BUG_ON(bd
->remainder
< len
);
710 bd
->remainder
-= len
;
713 static inline void prep_byte_width_lli(struct pl08x_lli_build_data
*bd
,
714 u32
*cctl
, u32 len
, int num_llis
, size_t *total_bytes
)
716 *cctl
= pl08x_cctl_bits(*cctl
, 1, 1, len
);
717 pl08x_fill_lli_for_desc(bd
, num_llis
, len
, *cctl
);
718 (*total_bytes
) += len
;
722 * This fills in the table of LLIs for the transfer descriptor
723 * Note that we assume we never have to change the burst sizes
726 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data
*pl08x
,
727 struct pl08x_txd
*txd
)
729 struct pl08x_bus_data
*mbus
, *sbus
;
730 struct pl08x_lli_build_data bd
;
732 u32 cctl
, early_bytes
= 0;
733 size_t max_bytes_per_lli
, total_bytes
;
734 struct pl08x_lli
*llis_va
;
735 struct pl08x_sg
*dsg
;
737 txd
->llis_va
= dma_pool_alloc(pl08x
->pool
, GFP_NOWAIT
, &txd
->llis_bus
);
739 dev_err(&pl08x
->adev
->dev
, "%s no memory for llis\n", __func__
);
746 bd
.lli_bus
= (pl08x
->lli_buses
& PL08X_AHB2
) ? PL080_LLI_LM_AHB2
: 0;
749 /* Find maximum width of the source bus */
751 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_SWIDTH_MASK
) >>
752 PL080_CONTROL_SWIDTH_SHIFT
);
754 /* Find maximum width of the destination bus */
756 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_DWIDTH_MASK
) >>
757 PL080_CONTROL_DWIDTH_SHIFT
);
759 list_for_each_entry(dsg
, &txd
->dsg_list
, node
) {
763 bd
.srcbus
.addr
= dsg
->src_addr
;
764 bd
.dstbus
.addr
= dsg
->dst_addr
;
765 bd
.remainder
= dsg
->len
;
766 bd
.srcbus
.buswidth
= bd
.srcbus
.maxwidth
;
767 bd
.dstbus
.buswidth
= bd
.dstbus
.maxwidth
;
769 pl08x_choose_master_bus(&bd
, &mbus
, &sbus
, cctl
);
771 dev_vdbg(&pl08x
->adev
->dev
, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
772 bd
.srcbus
.addr
, cctl
& PL080_CONTROL_SRC_INCR
? "+" : "",
774 bd
.dstbus
.addr
, cctl
& PL080_CONTROL_DST_INCR
? "+" : "",
777 dev_vdbg(&pl08x
->adev
->dev
, "mbus=%s sbus=%s\n",
778 mbus
== &bd
.srcbus
? "src" : "dst",
779 sbus
== &bd
.srcbus
? "src" : "dst");
782 * Zero length is only allowed if all these requirements are
784 * - flow controller is peripheral.
785 * - src.addr is aligned to src.width
786 * - dst.addr is aligned to dst.width
788 * sg_len == 1 should be true, as there can be two cases here:
790 * - Memory addresses are contiguous and are not scattered.
791 * Here, Only one sg will be passed by user driver, with
792 * memory address and zero length. We pass this to controller
793 * and after the transfer it will receive the last burst
794 * request from peripheral and so transfer finishes.
796 * - Memory addresses are scattered and are not contiguous.
797 * Here, Obviously as DMA controller doesn't know when a lli's
798 * transfer gets over, it can't load next lli. So in this
799 * case, there has to be an assumption that only one lli is
800 * supported. Thus, we can't have scattered addresses.
803 u32 fc
= (txd
->ccfg
& PL080_CONFIG_FLOW_CONTROL_MASK
) >>
804 PL080_CONFIG_FLOW_CONTROL_SHIFT
;
805 if (!((fc
>= PL080_FLOW_SRC2DST_DST
) &&
806 (fc
<= PL080_FLOW_SRC2DST_SRC
))) {
807 dev_err(&pl08x
->adev
->dev
, "%s sg len can't be zero",
812 if ((bd
.srcbus
.addr
% bd
.srcbus
.buswidth
) ||
813 (bd
.dstbus
.addr
% bd
.dstbus
.buswidth
)) {
814 dev_err(&pl08x
->adev
->dev
,
815 "%s src & dst address must be aligned to src"
816 " & dst width if peripheral is flow controller",
821 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
822 bd
.dstbus
.buswidth
, 0);
823 pl08x_fill_lli_for_desc(&bd
, num_llis
++, 0, cctl
);
828 * Send byte by byte for following cases
829 * - Less than a bus width available
830 * - until master bus is aligned
832 if (bd
.remainder
< mbus
->buswidth
)
833 early_bytes
= bd
.remainder
;
834 else if ((mbus
->addr
) % (mbus
->buswidth
)) {
835 early_bytes
= mbus
->buswidth
- (mbus
->addr
) %
837 if ((bd
.remainder
- early_bytes
) < mbus
->buswidth
)
838 early_bytes
= bd
.remainder
;
842 dev_vdbg(&pl08x
->adev
->dev
,
843 "%s byte width LLIs (remain 0x%08x)\n",
844 __func__
, bd
.remainder
);
845 prep_byte_width_lli(&bd
, &cctl
, early_bytes
, num_llis
++,
852 * - if slave is not then we must set its width down
854 if (sbus
->addr
% sbus
->buswidth
) {
855 dev_dbg(&pl08x
->adev
->dev
,
856 "%s set down bus width to one byte\n",
863 * Bytes transferred = tsize * src width, not
866 max_bytes_per_lli
= bd
.srcbus
.buswidth
*
867 PL080_CONTROL_TRANSFER_SIZE_MASK
;
868 dev_vdbg(&pl08x
->adev
->dev
,
869 "%s max bytes per lli = %zu\n",
870 __func__
, max_bytes_per_lli
);
873 * Make largest possible LLIs until less than one bus
876 while (bd
.remainder
> (mbus
->buswidth
- 1)) {
877 size_t lli_len
, tsize
, width
;
880 * If enough left try to send max possible,
881 * otherwise try to send the remainder
883 lli_len
= min(bd
.remainder
, max_bytes_per_lli
);
886 * Check against maximum bus alignment:
887 * Calculate actual transfer size in relation to
888 * bus width an get a maximum remainder of the
889 * highest bus width - 1
891 width
= max(mbus
->buswidth
, sbus
->buswidth
);
892 lli_len
= (lli_len
/ width
) * width
;
893 tsize
= lli_len
/ bd
.srcbus
.buswidth
;
895 dev_vdbg(&pl08x
->adev
->dev
,
896 "%s fill lli with single lli chunk of "
897 "size 0x%08zx (remainder 0x%08zx)\n",
898 __func__
, lli_len
, bd
.remainder
);
900 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
901 bd
.dstbus
.buswidth
, tsize
);
902 pl08x_fill_lli_for_desc(&bd
, num_llis
++,
904 total_bytes
+= lli_len
;
911 dev_vdbg(&pl08x
->adev
->dev
,
912 "%s align with boundary, send odd bytes (remain %zu)\n",
913 __func__
, bd
.remainder
);
914 prep_byte_width_lli(&bd
, &cctl
, bd
.remainder
,
915 num_llis
++, &total_bytes
);
919 if (total_bytes
!= dsg
->len
) {
920 dev_err(&pl08x
->adev
->dev
,
921 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
922 __func__
, total_bytes
, dsg
->len
);
926 if (num_llis
>= MAX_NUM_TSFR_LLIS
) {
927 dev_err(&pl08x
->adev
->dev
,
928 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
929 __func__
, (u32
) MAX_NUM_TSFR_LLIS
);
934 llis_va
= txd
->llis_va
;
935 /* The final LLI terminates the LLI. */
936 llis_va
[num_llis
- 1].lli
= 0;
937 /* The final LLI element shall also fire an interrupt. */
938 llis_va
[num_llis
- 1].cctl
|= PL080_CONTROL_TC_IRQ_EN
;
944 dev_vdbg(&pl08x
->adev
->dev
,
945 "%-3s %-9s %-10s %-10s %-10s %s\n",
946 "lli", "", "csrc", "cdst", "clli", "cctl");
947 for (i
= 0; i
< num_llis
; i
++) {
948 dev_vdbg(&pl08x
->adev
->dev
,
949 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
950 i
, &llis_va
[i
], llis_va
[i
].src
,
951 llis_va
[i
].dst
, llis_va
[i
].lli
, llis_va
[i
].cctl
960 /* You should call this with the struct pl08x lock held */
961 static void pl08x_free_txd(struct pl08x_driver_data
*pl08x
,
962 struct pl08x_txd
*txd
)
964 struct pl08x_sg
*dsg
, *_dsg
;
968 dma_pool_free(pl08x
->pool
, txd
->llis_va
, txd
->llis_bus
);
972 list_for_each_entry_safe(dsg
, _dsg
, &txd
->dsg_list
, node
) {
973 list_del(&dsg
->node
);
980 static void pl08x_free_txd_list(struct pl08x_driver_data
*pl08x
,
981 struct pl08x_dma_chan
*plchan
)
983 struct pl08x_txd
*txdi
= NULL
;
984 struct pl08x_txd
*next
;
986 if (!list_empty(&plchan
->pend_list
)) {
987 list_for_each_entry_safe(txdi
,
988 next
, &plchan
->pend_list
, node
) {
989 list_del(&txdi
->node
);
990 pl08x_free_txd(pl08x
, txdi
);
998 static int pl08x_alloc_chan_resources(struct dma_chan
*chan
)
1003 static void pl08x_free_chan_resources(struct dma_chan
*chan
)
1008 * This should be called with the channel plchan->lock held
1010 static int prep_phy_channel(struct pl08x_dma_chan
*plchan
,
1011 struct pl08x_txd
*txd
)
1013 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1014 struct pl08x_phy_chan
*ch
;
1017 /* Check if we already have a channel */
1018 if (plchan
->phychan
) {
1019 ch
= plchan
->phychan
;
1023 ch
= pl08x_get_phy_channel(pl08x
, plchan
);
1025 /* No physical channel available, cope with it */
1026 dev_dbg(&pl08x
->adev
->dev
, "no physical channel available for xfer on %s\n", plchan
->name
);
1031 * OK we have a physical channel: for memcpy() this is all we
1032 * need, but for slaves the physical signals may be muxed!
1033 * Can the platform allow us to use this channel?
1035 if (plchan
->slave
) {
1036 ret
= pl08x_request_mux(plchan
, ch
);
1038 dev_dbg(&pl08x
->adev
->dev
,
1039 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1040 ch
->id
, plchan
->name
);
1041 /* Release physical channel & return */
1042 pl08x_put_phy_channel(pl08x
, ch
);
1047 plchan
->phychan
= ch
;
1048 dev_dbg(&pl08x
->adev
->dev
, "allocated physical channel %d and signal %d for xfer on %s\n",
1054 /* Assign the flow control signal to this channel */
1055 if (txd
->direction
== DMA_MEM_TO_DEV
)
1056 txd
->ccfg
|= ch
->signal
<< PL080_CONFIG_DST_SEL_SHIFT
;
1057 else if (txd
->direction
== DMA_DEV_TO_MEM
)
1058 txd
->ccfg
|= ch
->signal
<< PL080_CONFIG_SRC_SEL_SHIFT
;
1060 plchan
->phychan_hold
++;
1065 static void release_phy_channel(struct pl08x_dma_chan
*plchan
)
1067 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1069 pl08x_release_mux(plchan
);
1070 pl08x_put_phy_channel(pl08x
, plchan
->phychan
);
1071 plchan
->phychan
= NULL
;
1074 static dma_cookie_t
pl08x_tx_submit(struct dma_async_tx_descriptor
*tx
)
1076 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(tx
->chan
);
1077 struct pl08x_txd
*txd
= to_pl08x_txd(tx
);
1078 unsigned long flags
;
1079 dma_cookie_t cookie
;
1081 spin_lock_irqsave(&plchan
->lock
, flags
);
1082 cookie
= dma_cookie_assign(tx
);
1084 /* Put this onto the pending list */
1085 list_add_tail(&txd
->node
, &plchan
->pend_list
);
1088 * If there was no physical channel available for this memcpy,
1089 * stack the request up and indicate that the channel is waiting
1090 * for a free physical channel.
1092 if (!plchan
->slave
&& !plchan
->phychan
) {
1093 /* Do this memcpy whenever there is a channel ready */
1094 plchan
->state
= PL08X_CHAN_WAITING
;
1095 plchan
->waiting
= txd
;
1097 plchan
->phychan_hold
--;
1100 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1105 static struct dma_async_tx_descriptor
*pl08x_prep_dma_interrupt(
1106 struct dma_chan
*chan
, unsigned long flags
)
1108 struct dma_async_tx_descriptor
*retval
= NULL
;
1114 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1115 * If slaves are relying on interrupts to signal completion this function
1116 * must not be called with interrupts disabled.
1118 static enum dma_status
pl08x_dma_tx_status(struct dma_chan
*chan
,
1119 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
1121 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1122 enum dma_status ret
;
1124 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1125 if (ret
== DMA_SUCCESS
)
1129 * This cookie not complete yet
1130 * Get number of bytes left in the active transactions and queue
1132 dma_set_residue(txstate
, pl08x_getbytes_chan(plchan
));
1134 if (plchan
->state
== PL08X_CHAN_PAUSED
)
1137 /* Whether waiting or running, we're in progress */
1138 return DMA_IN_PROGRESS
;
1141 /* PrimeCell DMA extension */
1142 struct burst_table
{
1147 static const struct burst_table burst_sizes
[] = {
1150 .reg
= PL080_BSIZE_256
,
1154 .reg
= PL080_BSIZE_128
,
1158 .reg
= PL080_BSIZE_64
,
1162 .reg
= PL080_BSIZE_32
,
1166 .reg
= PL080_BSIZE_16
,
1170 .reg
= PL080_BSIZE_8
,
1174 .reg
= PL080_BSIZE_4
,
1178 .reg
= PL080_BSIZE_1
,
1183 * Given the source and destination available bus masks, select which
1184 * will be routed to each port. We try to have source and destination
1185 * on separate ports, but always respect the allowable settings.
1187 static u32
pl08x_select_bus(u8 src
, u8 dst
)
1191 if (!(dst
& PL08X_AHB1
) || ((dst
& PL08X_AHB2
) && (src
& PL08X_AHB1
)))
1192 cctl
|= PL080_CONTROL_DST_AHB2
;
1193 if (!(src
& PL08X_AHB1
) || ((src
& PL08X_AHB2
) && !(dst
& PL08X_AHB2
)))
1194 cctl
|= PL080_CONTROL_SRC_AHB2
;
1199 static u32
pl08x_cctl(u32 cctl
)
1201 cctl
&= ~(PL080_CONTROL_SRC_AHB2
| PL080_CONTROL_DST_AHB2
|
1202 PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
|
1203 PL080_CONTROL_PROT_MASK
);
1205 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1206 return cctl
| PL080_CONTROL_PROT_SYS
;
1209 static u32
pl08x_width(enum dma_slave_buswidth width
)
1212 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
1213 return PL080_WIDTH_8BIT
;
1214 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
1215 return PL080_WIDTH_16BIT
;
1216 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
1217 return PL080_WIDTH_32BIT
;
1223 static u32
pl08x_burst(u32 maxburst
)
1227 for (i
= 0; i
< ARRAY_SIZE(burst_sizes
); i
++)
1228 if (burst_sizes
[i
].burstwords
<= maxburst
)
1231 return burst_sizes
[i
].reg
;
1234 static u32
pl08x_get_cctl(struct pl08x_dma_chan
*plchan
,
1235 enum dma_slave_buswidth addr_width
, u32 maxburst
)
1237 u32 width
, burst
, cctl
= 0;
1239 width
= pl08x_width(addr_width
);
1243 cctl
|= width
<< PL080_CONTROL_SWIDTH_SHIFT
;
1244 cctl
|= width
<< PL080_CONTROL_DWIDTH_SHIFT
;
1247 * If this channel will only request single transfers, set this
1248 * down to ONE element. Also select one element if no maxburst
1251 if (plchan
->cd
->single
)
1254 burst
= pl08x_burst(maxburst
);
1255 cctl
|= burst
<< PL080_CONTROL_SB_SIZE_SHIFT
;
1256 cctl
|= burst
<< PL080_CONTROL_DB_SIZE_SHIFT
;
1258 return pl08x_cctl(cctl
);
1261 static int dma_set_runtime_config(struct dma_chan
*chan
,
1262 struct dma_slave_config
*config
)
1264 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1269 /* Reject definitely invalid configurations */
1270 if (config
->src_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
||
1271 config
->dst_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
)
1274 plchan
->cfg
= *config
;
1280 * Slave transactions callback to the slave device to allow
1281 * synchronization of slave DMA signals with the DMAC enable
1283 static void pl08x_issue_pending(struct dma_chan
*chan
)
1285 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1286 unsigned long flags
;
1288 spin_lock_irqsave(&plchan
->lock
, flags
);
1289 /* Something is already active, or we're waiting for a channel... */
1290 if (plchan
->at
|| plchan
->state
== PL08X_CHAN_WAITING
) {
1291 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1295 /* Take the first element in the queue and execute it */
1296 if (!list_empty(&plchan
->pend_list
)) {
1297 struct pl08x_txd
*next
;
1299 next
= list_first_entry(&plchan
->pend_list
,
1302 list_del(&next
->node
);
1303 plchan
->state
= PL08X_CHAN_RUNNING
;
1305 pl08x_start_txd(plchan
, next
);
1308 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1311 static int pl08x_prep_channel_resources(struct pl08x_dma_chan
*plchan
,
1312 struct pl08x_txd
*txd
)
1314 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1315 unsigned long flags
;
1318 num_llis
= pl08x_fill_llis_for_desc(pl08x
, txd
);
1320 spin_lock_irqsave(&plchan
->lock
, flags
);
1321 pl08x_free_txd(pl08x
, txd
);
1322 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1326 spin_lock_irqsave(&plchan
->lock
, flags
);
1329 * See if we already have a physical channel allocated,
1330 * else this is the time to try to get one.
1332 ret
= prep_phy_channel(plchan
, txd
);
1335 * No physical channel was available.
1337 * memcpy transfers can be sorted out at submission time.
1339 * Slave transfers may have been denied due to platform
1340 * channel muxing restrictions. Since there is no guarantee
1341 * that this will ever be resolved, and the signal must be
1342 * acquired AFTER acquiring the physical channel, we will let
1343 * them be NACK:ed with -EBUSY here. The drivers can retry
1344 * the prep() call if they are eager on doing this using DMA.
1346 if (plchan
->slave
) {
1347 pl08x_free_txd_list(pl08x
, plchan
);
1348 pl08x_free_txd(pl08x
, txd
);
1349 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1354 * Else we're all set, paused and ready to roll, status
1355 * will switch to PL08X_CHAN_RUNNING when we call
1356 * issue_pending(). If there is something running on the
1357 * channel already we don't change its state.
1359 if (plchan
->state
== PL08X_CHAN_IDLE
)
1360 plchan
->state
= PL08X_CHAN_PAUSED
;
1362 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1367 static struct pl08x_txd
*pl08x_get_txd(struct pl08x_dma_chan
*plchan
,
1368 unsigned long flags
)
1370 struct pl08x_txd
*txd
= kzalloc(sizeof(*txd
), GFP_NOWAIT
);
1373 dma_async_tx_descriptor_init(&txd
->tx
, &plchan
->chan
);
1374 txd
->tx
.flags
= flags
;
1375 txd
->tx
.tx_submit
= pl08x_tx_submit
;
1376 INIT_LIST_HEAD(&txd
->node
);
1377 INIT_LIST_HEAD(&txd
->dsg_list
);
1379 /* Always enable error and terminal interrupts */
1380 txd
->ccfg
= PL080_CONFIG_ERR_IRQ_MASK
|
1381 PL080_CONFIG_TC_IRQ_MASK
;
1387 * Initialize a descriptor to be used by memcpy submit
1389 static struct dma_async_tx_descriptor
*pl08x_prep_dma_memcpy(
1390 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1391 size_t len
, unsigned long flags
)
1393 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1394 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1395 struct pl08x_txd
*txd
;
1396 struct pl08x_sg
*dsg
;
1399 txd
= pl08x_get_txd(plchan
, flags
);
1401 dev_err(&pl08x
->adev
->dev
,
1402 "%s no memory for descriptor\n", __func__
);
1406 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1408 pl08x_free_txd(pl08x
, txd
);
1409 dev_err(&pl08x
->adev
->dev
, "%s no memory for pl080 sg\n",
1413 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1415 txd
->direction
= DMA_MEM_TO_MEM
;
1416 dsg
->src_addr
= src
;
1417 dsg
->dst_addr
= dest
;
1420 /* Set platform data for m2m */
1421 txd
->ccfg
|= PL080_FLOW_MEM2MEM
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1422 txd
->cctl
= pl08x
->pd
->memcpy_channel
.cctl_memcpy
&
1423 ~(PL080_CONTROL_DST_AHB2
| PL080_CONTROL_SRC_AHB2
);
1425 /* Both to be incremented or the code will break */
1426 txd
->cctl
|= PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
;
1428 if (pl08x
->vd
->dualmaster
)
1429 txd
->cctl
|= pl08x_select_bus(pl08x
->mem_buses
,
1432 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1439 static struct dma_async_tx_descriptor
*pl08x_prep_slave_sg(
1440 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1441 unsigned int sg_len
, enum dma_transfer_direction direction
,
1442 unsigned long flags
, void *context
)
1444 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1445 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1446 struct pl08x_txd
*txd
;
1447 struct pl08x_sg
*dsg
;
1448 struct scatterlist
*sg
;
1449 enum dma_slave_buswidth addr_width
;
1450 dma_addr_t slave_addr
;
1452 u8 src_buses
, dst_buses
;
1455 dev_dbg(&pl08x
->adev
->dev
, "%s prepare transaction of %d bytes from %s\n",
1456 __func__
, sg_dma_len(sgl
), plchan
->name
);
1458 txd
= pl08x_get_txd(plchan
, flags
);
1460 dev_err(&pl08x
->adev
->dev
, "%s no txd\n", __func__
);
1465 * Set up addresses, the PrimeCell configured address
1466 * will take precedence since this may configure the
1467 * channel target address dynamically at runtime.
1469 txd
->direction
= direction
;
1471 if (direction
== DMA_MEM_TO_DEV
) {
1472 cctl
= PL080_CONTROL_SRC_INCR
;
1473 slave_addr
= plchan
->cfg
.dst_addr
;
1474 addr_width
= plchan
->cfg
.dst_addr_width
;
1475 maxburst
= plchan
->cfg
.dst_maxburst
;
1476 src_buses
= pl08x
->mem_buses
;
1477 dst_buses
= plchan
->cd
->periph_buses
;
1478 } else if (direction
== DMA_DEV_TO_MEM
) {
1479 cctl
= PL080_CONTROL_DST_INCR
;
1480 slave_addr
= plchan
->cfg
.src_addr
;
1481 addr_width
= plchan
->cfg
.src_addr_width
;
1482 maxburst
= plchan
->cfg
.src_maxburst
;
1483 src_buses
= plchan
->cd
->periph_buses
;
1484 dst_buses
= pl08x
->mem_buses
;
1486 pl08x_free_txd(pl08x
, txd
);
1487 dev_err(&pl08x
->adev
->dev
,
1488 "%s direction unsupported\n", __func__
);
1492 cctl
|= pl08x_get_cctl(plchan
, addr_width
, maxburst
);
1494 pl08x_free_txd(pl08x
, txd
);
1495 dev_err(&pl08x
->adev
->dev
,
1496 "DMA slave configuration botched?\n");
1500 txd
->cctl
= cctl
| pl08x_select_bus(src_buses
, dst_buses
);
1502 if (plchan
->cfg
.device_fc
)
1503 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER_PER
:
1504 PL080_FLOW_PER2MEM_PER
;
1506 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER
:
1509 txd
->ccfg
|= tmp
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1511 for_each_sg(sgl
, sg
, sg_len
, tmp
) {
1512 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1514 pl08x_free_txd(pl08x
, txd
);
1515 dev_err(&pl08x
->adev
->dev
, "%s no mem for pl080 sg\n",
1519 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1521 dsg
->len
= sg_dma_len(sg
);
1522 if (direction
== DMA_MEM_TO_DEV
) {
1523 dsg
->src_addr
= sg_dma_address(sg
);
1524 dsg
->dst_addr
= slave_addr
;
1526 dsg
->src_addr
= slave_addr
;
1527 dsg
->dst_addr
= sg_dma_address(sg
);
1531 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1538 static int pl08x_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1541 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1542 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1543 unsigned long flags
;
1546 /* Controls applicable to inactive channels */
1547 if (cmd
== DMA_SLAVE_CONFIG
) {
1548 return dma_set_runtime_config(chan
,
1549 (struct dma_slave_config
*)arg
);
1553 * Anything succeeds on channels with no physical allocation and
1554 * no queued transfers.
1556 spin_lock_irqsave(&plchan
->lock
, flags
);
1557 if (!plchan
->phychan
&& !plchan
->at
) {
1558 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1563 case DMA_TERMINATE_ALL
:
1564 plchan
->state
= PL08X_CHAN_IDLE
;
1566 if (plchan
->phychan
) {
1567 pl08x_terminate_phy_chan(pl08x
, plchan
->phychan
);
1570 * Mark physical channel as free and free any slave
1573 release_phy_channel(plchan
);
1574 plchan
->phychan_hold
= 0;
1576 /* Dequeue jobs and free LLIs */
1578 pl08x_free_txd(pl08x
, plchan
->at
);
1581 /* Dequeue jobs not yet fired as well */
1582 pl08x_free_txd_list(pl08x
, plchan
);
1585 pl08x_pause_phy_chan(plchan
->phychan
);
1586 plchan
->state
= PL08X_CHAN_PAUSED
;
1589 pl08x_resume_phy_chan(plchan
->phychan
);
1590 plchan
->state
= PL08X_CHAN_RUNNING
;
1593 /* Unknown command */
1598 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1603 bool pl08x_filter_id(struct dma_chan
*chan
, void *chan_id
)
1605 struct pl08x_dma_chan
*plchan
;
1606 char *name
= chan_id
;
1608 /* Reject channels for devices not bound to this driver */
1609 if (chan
->device
->dev
->driver
!= &pl08x_amba_driver
.drv
)
1612 plchan
= to_pl08x_chan(chan
);
1614 /* Check that the channel is not taken! */
1615 if (!strcmp(plchan
->name
, name
))
1622 * Just check that the device is there and active
1623 * TODO: turn this bit on/off depending on the number of physical channels
1624 * actually used, if it is zero... well shut it off. That will save some
1625 * power. Cut the clock at the same time.
1627 static void pl08x_ensure_on(struct pl08x_driver_data
*pl08x
)
1629 /* The Nomadik variant does not have the config register */
1630 if (pl08x
->vd
->nomadik
)
1632 writel(PL080_CONFIG_ENABLE
, pl08x
->base
+ PL080_CONFIG
);
1635 static void pl08x_unmap_buffers(struct pl08x_txd
*txd
)
1637 struct device
*dev
= txd
->tx
.chan
->device
->dev
;
1638 struct pl08x_sg
*dsg
;
1640 if (!(txd
->tx
.flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
1641 if (txd
->tx
.flags
& DMA_COMPL_SRC_UNMAP_SINGLE
)
1642 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1643 dma_unmap_single(dev
, dsg
->src_addr
, dsg
->len
,
1646 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1647 dma_unmap_page(dev
, dsg
->src_addr
, dsg
->len
,
1651 if (!(txd
->tx
.flags
& DMA_COMPL_SKIP_DEST_UNMAP
)) {
1652 if (txd
->tx
.flags
& DMA_COMPL_DEST_UNMAP_SINGLE
)
1653 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1654 dma_unmap_single(dev
, dsg
->dst_addr
, dsg
->len
,
1657 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1658 dma_unmap_page(dev
, dsg
->dst_addr
, dsg
->len
,
1663 static void pl08x_tasklet(unsigned long data
)
1665 struct pl08x_dma_chan
*plchan
= (struct pl08x_dma_chan
*) data
;
1666 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1667 struct pl08x_txd
*txd
;
1668 unsigned long flags
;
1670 spin_lock_irqsave(&plchan
->lock
, flags
);
1676 /* Update last completed */
1677 dma_cookie_complete(&txd
->tx
);
1680 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1681 if (!list_empty(&plchan
->pend_list
)) {
1682 struct pl08x_txd
*next
;
1684 next
= list_first_entry(&plchan
->pend_list
,
1687 list_del(&next
->node
);
1689 pl08x_start_txd(plchan
, next
);
1690 } else if (plchan
->phychan_hold
) {
1692 * This channel is still in use - we have a new txd being
1693 * prepared and will soon be queued. Don't give up the
1697 struct pl08x_dma_chan
*waiting
= NULL
;
1700 * No more jobs, so free up the physical channel
1701 * Free any allocated signal on slave transfers too
1703 release_phy_channel(plchan
);
1704 plchan
->state
= PL08X_CHAN_IDLE
;
1707 * And NOW before anyone else can grab that free:d up
1708 * physical channel, see if there is some memcpy pending
1709 * that seriously needs to start because of being stacked
1710 * up while we were choking the physical channels with data.
1712 list_for_each_entry(waiting
, &pl08x
->memcpy
.channels
,
1714 if (waiting
->state
== PL08X_CHAN_WAITING
&&
1715 waiting
->waiting
!= NULL
) {
1718 /* This should REALLY not fail now */
1719 ret
= prep_phy_channel(waiting
,
1722 waiting
->phychan_hold
--;
1723 waiting
->state
= PL08X_CHAN_RUNNING
;
1724 waiting
->waiting
= NULL
;
1725 pl08x_issue_pending(&waiting
->chan
);
1731 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1734 dma_async_tx_callback callback
= txd
->tx
.callback
;
1735 void *callback_param
= txd
->tx
.callback_param
;
1737 /* Don't try to unmap buffers on slave channels */
1739 pl08x_unmap_buffers(txd
);
1741 /* Free the descriptor */
1742 spin_lock_irqsave(&plchan
->lock
, flags
);
1743 pl08x_free_txd(pl08x
, txd
);
1744 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1746 /* Callback to signal completion */
1748 callback(callback_param
);
1752 static irqreturn_t
pl08x_irq(int irq
, void *dev
)
1754 struct pl08x_driver_data
*pl08x
= dev
;
1755 u32 mask
= 0, err
, tc
, i
;
1757 /* check & clear - ERR & TC interrupts */
1758 err
= readl(pl08x
->base
+ PL080_ERR_STATUS
);
1760 dev_err(&pl08x
->adev
->dev
, "%s error interrupt, register value 0x%08x\n",
1762 writel(err
, pl08x
->base
+ PL080_ERR_CLEAR
);
1764 tc
= readl(pl08x
->base
+ PL080_TC_STATUS
);
1766 writel(tc
, pl08x
->base
+ PL080_TC_CLEAR
);
1771 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1772 if (((1 << i
) & err
) || ((1 << i
) & tc
)) {
1773 /* Locate physical channel */
1774 struct pl08x_phy_chan
*phychan
= &pl08x
->phy_chans
[i
];
1775 struct pl08x_dma_chan
*plchan
= phychan
->serving
;
1778 dev_err(&pl08x
->adev
->dev
,
1779 "%s Error TC interrupt on unused channel: 0x%08x\n",
1784 /* Schedule tasklet on this channel */
1785 tasklet_schedule(&plchan
->tasklet
);
1790 return mask
? IRQ_HANDLED
: IRQ_NONE
;
1793 static void pl08x_dma_slave_init(struct pl08x_dma_chan
*chan
)
1796 chan
->name
= chan
->cd
->bus_id
;
1797 chan
->cfg
.src_addr
= chan
->cd
->addr
;
1798 chan
->cfg
.dst_addr
= chan
->cd
->addr
;
1802 * Initialise the DMAC memcpy/slave channels.
1803 * Make a local wrapper to hold required data
1805 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data
*pl08x
,
1806 struct dma_device
*dmadev
, unsigned int channels
, bool slave
)
1808 struct pl08x_dma_chan
*chan
;
1811 INIT_LIST_HEAD(&dmadev
->channels
);
1814 * Register as many many memcpy as we have physical channels,
1815 * we won't always be able to use all but the code will have
1816 * to cope with that situation.
1818 for (i
= 0; i
< channels
; i
++) {
1819 chan
= kzalloc(sizeof(*chan
), GFP_KERNEL
);
1821 dev_err(&pl08x
->adev
->dev
,
1822 "%s no memory for channel\n", __func__
);
1827 chan
->state
= PL08X_CHAN_IDLE
;
1830 chan
->cd
= &pl08x
->pd
->slave_channels
[i
];
1831 pl08x_dma_slave_init(chan
);
1833 chan
->cd
= &pl08x
->pd
->memcpy_channel
;
1834 chan
->name
= kasprintf(GFP_KERNEL
, "memcpy%d", i
);
1840 dev_dbg(&pl08x
->adev
->dev
,
1841 "initialize virtual channel \"%s\"\n",
1844 chan
->chan
.device
= dmadev
;
1845 dma_cookie_init(&chan
->chan
);
1847 spin_lock_init(&chan
->lock
);
1848 INIT_LIST_HEAD(&chan
->pend_list
);
1849 tasklet_init(&chan
->tasklet
, pl08x_tasklet
,
1850 (unsigned long) chan
);
1852 list_add_tail(&chan
->chan
.device_node
, &dmadev
->channels
);
1854 dev_info(&pl08x
->adev
->dev
, "initialized %d virtual %s channels\n",
1855 i
, slave
? "slave" : "memcpy");
1859 static void pl08x_free_virtual_channels(struct dma_device
*dmadev
)
1861 struct pl08x_dma_chan
*chan
= NULL
;
1862 struct pl08x_dma_chan
*next
;
1864 list_for_each_entry_safe(chan
,
1865 next
, &dmadev
->channels
, chan
.device_node
) {
1866 list_del(&chan
->chan
.device_node
);
1871 #ifdef CONFIG_DEBUG_FS
1872 static const char *pl08x_state_str(enum pl08x_dma_chan_state state
)
1875 case PL08X_CHAN_IDLE
:
1877 case PL08X_CHAN_RUNNING
:
1879 case PL08X_CHAN_PAUSED
:
1881 case PL08X_CHAN_WAITING
:
1886 return "UNKNOWN STATE";
1889 static int pl08x_debugfs_show(struct seq_file
*s
, void *data
)
1891 struct pl08x_driver_data
*pl08x
= s
->private;
1892 struct pl08x_dma_chan
*chan
;
1893 struct pl08x_phy_chan
*ch
;
1894 unsigned long flags
;
1897 seq_printf(s
, "PL08x physical channels:\n");
1898 seq_printf(s
, "CHANNEL:\tUSER:\n");
1899 seq_printf(s
, "--------\t-----\n");
1900 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1901 struct pl08x_dma_chan
*virt_chan
;
1903 ch
= &pl08x
->phy_chans
[i
];
1905 spin_lock_irqsave(&ch
->lock
, flags
);
1906 virt_chan
= ch
->serving
;
1908 seq_printf(s
, "%d\t\t%s%s\n",
1910 virt_chan
? virt_chan
->name
: "(none)",
1911 ch
->locked
? " LOCKED" : "");
1913 spin_unlock_irqrestore(&ch
->lock
, flags
);
1916 seq_printf(s
, "\nPL08x virtual memcpy channels:\n");
1917 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1918 seq_printf(s
, "--------\t------\n");
1919 list_for_each_entry(chan
, &pl08x
->memcpy
.channels
, chan
.device_node
) {
1920 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1921 pl08x_state_str(chan
->state
));
1924 seq_printf(s
, "\nPL08x virtual slave channels:\n");
1925 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1926 seq_printf(s
, "--------\t------\n");
1927 list_for_each_entry(chan
, &pl08x
->slave
.channels
, chan
.device_node
) {
1928 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1929 pl08x_state_str(chan
->state
));
1935 static int pl08x_debugfs_open(struct inode
*inode
, struct file
*file
)
1937 return single_open(file
, pl08x_debugfs_show
, inode
->i_private
);
1940 static const struct file_operations pl08x_debugfs_operations
= {
1941 .open
= pl08x_debugfs_open
,
1943 .llseek
= seq_lseek
,
1944 .release
= single_release
,
1947 static void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1949 /* Expose a simple debugfs interface to view all clocks */
1950 (void) debugfs_create_file(dev_name(&pl08x
->adev
->dev
),
1951 S_IFREG
| S_IRUGO
, NULL
, pl08x
,
1952 &pl08x_debugfs_operations
);
1956 static inline void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1961 static int pl08x_probe(struct amba_device
*adev
, const struct amba_id
*id
)
1963 struct pl08x_driver_data
*pl08x
;
1964 const struct vendor_data
*vd
= id
->data
;
1968 ret
= amba_request_regions(adev
, NULL
);
1972 /* Create the driver state holder */
1973 pl08x
= kzalloc(sizeof(*pl08x
), GFP_KERNEL
);
1979 /* Initialize memcpy engine */
1980 dma_cap_set(DMA_MEMCPY
, pl08x
->memcpy
.cap_mask
);
1981 pl08x
->memcpy
.dev
= &adev
->dev
;
1982 pl08x
->memcpy
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1983 pl08x
->memcpy
.device_free_chan_resources
= pl08x_free_chan_resources
;
1984 pl08x
->memcpy
.device_prep_dma_memcpy
= pl08x_prep_dma_memcpy
;
1985 pl08x
->memcpy
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1986 pl08x
->memcpy
.device_tx_status
= pl08x_dma_tx_status
;
1987 pl08x
->memcpy
.device_issue_pending
= pl08x_issue_pending
;
1988 pl08x
->memcpy
.device_control
= pl08x_control
;
1990 /* Initialize slave engine */
1991 dma_cap_set(DMA_SLAVE
, pl08x
->slave
.cap_mask
);
1992 pl08x
->slave
.dev
= &adev
->dev
;
1993 pl08x
->slave
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1994 pl08x
->slave
.device_free_chan_resources
= pl08x_free_chan_resources
;
1995 pl08x
->slave
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1996 pl08x
->slave
.device_tx_status
= pl08x_dma_tx_status
;
1997 pl08x
->slave
.device_issue_pending
= pl08x_issue_pending
;
1998 pl08x
->slave
.device_prep_slave_sg
= pl08x_prep_slave_sg
;
1999 pl08x
->slave
.device_control
= pl08x_control
;
2001 /* Get the platform data */
2002 pl08x
->pd
= dev_get_platdata(&adev
->dev
);
2004 dev_err(&adev
->dev
, "no platform data supplied\n");
2005 goto out_no_platdata
;
2008 /* Assign useful pointers to the driver state */
2012 /* By default, AHB1 only. If dualmaster, from platform */
2013 pl08x
->lli_buses
= PL08X_AHB1
;
2014 pl08x
->mem_buses
= PL08X_AHB1
;
2015 if (pl08x
->vd
->dualmaster
) {
2016 pl08x
->lli_buses
= pl08x
->pd
->lli_buses
;
2017 pl08x
->mem_buses
= pl08x
->pd
->mem_buses
;
2020 /* A DMA memory pool for LLIs, align on 1-byte boundary */
2021 pl08x
->pool
= dma_pool_create(DRIVER_NAME
, &pl08x
->adev
->dev
,
2022 PL08X_LLI_TSFR_SIZE
, PL08X_ALIGN
, 0);
2025 goto out_no_lli_pool
;
2028 pl08x
->base
= ioremap(adev
->res
.start
, resource_size(&adev
->res
));
2031 goto out_no_ioremap
;
2034 /* Turn on the PL08x */
2035 pl08x_ensure_on(pl08x
);
2037 /* Attach the interrupt handler */
2038 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
2039 writel(0x000000FF, pl08x
->base
+ PL080_TC_CLEAR
);
2041 ret
= request_irq(adev
->irq
[0], pl08x_irq
, IRQF_DISABLED
,
2042 DRIVER_NAME
, pl08x
);
2044 dev_err(&adev
->dev
, "%s failed to request interrupt %d\n",
2045 __func__
, adev
->irq
[0]);
2049 /* Initialize physical channels */
2050 pl08x
->phy_chans
= kzalloc((vd
->channels
* sizeof(*pl08x
->phy_chans
)),
2052 if (!pl08x
->phy_chans
) {
2053 dev_err(&adev
->dev
, "%s failed to allocate "
2054 "physical channel holders\n",
2056 goto out_no_phychans
;
2059 for (i
= 0; i
< vd
->channels
; i
++) {
2060 struct pl08x_phy_chan
*ch
= &pl08x
->phy_chans
[i
];
2063 ch
->base
= pl08x
->base
+ PL080_Cx_BASE(i
);
2064 spin_lock_init(&ch
->lock
);
2068 * Nomadik variants can have channels that are locked
2069 * down for the secure world only. Lock up these channels
2070 * by perpetually serving a dummy virtual channel.
2075 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
2076 if (val
& (PL080N_CONFIG_ITPROT
| PL080N_CONFIG_SECPROT
)) {
2077 dev_info(&adev
->dev
, "physical channel %d reserved for secure access only\n", i
);
2082 dev_dbg(&adev
->dev
, "physical channel %d is %s\n",
2083 i
, pl08x_phy_channel_busy(ch
) ? "BUSY" : "FREE");
2086 /* Register as many memcpy channels as there are physical channels */
2087 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->memcpy
,
2088 pl08x
->vd
->channels
, false);
2090 dev_warn(&pl08x
->adev
->dev
,
2091 "%s failed to enumerate memcpy channels - %d\n",
2095 pl08x
->memcpy
.chancnt
= ret
;
2097 /* Register slave channels */
2098 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->slave
,
2099 pl08x
->pd
->num_slave_channels
, true);
2101 dev_warn(&pl08x
->adev
->dev
,
2102 "%s failed to enumerate slave channels - %d\n",
2106 pl08x
->slave
.chancnt
= ret
;
2108 ret
= dma_async_device_register(&pl08x
->memcpy
);
2110 dev_warn(&pl08x
->adev
->dev
,
2111 "%s failed to register memcpy as an async device - %d\n",
2113 goto out_no_memcpy_reg
;
2116 ret
= dma_async_device_register(&pl08x
->slave
);
2118 dev_warn(&pl08x
->adev
->dev
,
2119 "%s failed to register slave as an async device - %d\n",
2121 goto out_no_slave_reg
;
2124 amba_set_drvdata(adev
, pl08x
);
2125 init_pl08x_debugfs(pl08x
);
2126 dev_info(&pl08x
->adev
->dev
, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2127 amba_part(adev
), amba_rev(adev
),
2128 (unsigned long long)adev
->res
.start
, adev
->irq
[0]);
2133 dma_async_device_unregister(&pl08x
->memcpy
);
2135 pl08x_free_virtual_channels(&pl08x
->slave
);
2137 pl08x_free_virtual_channels(&pl08x
->memcpy
);
2139 kfree(pl08x
->phy_chans
);
2141 free_irq(adev
->irq
[0], pl08x
);
2143 iounmap(pl08x
->base
);
2145 dma_pool_destroy(pl08x
->pool
);
2150 amba_release_regions(adev
);
2154 /* PL080 has 8 channels and the PL080 have just 2 */
2155 static struct vendor_data vendor_pl080
= {
2160 static struct vendor_data vendor_nomadik
= {
2166 static struct vendor_data vendor_pl081
= {
2168 .dualmaster
= false,
2171 static struct amba_id pl08x_ids
[] = {
2176 .data
= &vendor_pl080
,
2182 .data
= &vendor_pl081
,
2184 /* Nomadik 8815 PL080 variant */
2188 .data
= &vendor_nomadik
,
2193 MODULE_DEVICE_TABLE(amba
, pl08x_ids
);
2195 static struct amba_driver pl08x_amba_driver
= {
2196 .drv
.name
= DRIVER_NAME
,
2197 .id_table
= pl08x_ids
,
2198 .probe
= pl08x_probe
,
2201 static int __init
pl08x_init(void)
2204 retval
= amba_driver_register(&pl08x_amba_driver
);
2206 printk(KERN_WARNING DRIVER_NAME
2207 "failed to register as an AMBA device (%d)\n",
2211 subsys_initcall(pl08x_init
);