2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <asm/hardware/pl080.h>
88 #include "dmaengine.h"
91 #define DRIVER_NAME "pl08xdmac"
93 static struct amba_driver pl08x_amba_driver
;
94 struct pl08x_driver_data
;
97 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
98 * @channels: the number of channels available in this variant
99 * @dualmaster: whether this version supports dual AHB masters or not.
100 * @nomadik: whether the channels have Nomadik security extension bits
101 * that need to be checked for permission before use and some registers are
111 * PL08X private data structures
112 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
113 * start & end do not - their bus bit info is in cctl. Also note that these
114 * are fixed 32-bit quantities.
124 * struct pl08x_bus_data - information of source or destination
125 * busses for a transfer
126 * @addr: current address
127 * @maxwidth: the maximum width of a transfer on this bus
128 * @buswidth: the width of this bus in bytes: 1, 2 or 4
130 struct pl08x_bus_data
{
137 * struct pl08x_phy_chan - holder for the physical channels
138 * @id: physical index to this channel
139 * @lock: a lock to use when altering an instance of this struct
140 * @serving: the virtual channel currently being served by this physical
142 * @locked: channel unavailable for the system, e.g. dedicated to secure
145 struct pl08x_phy_chan
{
149 struct pl08x_dma_chan
*serving
;
154 * struct pl08x_sg - structure containing data per sg
155 * @src_addr: src address of sg
156 * @dst_addr: dst address of sg
157 * @len: transfer len in bytes
158 * @node: node for txd's dsg_list
164 struct list_head node
;
168 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
169 * @vd: virtual DMA descriptor
170 * @node: node for txd list for channels
171 * @dsg_list: list of children sg's
172 * @llis_bus: DMA memory address (physical) start for the LLIs
173 * @llis_va: virtual memory address start for the LLIs
174 * @cctl: control reg values for current txd
175 * @ccfg: config reg values for current txd
178 struct virt_dma_desc vd
;
179 struct list_head node
;
180 struct list_head dsg_list
;
182 struct pl08x_lli
*llis_va
;
183 /* Default cctl value for LLIs */
186 * Settings to be put into the physical channel when we
187 * trigger this txd. Other registers are in llis_va[0].
193 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
195 * @PL08X_CHAN_IDLE: the channel is idle
196 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
197 * channel and is running a transfer on it
198 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
199 * channel, but the transfer is currently paused
200 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
201 * channel to become available (only pertains to memcpy channels)
203 enum pl08x_dma_chan_state
{
211 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
212 * @vc: wrappped virtual channel
213 * @phychan: the physical channel utilized by this channel, if there is one
214 * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
215 * @name: name of channel
216 * @cd: channel platform data
217 * @runtime_addr: address for RX/TX according to the runtime config
218 * @done_list: list of completed transactions
219 * @at: active transaction on this channel
220 * @lock: a lock for this channel data
221 * @host: a pointer to the host (internal use)
222 * @state: whether the channel is idle, paused, running etc
223 * @slave: whether this channel is a device (slave) or for memcpy
224 * @signal: the physical DMA request signal which this channel is using
225 * @mux_use: count of descriptors using this DMA request signal setting
227 struct pl08x_dma_chan
{
228 struct virt_dma_chan vc
;
229 struct pl08x_phy_chan
*phychan
;
230 struct tasklet_struct tasklet
;
232 const struct pl08x_channel_data
*cd
;
233 struct dma_slave_config cfg
;
234 struct list_head done_list
;
235 struct pl08x_txd
*at
;
236 struct pl08x_driver_data
*host
;
237 enum pl08x_dma_chan_state state
;
244 * struct pl08x_driver_data - the local state holder for the PL08x
245 * @slave: slave engine for this instance
246 * @memcpy: memcpy engine for this instance
247 * @base: virtual memory base (remapped) for the PL08x
248 * @adev: the corresponding AMBA (PrimeCell) bus entry
249 * @vd: vendor data for this PL08x variant
250 * @pd: platform data passed in from the platform/machine
251 * @phy_chans: array of data for the physical channels
252 * @pool: a pool for the LLI descriptors
253 * @pool_ctr: counter of LLIs in the pool
254 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
256 * @mem_buses: set to indicate memory transfers on AHB2.
257 * @lock: a spinlock for this struct
259 struct pl08x_driver_data
{
260 struct dma_device slave
;
261 struct dma_device memcpy
;
263 struct amba_device
*adev
;
264 const struct vendor_data
*vd
;
265 struct pl08x_platform_data
*pd
;
266 struct pl08x_phy_chan
*phy_chans
;
267 struct dma_pool
*pool
;
274 * PL08X specific defines
277 /* Size (bytes) of each LLI buffer allocated for one transfer */
278 # define PL08X_LLI_TSFR_SIZE 0x2000
280 /* Maximum times we call dma_pool_alloc on this pool without freeing */
281 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
282 #define PL08X_ALIGN 8
284 static inline struct pl08x_dma_chan
*to_pl08x_chan(struct dma_chan
*chan
)
286 return container_of(chan
, struct pl08x_dma_chan
, vc
.chan
);
289 static inline struct pl08x_txd
*to_pl08x_txd(struct dma_async_tx_descriptor
*tx
)
291 return container_of(tx
, struct pl08x_txd
, vd
.tx
);
297 * This gives us the DMA request input to the PL08x primecell which the
298 * peripheral described by the channel data will be routed to, possibly
299 * via a board/SoC specific external MUX. One important point to note
300 * here is that this does not depend on the physical channel.
302 static int pl08x_request_mux(struct pl08x_dma_chan
*plchan
)
304 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
307 if (plchan
->mux_use
++ == 0 && pd
->get_signal
) {
308 ret
= pd
->get_signal(plchan
->cd
);
314 plchan
->signal
= ret
;
319 static void pl08x_release_mux(struct pl08x_dma_chan
*plchan
)
321 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
323 if (plchan
->signal
>= 0) {
324 WARN_ON(plchan
->mux_use
== 0);
326 if (--plchan
->mux_use
== 0 && pd
->put_signal
) {
327 pd
->put_signal(plchan
->cd
, plchan
->signal
);
334 * Physical channel handling
337 /* Whether a certain channel is busy or not */
338 static int pl08x_phy_channel_busy(struct pl08x_phy_chan
*ch
)
342 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
343 return val
& PL080_CONFIG_ACTIVE
;
347 * Set the initial DMA register values i.e. those for the first LLI
348 * The next LLI pointer and the configuration interrupt bit have
349 * been set when the LLIs were constructed. Poke them into the hardware
350 * and start the transfer.
352 static void pl08x_start_next_txd(struct pl08x_dma_chan
*plchan
)
354 struct pl08x_driver_data
*pl08x
= plchan
->host
;
355 struct pl08x_phy_chan
*phychan
= plchan
->phychan
;
356 struct virt_dma_desc
*vd
= vchan_next_desc(&plchan
->vc
);
357 struct pl08x_txd
*txd
= to_pl08x_txd(&vd
->tx
);
358 struct pl08x_lli
*lli
;
361 list_del(&txd
->vd
.node
);
365 /* Wait for channel inactive */
366 while (pl08x_phy_channel_busy(phychan
))
369 lli
= &txd
->llis_va
[0];
371 dev_vdbg(&pl08x
->adev
->dev
,
372 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
373 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
374 phychan
->id
, lli
->src
, lli
->dst
, lli
->lli
, lli
->cctl
,
377 writel(lli
->src
, phychan
->base
+ PL080_CH_SRC_ADDR
);
378 writel(lli
->dst
, phychan
->base
+ PL080_CH_DST_ADDR
);
379 writel(lli
->lli
, phychan
->base
+ PL080_CH_LLI
);
380 writel(lli
->cctl
, phychan
->base
+ PL080_CH_CONTROL
);
381 writel(txd
->ccfg
, phychan
->base
+ PL080_CH_CONFIG
);
383 /* Enable the DMA channel */
384 /* Do not access config register until channel shows as disabled */
385 while (readl(pl08x
->base
+ PL080_EN_CHAN
) & (1 << phychan
->id
))
388 /* Do not access config register until channel shows as inactive */
389 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
390 while ((val
& PL080_CONFIG_ACTIVE
) || (val
& PL080_CONFIG_ENABLE
))
391 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
393 writel(val
| PL080_CONFIG_ENABLE
, phychan
->base
+ PL080_CH_CONFIG
);
397 * Pause the channel by setting the HALT bit.
399 * For M->P transfers, pause the DMAC first and then stop the peripheral -
400 * the FIFO can only drain if the peripheral is still requesting data.
401 * (note: this can still timeout if the DMAC FIFO never drains of data.)
403 * For P->M transfers, disable the peripheral first to stop it filling
404 * the DMAC FIFO, and then pause the DMAC.
406 static void pl08x_pause_phy_chan(struct pl08x_phy_chan
*ch
)
411 /* Set the HALT bit and wait for the FIFO to drain */
412 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
413 val
|= PL080_CONFIG_HALT
;
414 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
416 /* Wait for channel inactive */
417 for (timeout
= 1000; timeout
; timeout
--) {
418 if (!pl08x_phy_channel_busy(ch
))
422 if (pl08x_phy_channel_busy(ch
))
423 pr_err("pl08x: channel%u timeout waiting for pause\n", ch
->id
);
426 static void pl08x_resume_phy_chan(struct pl08x_phy_chan
*ch
)
430 /* Clear the HALT bit */
431 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
432 val
&= ~PL080_CONFIG_HALT
;
433 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
437 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
438 * clears any pending interrupt status. This should not be used for
439 * an on-going transfer, but as a method of shutting down a channel
440 * (eg, when it's no longer used) or terminating a transfer.
442 static void pl08x_terminate_phy_chan(struct pl08x_driver_data
*pl08x
,
443 struct pl08x_phy_chan
*ch
)
445 u32 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
447 val
&= ~(PL080_CONFIG_ENABLE
| PL080_CONFIG_ERR_IRQ_MASK
|
448 PL080_CONFIG_TC_IRQ_MASK
);
450 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
452 writel(1 << ch
->id
, pl08x
->base
+ PL080_ERR_CLEAR
);
453 writel(1 << ch
->id
, pl08x
->base
+ PL080_TC_CLEAR
);
456 static inline u32
get_bytes_in_cctl(u32 cctl
)
458 /* The source width defines the number of bytes */
459 u32 bytes
= cctl
& PL080_CONTROL_TRANSFER_SIZE_MASK
;
461 switch (cctl
>> PL080_CONTROL_SWIDTH_SHIFT
) {
462 case PL080_WIDTH_8BIT
:
464 case PL080_WIDTH_16BIT
:
467 case PL080_WIDTH_32BIT
:
474 /* The channel should be paused when calling this */
475 static u32
pl08x_getbytes_chan(struct pl08x_dma_chan
*plchan
)
477 struct pl08x_phy_chan
*ch
;
478 struct pl08x_txd
*txd
;
482 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
483 ch
= plchan
->phychan
;
487 * Follow the LLIs to get the number of remaining
488 * bytes in the currently active transaction.
491 u32 clli
= readl(ch
->base
+ PL080_CH_LLI
) & ~PL080_LLI_LM_AHB2
;
493 /* First get the remaining bytes in the active transfer */
494 bytes
= get_bytes_in_cctl(readl(ch
->base
+ PL080_CH_CONTROL
));
497 struct pl08x_lli
*llis_va
= txd
->llis_va
;
498 dma_addr_t llis_bus
= txd
->llis_bus
;
501 BUG_ON(clli
< llis_bus
|| clli
>= llis_bus
+
502 sizeof(struct pl08x_lli
) * MAX_NUM_TSFR_LLIS
);
505 * Locate the next LLI - as this is an array,
506 * it's simple maths to find.
508 index
= (clli
- llis_bus
) / sizeof(struct pl08x_lli
);
510 for (; index
< MAX_NUM_TSFR_LLIS
; index
++) {
511 bytes
+= get_bytes_in_cctl(llis_va
[index
].cctl
);
514 * A LLI pointer of 0 terminates the LLI list
516 if (!llis_va
[index
].lli
)
522 /* Sum up all queued transactions */
523 if (!list_empty(&plchan
->vc
.desc_issued
)) {
524 struct pl08x_txd
*txdi
;
525 list_for_each_entry(txdi
, &plchan
->vc
.desc_issued
, vd
.node
) {
526 struct pl08x_sg
*dsg
;
527 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
532 if (!list_empty(&plchan
->vc
.desc_submitted
)) {
533 struct pl08x_txd
*txdi
;
534 list_for_each_entry(txdi
, &plchan
->vc
.desc_submitted
, vd
.node
) {
535 struct pl08x_sg
*dsg
;
536 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
541 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
547 * Allocate a physical channel for a virtual channel
549 * Try to locate a physical channel to be used for this transfer. If all
550 * are taken return NULL and the requester will have to cope by using
551 * some fallback PIO mode or retrying later.
553 static struct pl08x_phy_chan
*
554 pl08x_get_phy_channel(struct pl08x_driver_data
*pl08x
,
555 struct pl08x_dma_chan
*virt_chan
)
557 struct pl08x_phy_chan
*ch
= NULL
;
561 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
562 ch
= &pl08x
->phy_chans
[i
];
564 spin_lock_irqsave(&ch
->lock
, flags
);
566 if (!ch
->locked
&& !ch
->serving
) {
567 ch
->serving
= virt_chan
;
568 spin_unlock_irqrestore(&ch
->lock
, flags
);
572 spin_unlock_irqrestore(&ch
->lock
, flags
);
575 if (i
== pl08x
->vd
->channels
) {
576 /* No physical channel available, cope with it */
583 /* Mark the physical channel as free. Note, this write is atomic. */
584 static inline void pl08x_put_phy_channel(struct pl08x_driver_data
*pl08x
,
585 struct pl08x_phy_chan
*ch
)
591 * Try to allocate a physical channel. When successful, assign it to
592 * this virtual channel, and initiate the next descriptor. The
593 * virtual channel lock must be held at this point.
595 static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan
*plchan
)
597 struct pl08x_driver_data
*pl08x
= plchan
->host
;
598 struct pl08x_phy_chan
*ch
;
600 ch
= pl08x_get_phy_channel(pl08x
, plchan
);
602 dev_dbg(&pl08x
->adev
->dev
, "no physical channel available for xfer on %s\n", plchan
->name
);
603 plchan
->state
= PL08X_CHAN_WAITING
;
607 dev_dbg(&pl08x
->adev
->dev
, "allocated physical channel %d for xfer on %s\n",
608 ch
->id
, plchan
->name
);
610 plchan
->phychan
= ch
;
611 plchan
->state
= PL08X_CHAN_RUNNING
;
612 pl08x_start_next_txd(plchan
);
615 static void pl08x_phy_reassign_start(struct pl08x_phy_chan
*ch
,
616 struct pl08x_dma_chan
*plchan
)
618 struct pl08x_driver_data
*pl08x
= plchan
->host
;
620 dev_dbg(&pl08x
->adev
->dev
, "reassigned physical channel %d for xfer on %s\n",
621 ch
->id
, plchan
->name
);
624 * We do this without taking the lock; we're really only concerned
625 * about whether this pointer is NULL or not, and we're guaranteed
626 * that this will only be called when it _already_ is non-NULL.
628 ch
->serving
= plchan
;
629 plchan
->phychan
= ch
;
630 plchan
->state
= PL08X_CHAN_RUNNING
;
631 pl08x_start_next_txd(plchan
);
635 * Free a physical DMA channel, potentially reallocating it to another
636 * virtual channel if we have any pending.
638 static void pl08x_phy_free(struct pl08x_dma_chan
*plchan
)
640 struct pl08x_driver_data
*pl08x
= plchan
->host
;
641 struct pl08x_dma_chan
*p
, *next
;
646 /* Find a waiting virtual channel for the next transfer. */
647 list_for_each_entry(p
, &pl08x
->memcpy
.channels
, vc
.chan
.device_node
)
648 if (p
->state
== PL08X_CHAN_WAITING
) {
654 list_for_each_entry(p
, &pl08x
->slave
.channels
, vc
.chan
.device_node
)
655 if (p
->state
== PL08X_CHAN_WAITING
) {
661 /* Ensure that the physical channel is stopped */
662 pl08x_terminate_phy_chan(pl08x
, plchan
->phychan
);
668 * Eww. We know this isn't going to deadlock
669 * but lockdep probably doesn't.
671 spin_lock(&next
->vc
.lock
);
672 /* Re-check the state now that we have the lock */
673 success
= next
->state
== PL08X_CHAN_WAITING
;
675 pl08x_phy_reassign_start(plchan
->phychan
, next
);
676 spin_unlock(&next
->vc
.lock
);
678 /* If the state changed, try to find another channel */
682 /* No more jobs, so free up the physical channel */
683 pl08x_put_phy_channel(pl08x
, plchan
->phychan
);
686 plchan
->phychan
= NULL
;
687 plchan
->state
= PL08X_CHAN_IDLE
;
694 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded
)
697 case PL080_WIDTH_8BIT
:
699 case PL080_WIDTH_16BIT
:
701 case PL080_WIDTH_32BIT
:
710 static inline u32
pl08x_cctl_bits(u32 cctl
, u8 srcwidth
, u8 dstwidth
,
715 /* Remove all src, dst and transfer size bits */
716 retbits
&= ~PL080_CONTROL_DWIDTH_MASK
;
717 retbits
&= ~PL080_CONTROL_SWIDTH_MASK
;
718 retbits
&= ~PL080_CONTROL_TRANSFER_SIZE_MASK
;
720 /* Then set the bits according to the parameters */
723 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
726 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
729 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
738 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
741 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
744 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
751 retbits
|= tsize
<< PL080_CONTROL_TRANSFER_SIZE_SHIFT
;
755 struct pl08x_lli_build_data
{
756 struct pl08x_txd
*txd
;
757 struct pl08x_bus_data srcbus
;
758 struct pl08x_bus_data dstbus
;
764 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
765 * victim in case src & dest are not similarly aligned. i.e. If after aligning
766 * masters address with width requirements of transfer (by sending few byte by
767 * byte data), slave is still not aligned, then its width will be reduced to
769 * - prefers the destination bus if both available
770 * - prefers bus with fixed address (i.e. peripheral)
772 static void pl08x_choose_master_bus(struct pl08x_lli_build_data
*bd
,
773 struct pl08x_bus_data
**mbus
, struct pl08x_bus_data
**sbus
, u32 cctl
)
775 if (!(cctl
& PL080_CONTROL_DST_INCR
)) {
778 } else if (!(cctl
& PL080_CONTROL_SRC_INCR
)) {
782 if (bd
->dstbus
.buswidth
>= bd
->srcbus
.buswidth
) {
793 * Fills in one LLI for a certain transfer descriptor and advance the counter
795 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data
*bd
,
796 int num_llis
, int len
, u32 cctl
)
798 struct pl08x_lli
*llis_va
= bd
->txd
->llis_va
;
799 dma_addr_t llis_bus
= bd
->txd
->llis_bus
;
801 BUG_ON(num_llis
>= MAX_NUM_TSFR_LLIS
);
803 llis_va
[num_llis
].cctl
= cctl
;
804 llis_va
[num_llis
].src
= bd
->srcbus
.addr
;
805 llis_va
[num_llis
].dst
= bd
->dstbus
.addr
;
806 llis_va
[num_llis
].lli
= llis_bus
+ (num_llis
+ 1) *
807 sizeof(struct pl08x_lli
);
808 llis_va
[num_llis
].lli
|= bd
->lli_bus
;
810 if (cctl
& PL080_CONTROL_SRC_INCR
)
811 bd
->srcbus
.addr
+= len
;
812 if (cctl
& PL080_CONTROL_DST_INCR
)
813 bd
->dstbus
.addr
+= len
;
815 BUG_ON(bd
->remainder
< len
);
817 bd
->remainder
-= len
;
820 static inline void prep_byte_width_lli(struct pl08x_lli_build_data
*bd
,
821 u32
*cctl
, u32 len
, int num_llis
, size_t *total_bytes
)
823 *cctl
= pl08x_cctl_bits(*cctl
, 1, 1, len
);
824 pl08x_fill_lli_for_desc(bd
, num_llis
, len
, *cctl
);
825 (*total_bytes
) += len
;
829 * This fills in the table of LLIs for the transfer descriptor
830 * Note that we assume we never have to change the burst sizes
833 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data
*pl08x
,
834 struct pl08x_txd
*txd
)
836 struct pl08x_bus_data
*mbus
, *sbus
;
837 struct pl08x_lli_build_data bd
;
839 u32 cctl
, early_bytes
= 0;
840 size_t max_bytes_per_lli
, total_bytes
;
841 struct pl08x_lli
*llis_va
;
842 struct pl08x_sg
*dsg
;
844 txd
->llis_va
= dma_pool_alloc(pl08x
->pool
, GFP_NOWAIT
, &txd
->llis_bus
);
846 dev_err(&pl08x
->adev
->dev
, "%s no memory for llis\n", __func__
);
853 bd
.lli_bus
= (pl08x
->lli_buses
& PL08X_AHB2
) ? PL080_LLI_LM_AHB2
: 0;
856 /* Find maximum width of the source bus */
858 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_SWIDTH_MASK
) >>
859 PL080_CONTROL_SWIDTH_SHIFT
);
861 /* Find maximum width of the destination bus */
863 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_DWIDTH_MASK
) >>
864 PL080_CONTROL_DWIDTH_SHIFT
);
866 list_for_each_entry(dsg
, &txd
->dsg_list
, node
) {
870 bd
.srcbus
.addr
= dsg
->src_addr
;
871 bd
.dstbus
.addr
= dsg
->dst_addr
;
872 bd
.remainder
= dsg
->len
;
873 bd
.srcbus
.buswidth
= bd
.srcbus
.maxwidth
;
874 bd
.dstbus
.buswidth
= bd
.dstbus
.maxwidth
;
876 pl08x_choose_master_bus(&bd
, &mbus
, &sbus
, cctl
);
878 dev_vdbg(&pl08x
->adev
->dev
, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
879 bd
.srcbus
.addr
, cctl
& PL080_CONTROL_SRC_INCR
? "+" : "",
881 bd
.dstbus
.addr
, cctl
& PL080_CONTROL_DST_INCR
? "+" : "",
884 dev_vdbg(&pl08x
->adev
->dev
, "mbus=%s sbus=%s\n",
885 mbus
== &bd
.srcbus
? "src" : "dst",
886 sbus
== &bd
.srcbus
? "src" : "dst");
889 * Zero length is only allowed if all these requirements are
891 * - flow controller is peripheral.
892 * - src.addr is aligned to src.width
893 * - dst.addr is aligned to dst.width
895 * sg_len == 1 should be true, as there can be two cases here:
897 * - Memory addresses are contiguous and are not scattered.
898 * Here, Only one sg will be passed by user driver, with
899 * memory address and zero length. We pass this to controller
900 * and after the transfer it will receive the last burst
901 * request from peripheral and so transfer finishes.
903 * - Memory addresses are scattered and are not contiguous.
904 * Here, Obviously as DMA controller doesn't know when a lli's
905 * transfer gets over, it can't load next lli. So in this
906 * case, there has to be an assumption that only one lli is
907 * supported. Thus, we can't have scattered addresses.
910 u32 fc
= (txd
->ccfg
& PL080_CONFIG_FLOW_CONTROL_MASK
) >>
911 PL080_CONFIG_FLOW_CONTROL_SHIFT
;
912 if (!((fc
>= PL080_FLOW_SRC2DST_DST
) &&
913 (fc
<= PL080_FLOW_SRC2DST_SRC
))) {
914 dev_err(&pl08x
->adev
->dev
, "%s sg len can't be zero",
919 if ((bd
.srcbus
.addr
% bd
.srcbus
.buswidth
) ||
920 (bd
.dstbus
.addr
% bd
.dstbus
.buswidth
)) {
921 dev_err(&pl08x
->adev
->dev
,
922 "%s src & dst address must be aligned to src"
923 " & dst width if peripheral is flow controller",
928 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
929 bd
.dstbus
.buswidth
, 0);
930 pl08x_fill_lli_for_desc(&bd
, num_llis
++, 0, cctl
);
935 * Send byte by byte for following cases
936 * - Less than a bus width available
937 * - until master bus is aligned
939 if (bd
.remainder
< mbus
->buswidth
)
940 early_bytes
= bd
.remainder
;
941 else if ((mbus
->addr
) % (mbus
->buswidth
)) {
942 early_bytes
= mbus
->buswidth
- (mbus
->addr
) %
944 if ((bd
.remainder
- early_bytes
) < mbus
->buswidth
)
945 early_bytes
= bd
.remainder
;
949 dev_vdbg(&pl08x
->adev
->dev
,
950 "%s byte width LLIs (remain 0x%08x)\n",
951 __func__
, bd
.remainder
);
952 prep_byte_width_lli(&bd
, &cctl
, early_bytes
, num_llis
++,
959 * - if slave is not then we must set its width down
961 if (sbus
->addr
% sbus
->buswidth
) {
962 dev_dbg(&pl08x
->adev
->dev
,
963 "%s set down bus width to one byte\n",
970 * Bytes transferred = tsize * src width, not
973 max_bytes_per_lli
= bd
.srcbus
.buswidth
*
974 PL080_CONTROL_TRANSFER_SIZE_MASK
;
975 dev_vdbg(&pl08x
->adev
->dev
,
976 "%s max bytes per lli = %zu\n",
977 __func__
, max_bytes_per_lli
);
980 * Make largest possible LLIs until less than one bus
983 while (bd
.remainder
> (mbus
->buswidth
- 1)) {
984 size_t lli_len
, tsize
, width
;
987 * If enough left try to send max possible,
988 * otherwise try to send the remainder
990 lli_len
= min(bd
.remainder
, max_bytes_per_lli
);
993 * Check against maximum bus alignment:
994 * Calculate actual transfer size in relation to
995 * bus width an get a maximum remainder of the
996 * highest bus width - 1
998 width
= max(mbus
->buswidth
, sbus
->buswidth
);
999 lli_len
= (lli_len
/ width
) * width
;
1000 tsize
= lli_len
/ bd
.srcbus
.buswidth
;
1002 dev_vdbg(&pl08x
->adev
->dev
,
1003 "%s fill lli with single lli chunk of "
1004 "size 0x%08zx (remainder 0x%08zx)\n",
1005 __func__
, lli_len
, bd
.remainder
);
1007 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
1008 bd
.dstbus
.buswidth
, tsize
);
1009 pl08x_fill_lli_for_desc(&bd
, num_llis
++,
1011 total_bytes
+= lli_len
;
1015 * Send any odd bytes
1018 dev_vdbg(&pl08x
->adev
->dev
,
1019 "%s align with boundary, send odd bytes (remain %zu)\n",
1020 __func__
, bd
.remainder
);
1021 prep_byte_width_lli(&bd
, &cctl
, bd
.remainder
,
1022 num_llis
++, &total_bytes
);
1026 if (total_bytes
!= dsg
->len
) {
1027 dev_err(&pl08x
->adev
->dev
,
1028 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
1029 __func__
, total_bytes
, dsg
->len
);
1033 if (num_llis
>= MAX_NUM_TSFR_LLIS
) {
1034 dev_err(&pl08x
->adev
->dev
,
1035 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
1036 __func__
, (u32
) MAX_NUM_TSFR_LLIS
);
1041 llis_va
= txd
->llis_va
;
1042 /* The final LLI terminates the LLI. */
1043 llis_va
[num_llis
- 1].lli
= 0;
1044 /* The final LLI element shall also fire an interrupt. */
1045 llis_va
[num_llis
- 1].cctl
|= PL080_CONTROL_TC_IRQ_EN
;
1047 #ifdef VERBOSE_DEBUG
1051 dev_vdbg(&pl08x
->adev
->dev
,
1052 "%-3s %-9s %-10s %-10s %-10s %s\n",
1053 "lli", "", "csrc", "cdst", "clli", "cctl");
1054 for (i
= 0; i
< num_llis
; i
++) {
1055 dev_vdbg(&pl08x
->adev
->dev
,
1056 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1057 i
, &llis_va
[i
], llis_va
[i
].src
,
1058 llis_va
[i
].dst
, llis_va
[i
].lli
, llis_va
[i
].cctl
1067 /* You should call this with the struct pl08x lock held */
1068 static void pl08x_free_txd(struct pl08x_driver_data
*pl08x
,
1069 struct pl08x_txd
*txd
)
1071 struct pl08x_sg
*dsg
, *_dsg
;
1075 dma_pool_free(pl08x
->pool
, txd
->llis_va
, txd
->llis_bus
);
1079 list_for_each_entry_safe(dsg
, _dsg
, &txd
->dsg_list
, node
) {
1080 list_del(&dsg
->node
);
1087 static void pl08x_free_txd_list(struct pl08x_driver_data
*pl08x
,
1088 struct pl08x_dma_chan
*plchan
)
1091 struct pl08x_txd
*txd
;
1093 vchan_get_all_descriptors(&plchan
->vc
, &head
);
1095 while (!list_empty(&head
)) {
1096 txd
= list_first_entry(&head
, struct pl08x_txd
, vd
.node
);
1097 pl08x_release_mux(plchan
);
1098 list_del(&txd
->vd
.node
);
1099 pl08x_free_txd(pl08x
, txd
);
1104 * The DMA ENGINE API
1106 static int pl08x_alloc_chan_resources(struct dma_chan
*chan
)
1111 static void pl08x_free_chan_resources(struct dma_chan
*chan
)
1115 static struct dma_async_tx_descriptor
*pl08x_prep_dma_interrupt(
1116 struct dma_chan
*chan
, unsigned long flags
)
1118 struct dma_async_tx_descriptor
*retval
= NULL
;
1124 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1125 * If slaves are relying on interrupts to signal completion this function
1126 * must not be called with interrupts disabled.
1128 static enum dma_status
pl08x_dma_tx_status(struct dma_chan
*chan
,
1129 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
1131 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1132 enum dma_status ret
;
1134 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1135 if (ret
== DMA_SUCCESS
)
1139 * This cookie not complete yet
1140 * Get number of bytes left in the active transactions and queue
1142 dma_set_residue(txstate
, pl08x_getbytes_chan(plchan
));
1144 if (plchan
->state
== PL08X_CHAN_PAUSED
)
1147 /* Whether waiting or running, we're in progress */
1148 return DMA_IN_PROGRESS
;
1151 /* PrimeCell DMA extension */
1152 struct burst_table
{
1157 static const struct burst_table burst_sizes
[] = {
1160 .reg
= PL080_BSIZE_256
,
1164 .reg
= PL080_BSIZE_128
,
1168 .reg
= PL080_BSIZE_64
,
1172 .reg
= PL080_BSIZE_32
,
1176 .reg
= PL080_BSIZE_16
,
1180 .reg
= PL080_BSIZE_8
,
1184 .reg
= PL080_BSIZE_4
,
1188 .reg
= PL080_BSIZE_1
,
1193 * Given the source and destination available bus masks, select which
1194 * will be routed to each port. We try to have source and destination
1195 * on separate ports, but always respect the allowable settings.
1197 static u32
pl08x_select_bus(u8 src
, u8 dst
)
1201 if (!(dst
& PL08X_AHB1
) || ((dst
& PL08X_AHB2
) && (src
& PL08X_AHB1
)))
1202 cctl
|= PL080_CONTROL_DST_AHB2
;
1203 if (!(src
& PL08X_AHB1
) || ((src
& PL08X_AHB2
) && !(dst
& PL08X_AHB2
)))
1204 cctl
|= PL080_CONTROL_SRC_AHB2
;
1209 static u32
pl08x_cctl(u32 cctl
)
1211 cctl
&= ~(PL080_CONTROL_SRC_AHB2
| PL080_CONTROL_DST_AHB2
|
1212 PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
|
1213 PL080_CONTROL_PROT_MASK
);
1215 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1216 return cctl
| PL080_CONTROL_PROT_SYS
;
1219 static u32
pl08x_width(enum dma_slave_buswidth width
)
1222 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
1223 return PL080_WIDTH_8BIT
;
1224 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
1225 return PL080_WIDTH_16BIT
;
1226 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
1227 return PL080_WIDTH_32BIT
;
1233 static u32
pl08x_burst(u32 maxburst
)
1237 for (i
= 0; i
< ARRAY_SIZE(burst_sizes
); i
++)
1238 if (burst_sizes
[i
].burstwords
<= maxburst
)
1241 return burst_sizes
[i
].reg
;
1244 static u32
pl08x_get_cctl(struct pl08x_dma_chan
*plchan
,
1245 enum dma_slave_buswidth addr_width
, u32 maxburst
)
1247 u32 width
, burst
, cctl
= 0;
1249 width
= pl08x_width(addr_width
);
1253 cctl
|= width
<< PL080_CONTROL_SWIDTH_SHIFT
;
1254 cctl
|= width
<< PL080_CONTROL_DWIDTH_SHIFT
;
1257 * If this channel will only request single transfers, set this
1258 * down to ONE element. Also select one element if no maxburst
1261 if (plchan
->cd
->single
)
1264 burst
= pl08x_burst(maxburst
);
1265 cctl
|= burst
<< PL080_CONTROL_SB_SIZE_SHIFT
;
1266 cctl
|= burst
<< PL080_CONTROL_DB_SIZE_SHIFT
;
1268 return pl08x_cctl(cctl
);
1271 static int dma_set_runtime_config(struct dma_chan
*chan
,
1272 struct dma_slave_config
*config
)
1274 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1279 /* Reject definitely invalid configurations */
1280 if (config
->src_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
||
1281 config
->dst_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
)
1284 plchan
->cfg
= *config
;
1290 * Slave transactions callback to the slave device to allow
1291 * synchronization of slave DMA signals with the DMAC enable
1293 static void pl08x_issue_pending(struct dma_chan
*chan
)
1295 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1296 unsigned long flags
;
1298 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1299 if (vchan_issue_pending(&plchan
->vc
)) {
1300 if (!plchan
->phychan
&& plchan
->state
!= PL08X_CHAN_WAITING
)
1301 pl08x_phy_alloc_and_start(plchan
);
1303 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1306 static int pl08x_prep_channel_resources(struct pl08x_dma_chan
*plchan
,
1307 struct pl08x_txd
*txd
)
1309 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1312 num_llis
= pl08x_fill_llis_for_desc(pl08x
, txd
);
1314 unsigned long flags
;
1316 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1317 pl08x_free_txd(pl08x
, txd
);
1318 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1325 static struct pl08x_txd
*pl08x_get_txd(struct pl08x_dma_chan
*plchan
)
1327 struct pl08x_txd
*txd
= kzalloc(sizeof(*txd
), GFP_NOWAIT
);
1330 INIT_LIST_HEAD(&txd
->dsg_list
);
1332 /* Always enable error and terminal interrupts */
1333 txd
->ccfg
= PL080_CONFIG_ERR_IRQ_MASK
|
1334 PL080_CONFIG_TC_IRQ_MASK
;
1340 * Initialize a descriptor to be used by memcpy submit
1342 static struct dma_async_tx_descriptor
*pl08x_prep_dma_memcpy(
1343 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1344 size_t len
, unsigned long flags
)
1346 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1347 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1348 struct pl08x_txd
*txd
;
1349 struct pl08x_sg
*dsg
;
1352 txd
= pl08x_get_txd(plchan
);
1354 dev_err(&pl08x
->adev
->dev
,
1355 "%s no memory for descriptor\n", __func__
);
1359 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1361 pl08x_free_txd(pl08x
, txd
);
1362 dev_err(&pl08x
->adev
->dev
, "%s no memory for pl080 sg\n",
1366 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1368 dsg
->src_addr
= src
;
1369 dsg
->dst_addr
= dest
;
1372 /* Set platform data for m2m */
1373 txd
->ccfg
|= PL080_FLOW_MEM2MEM
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1374 txd
->cctl
= pl08x
->pd
->memcpy_channel
.cctl_memcpy
&
1375 ~(PL080_CONTROL_DST_AHB2
| PL080_CONTROL_SRC_AHB2
);
1377 /* Both to be incremented or the code will break */
1378 txd
->cctl
|= PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
;
1380 if (pl08x
->vd
->dualmaster
)
1381 txd
->cctl
|= pl08x_select_bus(pl08x
->mem_buses
,
1384 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1388 return vchan_tx_prep(&plchan
->vc
, &txd
->vd
, flags
);
1391 static struct dma_async_tx_descriptor
*pl08x_prep_slave_sg(
1392 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1393 unsigned int sg_len
, enum dma_transfer_direction direction
,
1394 unsigned long flags
, void *context
)
1396 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1397 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1398 struct pl08x_txd
*txd
;
1399 struct pl08x_sg
*dsg
;
1400 struct scatterlist
*sg
;
1401 enum dma_slave_buswidth addr_width
;
1402 dma_addr_t slave_addr
;
1404 u8 src_buses
, dst_buses
;
1407 dev_dbg(&pl08x
->adev
->dev
, "%s prepare transaction of %d bytes from %s\n",
1408 __func__
, sg_dma_len(sgl
), plchan
->name
);
1410 txd
= pl08x_get_txd(plchan
);
1412 dev_err(&pl08x
->adev
->dev
, "%s no txd\n", __func__
);
1417 * Set up addresses, the PrimeCell configured address
1418 * will take precedence since this may configure the
1419 * channel target address dynamically at runtime.
1421 if (direction
== DMA_MEM_TO_DEV
) {
1422 cctl
= PL080_CONTROL_SRC_INCR
;
1423 slave_addr
= plchan
->cfg
.dst_addr
;
1424 addr_width
= plchan
->cfg
.dst_addr_width
;
1425 maxburst
= plchan
->cfg
.dst_maxburst
;
1426 src_buses
= pl08x
->mem_buses
;
1427 dst_buses
= plchan
->cd
->periph_buses
;
1428 } else if (direction
== DMA_DEV_TO_MEM
) {
1429 cctl
= PL080_CONTROL_DST_INCR
;
1430 slave_addr
= plchan
->cfg
.src_addr
;
1431 addr_width
= plchan
->cfg
.src_addr_width
;
1432 maxburst
= plchan
->cfg
.src_maxburst
;
1433 src_buses
= plchan
->cd
->periph_buses
;
1434 dst_buses
= pl08x
->mem_buses
;
1436 pl08x_free_txd(pl08x
, txd
);
1437 dev_err(&pl08x
->adev
->dev
,
1438 "%s direction unsupported\n", __func__
);
1442 cctl
|= pl08x_get_cctl(plchan
, addr_width
, maxburst
);
1444 pl08x_free_txd(pl08x
, txd
);
1445 dev_err(&pl08x
->adev
->dev
,
1446 "DMA slave configuration botched?\n");
1450 txd
->cctl
= cctl
| pl08x_select_bus(src_buses
, dst_buses
);
1452 if (plchan
->cfg
.device_fc
)
1453 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER_PER
:
1454 PL080_FLOW_PER2MEM_PER
;
1456 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER
:
1459 txd
->ccfg
|= tmp
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1461 ret
= pl08x_request_mux(plchan
);
1463 pl08x_free_txd(pl08x
, txd
);
1464 dev_dbg(&pl08x
->adev
->dev
,
1465 "unable to mux for transfer on %s due to platform restrictions\n",
1470 dev_dbg(&pl08x
->adev
->dev
, "allocated DMA request signal %d for xfer on %s\n",
1471 plchan
->signal
, plchan
->name
);
1473 /* Assign the flow control signal to this channel */
1474 if (direction
== DMA_MEM_TO_DEV
)
1475 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_DST_SEL_SHIFT
;
1477 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_SRC_SEL_SHIFT
;
1479 for_each_sg(sgl
, sg
, sg_len
, tmp
) {
1480 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1482 pl08x_release_mux(plchan
);
1483 pl08x_free_txd(pl08x
, txd
);
1484 dev_err(&pl08x
->adev
->dev
, "%s no mem for pl080 sg\n",
1488 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1490 dsg
->len
= sg_dma_len(sg
);
1491 if (direction
== DMA_MEM_TO_DEV
) {
1492 dsg
->src_addr
= sg_dma_address(sg
);
1493 dsg
->dst_addr
= slave_addr
;
1495 dsg
->src_addr
= slave_addr
;
1496 dsg
->dst_addr
= sg_dma_address(sg
);
1500 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1504 return vchan_tx_prep(&plchan
->vc
, &txd
->vd
, flags
);
1507 static int pl08x_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1510 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1511 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1512 unsigned long flags
;
1515 /* Controls applicable to inactive channels */
1516 if (cmd
== DMA_SLAVE_CONFIG
) {
1517 return dma_set_runtime_config(chan
,
1518 (struct dma_slave_config
*)arg
);
1522 * Anything succeeds on channels with no physical allocation and
1523 * no queued transfers.
1525 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1526 if (!plchan
->phychan
&& !plchan
->at
) {
1527 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1532 case DMA_TERMINATE_ALL
:
1533 plchan
->state
= PL08X_CHAN_IDLE
;
1535 if (plchan
->phychan
) {
1537 * Mark physical channel as free and free any slave
1540 pl08x_phy_free(plchan
);
1542 /* Dequeue jobs and free LLIs */
1544 /* Killing this one off, release its mux */
1545 pl08x_release_mux(plchan
);
1546 pl08x_free_txd(pl08x
, plchan
->at
);
1549 /* Dequeue jobs not yet fired as well */
1550 pl08x_free_txd_list(pl08x
, plchan
);
1553 pl08x_pause_phy_chan(plchan
->phychan
);
1554 plchan
->state
= PL08X_CHAN_PAUSED
;
1557 pl08x_resume_phy_chan(plchan
->phychan
);
1558 plchan
->state
= PL08X_CHAN_RUNNING
;
1561 /* Unknown command */
1566 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1571 bool pl08x_filter_id(struct dma_chan
*chan
, void *chan_id
)
1573 struct pl08x_dma_chan
*plchan
;
1574 char *name
= chan_id
;
1576 /* Reject channels for devices not bound to this driver */
1577 if (chan
->device
->dev
->driver
!= &pl08x_amba_driver
.drv
)
1580 plchan
= to_pl08x_chan(chan
);
1582 /* Check that the channel is not taken! */
1583 if (!strcmp(plchan
->name
, name
))
1590 * Just check that the device is there and active
1591 * TODO: turn this bit on/off depending on the number of physical channels
1592 * actually used, if it is zero... well shut it off. That will save some
1593 * power. Cut the clock at the same time.
1595 static void pl08x_ensure_on(struct pl08x_driver_data
*pl08x
)
1597 /* The Nomadik variant does not have the config register */
1598 if (pl08x
->vd
->nomadik
)
1600 writel(PL080_CONFIG_ENABLE
, pl08x
->base
+ PL080_CONFIG
);
1603 static void pl08x_unmap_buffers(struct pl08x_txd
*txd
)
1605 struct device
*dev
= txd
->vd
.tx
.chan
->device
->dev
;
1606 struct pl08x_sg
*dsg
;
1608 if (!(txd
->vd
.tx
.flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
1609 if (txd
->vd
.tx
.flags
& DMA_COMPL_SRC_UNMAP_SINGLE
)
1610 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1611 dma_unmap_single(dev
, dsg
->src_addr
, dsg
->len
,
1614 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1615 dma_unmap_page(dev
, dsg
->src_addr
, dsg
->len
,
1619 if (!(txd
->vd
.tx
.flags
& DMA_COMPL_SKIP_DEST_UNMAP
)) {
1620 if (txd
->vd
.tx
.flags
& DMA_COMPL_DEST_UNMAP_SINGLE
)
1621 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1622 dma_unmap_single(dev
, dsg
->dst_addr
, dsg
->len
,
1625 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1626 dma_unmap_page(dev
, dsg
->dst_addr
, dsg
->len
,
1631 static void pl08x_tasklet(unsigned long data
)
1633 struct pl08x_dma_chan
*plchan
= (struct pl08x_dma_chan
*) data
;
1634 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1635 unsigned long flags
;
1638 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1639 list_splice_tail_init(&plchan
->done_list
, &head
);
1640 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1642 while (!list_empty(&head
)) {
1643 struct pl08x_txd
*txd
= list_first_entry(&head
,
1644 struct pl08x_txd
, node
);
1645 dma_async_tx_callback callback
= txd
->vd
.tx
.callback
;
1646 void *callback_param
= txd
->vd
.tx
.callback_param
;
1648 list_del(&txd
->node
);
1650 /* Don't try to unmap buffers on slave channels */
1652 pl08x_unmap_buffers(txd
);
1654 /* Free the descriptor */
1655 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1656 pl08x_free_txd(pl08x
, txd
);
1657 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1659 /* Callback to signal completion */
1661 callback(callback_param
);
1665 static irqreturn_t
pl08x_irq(int irq
, void *dev
)
1667 struct pl08x_driver_data
*pl08x
= dev
;
1668 u32 mask
= 0, err
, tc
, i
;
1670 /* check & clear - ERR & TC interrupts */
1671 err
= readl(pl08x
->base
+ PL080_ERR_STATUS
);
1673 dev_err(&pl08x
->adev
->dev
, "%s error interrupt, register value 0x%08x\n",
1675 writel(err
, pl08x
->base
+ PL080_ERR_CLEAR
);
1677 tc
= readl(pl08x
->base
+ PL080_TC_STATUS
);
1679 writel(tc
, pl08x
->base
+ PL080_TC_CLEAR
);
1684 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1685 if (((1 << i
) & err
) || ((1 << i
) & tc
)) {
1686 /* Locate physical channel */
1687 struct pl08x_phy_chan
*phychan
= &pl08x
->phy_chans
[i
];
1688 struct pl08x_dma_chan
*plchan
= phychan
->serving
;
1689 struct pl08x_txd
*tx
;
1692 dev_err(&pl08x
->adev
->dev
,
1693 "%s Error TC interrupt on unused channel: 0x%08x\n",
1698 spin_lock(&plchan
->vc
.lock
);
1703 * This descriptor is done, release its mux
1706 pl08x_release_mux(plchan
);
1707 dma_cookie_complete(&tx
->vd
.tx
);
1708 list_add_tail(&tx
->node
, &plchan
->done_list
);
1711 * And start the next descriptor (if any),
1712 * otherwise free this channel.
1714 if (vchan_next_desc(&plchan
->vc
))
1715 pl08x_start_next_txd(plchan
);
1717 pl08x_phy_free(plchan
);
1719 spin_unlock(&plchan
->vc
.lock
);
1721 /* Schedule tasklet on this channel */
1722 tasklet_schedule(&plchan
->tasklet
);
1727 return mask
? IRQ_HANDLED
: IRQ_NONE
;
1730 static void pl08x_dma_slave_init(struct pl08x_dma_chan
*chan
)
1733 chan
->name
= chan
->cd
->bus_id
;
1734 chan
->cfg
.src_addr
= chan
->cd
->addr
;
1735 chan
->cfg
.dst_addr
= chan
->cd
->addr
;
1739 * Initialise the DMAC memcpy/slave channels.
1740 * Make a local wrapper to hold required data
1742 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data
*pl08x
,
1743 struct dma_device
*dmadev
, unsigned int channels
, bool slave
)
1745 struct pl08x_dma_chan
*chan
;
1748 INIT_LIST_HEAD(&dmadev
->channels
);
1751 * Register as many many memcpy as we have physical channels,
1752 * we won't always be able to use all but the code will have
1753 * to cope with that situation.
1755 for (i
= 0; i
< channels
; i
++) {
1756 chan
= kzalloc(sizeof(*chan
), GFP_KERNEL
);
1758 dev_err(&pl08x
->adev
->dev
,
1759 "%s no memory for channel\n", __func__
);
1764 chan
->state
= PL08X_CHAN_IDLE
;
1768 chan
->cd
= &pl08x
->pd
->slave_channels
[i
];
1769 pl08x_dma_slave_init(chan
);
1771 chan
->cd
= &pl08x
->pd
->memcpy_channel
;
1772 chan
->name
= kasprintf(GFP_KERNEL
, "memcpy%d", i
);
1778 dev_dbg(&pl08x
->adev
->dev
,
1779 "initialize virtual channel \"%s\"\n",
1782 INIT_LIST_HEAD(&chan
->done_list
);
1783 tasklet_init(&chan
->tasklet
, pl08x_tasklet
,
1784 (unsigned long) chan
);
1786 vchan_init(&chan
->vc
, dmadev
);
1788 dev_info(&pl08x
->adev
->dev
, "initialized %d virtual %s channels\n",
1789 i
, slave
? "slave" : "memcpy");
1793 static void pl08x_free_virtual_channels(struct dma_device
*dmadev
)
1795 struct pl08x_dma_chan
*chan
= NULL
;
1796 struct pl08x_dma_chan
*next
;
1798 list_for_each_entry_safe(chan
,
1799 next
, &dmadev
->channels
, vc
.chan
.device_node
) {
1800 list_del(&chan
->vc
.chan
.device_node
);
1805 #ifdef CONFIG_DEBUG_FS
1806 static const char *pl08x_state_str(enum pl08x_dma_chan_state state
)
1809 case PL08X_CHAN_IDLE
:
1811 case PL08X_CHAN_RUNNING
:
1813 case PL08X_CHAN_PAUSED
:
1815 case PL08X_CHAN_WAITING
:
1820 return "UNKNOWN STATE";
1823 static int pl08x_debugfs_show(struct seq_file
*s
, void *data
)
1825 struct pl08x_driver_data
*pl08x
= s
->private;
1826 struct pl08x_dma_chan
*chan
;
1827 struct pl08x_phy_chan
*ch
;
1828 unsigned long flags
;
1831 seq_printf(s
, "PL08x physical channels:\n");
1832 seq_printf(s
, "CHANNEL:\tUSER:\n");
1833 seq_printf(s
, "--------\t-----\n");
1834 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1835 struct pl08x_dma_chan
*virt_chan
;
1837 ch
= &pl08x
->phy_chans
[i
];
1839 spin_lock_irqsave(&ch
->lock
, flags
);
1840 virt_chan
= ch
->serving
;
1842 seq_printf(s
, "%d\t\t%s%s\n",
1844 virt_chan
? virt_chan
->name
: "(none)",
1845 ch
->locked
? " LOCKED" : "");
1847 spin_unlock_irqrestore(&ch
->lock
, flags
);
1850 seq_printf(s
, "\nPL08x virtual memcpy channels:\n");
1851 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1852 seq_printf(s
, "--------\t------\n");
1853 list_for_each_entry(chan
, &pl08x
->memcpy
.channels
, vc
.chan
.device_node
) {
1854 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1855 pl08x_state_str(chan
->state
));
1858 seq_printf(s
, "\nPL08x virtual slave channels:\n");
1859 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1860 seq_printf(s
, "--------\t------\n");
1861 list_for_each_entry(chan
, &pl08x
->slave
.channels
, vc
.chan
.device_node
) {
1862 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1863 pl08x_state_str(chan
->state
));
1869 static int pl08x_debugfs_open(struct inode
*inode
, struct file
*file
)
1871 return single_open(file
, pl08x_debugfs_show
, inode
->i_private
);
1874 static const struct file_operations pl08x_debugfs_operations
= {
1875 .open
= pl08x_debugfs_open
,
1877 .llseek
= seq_lseek
,
1878 .release
= single_release
,
1881 static void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1883 /* Expose a simple debugfs interface to view all clocks */
1884 (void) debugfs_create_file(dev_name(&pl08x
->adev
->dev
),
1885 S_IFREG
| S_IRUGO
, NULL
, pl08x
,
1886 &pl08x_debugfs_operations
);
1890 static inline void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1895 static int pl08x_probe(struct amba_device
*adev
, const struct amba_id
*id
)
1897 struct pl08x_driver_data
*pl08x
;
1898 const struct vendor_data
*vd
= id
->data
;
1902 ret
= amba_request_regions(adev
, NULL
);
1906 /* Create the driver state holder */
1907 pl08x
= kzalloc(sizeof(*pl08x
), GFP_KERNEL
);
1913 /* Initialize memcpy engine */
1914 dma_cap_set(DMA_MEMCPY
, pl08x
->memcpy
.cap_mask
);
1915 pl08x
->memcpy
.dev
= &adev
->dev
;
1916 pl08x
->memcpy
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1917 pl08x
->memcpy
.device_free_chan_resources
= pl08x_free_chan_resources
;
1918 pl08x
->memcpy
.device_prep_dma_memcpy
= pl08x_prep_dma_memcpy
;
1919 pl08x
->memcpy
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1920 pl08x
->memcpy
.device_tx_status
= pl08x_dma_tx_status
;
1921 pl08x
->memcpy
.device_issue_pending
= pl08x_issue_pending
;
1922 pl08x
->memcpy
.device_control
= pl08x_control
;
1924 /* Initialize slave engine */
1925 dma_cap_set(DMA_SLAVE
, pl08x
->slave
.cap_mask
);
1926 pl08x
->slave
.dev
= &adev
->dev
;
1927 pl08x
->slave
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1928 pl08x
->slave
.device_free_chan_resources
= pl08x_free_chan_resources
;
1929 pl08x
->slave
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1930 pl08x
->slave
.device_tx_status
= pl08x_dma_tx_status
;
1931 pl08x
->slave
.device_issue_pending
= pl08x_issue_pending
;
1932 pl08x
->slave
.device_prep_slave_sg
= pl08x_prep_slave_sg
;
1933 pl08x
->slave
.device_control
= pl08x_control
;
1935 /* Get the platform data */
1936 pl08x
->pd
= dev_get_platdata(&adev
->dev
);
1938 dev_err(&adev
->dev
, "no platform data supplied\n");
1939 goto out_no_platdata
;
1942 /* Assign useful pointers to the driver state */
1946 /* By default, AHB1 only. If dualmaster, from platform */
1947 pl08x
->lli_buses
= PL08X_AHB1
;
1948 pl08x
->mem_buses
= PL08X_AHB1
;
1949 if (pl08x
->vd
->dualmaster
) {
1950 pl08x
->lli_buses
= pl08x
->pd
->lli_buses
;
1951 pl08x
->mem_buses
= pl08x
->pd
->mem_buses
;
1954 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1955 pl08x
->pool
= dma_pool_create(DRIVER_NAME
, &pl08x
->adev
->dev
,
1956 PL08X_LLI_TSFR_SIZE
, PL08X_ALIGN
, 0);
1959 goto out_no_lli_pool
;
1962 pl08x
->base
= ioremap(adev
->res
.start
, resource_size(&adev
->res
));
1965 goto out_no_ioremap
;
1968 /* Turn on the PL08x */
1969 pl08x_ensure_on(pl08x
);
1971 /* Attach the interrupt handler */
1972 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
1973 writel(0x000000FF, pl08x
->base
+ PL080_TC_CLEAR
);
1975 ret
= request_irq(adev
->irq
[0], pl08x_irq
, IRQF_DISABLED
,
1976 DRIVER_NAME
, pl08x
);
1978 dev_err(&adev
->dev
, "%s failed to request interrupt %d\n",
1979 __func__
, adev
->irq
[0]);
1983 /* Initialize physical channels */
1984 pl08x
->phy_chans
= kzalloc((vd
->channels
* sizeof(*pl08x
->phy_chans
)),
1986 if (!pl08x
->phy_chans
) {
1987 dev_err(&adev
->dev
, "%s failed to allocate "
1988 "physical channel holders\n",
1990 goto out_no_phychans
;
1993 for (i
= 0; i
< vd
->channels
; i
++) {
1994 struct pl08x_phy_chan
*ch
= &pl08x
->phy_chans
[i
];
1997 ch
->base
= pl08x
->base
+ PL080_Cx_BASE(i
);
1998 spin_lock_init(&ch
->lock
);
2001 * Nomadik variants can have channels that are locked
2002 * down for the secure world only. Lock up these channels
2003 * by perpetually serving a dummy virtual channel.
2008 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
2009 if (val
& (PL080N_CONFIG_ITPROT
| PL080N_CONFIG_SECPROT
)) {
2010 dev_info(&adev
->dev
, "physical channel %d reserved for secure access only\n", i
);
2015 dev_dbg(&adev
->dev
, "physical channel %d is %s\n",
2016 i
, pl08x_phy_channel_busy(ch
) ? "BUSY" : "FREE");
2019 /* Register as many memcpy channels as there are physical channels */
2020 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->memcpy
,
2021 pl08x
->vd
->channels
, false);
2023 dev_warn(&pl08x
->adev
->dev
,
2024 "%s failed to enumerate memcpy channels - %d\n",
2028 pl08x
->memcpy
.chancnt
= ret
;
2030 /* Register slave channels */
2031 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->slave
,
2032 pl08x
->pd
->num_slave_channels
, true);
2034 dev_warn(&pl08x
->adev
->dev
,
2035 "%s failed to enumerate slave channels - %d\n",
2039 pl08x
->slave
.chancnt
= ret
;
2041 ret
= dma_async_device_register(&pl08x
->memcpy
);
2043 dev_warn(&pl08x
->adev
->dev
,
2044 "%s failed to register memcpy as an async device - %d\n",
2046 goto out_no_memcpy_reg
;
2049 ret
= dma_async_device_register(&pl08x
->slave
);
2051 dev_warn(&pl08x
->adev
->dev
,
2052 "%s failed to register slave as an async device - %d\n",
2054 goto out_no_slave_reg
;
2057 amba_set_drvdata(adev
, pl08x
);
2058 init_pl08x_debugfs(pl08x
);
2059 dev_info(&pl08x
->adev
->dev
, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2060 amba_part(adev
), amba_rev(adev
),
2061 (unsigned long long)adev
->res
.start
, adev
->irq
[0]);
2066 dma_async_device_unregister(&pl08x
->memcpy
);
2068 pl08x_free_virtual_channels(&pl08x
->slave
);
2070 pl08x_free_virtual_channels(&pl08x
->memcpy
);
2072 kfree(pl08x
->phy_chans
);
2074 free_irq(adev
->irq
[0], pl08x
);
2076 iounmap(pl08x
->base
);
2078 dma_pool_destroy(pl08x
->pool
);
2083 amba_release_regions(adev
);
2087 /* PL080 has 8 channels and the PL080 have just 2 */
2088 static struct vendor_data vendor_pl080
= {
2093 static struct vendor_data vendor_nomadik
= {
2099 static struct vendor_data vendor_pl081
= {
2101 .dualmaster
= false,
2104 static struct amba_id pl08x_ids
[] = {
2109 .data
= &vendor_pl080
,
2115 .data
= &vendor_pl081
,
2117 /* Nomadik 8815 PL080 variant */
2121 .data
= &vendor_nomadik
,
2126 MODULE_DEVICE_TABLE(amba
, pl08x_ids
);
2128 static struct amba_driver pl08x_amba_driver
= {
2129 .drv
.name
= DRIVER_NAME
,
2130 .id_table
= pl08x_ids
,
2131 .probe
= pl08x_probe
,
2134 static int __init
pl08x_init(void)
2137 retval
= amba_driver_register(&pl08x_amba_driver
);
2139 printk(KERN_WARNING DRIVER_NAME
2140 "failed to register as an AMBA device (%d)\n",
2144 subsys_initcall(pl08x_init
);