2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <asm/hardware/pl080.h>
88 #include "dmaengine.h"
90 #define DRIVER_NAME "pl08xdmac"
92 static struct amba_driver pl08x_amba_driver
;
93 struct pl08x_driver_data
;
96 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
97 * @channels: the number of channels available in this variant
98 * @dualmaster: whether this version supports dual AHB masters or not.
99 * @nomadik: whether the channels have Nomadik security extension bits
100 * that need to be checked for permission before use and some registers are
110 * PL08X private data structures
111 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
112 * start & end do not - their bus bit info is in cctl. Also note that these
113 * are fixed 32-bit quantities.
123 * struct pl08x_bus_data - information of source or destination
124 * busses for a transfer
125 * @addr: current address
126 * @maxwidth: the maximum width of a transfer on this bus
127 * @buswidth: the width of this bus in bytes: 1, 2 or 4
129 struct pl08x_bus_data
{
136 * struct pl08x_phy_chan - holder for the physical channels
137 * @id: physical index to this channel
138 * @lock: a lock to use when altering an instance of this struct
139 * @serving: the virtual channel currently being served by this physical
141 * @locked: channel unavailable for the system, e.g. dedicated to secure
144 struct pl08x_phy_chan
{
148 struct pl08x_dma_chan
*serving
;
153 * struct pl08x_sg - structure containing data per sg
154 * @src_addr: src address of sg
155 * @dst_addr: dst address of sg
156 * @len: transfer len in bytes
157 * @node: node for txd's dsg_list
163 struct list_head node
;
167 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
168 * @tx: async tx descriptor
169 * @node: node for txd list for channels
170 * @dsg_list: list of children sg's
171 * @llis_bus: DMA memory address (physical) start for the LLIs
172 * @llis_va: virtual memory address start for the LLIs
173 * @cctl: control reg values for current txd
174 * @ccfg: config reg values for current txd
177 struct dma_async_tx_descriptor tx
;
178 struct list_head node
;
179 struct list_head dsg_list
;
181 struct pl08x_lli
*llis_va
;
182 /* Default cctl value for LLIs */
185 * Settings to be put into the physical channel when we
186 * trigger this txd. Other registers are in llis_va[0].
192 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
194 * @PL08X_CHAN_IDLE: the channel is idle
195 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
196 * channel and is running a transfer on it
197 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
198 * channel, but the transfer is currently paused
199 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
200 * channel to become available (only pertains to memcpy channels)
202 enum pl08x_dma_chan_state
{
210 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
211 * @chan: wrappped abstract channel
212 * @phychan: the physical channel utilized by this channel, if there is one
213 * @phychan_hold: if non-zero, hold on to the physical channel even if we
214 * have no pending entries
215 * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
216 * @name: name of channel
217 * @cd: channel platform data
218 * @runtime_addr: address for RX/TX according to the runtime config
219 * @pend_list: queued transactions pending on this channel
220 * @done_list: list of completed transactions
221 * @at: active transaction on this channel
222 * @lock: a lock for this channel data
223 * @host: a pointer to the host (internal use)
224 * @state: whether the channel is idle, paused, running etc
225 * @slave: whether this channel is a device (slave) or for memcpy
226 * @waiting: a TX descriptor on this channel which is waiting for a physical
227 * channel to become available
228 * @signal: the physical DMA request signal which this channel is using
229 * @mux_use: count of descriptors using this DMA request signal setting
231 struct pl08x_dma_chan
{
232 struct dma_chan chan
;
233 struct pl08x_phy_chan
*phychan
;
235 struct tasklet_struct tasklet
;
237 const struct pl08x_channel_data
*cd
;
238 struct dma_slave_config cfg
;
239 struct list_head pend_list
;
240 struct list_head done_list
;
241 struct pl08x_txd
*at
;
243 struct pl08x_driver_data
*host
;
244 enum pl08x_dma_chan_state state
;
246 struct pl08x_txd
*waiting
;
252 * struct pl08x_driver_data - the local state holder for the PL08x
253 * @slave: slave engine for this instance
254 * @memcpy: memcpy engine for this instance
255 * @base: virtual memory base (remapped) for the PL08x
256 * @adev: the corresponding AMBA (PrimeCell) bus entry
257 * @vd: vendor data for this PL08x variant
258 * @pd: platform data passed in from the platform/machine
259 * @phy_chans: array of data for the physical channels
260 * @pool: a pool for the LLI descriptors
261 * @pool_ctr: counter of LLIs in the pool
262 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
264 * @mem_buses: set to indicate memory transfers on AHB2.
265 * @lock: a spinlock for this struct
267 struct pl08x_driver_data
{
268 struct dma_device slave
;
269 struct dma_device memcpy
;
271 struct amba_device
*adev
;
272 const struct vendor_data
*vd
;
273 struct pl08x_platform_data
*pd
;
274 struct pl08x_phy_chan
*phy_chans
;
275 struct dma_pool
*pool
;
282 * PL08X specific defines
285 /* Size (bytes) of each LLI buffer allocated for one transfer */
286 # define PL08X_LLI_TSFR_SIZE 0x2000
288 /* Maximum times we call dma_pool_alloc on this pool without freeing */
289 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
290 #define PL08X_ALIGN 8
292 static inline struct pl08x_dma_chan
*to_pl08x_chan(struct dma_chan
*chan
)
294 return container_of(chan
, struct pl08x_dma_chan
, chan
);
297 static inline struct pl08x_txd
*to_pl08x_txd(struct dma_async_tx_descriptor
*tx
)
299 return container_of(tx
, struct pl08x_txd
, tx
);
305 * This gives us the DMA request input to the PL08x primecell which the
306 * peripheral described by the channel data will be routed to, possibly
307 * via a board/SoC specific external MUX. One important point to note
308 * here is that this does not depend on the physical channel.
310 static int pl08x_request_mux(struct pl08x_dma_chan
*plchan
)
312 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
315 if (plchan
->mux_use
++ == 0 && pd
->get_signal
) {
316 ret
= pd
->get_signal(plchan
->cd
);
322 plchan
->signal
= ret
;
327 static void pl08x_release_mux(struct pl08x_dma_chan
*plchan
)
329 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
331 if (plchan
->signal
>= 0) {
332 WARN_ON(plchan
->mux_use
== 0);
334 if (--plchan
->mux_use
== 0 && pd
->put_signal
) {
335 pd
->put_signal(plchan
->cd
, plchan
->signal
);
342 * Physical channel handling
345 /* Whether a certain channel is busy or not */
346 static int pl08x_phy_channel_busy(struct pl08x_phy_chan
*ch
)
350 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
351 return val
& PL080_CONFIG_ACTIVE
;
355 * Set the initial DMA register values i.e. those for the first LLI
356 * The next LLI pointer and the configuration interrupt bit have
357 * been set when the LLIs were constructed. Poke them into the hardware
358 * and start the transfer.
360 static void pl08x_start_txd(struct pl08x_dma_chan
*plchan
,
361 struct pl08x_txd
*txd
)
363 struct pl08x_driver_data
*pl08x
= plchan
->host
;
364 struct pl08x_phy_chan
*phychan
= plchan
->phychan
;
365 struct pl08x_lli
*lli
= &txd
->llis_va
[0];
370 /* Wait for channel inactive */
371 while (pl08x_phy_channel_busy(phychan
))
374 dev_vdbg(&pl08x
->adev
->dev
,
375 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
376 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
377 phychan
->id
, lli
->src
, lli
->dst
, lli
->lli
, lli
->cctl
,
380 writel(lli
->src
, phychan
->base
+ PL080_CH_SRC_ADDR
);
381 writel(lli
->dst
, phychan
->base
+ PL080_CH_DST_ADDR
);
382 writel(lli
->lli
, phychan
->base
+ PL080_CH_LLI
);
383 writel(lli
->cctl
, phychan
->base
+ PL080_CH_CONTROL
);
384 writel(txd
->ccfg
, phychan
->base
+ PL080_CH_CONFIG
);
386 /* Enable the DMA channel */
387 /* Do not access config register until channel shows as disabled */
388 while (readl(pl08x
->base
+ PL080_EN_CHAN
) & (1 << phychan
->id
))
391 /* Do not access config register until channel shows as inactive */
392 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
393 while ((val
& PL080_CONFIG_ACTIVE
) || (val
& PL080_CONFIG_ENABLE
))
394 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
396 writel(val
| PL080_CONFIG_ENABLE
, phychan
->base
+ PL080_CH_CONFIG
);
400 * Pause the channel by setting the HALT bit.
402 * For M->P transfers, pause the DMAC first and then stop the peripheral -
403 * the FIFO can only drain if the peripheral is still requesting data.
404 * (note: this can still timeout if the DMAC FIFO never drains of data.)
406 * For P->M transfers, disable the peripheral first to stop it filling
407 * the DMAC FIFO, and then pause the DMAC.
409 static void pl08x_pause_phy_chan(struct pl08x_phy_chan
*ch
)
414 /* Set the HALT bit and wait for the FIFO to drain */
415 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
416 val
|= PL080_CONFIG_HALT
;
417 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
419 /* Wait for channel inactive */
420 for (timeout
= 1000; timeout
; timeout
--) {
421 if (!pl08x_phy_channel_busy(ch
))
425 if (pl08x_phy_channel_busy(ch
))
426 pr_err("pl08x: channel%u timeout waiting for pause\n", ch
->id
);
429 static void pl08x_resume_phy_chan(struct pl08x_phy_chan
*ch
)
433 /* Clear the HALT bit */
434 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
435 val
&= ~PL080_CONFIG_HALT
;
436 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
440 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
441 * clears any pending interrupt status. This should not be used for
442 * an on-going transfer, but as a method of shutting down a channel
443 * (eg, when it's no longer used) or terminating a transfer.
445 static void pl08x_terminate_phy_chan(struct pl08x_driver_data
*pl08x
,
446 struct pl08x_phy_chan
*ch
)
448 u32 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
450 val
&= ~(PL080_CONFIG_ENABLE
| PL080_CONFIG_ERR_IRQ_MASK
|
451 PL080_CONFIG_TC_IRQ_MASK
);
453 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
455 writel(1 << ch
->id
, pl08x
->base
+ PL080_ERR_CLEAR
);
456 writel(1 << ch
->id
, pl08x
->base
+ PL080_TC_CLEAR
);
459 static inline u32
get_bytes_in_cctl(u32 cctl
)
461 /* The source width defines the number of bytes */
462 u32 bytes
= cctl
& PL080_CONTROL_TRANSFER_SIZE_MASK
;
464 switch (cctl
>> PL080_CONTROL_SWIDTH_SHIFT
) {
465 case PL080_WIDTH_8BIT
:
467 case PL080_WIDTH_16BIT
:
470 case PL080_WIDTH_32BIT
:
477 /* The channel should be paused when calling this */
478 static u32
pl08x_getbytes_chan(struct pl08x_dma_chan
*plchan
)
480 struct pl08x_phy_chan
*ch
;
481 struct pl08x_txd
*txd
;
485 spin_lock_irqsave(&plchan
->lock
, flags
);
486 ch
= plchan
->phychan
;
490 * Follow the LLIs to get the number of remaining
491 * bytes in the currently active transaction.
494 u32 clli
= readl(ch
->base
+ PL080_CH_LLI
) & ~PL080_LLI_LM_AHB2
;
496 /* First get the remaining bytes in the active transfer */
497 bytes
= get_bytes_in_cctl(readl(ch
->base
+ PL080_CH_CONTROL
));
500 struct pl08x_lli
*llis_va
= txd
->llis_va
;
501 dma_addr_t llis_bus
= txd
->llis_bus
;
504 BUG_ON(clli
< llis_bus
|| clli
>= llis_bus
+
505 sizeof(struct pl08x_lli
) * MAX_NUM_TSFR_LLIS
);
508 * Locate the next LLI - as this is an array,
509 * it's simple maths to find.
511 index
= (clli
- llis_bus
) / sizeof(struct pl08x_lli
);
513 for (; index
< MAX_NUM_TSFR_LLIS
; index
++) {
514 bytes
+= get_bytes_in_cctl(llis_va
[index
].cctl
);
517 * A LLI pointer of 0 terminates the LLI list
519 if (!llis_va
[index
].lli
)
525 /* Sum up all queued transactions */
526 if (!list_empty(&plchan
->pend_list
)) {
527 struct pl08x_txd
*txdi
;
528 list_for_each_entry(txdi
, &plchan
->pend_list
, node
) {
529 struct pl08x_sg
*dsg
;
530 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
535 spin_unlock_irqrestore(&plchan
->lock
, flags
);
541 * Allocate a physical channel for a virtual channel
543 * Try to locate a physical channel to be used for this transfer. If all
544 * are taken return NULL and the requester will have to cope by using
545 * some fallback PIO mode or retrying later.
547 static struct pl08x_phy_chan
*
548 pl08x_get_phy_channel(struct pl08x_driver_data
*pl08x
,
549 struct pl08x_dma_chan
*virt_chan
)
551 struct pl08x_phy_chan
*ch
= NULL
;
555 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
556 ch
= &pl08x
->phy_chans
[i
];
558 spin_lock_irqsave(&ch
->lock
, flags
);
560 if (!ch
->locked
&& !ch
->serving
) {
561 ch
->serving
= virt_chan
;
562 spin_unlock_irqrestore(&ch
->lock
, flags
);
566 spin_unlock_irqrestore(&ch
->lock
, flags
);
569 if (i
== pl08x
->vd
->channels
) {
570 /* No physical channel available, cope with it */
577 static inline void pl08x_put_phy_channel(struct pl08x_driver_data
*pl08x
,
578 struct pl08x_phy_chan
*ch
)
582 spin_lock_irqsave(&ch
->lock
, flags
);
584 /* Stop the channel and clear its interrupts */
585 pl08x_terminate_phy_chan(pl08x
, ch
);
587 /* Mark it as free */
589 spin_unlock_irqrestore(&ch
->lock
, flags
);
596 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded
)
599 case PL080_WIDTH_8BIT
:
601 case PL080_WIDTH_16BIT
:
603 case PL080_WIDTH_32BIT
:
612 static inline u32
pl08x_cctl_bits(u32 cctl
, u8 srcwidth
, u8 dstwidth
,
617 /* Remove all src, dst and transfer size bits */
618 retbits
&= ~PL080_CONTROL_DWIDTH_MASK
;
619 retbits
&= ~PL080_CONTROL_SWIDTH_MASK
;
620 retbits
&= ~PL080_CONTROL_TRANSFER_SIZE_MASK
;
622 /* Then set the bits according to the parameters */
625 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
628 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
631 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
640 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
643 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
646 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
653 retbits
|= tsize
<< PL080_CONTROL_TRANSFER_SIZE_SHIFT
;
657 struct pl08x_lli_build_data
{
658 struct pl08x_txd
*txd
;
659 struct pl08x_bus_data srcbus
;
660 struct pl08x_bus_data dstbus
;
666 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
667 * victim in case src & dest are not similarly aligned. i.e. If after aligning
668 * masters address with width requirements of transfer (by sending few byte by
669 * byte data), slave is still not aligned, then its width will be reduced to
671 * - prefers the destination bus if both available
672 * - prefers bus with fixed address (i.e. peripheral)
674 static void pl08x_choose_master_bus(struct pl08x_lli_build_data
*bd
,
675 struct pl08x_bus_data
**mbus
, struct pl08x_bus_data
**sbus
, u32 cctl
)
677 if (!(cctl
& PL080_CONTROL_DST_INCR
)) {
680 } else if (!(cctl
& PL080_CONTROL_SRC_INCR
)) {
684 if (bd
->dstbus
.buswidth
>= bd
->srcbus
.buswidth
) {
695 * Fills in one LLI for a certain transfer descriptor and advance the counter
697 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data
*bd
,
698 int num_llis
, int len
, u32 cctl
)
700 struct pl08x_lli
*llis_va
= bd
->txd
->llis_va
;
701 dma_addr_t llis_bus
= bd
->txd
->llis_bus
;
703 BUG_ON(num_llis
>= MAX_NUM_TSFR_LLIS
);
705 llis_va
[num_llis
].cctl
= cctl
;
706 llis_va
[num_llis
].src
= bd
->srcbus
.addr
;
707 llis_va
[num_llis
].dst
= bd
->dstbus
.addr
;
708 llis_va
[num_llis
].lli
= llis_bus
+ (num_llis
+ 1) *
709 sizeof(struct pl08x_lli
);
710 llis_va
[num_llis
].lli
|= bd
->lli_bus
;
712 if (cctl
& PL080_CONTROL_SRC_INCR
)
713 bd
->srcbus
.addr
+= len
;
714 if (cctl
& PL080_CONTROL_DST_INCR
)
715 bd
->dstbus
.addr
+= len
;
717 BUG_ON(bd
->remainder
< len
);
719 bd
->remainder
-= len
;
722 static inline void prep_byte_width_lli(struct pl08x_lli_build_data
*bd
,
723 u32
*cctl
, u32 len
, int num_llis
, size_t *total_bytes
)
725 *cctl
= pl08x_cctl_bits(*cctl
, 1, 1, len
);
726 pl08x_fill_lli_for_desc(bd
, num_llis
, len
, *cctl
);
727 (*total_bytes
) += len
;
731 * This fills in the table of LLIs for the transfer descriptor
732 * Note that we assume we never have to change the burst sizes
735 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data
*pl08x
,
736 struct pl08x_txd
*txd
)
738 struct pl08x_bus_data
*mbus
, *sbus
;
739 struct pl08x_lli_build_data bd
;
741 u32 cctl
, early_bytes
= 0;
742 size_t max_bytes_per_lli
, total_bytes
;
743 struct pl08x_lli
*llis_va
;
744 struct pl08x_sg
*dsg
;
746 txd
->llis_va
= dma_pool_alloc(pl08x
->pool
, GFP_NOWAIT
, &txd
->llis_bus
);
748 dev_err(&pl08x
->adev
->dev
, "%s no memory for llis\n", __func__
);
755 bd
.lli_bus
= (pl08x
->lli_buses
& PL08X_AHB2
) ? PL080_LLI_LM_AHB2
: 0;
758 /* Find maximum width of the source bus */
760 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_SWIDTH_MASK
) >>
761 PL080_CONTROL_SWIDTH_SHIFT
);
763 /* Find maximum width of the destination bus */
765 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_DWIDTH_MASK
) >>
766 PL080_CONTROL_DWIDTH_SHIFT
);
768 list_for_each_entry(dsg
, &txd
->dsg_list
, node
) {
772 bd
.srcbus
.addr
= dsg
->src_addr
;
773 bd
.dstbus
.addr
= dsg
->dst_addr
;
774 bd
.remainder
= dsg
->len
;
775 bd
.srcbus
.buswidth
= bd
.srcbus
.maxwidth
;
776 bd
.dstbus
.buswidth
= bd
.dstbus
.maxwidth
;
778 pl08x_choose_master_bus(&bd
, &mbus
, &sbus
, cctl
);
780 dev_vdbg(&pl08x
->adev
->dev
, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
781 bd
.srcbus
.addr
, cctl
& PL080_CONTROL_SRC_INCR
? "+" : "",
783 bd
.dstbus
.addr
, cctl
& PL080_CONTROL_DST_INCR
? "+" : "",
786 dev_vdbg(&pl08x
->adev
->dev
, "mbus=%s sbus=%s\n",
787 mbus
== &bd
.srcbus
? "src" : "dst",
788 sbus
== &bd
.srcbus
? "src" : "dst");
791 * Zero length is only allowed if all these requirements are
793 * - flow controller is peripheral.
794 * - src.addr is aligned to src.width
795 * - dst.addr is aligned to dst.width
797 * sg_len == 1 should be true, as there can be two cases here:
799 * - Memory addresses are contiguous and are not scattered.
800 * Here, Only one sg will be passed by user driver, with
801 * memory address and zero length. We pass this to controller
802 * and after the transfer it will receive the last burst
803 * request from peripheral and so transfer finishes.
805 * - Memory addresses are scattered and are not contiguous.
806 * Here, Obviously as DMA controller doesn't know when a lli's
807 * transfer gets over, it can't load next lli. So in this
808 * case, there has to be an assumption that only one lli is
809 * supported. Thus, we can't have scattered addresses.
812 u32 fc
= (txd
->ccfg
& PL080_CONFIG_FLOW_CONTROL_MASK
) >>
813 PL080_CONFIG_FLOW_CONTROL_SHIFT
;
814 if (!((fc
>= PL080_FLOW_SRC2DST_DST
) &&
815 (fc
<= PL080_FLOW_SRC2DST_SRC
))) {
816 dev_err(&pl08x
->adev
->dev
, "%s sg len can't be zero",
821 if ((bd
.srcbus
.addr
% bd
.srcbus
.buswidth
) ||
822 (bd
.dstbus
.addr
% bd
.dstbus
.buswidth
)) {
823 dev_err(&pl08x
->adev
->dev
,
824 "%s src & dst address must be aligned to src"
825 " & dst width if peripheral is flow controller",
830 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
831 bd
.dstbus
.buswidth
, 0);
832 pl08x_fill_lli_for_desc(&bd
, num_llis
++, 0, cctl
);
837 * Send byte by byte for following cases
838 * - Less than a bus width available
839 * - until master bus is aligned
841 if (bd
.remainder
< mbus
->buswidth
)
842 early_bytes
= bd
.remainder
;
843 else if ((mbus
->addr
) % (mbus
->buswidth
)) {
844 early_bytes
= mbus
->buswidth
- (mbus
->addr
) %
846 if ((bd
.remainder
- early_bytes
) < mbus
->buswidth
)
847 early_bytes
= bd
.remainder
;
851 dev_vdbg(&pl08x
->adev
->dev
,
852 "%s byte width LLIs (remain 0x%08x)\n",
853 __func__
, bd
.remainder
);
854 prep_byte_width_lli(&bd
, &cctl
, early_bytes
, num_llis
++,
861 * - if slave is not then we must set its width down
863 if (sbus
->addr
% sbus
->buswidth
) {
864 dev_dbg(&pl08x
->adev
->dev
,
865 "%s set down bus width to one byte\n",
872 * Bytes transferred = tsize * src width, not
875 max_bytes_per_lli
= bd
.srcbus
.buswidth
*
876 PL080_CONTROL_TRANSFER_SIZE_MASK
;
877 dev_vdbg(&pl08x
->adev
->dev
,
878 "%s max bytes per lli = %zu\n",
879 __func__
, max_bytes_per_lli
);
882 * Make largest possible LLIs until less than one bus
885 while (bd
.remainder
> (mbus
->buswidth
- 1)) {
886 size_t lli_len
, tsize
, width
;
889 * If enough left try to send max possible,
890 * otherwise try to send the remainder
892 lli_len
= min(bd
.remainder
, max_bytes_per_lli
);
895 * Check against maximum bus alignment:
896 * Calculate actual transfer size in relation to
897 * bus width an get a maximum remainder of the
898 * highest bus width - 1
900 width
= max(mbus
->buswidth
, sbus
->buswidth
);
901 lli_len
= (lli_len
/ width
) * width
;
902 tsize
= lli_len
/ bd
.srcbus
.buswidth
;
904 dev_vdbg(&pl08x
->adev
->dev
,
905 "%s fill lli with single lli chunk of "
906 "size 0x%08zx (remainder 0x%08zx)\n",
907 __func__
, lli_len
, bd
.remainder
);
909 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
910 bd
.dstbus
.buswidth
, tsize
);
911 pl08x_fill_lli_for_desc(&bd
, num_llis
++,
913 total_bytes
+= lli_len
;
920 dev_vdbg(&pl08x
->adev
->dev
,
921 "%s align with boundary, send odd bytes (remain %zu)\n",
922 __func__
, bd
.remainder
);
923 prep_byte_width_lli(&bd
, &cctl
, bd
.remainder
,
924 num_llis
++, &total_bytes
);
928 if (total_bytes
!= dsg
->len
) {
929 dev_err(&pl08x
->adev
->dev
,
930 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
931 __func__
, total_bytes
, dsg
->len
);
935 if (num_llis
>= MAX_NUM_TSFR_LLIS
) {
936 dev_err(&pl08x
->adev
->dev
,
937 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
938 __func__
, (u32
) MAX_NUM_TSFR_LLIS
);
943 llis_va
= txd
->llis_va
;
944 /* The final LLI terminates the LLI. */
945 llis_va
[num_llis
- 1].lli
= 0;
946 /* The final LLI element shall also fire an interrupt. */
947 llis_va
[num_llis
- 1].cctl
|= PL080_CONTROL_TC_IRQ_EN
;
953 dev_vdbg(&pl08x
->adev
->dev
,
954 "%-3s %-9s %-10s %-10s %-10s %s\n",
955 "lli", "", "csrc", "cdst", "clli", "cctl");
956 for (i
= 0; i
< num_llis
; i
++) {
957 dev_vdbg(&pl08x
->adev
->dev
,
958 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
959 i
, &llis_va
[i
], llis_va
[i
].src
,
960 llis_va
[i
].dst
, llis_va
[i
].lli
, llis_va
[i
].cctl
969 /* You should call this with the struct pl08x lock held */
970 static void pl08x_free_txd(struct pl08x_driver_data
*pl08x
,
971 struct pl08x_txd
*txd
)
973 struct pl08x_sg
*dsg
, *_dsg
;
977 dma_pool_free(pl08x
->pool
, txd
->llis_va
, txd
->llis_bus
);
981 list_for_each_entry_safe(dsg
, _dsg
, &txd
->dsg_list
, node
) {
982 list_del(&dsg
->node
);
989 static void pl08x_free_txd_list(struct pl08x_driver_data
*pl08x
,
990 struct pl08x_dma_chan
*plchan
)
992 struct pl08x_txd
*txdi
= NULL
;
993 struct pl08x_txd
*next
;
995 if (!list_empty(&plchan
->pend_list
)) {
996 list_for_each_entry_safe(txdi
,
997 next
, &plchan
->pend_list
, node
) {
998 pl08x_release_mux(plchan
);
999 list_del(&txdi
->node
);
1000 pl08x_free_txd(pl08x
, txdi
);
1006 * The DMA ENGINE API
1008 static int pl08x_alloc_chan_resources(struct dma_chan
*chan
)
1013 static void pl08x_free_chan_resources(struct dma_chan
*chan
)
1018 * This should be called with the channel plchan->lock held
1020 static int prep_phy_channel(struct pl08x_dma_chan
*plchan
)
1022 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1023 struct pl08x_phy_chan
*ch
;
1025 /* Check if we already have a channel */
1026 if (plchan
->phychan
) {
1027 ch
= plchan
->phychan
;
1031 ch
= pl08x_get_phy_channel(pl08x
, plchan
);
1033 /* No physical channel available, cope with it */
1034 dev_dbg(&pl08x
->adev
->dev
, "no physical channel available for xfer on %s\n", plchan
->name
);
1038 plchan
->phychan
= ch
;
1039 dev_dbg(&pl08x
->adev
->dev
, "allocated physical channel %d for xfer on %s\n",
1040 ch
->id
, plchan
->name
);
1043 plchan
->phychan_hold
++;
1048 static void release_phy_channel(struct pl08x_dma_chan
*plchan
)
1050 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1052 pl08x_put_phy_channel(pl08x
, plchan
->phychan
);
1053 plchan
->phychan
= NULL
;
1056 static dma_cookie_t
pl08x_tx_submit(struct dma_async_tx_descriptor
*tx
)
1058 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(tx
->chan
);
1059 struct pl08x_txd
*txd
= to_pl08x_txd(tx
);
1060 unsigned long flags
;
1061 dma_cookie_t cookie
;
1063 spin_lock_irqsave(&plchan
->lock
, flags
);
1064 cookie
= dma_cookie_assign(tx
);
1066 /* Put this onto the pending list */
1067 list_add_tail(&txd
->node
, &plchan
->pend_list
);
1070 * If there was no physical channel available for this memcpy,
1071 * stack the request up and indicate that the channel is waiting
1072 * for a free physical channel.
1074 if (!plchan
->slave
&& !plchan
->phychan
) {
1075 /* Do this memcpy whenever there is a channel ready */
1076 plchan
->state
= PL08X_CHAN_WAITING
;
1077 plchan
->waiting
= txd
;
1079 plchan
->phychan_hold
--;
1082 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1087 static struct dma_async_tx_descriptor
*pl08x_prep_dma_interrupt(
1088 struct dma_chan
*chan
, unsigned long flags
)
1090 struct dma_async_tx_descriptor
*retval
= NULL
;
1096 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1097 * If slaves are relying on interrupts to signal completion this function
1098 * must not be called with interrupts disabled.
1100 static enum dma_status
pl08x_dma_tx_status(struct dma_chan
*chan
,
1101 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
1103 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1104 enum dma_status ret
;
1106 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1107 if (ret
== DMA_SUCCESS
)
1111 * This cookie not complete yet
1112 * Get number of bytes left in the active transactions and queue
1114 dma_set_residue(txstate
, pl08x_getbytes_chan(plchan
));
1116 if (plchan
->state
== PL08X_CHAN_PAUSED
)
1119 /* Whether waiting or running, we're in progress */
1120 return DMA_IN_PROGRESS
;
1123 /* PrimeCell DMA extension */
1124 struct burst_table
{
1129 static const struct burst_table burst_sizes
[] = {
1132 .reg
= PL080_BSIZE_256
,
1136 .reg
= PL080_BSIZE_128
,
1140 .reg
= PL080_BSIZE_64
,
1144 .reg
= PL080_BSIZE_32
,
1148 .reg
= PL080_BSIZE_16
,
1152 .reg
= PL080_BSIZE_8
,
1156 .reg
= PL080_BSIZE_4
,
1160 .reg
= PL080_BSIZE_1
,
1165 * Given the source and destination available bus masks, select which
1166 * will be routed to each port. We try to have source and destination
1167 * on separate ports, but always respect the allowable settings.
1169 static u32
pl08x_select_bus(u8 src
, u8 dst
)
1173 if (!(dst
& PL08X_AHB1
) || ((dst
& PL08X_AHB2
) && (src
& PL08X_AHB1
)))
1174 cctl
|= PL080_CONTROL_DST_AHB2
;
1175 if (!(src
& PL08X_AHB1
) || ((src
& PL08X_AHB2
) && !(dst
& PL08X_AHB2
)))
1176 cctl
|= PL080_CONTROL_SRC_AHB2
;
1181 static u32
pl08x_cctl(u32 cctl
)
1183 cctl
&= ~(PL080_CONTROL_SRC_AHB2
| PL080_CONTROL_DST_AHB2
|
1184 PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
|
1185 PL080_CONTROL_PROT_MASK
);
1187 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1188 return cctl
| PL080_CONTROL_PROT_SYS
;
1191 static u32
pl08x_width(enum dma_slave_buswidth width
)
1194 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
1195 return PL080_WIDTH_8BIT
;
1196 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
1197 return PL080_WIDTH_16BIT
;
1198 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
1199 return PL080_WIDTH_32BIT
;
1205 static u32
pl08x_burst(u32 maxburst
)
1209 for (i
= 0; i
< ARRAY_SIZE(burst_sizes
); i
++)
1210 if (burst_sizes
[i
].burstwords
<= maxburst
)
1213 return burst_sizes
[i
].reg
;
1216 static u32
pl08x_get_cctl(struct pl08x_dma_chan
*plchan
,
1217 enum dma_slave_buswidth addr_width
, u32 maxburst
)
1219 u32 width
, burst
, cctl
= 0;
1221 width
= pl08x_width(addr_width
);
1225 cctl
|= width
<< PL080_CONTROL_SWIDTH_SHIFT
;
1226 cctl
|= width
<< PL080_CONTROL_DWIDTH_SHIFT
;
1229 * If this channel will only request single transfers, set this
1230 * down to ONE element. Also select one element if no maxburst
1233 if (plchan
->cd
->single
)
1236 burst
= pl08x_burst(maxburst
);
1237 cctl
|= burst
<< PL080_CONTROL_SB_SIZE_SHIFT
;
1238 cctl
|= burst
<< PL080_CONTROL_DB_SIZE_SHIFT
;
1240 return pl08x_cctl(cctl
);
1243 static int dma_set_runtime_config(struct dma_chan
*chan
,
1244 struct dma_slave_config
*config
)
1246 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1251 /* Reject definitely invalid configurations */
1252 if (config
->src_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
||
1253 config
->dst_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
)
1256 plchan
->cfg
= *config
;
1262 * Slave transactions callback to the slave device to allow
1263 * synchronization of slave DMA signals with the DMAC enable
1265 static void pl08x_issue_pending(struct dma_chan
*chan
)
1267 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1268 unsigned long flags
;
1270 spin_lock_irqsave(&plchan
->lock
, flags
);
1271 /* Something is already active, or we're waiting for a channel... */
1272 if (plchan
->at
|| plchan
->state
== PL08X_CHAN_WAITING
) {
1273 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1277 /* Take the first element in the queue and execute it */
1278 if (!list_empty(&plchan
->pend_list
)) {
1279 struct pl08x_txd
*next
;
1281 next
= list_first_entry(&plchan
->pend_list
,
1284 list_del(&next
->node
);
1285 plchan
->state
= PL08X_CHAN_RUNNING
;
1287 pl08x_start_txd(plchan
, next
);
1290 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1293 static int pl08x_prep_channel_resources(struct pl08x_dma_chan
*plchan
,
1294 struct pl08x_txd
*txd
)
1296 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1297 unsigned long flags
;
1300 num_llis
= pl08x_fill_llis_for_desc(pl08x
, txd
);
1302 spin_lock_irqsave(&plchan
->lock
, flags
);
1303 pl08x_free_txd(pl08x
, txd
);
1304 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1308 spin_lock_irqsave(&plchan
->lock
, flags
);
1311 * See if we already have a physical channel allocated,
1312 * else this is the time to try to get one.
1314 ret
= prep_phy_channel(plchan
);
1317 * No physical channel was available.
1319 * memcpy transfers can be sorted out at submission time.
1321 if (plchan
->slave
) {
1322 pl08x_free_txd_list(pl08x
, plchan
);
1323 pl08x_free_txd(pl08x
, txd
);
1324 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1329 * Else we're all set, paused and ready to roll, status
1330 * will switch to PL08X_CHAN_RUNNING when we call
1331 * issue_pending(). If there is something running on the
1332 * channel already we don't change its state.
1334 if (plchan
->state
== PL08X_CHAN_IDLE
)
1335 plchan
->state
= PL08X_CHAN_PAUSED
;
1337 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1342 static struct pl08x_txd
*pl08x_get_txd(struct pl08x_dma_chan
*plchan
,
1343 unsigned long flags
)
1345 struct pl08x_txd
*txd
= kzalloc(sizeof(*txd
), GFP_NOWAIT
);
1348 dma_async_tx_descriptor_init(&txd
->tx
, &plchan
->chan
);
1349 txd
->tx
.flags
= flags
;
1350 txd
->tx
.tx_submit
= pl08x_tx_submit
;
1351 INIT_LIST_HEAD(&txd
->node
);
1352 INIT_LIST_HEAD(&txd
->dsg_list
);
1354 /* Always enable error and terminal interrupts */
1355 txd
->ccfg
= PL080_CONFIG_ERR_IRQ_MASK
|
1356 PL080_CONFIG_TC_IRQ_MASK
;
1362 * Initialize a descriptor to be used by memcpy submit
1364 static struct dma_async_tx_descriptor
*pl08x_prep_dma_memcpy(
1365 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1366 size_t len
, unsigned long flags
)
1368 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1369 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1370 struct pl08x_txd
*txd
;
1371 struct pl08x_sg
*dsg
;
1374 txd
= pl08x_get_txd(plchan
, flags
);
1376 dev_err(&pl08x
->adev
->dev
,
1377 "%s no memory for descriptor\n", __func__
);
1381 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1383 pl08x_free_txd(pl08x
, txd
);
1384 dev_err(&pl08x
->adev
->dev
, "%s no memory for pl080 sg\n",
1388 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1390 dsg
->src_addr
= src
;
1391 dsg
->dst_addr
= dest
;
1394 /* Set platform data for m2m */
1395 txd
->ccfg
|= PL080_FLOW_MEM2MEM
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1396 txd
->cctl
= pl08x
->pd
->memcpy_channel
.cctl_memcpy
&
1397 ~(PL080_CONTROL_DST_AHB2
| PL080_CONTROL_SRC_AHB2
);
1399 /* Both to be incremented or the code will break */
1400 txd
->cctl
|= PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
;
1402 if (pl08x
->vd
->dualmaster
)
1403 txd
->cctl
|= pl08x_select_bus(pl08x
->mem_buses
,
1406 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1413 static struct dma_async_tx_descriptor
*pl08x_prep_slave_sg(
1414 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1415 unsigned int sg_len
, enum dma_transfer_direction direction
,
1416 unsigned long flags
, void *context
)
1418 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1419 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1420 struct pl08x_txd
*txd
;
1421 struct pl08x_sg
*dsg
;
1422 struct scatterlist
*sg
;
1423 enum dma_slave_buswidth addr_width
;
1424 dma_addr_t slave_addr
;
1426 u8 src_buses
, dst_buses
;
1429 dev_dbg(&pl08x
->adev
->dev
, "%s prepare transaction of %d bytes from %s\n",
1430 __func__
, sg_dma_len(sgl
), plchan
->name
);
1432 txd
= pl08x_get_txd(plchan
, flags
);
1434 dev_err(&pl08x
->adev
->dev
, "%s no txd\n", __func__
);
1439 * Set up addresses, the PrimeCell configured address
1440 * will take precedence since this may configure the
1441 * channel target address dynamically at runtime.
1443 if (direction
== DMA_MEM_TO_DEV
) {
1444 cctl
= PL080_CONTROL_SRC_INCR
;
1445 slave_addr
= plchan
->cfg
.dst_addr
;
1446 addr_width
= plchan
->cfg
.dst_addr_width
;
1447 maxburst
= plchan
->cfg
.dst_maxburst
;
1448 src_buses
= pl08x
->mem_buses
;
1449 dst_buses
= plchan
->cd
->periph_buses
;
1450 } else if (direction
== DMA_DEV_TO_MEM
) {
1451 cctl
= PL080_CONTROL_DST_INCR
;
1452 slave_addr
= plchan
->cfg
.src_addr
;
1453 addr_width
= plchan
->cfg
.src_addr_width
;
1454 maxburst
= plchan
->cfg
.src_maxburst
;
1455 src_buses
= plchan
->cd
->periph_buses
;
1456 dst_buses
= pl08x
->mem_buses
;
1458 pl08x_free_txd(pl08x
, txd
);
1459 dev_err(&pl08x
->adev
->dev
,
1460 "%s direction unsupported\n", __func__
);
1464 cctl
|= pl08x_get_cctl(plchan
, addr_width
, maxburst
);
1466 pl08x_free_txd(pl08x
, txd
);
1467 dev_err(&pl08x
->adev
->dev
,
1468 "DMA slave configuration botched?\n");
1472 txd
->cctl
= cctl
| pl08x_select_bus(src_buses
, dst_buses
);
1474 if (plchan
->cfg
.device_fc
)
1475 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER_PER
:
1476 PL080_FLOW_PER2MEM_PER
;
1478 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER
:
1481 txd
->ccfg
|= tmp
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1483 ret
= pl08x_request_mux(plchan
);
1485 pl08x_free_txd(pl08x
, txd
);
1486 dev_dbg(&pl08x
->adev
->dev
,
1487 "unable to mux for transfer on %s due to platform restrictions\n",
1492 dev_dbg(&pl08x
->adev
->dev
, "allocated DMA request signal %d for xfer on %s\n",
1493 plchan
->signal
, plchan
->name
);
1495 /* Assign the flow control signal to this channel */
1496 if (direction
== DMA_MEM_TO_DEV
)
1497 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_DST_SEL_SHIFT
;
1499 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_SRC_SEL_SHIFT
;
1501 for_each_sg(sgl
, sg
, sg_len
, tmp
) {
1502 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1504 pl08x_release_mux(plchan
);
1505 pl08x_free_txd(pl08x
, txd
);
1506 dev_err(&pl08x
->adev
->dev
, "%s no mem for pl080 sg\n",
1510 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1512 dsg
->len
= sg_dma_len(sg
);
1513 if (direction
== DMA_MEM_TO_DEV
) {
1514 dsg
->src_addr
= sg_dma_address(sg
);
1515 dsg
->dst_addr
= slave_addr
;
1517 dsg
->src_addr
= slave_addr
;
1518 dsg
->dst_addr
= sg_dma_address(sg
);
1522 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1529 static int pl08x_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1532 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1533 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1534 unsigned long flags
;
1537 /* Controls applicable to inactive channels */
1538 if (cmd
== DMA_SLAVE_CONFIG
) {
1539 return dma_set_runtime_config(chan
,
1540 (struct dma_slave_config
*)arg
);
1544 * Anything succeeds on channels with no physical allocation and
1545 * no queued transfers.
1547 spin_lock_irqsave(&plchan
->lock
, flags
);
1548 if (!plchan
->phychan
&& !plchan
->at
) {
1549 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1554 case DMA_TERMINATE_ALL
:
1555 plchan
->state
= PL08X_CHAN_IDLE
;
1557 if (plchan
->phychan
) {
1558 pl08x_terminate_phy_chan(pl08x
, plchan
->phychan
);
1561 * Mark physical channel as free and free any slave
1564 release_phy_channel(plchan
);
1565 plchan
->phychan_hold
= 0;
1567 /* Dequeue jobs and free LLIs */
1569 /* Killing this one off, release its mux */
1570 pl08x_release_mux(plchan
);
1571 pl08x_free_txd(pl08x
, plchan
->at
);
1574 /* Dequeue jobs not yet fired as well */
1575 pl08x_free_txd_list(pl08x
, plchan
);
1578 pl08x_pause_phy_chan(plchan
->phychan
);
1579 plchan
->state
= PL08X_CHAN_PAUSED
;
1582 pl08x_resume_phy_chan(plchan
->phychan
);
1583 plchan
->state
= PL08X_CHAN_RUNNING
;
1586 /* Unknown command */
1591 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1596 bool pl08x_filter_id(struct dma_chan
*chan
, void *chan_id
)
1598 struct pl08x_dma_chan
*plchan
;
1599 char *name
= chan_id
;
1601 /* Reject channels for devices not bound to this driver */
1602 if (chan
->device
->dev
->driver
!= &pl08x_amba_driver
.drv
)
1605 plchan
= to_pl08x_chan(chan
);
1607 /* Check that the channel is not taken! */
1608 if (!strcmp(plchan
->name
, name
))
1615 * Just check that the device is there and active
1616 * TODO: turn this bit on/off depending on the number of physical channels
1617 * actually used, if it is zero... well shut it off. That will save some
1618 * power. Cut the clock at the same time.
1620 static void pl08x_ensure_on(struct pl08x_driver_data
*pl08x
)
1622 /* The Nomadik variant does not have the config register */
1623 if (pl08x
->vd
->nomadik
)
1625 writel(PL080_CONFIG_ENABLE
, pl08x
->base
+ PL080_CONFIG
);
1628 static void pl08x_unmap_buffers(struct pl08x_txd
*txd
)
1630 struct device
*dev
= txd
->tx
.chan
->device
->dev
;
1631 struct pl08x_sg
*dsg
;
1633 if (!(txd
->tx
.flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
1634 if (txd
->tx
.flags
& DMA_COMPL_SRC_UNMAP_SINGLE
)
1635 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1636 dma_unmap_single(dev
, dsg
->src_addr
, dsg
->len
,
1639 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1640 dma_unmap_page(dev
, dsg
->src_addr
, dsg
->len
,
1644 if (!(txd
->tx
.flags
& DMA_COMPL_SKIP_DEST_UNMAP
)) {
1645 if (txd
->tx
.flags
& DMA_COMPL_DEST_UNMAP_SINGLE
)
1646 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1647 dma_unmap_single(dev
, dsg
->dst_addr
, dsg
->len
,
1650 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1651 dma_unmap_page(dev
, dsg
->dst_addr
, dsg
->len
,
1656 static void pl08x_tasklet(unsigned long data
)
1658 struct pl08x_dma_chan
*plchan
= (struct pl08x_dma_chan
*) data
;
1659 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1660 unsigned long flags
;
1663 spin_lock_irqsave(&plchan
->lock
, flags
);
1664 list_splice_tail_init(&plchan
->done_list
, &head
);
1666 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1667 if (!list_empty(&plchan
->pend_list
)) {
1668 struct pl08x_txd
*next
;
1670 next
= list_first_entry(&plchan
->pend_list
,
1673 list_del(&next
->node
);
1675 pl08x_start_txd(plchan
, next
);
1676 } else if (plchan
->phychan_hold
) {
1678 * This channel is still in use - we have a new txd being
1679 * prepared and will soon be queued. Don't give up the
1683 struct pl08x_dma_chan
*waiting
= NULL
;
1686 * No more jobs, so free up the physical channel
1688 release_phy_channel(plchan
);
1689 plchan
->state
= PL08X_CHAN_IDLE
;
1692 * And NOW before anyone else can grab that free:d up
1693 * physical channel, see if there is some memcpy pending
1694 * that seriously needs to start because of being stacked
1695 * up while we were choking the physical channels with data.
1697 list_for_each_entry(waiting
, &pl08x
->memcpy
.channels
,
1699 if (waiting
->state
== PL08X_CHAN_WAITING
&&
1700 waiting
->waiting
!= NULL
) {
1703 /* This should REALLY not fail now */
1704 ret
= prep_phy_channel(waiting
);
1706 waiting
->phychan_hold
--;
1707 waiting
->state
= PL08X_CHAN_RUNNING
;
1708 waiting
->waiting
= NULL
;
1709 pl08x_issue_pending(&waiting
->chan
);
1715 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1717 while (!list_empty(&head
)) {
1718 struct pl08x_txd
*txd
= list_first_entry(&head
,
1719 struct pl08x_txd
, node
);
1720 dma_async_tx_callback callback
= txd
->tx
.callback
;
1721 void *callback_param
= txd
->tx
.callback_param
;
1723 list_del(&txd
->node
);
1725 /* Don't try to unmap buffers on slave channels */
1727 pl08x_unmap_buffers(txd
);
1729 /* Free the descriptor */
1730 spin_lock_irqsave(&plchan
->lock
, flags
);
1731 pl08x_free_txd(pl08x
, txd
);
1732 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1734 /* Callback to signal completion */
1736 callback(callback_param
);
1740 static irqreturn_t
pl08x_irq(int irq
, void *dev
)
1742 struct pl08x_driver_data
*pl08x
= dev
;
1743 u32 mask
= 0, err
, tc
, i
;
1745 /* check & clear - ERR & TC interrupts */
1746 err
= readl(pl08x
->base
+ PL080_ERR_STATUS
);
1748 dev_err(&pl08x
->adev
->dev
, "%s error interrupt, register value 0x%08x\n",
1750 writel(err
, pl08x
->base
+ PL080_ERR_CLEAR
);
1752 tc
= readl(pl08x
->base
+ PL080_TC_STATUS
);
1754 writel(tc
, pl08x
->base
+ PL080_TC_CLEAR
);
1759 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1760 if (((1 << i
) & err
) || ((1 << i
) & tc
)) {
1761 /* Locate physical channel */
1762 struct pl08x_phy_chan
*phychan
= &pl08x
->phy_chans
[i
];
1763 struct pl08x_dma_chan
*plchan
= phychan
->serving
;
1764 struct pl08x_txd
*tx
;
1767 dev_err(&pl08x
->adev
->dev
,
1768 "%s Error TC interrupt on unused channel: 0x%08x\n",
1773 spin_lock(&plchan
->lock
);
1778 * This descriptor is done, release its mux
1781 pl08x_release_mux(plchan
);
1782 dma_cookie_complete(&tx
->tx
);
1783 list_add_tail(&tx
->node
, &plchan
->done_list
);
1785 spin_unlock(&plchan
->lock
);
1787 /* Schedule tasklet on this channel */
1788 tasklet_schedule(&plchan
->tasklet
);
1793 return mask
? IRQ_HANDLED
: IRQ_NONE
;
1796 static void pl08x_dma_slave_init(struct pl08x_dma_chan
*chan
)
1799 chan
->name
= chan
->cd
->bus_id
;
1800 chan
->cfg
.src_addr
= chan
->cd
->addr
;
1801 chan
->cfg
.dst_addr
= chan
->cd
->addr
;
1805 * Initialise the DMAC memcpy/slave channels.
1806 * Make a local wrapper to hold required data
1808 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data
*pl08x
,
1809 struct dma_device
*dmadev
, unsigned int channels
, bool slave
)
1811 struct pl08x_dma_chan
*chan
;
1814 INIT_LIST_HEAD(&dmadev
->channels
);
1817 * Register as many many memcpy as we have physical channels,
1818 * we won't always be able to use all but the code will have
1819 * to cope with that situation.
1821 for (i
= 0; i
< channels
; i
++) {
1822 chan
= kzalloc(sizeof(*chan
), GFP_KERNEL
);
1824 dev_err(&pl08x
->adev
->dev
,
1825 "%s no memory for channel\n", __func__
);
1830 chan
->state
= PL08X_CHAN_IDLE
;
1834 chan
->cd
= &pl08x
->pd
->slave_channels
[i
];
1835 pl08x_dma_slave_init(chan
);
1837 chan
->cd
= &pl08x
->pd
->memcpy_channel
;
1838 chan
->name
= kasprintf(GFP_KERNEL
, "memcpy%d", i
);
1844 dev_dbg(&pl08x
->adev
->dev
,
1845 "initialize virtual channel \"%s\"\n",
1848 chan
->chan
.device
= dmadev
;
1849 dma_cookie_init(&chan
->chan
);
1851 spin_lock_init(&chan
->lock
);
1852 INIT_LIST_HEAD(&chan
->pend_list
);
1853 INIT_LIST_HEAD(&chan
->done_list
);
1854 tasklet_init(&chan
->tasklet
, pl08x_tasklet
,
1855 (unsigned long) chan
);
1857 list_add_tail(&chan
->chan
.device_node
, &dmadev
->channels
);
1859 dev_info(&pl08x
->adev
->dev
, "initialized %d virtual %s channels\n",
1860 i
, slave
? "slave" : "memcpy");
1864 static void pl08x_free_virtual_channels(struct dma_device
*dmadev
)
1866 struct pl08x_dma_chan
*chan
= NULL
;
1867 struct pl08x_dma_chan
*next
;
1869 list_for_each_entry_safe(chan
,
1870 next
, &dmadev
->channels
, chan
.device_node
) {
1871 list_del(&chan
->chan
.device_node
);
1876 #ifdef CONFIG_DEBUG_FS
1877 static const char *pl08x_state_str(enum pl08x_dma_chan_state state
)
1880 case PL08X_CHAN_IDLE
:
1882 case PL08X_CHAN_RUNNING
:
1884 case PL08X_CHAN_PAUSED
:
1886 case PL08X_CHAN_WAITING
:
1891 return "UNKNOWN STATE";
1894 static int pl08x_debugfs_show(struct seq_file
*s
, void *data
)
1896 struct pl08x_driver_data
*pl08x
= s
->private;
1897 struct pl08x_dma_chan
*chan
;
1898 struct pl08x_phy_chan
*ch
;
1899 unsigned long flags
;
1902 seq_printf(s
, "PL08x physical channels:\n");
1903 seq_printf(s
, "CHANNEL:\tUSER:\n");
1904 seq_printf(s
, "--------\t-----\n");
1905 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1906 struct pl08x_dma_chan
*virt_chan
;
1908 ch
= &pl08x
->phy_chans
[i
];
1910 spin_lock_irqsave(&ch
->lock
, flags
);
1911 virt_chan
= ch
->serving
;
1913 seq_printf(s
, "%d\t\t%s%s\n",
1915 virt_chan
? virt_chan
->name
: "(none)",
1916 ch
->locked
? " LOCKED" : "");
1918 spin_unlock_irqrestore(&ch
->lock
, flags
);
1921 seq_printf(s
, "\nPL08x virtual memcpy channels:\n");
1922 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1923 seq_printf(s
, "--------\t------\n");
1924 list_for_each_entry(chan
, &pl08x
->memcpy
.channels
, chan
.device_node
) {
1925 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1926 pl08x_state_str(chan
->state
));
1929 seq_printf(s
, "\nPL08x virtual slave channels:\n");
1930 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1931 seq_printf(s
, "--------\t------\n");
1932 list_for_each_entry(chan
, &pl08x
->slave
.channels
, chan
.device_node
) {
1933 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1934 pl08x_state_str(chan
->state
));
1940 static int pl08x_debugfs_open(struct inode
*inode
, struct file
*file
)
1942 return single_open(file
, pl08x_debugfs_show
, inode
->i_private
);
1945 static const struct file_operations pl08x_debugfs_operations
= {
1946 .open
= pl08x_debugfs_open
,
1948 .llseek
= seq_lseek
,
1949 .release
= single_release
,
1952 static void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1954 /* Expose a simple debugfs interface to view all clocks */
1955 (void) debugfs_create_file(dev_name(&pl08x
->adev
->dev
),
1956 S_IFREG
| S_IRUGO
, NULL
, pl08x
,
1957 &pl08x_debugfs_operations
);
1961 static inline void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1966 static int pl08x_probe(struct amba_device
*adev
, const struct amba_id
*id
)
1968 struct pl08x_driver_data
*pl08x
;
1969 const struct vendor_data
*vd
= id
->data
;
1973 ret
= amba_request_regions(adev
, NULL
);
1977 /* Create the driver state holder */
1978 pl08x
= kzalloc(sizeof(*pl08x
), GFP_KERNEL
);
1984 /* Initialize memcpy engine */
1985 dma_cap_set(DMA_MEMCPY
, pl08x
->memcpy
.cap_mask
);
1986 pl08x
->memcpy
.dev
= &adev
->dev
;
1987 pl08x
->memcpy
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1988 pl08x
->memcpy
.device_free_chan_resources
= pl08x_free_chan_resources
;
1989 pl08x
->memcpy
.device_prep_dma_memcpy
= pl08x_prep_dma_memcpy
;
1990 pl08x
->memcpy
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1991 pl08x
->memcpy
.device_tx_status
= pl08x_dma_tx_status
;
1992 pl08x
->memcpy
.device_issue_pending
= pl08x_issue_pending
;
1993 pl08x
->memcpy
.device_control
= pl08x_control
;
1995 /* Initialize slave engine */
1996 dma_cap_set(DMA_SLAVE
, pl08x
->slave
.cap_mask
);
1997 pl08x
->slave
.dev
= &adev
->dev
;
1998 pl08x
->slave
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1999 pl08x
->slave
.device_free_chan_resources
= pl08x_free_chan_resources
;
2000 pl08x
->slave
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
2001 pl08x
->slave
.device_tx_status
= pl08x_dma_tx_status
;
2002 pl08x
->slave
.device_issue_pending
= pl08x_issue_pending
;
2003 pl08x
->slave
.device_prep_slave_sg
= pl08x_prep_slave_sg
;
2004 pl08x
->slave
.device_control
= pl08x_control
;
2006 /* Get the platform data */
2007 pl08x
->pd
= dev_get_platdata(&adev
->dev
);
2009 dev_err(&adev
->dev
, "no platform data supplied\n");
2010 goto out_no_platdata
;
2013 /* Assign useful pointers to the driver state */
2017 /* By default, AHB1 only. If dualmaster, from platform */
2018 pl08x
->lli_buses
= PL08X_AHB1
;
2019 pl08x
->mem_buses
= PL08X_AHB1
;
2020 if (pl08x
->vd
->dualmaster
) {
2021 pl08x
->lli_buses
= pl08x
->pd
->lli_buses
;
2022 pl08x
->mem_buses
= pl08x
->pd
->mem_buses
;
2025 /* A DMA memory pool for LLIs, align on 1-byte boundary */
2026 pl08x
->pool
= dma_pool_create(DRIVER_NAME
, &pl08x
->adev
->dev
,
2027 PL08X_LLI_TSFR_SIZE
, PL08X_ALIGN
, 0);
2030 goto out_no_lli_pool
;
2033 pl08x
->base
= ioremap(adev
->res
.start
, resource_size(&adev
->res
));
2036 goto out_no_ioremap
;
2039 /* Turn on the PL08x */
2040 pl08x_ensure_on(pl08x
);
2042 /* Attach the interrupt handler */
2043 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
2044 writel(0x000000FF, pl08x
->base
+ PL080_TC_CLEAR
);
2046 ret
= request_irq(adev
->irq
[0], pl08x_irq
, IRQF_DISABLED
,
2047 DRIVER_NAME
, pl08x
);
2049 dev_err(&adev
->dev
, "%s failed to request interrupt %d\n",
2050 __func__
, adev
->irq
[0]);
2054 /* Initialize physical channels */
2055 pl08x
->phy_chans
= kzalloc((vd
->channels
* sizeof(*pl08x
->phy_chans
)),
2057 if (!pl08x
->phy_chans
) {
2058 dev_err(&adev
->dev
, "%s failed to allocate "
2059 "physical channel holders\n",
2061 goto out_no_phychans
;
2064 for (i
= 0; i
< vd
->channels
; i
++) {
2065 struct pl08x_phy_chan
*ch
= &pl08x
->phy_chans
[i
];
2068 ch
->base
= pl08x
->base
+ PL080_Cx_BASE(i
);
2069 spin_lock_init(&ch
->lock
);
2072 * Nomadik variants can have channels that are locked
2073 * down for the secure world only. Lock up these channels
2074 * by perpetually serving a dummy virtual channel.
2079 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
2080 if (val
& (PL080N_CONFIG_ITPROT
| PL080N_CONFIG_SECPROT
)) {
2081 dev_info(&adev
->dev
, "physical channel %d reserved for secure access only\n", i
);
2086 dev_dbg(&adev
->dev
, "physical channel %d is %s\n",
2087 i
, pl08x_phy_channel_busy(ch
) ? "BUSY" : "FREE");
2090 /* Register as many memcpy channels as there are physical channels */
2091 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->memcpy
,
2092 pl08x
->vd
->channels
, false);
2094 dev_warn(&pl08x
->adev
->dev
,
2095 "%s failed to enumerate memcpy channels - %d\n",
2099 pl08x
->memcpy
.chancnt
= ret
;
2101 /* Register slave channels */
2102 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->slave
,
2103 pl08x
->pd
->num_slave_channels
, true);
2105 dev_warn(&pl08x
->adev
->dev
,
2106 "%s failed to enumerate slave channels - %d\n",
2110 pl08x
->slave
.chancnt
= ret
;
2112 ret
= dma_async_device_register(&pl08x
->memcpy
);
2114 dev_warn(&pl08x
->adev
->dev
,
2115 "%s failed to register memcpy as an async device - %d\n",
2117 goto out_no_memcpy_reg
;
2120 ret
= dma_async_device_register(&pl08x
->slave
);
2122 dev_warn(&pl08x
->adev
->dev
,
2123 "%s failed to register slave as an async device - %d\n",
2125 goto out_no_slave_reg
;
2128 amba_set_drvdata(adev
, pl08x
);
2129 init_pl08x_debugfs(pl08x
);
2130 dev_info(&pl08x
->adev
->dev
, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2131 amba_part(adev
), amba_rev(adev
),
2132 (unsigned long long)adev
->res
.start
, adev
->irq
[0]);
2137 dma_async_device_unregister(&pl08x
->memcpy
);
2139 pl08x_free_virtual_channels(&pl08x
->slave
);
2141 pl08x_free_virtual_channels(&pl08x
->memcpy
);
2143 kfree(pl08x
->phy_chans
);
2145 free_irq(adev
->irq
[0], pl08x
);
2147 iounmap(pl08x
->base
);
2149 dma_pool_destroy(pl08x
->pool
);
2154 amba_release_regions(adev
);
2158 /* PL080 has 8 channels and the PL080 have just 2 */
2159 static struct vendor_data vendor_pl080
= {
2164 static struct vendor_data vendor_nomadik
= {
2170 static struct vendor_data vendor_pl081
= {
2172 .dualmaster
= false,
2175 static struct amba_id pl08x_ids
[] = {
2180 .data
= &vendor_pl080
,
2186 .data
= &vendor_pl081
,
2188 /* Nomadik 8815 PL080 variant */
2192 .data
= &vendor_nomadik
,
2197 MODULE_DEVICE_TABLE(amba
, pl08x_ids
);
2199 static struct amba_driver pl08x_amba_driver
= {
2200 .drv
.name
= DRIVER_NAME
,
2201 .id_table
= pl08x_ids
,
2202 .probe
= pl08x_probe
,
2205 static int __init
pl08x_init(void)
2208 retval
= amba_driver_register(&pl08x_amba_driver
);
2210 printk(KERN_WARNING DRIVER_NAME
2211 "failed to register as an AMBA device (%d)\n",
2215 subsys_initcall(pl08x_init
);