2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <asm/hardware/pl080.h>
88 #include "dmaengine.h"
90 #define DRIVER_NAME "pl08xdmac"
92 static struct amba_driver pl08x_amba_driver
;
93 struct pl08x_driver_data
;
96 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
97 * @channels: the number of channels available in this variant
98 * @dualmaster: whether this version supports dual AHB masters or not.
99 * @nomadik: whether the channels have Nomadik security extension bits
100 * that need to be checked for permission before use and some registers are
110 * PL08X private data structures
111 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
112 * start & end do not - their bus bit info is in cctl. Also note that these
113 * are fixed 32-bit quantities.
123 * struct pl08x_bus_data - information of source or destination
124 * busses for a transfer
125 * @addr: current address
126 * @maxwidth: the maximum width of a transfer on this bus
127 * @buswidth: the width of this bus in bytes: 1, 2 or 4
129 struct pl08x_bus_data
{
136 * struct pl08x_phy_chan - holder for the physical channels
137 * @id: physical index to this channel
138 * @lock: a lock to use when altering an instance of this struct
139 * @serving: the virtual channel currently being served by this physical
141 * @locked: channel unavailable for the system, e.g. dedicated to secure
144 struct pl08x_phy_chan
{
148 struct pl08x_dma_chan
*serving
;
153 * struct pl08x_sg - structure containing data per sg
154 * @src_addr: src address of sg
155 * @dst_addr: dst address of sg
156 * @len: transfer len in bytes
157 * @node: node for txd's dsg_list
163 struct list_head node
;
167 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
168 * @tx: async tx descriptor
169 * @node: node for txd list for channels
170 * @dsg_list: list of children sg's
171 * @llis_bus: DMA memory address (physical) start for the LLIs
172 * @llis_va: virtual memory address start for the LLIs
173 * @cctl: control reg values for current txd
174 * @ccfg: config reg values for current txd
177 struct dma_async_tx_descriptor tx
;
178 struct list_head node
;
179 struct list_head dsg_list
;
181 struct pl08x_lli
*llis_va
;
182 /* Default cctl value for LLIs */
185 * Settings to be put into the physical channel when we
186 * trigger this txd. Other registers are in llis_va[0].
192 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
194 * @PL08X_CHAN_IDLE: the channel is idle
195 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
196 * channel and is running a transfer on it
197 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
198 * channel, but the transfer is currently paused
199 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
200 * channel to become available (only pertains to memcpy channels)
202 enum pl08x_dma_chan_state
{
210 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
211 * @chan: wrappped abstract channel
212 * @phychan: the physical channel utilized by this channel, if there is one
213 * @phychan_hold: if non-zero, hold on to the physical channel even if we
214 * have no pending entries
215 * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
216 * @name: name of channel
217 * @cd: channel platform data
218 * @runtime_addr: address for RX/TX according to the runtime config
219 * @pend_list: queued transactions pending on this channel
220 * @done_list: list of completed transactions
221 * @at: active transaction on this channel
222 * @lock: a lock for this channel data
223 * @host: a pointer to the host (internal use)
224 * @state: whether the channel is idle, paused, running etc
225 * @slave: whether this channel is a device (slave) or for memcpy
226 * @signal: the physical DMA request signal which this channel is using
227 * @mux_use: count of descriptors using this DMA request signal setting
229 struct pl08x_dma_chan
{
230 struct dma_chan chan
;
231 struct pl08x_phy_chan
*phychan
;
233 struct tasklet_struct tasklet
;
235 const struct pl08x_channel_data
*cd
;
236 struct dma_slave_config cfg
;
237 struct list_head pend_list
;
238 struct list_head done_list
;
239 struct pl08x_txd
*at
;
241 struct pl08x_driver_data
*host
;
242 enum pl08x_dma_chan_state state
;
249 * struct pl08x_driver_data - the local state holder for the PL08x
250 * @slave: slave engine for this instance
251 * @memcpy: memcpy engine for this instance
252 * @base: virtual memory base (remapped) for the PL08x
253 * @adev: the corresponding AMBA (PrimeCell) bus entry
254 * @vd: vendor data for this PL08x variant
255 * @pd: platform data passed in from the platform/machine
256 * @phy_chans: array of data for the physical channels
257 * @pool: a pool for the LLI descriptors
258 * @pool_ctr: counter of LLIs in the pool
259 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
261 * @mem_buses: set to indicate memory transfers on AHB2.
262 * @lock: a spinlock for this struct
264 struct pl08x_driver_data
{
265 struct dma_device slave
;
266 struct dma_device memcpy
;
268 struct amba_device
*adev
;
269 const struct vendor_data
*vd
;
270 struct pl08x_platform_data
*pd
;
271 struct pl08x_phy_chan
*phy_chans
;
272 struct dma_pool
*pool
;
279 * PL08X specific defines
282 /* Size (bytes) of each LLI buffer allocated for one transfer */
283 # define PL08X_LLI_TSFR_SIZE 0x2000
285 /* Maximum times we call dma_pool_alloc on this pool without freeing */
286 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
287 #define PL08X_ALIGN 8
289 static inline struct pl08x_dma_chan
*to_pl08x_chan(struct dma_chan
*chan
)
291 return container_of(chan
, struct pl08x_dma_chan
, chan
);
294 static inline struct pl08x_txd
*to_pl08x_txd(struct dma_async_tx_descriptor
*tx
)
296 return container_of(tx
, struct pl08x_txd
, tx
);
302 * This gives us the DMA request input to the PL08x primecell which the
303 * peripheral described by the channel data will be routed to, possibly
304 * via a board/SoC specific external MUX. One important point to note
305 * here is that this does not depend on the physical channel.
307 static int pl08x_request_mux(struct pl08x_dma_chan
*plchan
)
309 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
312 if (plchan
->mux_use
++ == 0 && pd
->get_signal
) {
313 ret
= pd
->get_signal(plchan
->cd
);
319 plchan
->signal
= ret
;
324 static void pl08x_release_mux(struct pl08x_dma_chan
*plchan
)
326 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
328 if (plchan
->signal
>= 0) {
329 WARN_ON(plchan
->mux_use
== 0);
331 if (--plchan
->mux_use
== 0 && pd
->put_signal
) {
332 pd
->put_signal(plchan
->cd
, plchan
->signal
);
339 * Physical channel handling
342 /* Whether a certain channel is busy or not */
343 static int pl08x_phy_channel_busy(struct pl08x_phy_chan
*ch
)
347 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
348 return val
& PL080_CONFIG_ACTIVE
;
352 * Set the initial DMA register values i.e. those for the first LLI
353 * The next LLI pointer and the configuration interrupt bit have
354 * been set when the LLIs were constructed. Poke them into the hardware
355 * and start the transfer.
357 static void pl08x_start_next_txd(struct pl08x_dma_chan
*plchan
)
359 struct pl08x_driver_data
*pl08x
= plchan
->host
;
360 struct pl08x_phy_chan
*phychan
= plchan
->phychan
;
361 struct pl08x_lli
*lli
;
362 struct pl08x_txd
*txd
;
365 txd
= list_first_entry(&plchan
->pend_list
, struct pl08x_txd
, node
);
366 list_del(&txd
->node
);
370 /* Wait for channel inactive */
371 while (pl08x_phy_channel_busy(phychan
))
374 lli
= &txd
->llis_va
[0];
376 dev_vdbg(&pl08x
->adev
->dev
,
377 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
378 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
379 phychan
->id
, lli
->src
, lli
->dst
, lli
->lli
, lli
->cctl
,
382 writel(lli
->src
, phychan
->base
+ PL080_CH_SRC_ADDR
);
383 writel(lli
->dst
, phychan
->base
+ PL080_CH_DST_ADDR
);
384 writel(lli
->lli
, phychan
->base
+ PL080_CH_LLI
);
385 writel(lli
->cctl
, phychan
->base
+ PL080_CH_CONTROL
);
386 writel(txd
->ccfg
, phychan
->base
+ PL080_CH_CONFIG
);
388 /* Enable the DMA channel */
389 /* Do not access config register until channel shows as disabled */
390 while (readl(pl08x
->base
+ PL080_EN_CHAN
) & (1 << phychan
->id
))
393 /* Do not access config register until channel shows as inactive */
394 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
395 while ((val
& PL080_CONFIG_ACTIVE
) || (val
& PL080_CONFIG_ENABLE
))
396 val
= readl(phychan
->base
+ PL080_CH_CONFIG
);
398 writel(val
| PL080_CONFIG_ENABLE
, phychan
->base
+ PL080_CH_CONFIG
);
402 * Pause the channel by setting the HALT bit.
404 * For M->P transfers, pause the DMAC first and then stop the peripheral -
405 * the FIFO can only drain if the peripheral is still requesting data.
406 * (note: this can still timeout if the DMAC FIFO never drains of data.)
408 * For P->M transfers, disable the peripheral first to stop it filling
409 * the DMAC FIFO, and then pause the DMAC.
411 static void pl08x_pause_phy_chan(struct pl08x_phy_chan
*ch
)
416 /* Set the HALT bit and wait for the FIFO to drain */
417 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
418 val
|= PL080_CONFIG_HALT
;
419 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
421 /* Wait for channel inactive */
422 for (timeout
= 1000; timeout
; timeout
--) {
423 if (!pl08x_phy_channel_busy(ch
))
427 if (pl08x_phy_channel_busy(ch
))
428 pr_err("pl08x: channel%u timeout waiting for pause\n", ch
->id
);
431 static void pl08x_resume_phy_chan(struct pl08x_phy_chan
*ch
)
435 /* Clear the HALT bit */
436 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
437 val
&= ~PL080_CONFIG_HALT
;
438 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
442 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
443 * clears any pending interrupt status. This should not be used for
444 * an on-going transfer, but as a method of shutting down a channel
445 * (eg, when it's no longer used) or terminating a transfer.
447 static void pl08x_terminate_phy_chan(struct pl08x_driver_data
*pl08x
,
448 struct pl08x_phy_chan
*ch
)
450 u32 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
452 val
&= ~(PL080_CONFIG_ENABLE
| PL080_CONFIG_ERR_IRQ_MASK
|
453 PL080_CONFIG_TC_IRQ_MASK
);
455 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
457 writel(1 << ch
->id
, pl08x
->base
+ PL080_ERR_CLEAR
);
458 writel(1 << ch
->id
, pl08x
->base
+ PL080_TC_CLEAR
);
461 static inline u32
get_bytes_in_cctl(u32 cctl
)
463 /* The source width defines the number of bytes */
464 u32 bytes
= cctl
& PL080_CONTROL_TRANSFER_SIZE_MASK
;
466 switch (cctl
>> PL080_CONTROL_SWIDTH_SHIFT
) {
467 case PL080_WIDTH_8BIT
:
469 case PL080_WIDTH_16BIT
:
472 case PL080_WIDTH_32BIT
:
479 /* The channel should be paused when calling this */
480 static u32
pl08x_getbytes_chan(struct pl08x_dma_chan
*plchan
)
482 struct pl08x_phy_chan
*ch
;
483 struct pl08x_txd
*txd
;
487 spin_lock_irqsave(&plchan
->lock
, flags
);
488 ch
= plchan
->phychan
;
492 * Follow the LLIs to get the number of remaining
493 * bytes in the currently active transaction.
496 u32 clli
= readl(ch
->base
+ PL080_CH_LLI
) & ~PL080_LLI_LM_AHB2
;
498 /* First get the remaining bytes in the active transfer */
499 bytes
= get_bytes_in_cctl(readl(ch
->base
+ PL080_CH_CONTROL
));
502 struct pl08x_lli
*llis_va
= txd
->llis_va
;
503 dma_addr_t llis_bus
= txd
->llis_bus
;
506 BUG_ON(clli
< llis_bus
|| clli
>= llis_bus
+
507 sizeof(struct pl08x_lli
) * MAX_NUM_TSFR_LLIS
);
510 * Locate the next LLI - as this is an array,
511 * it's simple maths to find.
513 index
= (clli
- llis_bus
) / sizeof(struct pl08x_lli
);
515 for (; index
< MAX_NUM_TSFR_LLIS
; index
++) {
516 bytes
+= get_bytes_in_cctl(llis_va
[index
].cctl
);
519 * A LLI pointer of 0 terminates the LLI list
521 if (!llis_va
[index
].lli
)
527 /* Sum up all queued transactions */
528 if (!list_empty(&plchan
->pend_list
)) {
529 struct pl08x_txd
*txdi
;
530 list_for_each_entry(txdi
, &plchan
->pend_list
, node
) {
531 struct pl08x_sg
*dsg
;
532 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
537 spin_unlock_irqrestore(&plchan
->lock
, flags
);
543 * Allocate a physical channel for a virtual channel
545 * Try to locate a physical channel to be used for this transfer. If all
546 * are taken return NULL and the requester will have to cope by using
547 * some fallback PIO mode or retrying later.
549 static struct pl08x_phy_chan
*
550 pl08x_get_phy_channel(struct pl08x_driver_data
*pl08x
,
551 struct pl08x_dma_chan
*virt_chan
)
553 struct pl08x_phy_chan
*ch
= NULL
;
557 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
558 ch
= &pl08x
->phy_chans
[i
];
560 spin_lock_irqsave(&ch
->lock
, flags
);
562 if (!ch
->locked
&& !ch
->serving
) {
563 ch
->serving
= virt_chan
;
564 spin_unlock_irqrestore(&ch
->lock
, flags
);
568 spin_unlock_irqrestore(&ch
->lock
, flags
);
571 if (i
== pl08x
->vd
->channels
) {
572 /* No physical channel available, cope with it */
579 static inline void pl08x_put_phy_channel(struct pl08x_driver_data
*pl08x
,
580 struct pl08x_phy_chan
*ch
)
584 spin_lock_irqsave(&ch
->lock
, flags
);
586 /* Stop the channel and clear its interrupts */
587 pl08x_terminate_phy_chan(pl08x
, ch
);
589 /* Mark it as free */
591 spin_unlock_irqrestore(&ch
->lock
, flags
);
598 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded
)
601 case PL080_WIDTH_8BIT
:
603 case PL080_WIDTH_16BIT
:
605 case PL080_WIDTH_32BIT
:
614 static inline u32
pl08x_cctl_bits(u32 cctl
, u8 srcwidth
, u8 dstwidth
,
619 /* Remove all src, dst and transfer size bits */
620 retbits
&= ~PL080_CONTROL_DWIDTH_MASK
;
621 retbits
&= ~PL080_CONTROL_SWIDTH_MASK
;
622 retbits
&= ~PL080_CONTROL_TRANSFER_SIZE_MASK
;
624 /* Then set the bits according to the parameters */
627 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
630 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
633 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
642 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
645 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
648 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
655 retbits
|= tsize
<< PL080_CONTROL_TRANSFER_SIZE_SHIFT
;
659 struct pl08x_lli_build_data
{
660 struct pl08x_txd
*txd
;
661 struct pl08x_bus_data srcbus
;
662 struct pl08x_bus_data dstbus
;
668 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
669 * victim in case src & dest are not similarly aligned. i.e. If after aligning
670 * masters address with width requirements of transfer (by sending few byte by
671 * byte data), slave is still not aligned, then its width will be reduced to
673 * - prefers the destination bus if both available
674 * - prefers bus with fixed address (i.e. peripheral)
676 static void pl08x_choose_master_bus(struct pl08x_lli_build_data
*bd
,
677 struct pl08x_bus_data
**mbus
, struct pl08x_bus_data
**sbus
, u32 cctl
)
679 if (!(cctl
& PL080_CONTROL_DST_INCR
)) {
682 } else if (!(cctl
& PL080_CONTROL_SRC_INCR
)) {
686 if (bd
->dstbus
.buswidth
>= bd
->srcbus
.buswidth
) {
697 * Fills in one LLI for a certain transfer descriptor and advance the counter
699 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data
*bd
,
700 int num_llis
, int len
, u32 cctl
)
702 struct pl08x_lli
*llis_va
= bd
->txd
->llis_va
;
703 dma_addr_t llis_bus
= bd
->txd
->llis_bus
;
705 BUG_ON(num_llis
>= MAX_NUM_TSFR_LLIS
);
707 llis_va
[num_llis
].cctl
= cctl
;
708 llis_va
[num_llis
].src
= bd
->srcbus
.addr
;
709 llis_va
[num_llis
].dst
= bd
->dstbus
.addr
;
710 llis_va
[num_llis
].lli
= llis_bus
+ (num_llis
+ 1) *
711 sizeof(struct pl08x_lli
);
712 llis_va
[num_llis
].lli
|= bd
->lli_bus
;
714 if (cctl
& PL080_CONTROL_SRC_INCR
)
715 bd
->srcbus
.addr
+= len
;
716 if (cctl
& PL080_CONTROL_DST_INCR
)
717 bd
->dstbus
.addr
+= len
;
719 BUG_ON(bd
->remainder
< len
);
721 bd
->remainder
-= len
;
724 static inline void prep_byte_width_lli(struct pl08x_lli_build_data
*bd
,
725 u32
*cctl
, u32 len
, int num_llis
, size_t *total_bytes
)
727 *cctl
= pl08x_cctl_bits(*cctl
, 1, 1, len
);
728 pl08x_fill_lli_for_desc(bd
, num_llis
, len
, *cctl
);
729 (*total_bytes
) += len
;
733 * This fills in the table of LLIs for the transfer descriptor
734 * Note that we assume we never have to change the burst sizes
737 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data
*pl08x
,
738 struct pl08x_txd
*txd
)
740 struct pl08x_bus_data
*mbus
, *sbus
;
741 struct pl08x_lli_build_data bd
;
743 u32 cctl
, early_bytes
= 0;
744 size_t max_bytes_per_lli
, total_bytes
;
745 struct pl08x_lli
*llis_va
;
746 struct pl08x_sg
*dsg
;
748 txd
->llis_va
= dma_pool_alloc(pl08x
->pool
, GFP_NOWAIT
, &txd
->llis_bus
);
750 dev_err(&pl08x
->adev
->dev
, "%s no memory for llis\n", __func__
);
757 bd
.lli_bus
= (pl08x
->lli_buses
& PL08X_AHB2
) ? PL080_LLI_LM_AHB2
: 0;
760 /* Find maximum width of the source bus */
762 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_SWIDTH_MASK
) >>
763 PL080_CONTROL_SWIDTH_SHIFT
);
765 /* Find maximum width of the destination bus */
767 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_DWIDTH_MASK
) >>
768 PL080_CONTROL_DWIDTH_SHIFT
);
770 list_for_each_entry(dsg
, &txd
->dsg_list
, node
) {
774 bd
.srcbus
.addr
= dsg
->src_addr
;
775 bd
.dstbus
.addr
= dsg
->dst_addr
;
776 bd
.remainder
= dsg
->len
;
777 bd
.srcbus
.buswidth
= bd
.srcbus
.maxwidth
;
778 bd
.dstbus
.buswidth
= bd
.dstbus
.maxwidth
;
780 pl08x_choose_master_bus(&bd
, &mbus
, &sbus
, cctl
);
782 dev_vdbg(&pl08x
->adev
->dev
, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
783 bd
.srcbus
.addr
, cctl
& PL080_CONTROL_SRC_INCR
? "+" : "",
785 bd
.dstbus
.addr
, cctl
& PL080_CONTROL_DST_INCR
? "+" : "",
788 dev_vdbg(&pl08x
->adev
->dev
, "mbus=%s sbus=%s\n",
789 mbus
== &bd
.srcbus
? "src" : "dst",
790 sbus
== &bd
.srcbus
? "src" : "dst");
793 * Zero length is only allowed if all these requirements are
795 * - flow controller is peripheral.
796 * - src.addr is aligned to src.width
797 * - dst.addr is aligned to dst.width
799 * sg_len == 1 should be true, as there can be two cases here:
801 * - Memory addresses are contiguous and are not scattered.
802 * Here, Only one sg will be passed by user driver, with
803 * memory address and zero length. We pass this to controller
804 * and after the transfer it will receive the last burst
805 * request from peripheral and so transfer finishes.
807 * - Memory addresses are scattered and are not contiguous.
808 * Here, Obviously as DMA controller doesn't know when a lli's
809 * transfer gets over, it can't load next lli. So in this
810 * case, there has to be an assumption that only one lli is
811 * supported. Thus, we can't have scattered addresses.
814 u32 fc
= (txd
->ccfg
& PL080_CONFIG_FLOW_CONTROL_MASK
) >>
815 PL080_CONFIG_FLOW_CONTROL_SHIFT
;
816 if (!((fc
>= PL080_FLOW_SRC2DST_DST
) &&
817 (fc
<= PL080_FLOW_SRC2DST_SRC
))) {
818 dev_err(&pl08x
->adev
->dev
, "%s sg len can't be zero",
823 if ((bd
.srcbus
.addr
% bd
.srcbus
.buswidth
) ||
824 (bd
.dstbus
.addr
% bd
.dstbus
.buswidth
)) {
825 dev_err(&pl08x
->adev
->dev
,
826 "%s src & dst address must be aligned to src"
827 " & dst width if peripheral is flow controller",
832 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
833 bd
.dstbus
.buswidth
, 0);
834 pl08x_fill_lli_for_desc(&bd
, num_llis
++, 0, cctl
);
839 * Send byte by byte for following cases
840 * - Less than a bus width available
841 * - until master bus is aligned
843 if (bd
.remainder
< mbus
->buswidth
)
844 early_bytes
= bd
.remainder
;
845 else if ((mbus
->addr
) % (mbus
->buswidth
)) {
846 early_bytes
= mbus
->buswidth
- (mbus
->addr
) %
848 if ((bd
.remainder
- early_bytes
) < mbus
->buswidth
)
849 early_bytes
= bd
.remainder
;
853 dev_vdbg(&pl08x
->adev
->dev
,
854 "%s byte width LLIs (remain 0x%08x)\n",
855 __func__
, bd
.remainder
);
856 prep_byte_width_lli(&bd
, &cctl
, early_bytes
, num_llis
++,
863 * - if slave is not then we must set its width down
865 if (sbus
->addr
% sbus
->buswidth
) {
866 dev_dbg(&pl08x
->adev
->dev
,
867 "%s set down bus width to one byte\n",
874 * Bytes transferred = tsize * src width, not
877 max_bytes_per_lli
= bd
.srcbus
.buswidth
*
878 PL080_CONTROL_TRANSFER_SIZE_MASK
;
879 dev_vdbg(&pl08x
->adev
->dev
,
880 "%s max bytes per lli = %zu\n",
881 __func__
, max_bytes_per_lli
);
884 * Make largest possible LLIs until less than one bus
887 while (bd
.remainder
> (mbus
->buswidth
- 1)) {
888 size_t lli_len
, tsize
, width
;
891 * If enough left try to send max possible,
892 * otherwise try to send the remainder
894 lli_len
= min(bd
.remainder
, max_bytes_per_lli
);
897 * Check against maximum bus alignment:
898 * Calculate actual transfer size in relation to
899 * bus width an get a maximum remainder of the
900 * highest bus width - 1
902 width
= max(mbus
->buswidth
, sbus
->buswidth
);
903 lli_len
= (lli_len
/ width
) * width
;
904 tsize
= lli_len
/ bd
.srcbus
.buswidth
;
906 dev_vdbg(&pl08x
->adev
->dev
,
907 "%s fill lli with single lli chunk of "
908 "size 0x%08zx (remainder 0x%08zx)\n",
909 __func__
, lli_len
, bd
.remainder
);
911 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
912 bd
.dstbus
.buswidth
, tsize
);
913 pl08x_fill_lli_for_desc(&bd
, num_llis
++,
915 total_bytes
+= lli_len
;
922 dev_vdbg(&pl08x
->adev
->dev
,
923 "%s align with boundary, send odd bytes (remain %zu)\n",
924 __func__
, bd
.remainder
);
925 prep_byte_width_lli(&bd
, &cctl
, bd
.remainder
,
926 num_llis
++, &total_bytes
);
930 if (total_bytes
!= dsg
->len
) {
931 dev_err(&pl08x
->adev
->dev
,
932 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
933 __func__
, total_bytes
, dsg
->len
);
937 if (num_llis
>= MAX_NUM_TSFR_LLIS
) {
938 dev_err(&pl08x
->adev
->dev
,
939 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
940 __func__
, (u32
) MAX_NUM_TSFR_LLIS
);
945 llis_va
= txd
->llis_va
;
946 /* The final LLI terminates the LLI. */
947 llis_va
[num_llis
- 1].lli
= 0;
948 /* The final LLI element shall also fire an interrupt. */
949 llis_va
[num_llis
- 1].cctl
|= PL080_CONTROL_TC_IRQ_EN
;
955 dev_vdbg(&pl08x
->adev
->dev
,
956 "%-3s %-9s %-10s %-10s %-10s %s\n",
957 "lli", "", "csrc", "cdst", "clli", "cctl");
958 for (i
= 0; i
< num_llis
; i
++) {
959 dev_vdbg(&pl08x
->adev
->dev
,
960 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
961 i
, &llis_va
[i
], llis_va
[i
].src
,
962 llis_va
[i
].dst
, llis_va
[i
].lli
, llis_va
[i
].cctl
971 /* You should call this with the struct pl08x lock held */
972 static void pl08x_free_txd(struct pl08x_driver_data
*pl08x
,
973 struct pl08x_txd
*txd
)
975 struct pl08x_sg
*dsg
, *_dsg
;
979 dma_pool_free(pl08x
->pool
, txd
->llis_va
, txd
->llis_bus
);
983 list_for_each_entry_safe(dsg
, _dsg
, &txd
->dsg_list
, node
) {
984 list_del(&dsg
->node
);
991 static void pl08x_free_txd_list(struct pl08x_driver_data
*pl08x
,
992 struct pl08x_dma_chan
*plchan
)
994 struct pl08x_txd
*txdi
= NULL
;
995 struct pl08x_txd
*next
;
997 if (!list_empty(&plchan
->pend_list
)) {
998 list_for_each_entry_safe(txdi
,
999 next
, &plchan
->pend_list
, node
) {
1000 pl08x_release_mux(plchan
);
1001 list_del(&txdi
->node
);
1002 pl08x_free_txd(pl08x
, txdi
);
1008 * The DMA ENGINE API
1010 static int pl08x_alloc_chan_resources(struct dma_chan
*chan
)
1015 static void pl08x_free_chan_resources(struct dma_chan
*chan
)
1020 * This should be called with the channel plchan->lock held
1022 static int prep_phy_channel(struct pl08x_dma_chan
*plchan
)
1024 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1025 struct pl08x_phy_chan
*ch
;
1027 /* Check if we already have a channel */
1028 if (plchan
->phychan
) {
1029 ch
= plchan
->phychan
;
1033 ch
= pl08x_get_phy_channel(pl08x
, plchan
);
1035 /* No physical channel available, cope with it */
1036 dev_dbg(&pl08x
->adev
->dev
, "no physical channel available for xfer on %s\n", plchan
->name
);
1040 plchan
->phychan
= ch
;
1041 dev_dbg(&pl08x
->adev
->dev
, "allocated physical channel %d for xfer on %s\n",
1042 ch
->id
, plchan
->name
);
1045 plchan
->phychan_hold
++;
1050 static void release_phy_channel(struct pl08x_dma_chan
*plchan
)
1052 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1054 pl08x_put_phy_channel(pl08x
, plchan
->phychan
);
1055 plchan
->phychan
= NULL
;
1058 static dma_cookie_t
pl08x_tx_submit(struct dma_async_tx_descriptor
*tx
)
1060 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(tx
->chan
);
1061 struct pl08x_txd
*txd
= to_pl08x_txd(tx
);
1062 unsigned long flags
;
1063 dma_cookie_t cookie
;
1065 spin_lock_irqsave(&plchan
->lock
, flags
);
1066 cookie
= dma_cookie_assign(tx
);
1068 /* Put this onto the pending list */
1069 list_add_tail(&txd
->node
, &plchan
->pend_list
);
1072 * If there was no physical channel available for this memcpy,
1073 * stack the request up and indicate that the channel is waiting
1074 * for a free physical channel.
1076 if (!plchan
->slave
&& !plchan
->phychan
) {
1077 /* Do this memcpy whenever there is a channel ready */
1078 plchan
->state
= PL08X_CHAN_WAITING
;
1080 plchan
->phychan_hold
--;
1083 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1088 static struct dma_async_tx_descriptor
*pl08x_prep_dma_interrupt(
1089 struct dma_chan
*chan
, unsigned long flags
)
1091 struct dma_async_tx_descriptor
*retval
= NULL
;
1097 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1098 * If slaves are relying on interrupts to signal completion this function
1099 * must not be called with interrupts disabled.
1101 static enum dma_status
pl08x_dma_tx_status(struct dma_chan
*chan
,
1102 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
1104 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1105 enum dma_status ret
;
1107 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1108 if (ret
== DMA_SUCCESS
)
1112 * This cookie not complete yet
1113 * Get number of bytes left in the active transactions and queue
1115 dma_set_residue(txstate
, pl08x_getbytes_chan(plchan
));
1117 if (plchan
->state
== PL08X_CHAN_PAUSED
)
1120 /* Whether waiting or running, we're in progress */
1121 return DMA_IN_PROGRESS
;
1124 /* PrimeCell DMA extension */
1125 struct burst_table
{
1130 static const struct burst_table burst_sizes
[] = {
1133 .reg
= PL080_BSIZE_256
,
1137 .reg
= PL080_BSIZE_128
,
1141 .reg
= PL080_BSIZE_64
,
1145 .reg
= PL080_BSIZE_32
,
1149 .reg
= PL080_BSIZE_16
,
1153 .reg
= PL080_BSIZE_8
,
1157 .reg
= PL080_BSIZE_4
,
1161 .reg
= PL080_BSIZE_1
,
1166 * Given the source and destination available bus masks, select which
1167 * will be routed to each port. We try to have source and destination
1168 * on separate ports, but always respect the allowable settings.
1170 static u32
pl08x_select_bus(u8 src
, u8 dst
)
1174 if (!(dst
& PL08X_AHB1
) || ((dst
& PL08X_AHB2
) && (src
& PL08X_AHB1
)))
1175 cctl
|= PL080_CONTROL_DST_AHB2
;
1176 if (!(src
& PL08X_AHB1
) || ((src
& PL08X_AHB2
) && !(dst
& PL08X_AHB2
)))
1177 cctl
|= PL080_CONTROL_SRC_AHB2
;
1182 static u32
pl08x_cctl(u32 cctl
)
1184 cctl
&= ~(PL080_CONTROL_SRC_AHB2
| PL080_CONTROL_DST_AHB2
|
1185 PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
|
1186 PL080_CONTROL_PROT_MASK
);
1188 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1189 return cctl
| PL080_CONTROL_PROT_SYS
;
1192 static u32
pl08x_width(enum dma_slave_buswidth width
)
1195 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
1196 return PL080_WIDTH_8BIT
;
1197 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
1198 return PL080_WIDTH_16BIT
;
1199 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
1200 return PL080_WIDTH_32BIT
;
1206 static u32
pl08x_burst(u32 maxburst
)
1210 for (i
= 0; i
< ARRAY_SIZE(burst_sizes
); i
++)
1211 if (burst_sizes
[i
].burstwords
<= maxburst
)
1214 return burst_sizes
[i
].reg
;
1217 static u32
pl08x_get_cctl(struct pl08x_dma_chan
*plchan
,
1218 enum dma_slave_buswidth addr_width
, u32 maxburst
)
1220 u32 width
, burst
, cctl
= 0;
1222 width
= pl08x_width(addr_width
);
1226 cctl
|= width
<< PL080_CONTROL_SWIDTH_SHIFT
;
1227 cctl
|= width
<< PL080_CONTROL_DWIDTH_SHIFT
;
1230 * If this channel will only request single transfers, set this
1231 * down to ONE element. Also select one element if no maxburst
1234 if (plchan
->cd
->single
)
1237 burst
= pl08x_burst(maxburst
);
1238 cctl
|= burst
<< PL080_CONTROL_SB_SIZE_SHIFT
;
1239 cctl
|= burst
<< PL080_CONTROL_DB_SIZE_SHIFT
;
1241 return pl08x_cctl(cctl
);
1244 static int dma_set_runtime_config(struct dma_chan
*chan
,
1245 struct dma_slave_config
*config
)
1247 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1252 /* Reject definitely invalid configurations */
1253 if (config
->src_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
||
1254 config
->dst_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
)
1257 plchan
->cfg
= *config
;
1263 * Slave transactions callback to the slave device to allow
1264 * synchronization of slave DMA signals with the DMAC enable
1266 static void pl08x_issue_pending(struct dma_chan
*chan
)
1268 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1269 unsigned long flags
;
1271 spin_lock_irqsave(&plchan
->lock
, flags
);
1272 /* Something is already active, or we're waiting for a channel... */
1273 if (plchan
->at
|| plchan
->state
== PL08X_CHAN_WAITING
) {
1274 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1278 /* Take the first element in the queue and execute it */
1279 if (!list_empty(&plchan
->pend_list
)) {
1280 plchan
->state
= PL08X_CHAN_RUNNING
;
1281 pl08x_start_next_txd(plchan
);
1284 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1287 static int pl08x_prep_channel_resources(struct pl08x_dma_chan
*plchan
,
1288 struct pl08x_txd
*txd
)
1290 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1291 unsigned long flags
;
1294 num_llis
= pl08x_fill_llis_for_desc(pl08x
, txd
);
1296 spin_lock_irqsave(&plchan
->lock
, flags
);
1297 pl08x_free_txd(pl08x
, txd
);
1298 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1302 spin_lock_irqsave(&plchan
->lock
, flags
);
1305 * See if we already have a physical channel allocated,
1306 * else this is the time to try to get one.
1308 ret
= prep_phy_channel(plchan
);
1311 * No physical channel was available.
1313 * memcpy transfers can be sorted out at submission time.
1315 if (plchan
->slave
) {
1316 pl08x_free_txd_list(pl08x
, plchan
);
1317 pl08x_free_txd(pl08x
, txd
);
1318 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1323 * Else we're all set, paused and ready to roll, status
1324 * will switch to PL08X_CHAN_RUNNING when we call
1325 * issue_pending(). If there is something running on the
1326 * channel already we don't change its state.
1328 if (plchan
->state
== PL08X_CHAN_IDLE
)
1329 plchan
->state
= PL08X_CHAN_PAUSED
;
1331 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1336 static struct pl08x_txd
*pl08x_get_txd(struct pl08x_dma_chan
*plchan
,
1337 unsigned long flags
)
1339 struct pl08x_txd
*txd
= kzalloc(sizeof(*txd
), GFP_NOWAIT
);
1342 dma_async_tx_descriptor_init(&txd
->tx
, &plchan
->chan
);
1343 txd
->tx
.flags
= flags
;
1344 txd
->tx
.tx_submit
= pl08x_tx_submit
;
1345 INIT_LIST_HEAD(&txd
->node
);
1346 INIT_LIST_HEAD(&txd
->dsg_list
);
1348 /* Always enable error and terminal interrupts */
1349 txd
->ccfg
= PL080_CONFIG_ERR_IRQ_MASK
|
1350 PL080_CONFIG_TC_IRQ_MASK
;
1356 * Initialize a descriptor to be used by memcpy submit
1358 static struct dma_async_tx_descriptor
*pl08x_prep_dma_memcpy(
1359 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1360 size_t len
, unsigned long flags
)
1362 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1363 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1364 struct pl08x_txd
*txd
;
1365 struct pl08x_sg
*dsg
;
1368 txd
= pl08x_get_txd(plchan
, flags
);
1370 dev_err(&pl08x
->adev
->dev
,
1371 "%s no memory for descriptor\n", __func__
);
1375 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1377 pl08x_free_txd(pl08x
, txd
);
1378 dev_err(&pl08x
->adev
->dev
, "%s no memory for pl080 sg\n",
1382 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1384 dsg
->src_addr
= src
;
1385 dsg
->dst_addr
= dest
;
1388 /* Set platform data for m2m */
1389 txd
->ccfg
|= PL080_FLOW_MEM2MEM
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1390 txd
->cctl
= pl08x
->pd
->memcpy_channel
.cctl_memcpy
&
1391 ~(PL080_CONTROL_DST_AHB2
| PL080_CONTROL_SRC_AHB2
);
1393 /* Both to be incremented or the code will break */
1394 txd
->cctl
|= PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
;
1396 if (pl08x
->vd
->dualmaster
)
1397 txd
->cctl
|= pl08x_select_bus(pl08x
->mem_buses
,
1400 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1407 static struct dma_async_tx_descriptor
*pl08x_prep_slave_sg(
1408 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1409 unsigned int sg_len
, enum dma_transfer_direction direction
,
1410 unsigned long flags
, void *context
)
1412 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1413 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1414 struct pl08x_txd
*txd
;
1415 struct pl08x_sg
*dsg
;
1416 struct scatterlist
*sg
;
1417 enum dma_slave_buswidth addr_width
;
1418 dma_addr_t slave_addr
;
1420 u8 src_buses
, dst_buses
;
1423 dev_dbg(&pl08x
->adev
->dev
, "%s prepare transaction of %d bytes from %s\n",
1424 __func__
, sg_dma_len(sgl
), plchan
->name
);
1426 txd
= pl08x_get_txd(plchan
, flags
);
1428 dev_err(&pl08x
->adev
->dev
, "%s no txd\n", __func__
);
1433 * Set up addresses, the PrimeCell configured address
1434 * will take precedence since this may configure the
1435 * channel target address dynamically at runtime.
1437 if (direction
== DMA_MEM_TO_DEV
) {
1438 cctl
= PL080_CONTROL_SRC_INCR
;
1439 slave_addr
= plchan
->cfg
.dst_addr
;
1440 addr_width
= plchan
->cfg
.dst_addr_width
;
1441 maxburst
= plchan
->cfg
.dst_maxburst
;
1442 src_buses
= pl08x
->mem_buses
;
1443 dst_buses
= plchan
->cd
->periph_buses
;
1444 } else if (direction
== DMA_DEV_TO_MEM
) {
1445 cctl
= PL080_CONTROL_DST_INCR
;
1446 slave_addr
= plchan
->cfg
.src_addr
;
1447 addr_width
= plchan
->cfg
.src_addr_width
;
1448 maxburst
= plchan
->cfg
.src_maxburst
;
1449 src_buses
= plchan
->cd
->periph_buses
;
1450 dst_buses
= pl08x
->mem_buses
;
1452 pl08x_free_txd(pl08x
, txd
);
1453 dev_err(&pl08x
->adev
->dev
,
1454 "%s direction unsupported\n", __func__
);
1458 cctl
|= pl08x_get_cctl(plchan
, addr_width
, maxburst
);
1460 pl08x_free_txd(pl08x
, txd
);
1461 dev_err(&pl08x
->adev
->dev
,
1462 "DMA slave configuration botched?\n");
1466 txd
->cctl
= cctl
| pl08x_select_bus(src_buses
, dst_buses
);
1468 if (plchan
->cfg
.device_fc
)
1469 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER_PER
:
1470 PL080_FLOW_PER2MEM_PER
;
1472 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER
:
1475 txd
->ccfg
|= tmp
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1477 ret
= pl08x_request_mux(plchan
);
1479 pl08x_free_txd(pl08x
, txd
);
1480 dev_dbg(&pl08x
->adev
->dev
,
1481 "unable to mux for transfer on %s due to platform restrictions\n",
1486 dev_dbg(&pl08x
->adev
->dev
, "allocated DMA request signal %d for xfer on %s\n",
1487 plchan
->signal
, plchan
->name
);
1489 /* Assign the flow control signal to this channel */
1490 if (direction
== DMA_MEM_TO_DEV
)
1491 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_DST_SEL_SHIFT
;
1493 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_SRC_SEL_SHIFT
;
1495 for_each_sg(sgl
, sg
, sg_len
, tmp
) {
1496 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1498 pl08x_release_mux(plchan
);
1499 pl08x_free_txd(pl08x
, txd
);
1500 dev_err(&pl08x
->adev
->dev
, "%s no mem for pl080 sg\n",
1504 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1506 dsg
->len
= sg_dma_len(sg
);
1507 if (direction
== DMA_MEM_TO_DEV
) {
1508 dsg
->src_addr
= sg_dma_address(sg
);
1509 dsg
->dst_addr
= slave_addr
;
1511 dsg
->src_addr
= slave_addr
;
1512 dsg
->dst_addr
= sg_dma_address(sg
);
1516 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1523 static int pl08x_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1526 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1527 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1528 unsigned long flags
;
1531 /* Controls applicable to inactive channels */
1532 if (cmd
== DMA_SLAVE_CONFIG
) {
1533 return dma_set_runtime_config(chan
,
1534 (struct dma_slave_config
*)arg
);
1538 * Anything succeeds on channels with no physical allocation and
1539 * no queued transfers.
1541 spin_lock_irqsave(&plchan
->lock
, flags
);
1542 if (!plchan
->phychan
&& !plchan
->at
) {
1543 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1548 case DMA_TERMINATE_ALL
:
1549 plchan
->state
= PL08X_CHAN_IDLE
;
1551 if (plchan
->phychan
) {
1552 pl08x_terminate_phy_chan(pl08x
, plchan
->phychan
);
1555 * Mark physical channel as free and free any slave
1558 release_phy_channel(plchan
);
1559 plchan
->phychan_hold
= 0;
1561 /* Dequeue jobs and free LLIs */
1563 /* Killing this one off, release its mux */
1564 pl08x_release_mux(plchan
);
1565 pl08x_free_txd(pl08x
, plchan
->at
);
1568 /* Dequeue jobs not yet fired as well */
1569 pl08x_free_txd_list(pl08x
, plchan
);
1572 pl08x_pause_phy_chan(plchan
->phychan
);
1573 plchan
->state
= PL08X_CHAN_PAUSED
;
1576 pl08x_resume_phy_chan(plchan
->phychan
);
1577 plchan
->state
= PL08X_CHAN_RUNNING
;
1580 /* Unknown command */
1585 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1590 bool pl08x_filter_id(struct dma_chan
*chan
, void *chan_id
)
1592 struct pl08x_dma_chan
*plchan
;
1593 char *name
= chan_id
;
1595 /* Reject channels for devices not bound to this driver */
1596 if (chan
->device
->dev
->driver
!= &pl08x_amba_driver
.drv
)
1599 plchan
= to_pl08x_chan(chan
);
1601 /* Check that the channel is not taken! */
1602 if (!strcmp(plchan
->name
, name
))
1609 * Just check that the device is there and active
1610 * TODO: turn this bit on/off depending on the number of physical channels
1611 * actually used, if it is zero... well shut it off. That will save some
1612 * power. Cut the clock at the same time.
1614 static void pl08x_ensure_on(struct pl08x_driver_data
*pl08x
)
1616 /* The Nomadik variant does not have the config register */
1617 if (pl08x
->vd
->nomadik
)
1619 writel(PL080_CONFIG_ENABLE
, pl08x
->base
+ PL080_CONFIG
);
1622 static void pl08x_unmap_buffers(struct pl08x_txd
*txd
)
1624 struct device
*dev
= txd
->tx
.chan
->device
->dev
;
1625 struct pl08x_sg
*dsg
;
1627 if (!(txd
->tx
.flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
1628 if (txd
->tx
.flags
& DMA_COMPL_SRC_UNMAP_SINGLE
)
1629 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1630 dma_unmap_single(dev
, dsg
->src_addr
, dsg
->len
,
1633 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1634 dma_unmap_page(dev
, dsg
->src_addr
, dsg
->len
,
1638 if (!(txd
->tx
.flags
& DMA_COMPL_SKIP_DEST_UNMAP
)) {
1639 if (txd
->tx
.flags
& DMA_COMPL_DEST_UNMAP_SINGLE
)
1640 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1641 dma_unmap_single(dev
, dsg
->dst_addr
, dsg
->len
,
1644 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1645 dma_unmap_page(dev
, dsg
->dst_addr
, dsg
->len
,
1650 static void pl08x_tasklet(unsigned long data
)
1652 struct pl08x_dma_chan
*plchan
= (struct pl08x_dma_chan
*) data
;
1653 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1654 unsigned long flags
;
1657 spin_lock_irqsave(&plchan
->lock
, flags
);
1658 list_splice_tail_init(&plchan
->done_list
, &head
);
1660 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1661 if (!list_empty(&plchan
->pend_list
)) {
1662 pl08x_start_next_txd(plchan
);
1663 } else if (plchan
->phychan_hold
) {
1665 * This channel is still in use - we have a new txd being
1666 * prepared and will soon be queued. Don't give up the
1670 struct pl08x_dma_chan
*waiting
= NULL
;
1673 * No more jobs, so free up the physical channel
1675 release_phy_channel(plchan
);
1676 plchan
->state
= PL08X_CHAN_IDLE
;
1679 * And NOW before anyone else can grab that free:d up
1680 * physical channel, see if there is some memcpy pending
1681 * that seriously needs to start because of being stacked
1682 * up while we were choking the physical channels with data.
1684 list_for_each_entry(waiting
, &pl08x
->memcpy
.channels
,
1686 if (waiting
->state
== PL08X_CHAN_WAITING
) {
1689 /* This should REALLY not fail now */
1690 ret
= prep_phy_channel(waiting
);
1692 waiting
->phychan_hold
--;
1693 waiting
->state
= PL08X_CHAN_RUNNING
;
1695 * Eww. We know this isn't going to deadlock
1696 * but lockdep probably doens't.
1698 spin_lock(&waiting
->lock
);
1699 pl08x_start_next_txd(waiting
);
1700 spin_unlock(&waiting
->lock
);
1706 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1708 while (!list_empty(&head
)) {
1709 struct pl08x_txd
*txd
= list_first_entry(&head
,
1710 struct pl08x_txd
, node
);
1711 dma_async_tx_callback callback
= txd
->tx
.callback
;
1712 void *callback_param
= txd
->tx
.callback_param
;
1714 list_del(&txd
->node
);
1716 /* Don't try to unmap buffers on slave channels */
1718 pl08x_unmap_buffers(txd
);
1720 /* Free the descriptor */
1721 spin_lock_irqsave(&plchan
->lock
, flags
);
1722 pl08x_free_txd(pl08x
, txd
);
1723 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1725 /* Callback to signal completion */
1727 callback(callback_param
);
1731 static irqreturn_t
pl08x_irq(int irq
, void *dev
)
1733 struct pl08x_driver_data
*pl08x
= dev
;
1734 u32 mask
= 0, err
, tc
, i
;
1736 /* check & clear - ERR & TC interrupts */
1737 err
= readl(pl08x
->base
+ PL080_ERR_STATUS
);
1739 dev_err(&pl08x
->adev
->dev
, "%s error interrupt, register value 0x%08x\n",
1741 writel(err
, pl08x
->base
+ PL080_ERR_CLEAR
);
1743 tc
= readl(pl08x
->base
+ PL080_TC_STATUS
);
1745 writel(tc
, pl08x
->base
+ PL080_TC_CLEAR
);
1750 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1751 if (((1 << i
) & err
) || ((1 << i
) & tc
)) {
1752 /* Locate physical channel */
1753 struct pl08x_phy_chan
*phychan
= &pl08x
->phy_chans
[i
];
1754 struct pl08x_dma_chan
*plchan
= phychan
->serving
;
1755 struct pl08x_txd
*tx
;
1758 dev_err(&pl08x
->adev
->dev
,
1759 "%s Error TC interrupt on unused channel: 0x%08x\n",
1764 spin_lock(&plchan
->lock
);
1769 * This descriptor is done, release its mux
1772 pl08x_release_mux(plchan
);
1773 dma_cookie_complete(&tx
->tx
);
1774 list_add_tail(&tx
->node
, &plchan
->done_list
);
1776 spin_unlock(&plchan
->lock
);
1778 /* Schedule tasklet on this channel */
1779 tasklet_schedule(&plchan
->tasklet
);
1784 return mask
? IRQ_HANDLED
: IRQ_NONE
;
1787 static void pl08x_dma_slave_init(struct pl08x_dma_chan
*chan
)
1790 chan
->name
= chan
->cd
->bus_id
;
1791 chan
->cfg
.src_addr
= chan
->cd
->addr
;
1792 chan
->cfg
.dst_addr
= chan
->cd
->addr
;
1796 * Initialise the DMAC memcpy/slave channels.
1797 * Make a local wrapper to hold required data
1799 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data
*pl08x
,
1800 struct dma_device
*dmadev
, unsigned int channels
, bool slave
)
1802 struct pl08x_dma_chan
*chan
;
1805 INIT_LIST_HEAD(&dmadev
->channels
);
1808 * Register as many many memcpy as we have physical channels,
1809 * we won't always be able to use all but the code will have
1810 * to cope with that situation.
1812 for (i
= 0; i
< channels
; i
++) {
1813 chan
= kzalloc(sizeof(*chan
), GFP_KERNEL
);
1815 dev_err(&pl08x
->adev
->dev
,
1816 "%s no memory for channel\n", __func__
);
1821 chan
->state
= PL08X_CHAN_IDLE
;
1825 chan
->cd
= &pl08x
->pd
->slave_channels
[i
];
1826 pl08x_dma_slave_init(chan
);
1828 chan
->cd
= &pl08x
->pd
->memcpy_channel
;
1829 chan
->name
= kasprintf(GFP_KERNEL
, "memcpy%d", i
);
1835 dev_dbg(&pl08x
->adev
->dev
,
1836 "initialize virtual channel \"%s\"\n",
1839 chan
->chan
.device
= dmadev
;
1840 dma_cookie_init(&chan
->chan
);
1842 spin_lock_init(&chan
->lock
);
1843 INIT_LIST_HEAD(&chan
->pend_list
);
1844 INIT_LIST_HEAD(&chan
->done_list
);
1845 tasklet_init(&chan
->tasklet
, pl08x_tasklet
,
1846 (unsigned long) chan
);
1848 list_add_tail(&chan
->chan
.device_node
, &dmadev
->channels
);
1850 dev_info(&pl08x
->adev
->dev
, "initialized %d virtual %s channels\n",
1851 i
, slave
? "slave" : "memcpy");
1855 static void pl08x_free_virtual_channels(struct dma_device
*dmadev
)
1857 struct pl08x_dma_chan
*chan
= NULL
;
1858 struct pl08x_dma_chan
*next
;
1860 list_for_each_entry_safe(chan
,
1861 next
, &dmadev
->channels
, chan
.device_node
) {
1862 list_del(&chan
->chan
.device_node
);
1867 #ifdef CONFIG_DEBUG_FS
1868 static const char *pl08x_state_str(enum pl08x_dma_chan_state state
)
1871 case PL08X_CHAN_IDLE
:
1873 case PL08X_CHAN_RUNNING
:
1875 case PL08X_CHAN_PAUSED
:
1877 case PL08X_CHAN_WAITING
:
1882 return "UNKNOWN STATE";
1885 static int pl08x_debugfs_show(struct seq_file
*s
, void *data
)
1887 struct pl08x_driver_data
*pl08x
= s
->private;
1888 struct pl08x_dma_chan
*chan
;
1889 struct pl08x_phy_chan
*ch
;
1890 unsigned long flags
;
1893 seq_printf(s
, "PL08x physical channels:\n");
1894 seq_printf(s
, "CHANNEL:\tUSER:\n");
1895 seq_printf(s
, "--------\t-----\n");
1896 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1897 struct pl08x_dma_chan
*virt_chan
;
1899 ch
= &pl08x
->phy_chans
[i
];
1901 spin_lock_irqsave(&ch
->lock
, flags
);
1902 virt_chan
= ch
->serving
;
1904 seq_printf(s
, "%d\t\t%s%s\n",
1906 virt_chan
? virt_chan
->name
: "(none)",
1907 ch
->locked
? " LOCKED" : "");
1909 spin_unlock_irqrestore(&ch
->lock
, flags
);
1912 seq_printf(s
, "\nPL08x virtual memcpy channels:\n");
1913 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1914 seq_printf(s
, "--------\t------\n");
1915 list_for_each_entry(chan
, &pl08x
->memcpy
.channels
, chan
.device_node
) {
1916 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1917 pl08x_state_str(chan
->state
));
1920 seq_printf(s
, "\nPL08x virtual slave channels:\n");
1921 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1922 seq_printf(s
, "--------\t------\n");
1923 list_for_each_entry(chan
, &pl08x
->slave
.channels
, chan
.device_node
) {
1924 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1925 pl08x_state_str(chan
->state
));
1931 static int pl08x_debugfs_open(struct inode
*inode
, struct file
*file
)
1933 return single_open(file
, pl08x_debugfs_show
, inode
->i_private
);
1936 static const struct file_operations pl08x_debugfs_operations
= {
1937 .open
= pl08x_debugfs_open
,
1939 .llseek
= seq_lseek
,
1940 .release
= single_release
,
1943 static void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1945 /* Expose a simple debugfs interface to view all clocks */
1946 (void) debugfs_create_file(dev_name(&pl08x
->adev
->dev
),
1947 S_IFREG
| S_IRUGO
, NULL
, pl08x
,
1948 &pl08x_debugfs_operations
);
1952 static inline void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1957 static int pl08x_probe(struct amba_device
*adev
, const struct amba_id
*id
)
1959 struct pl08x_driver_data
*pl08x
;
1960 const struct vendor_data
*vd
= id
->data
;
1964 ret
= amba_request_regions(adev
, NULL
);
1968 /* Create the driver state holder */
1969 pl08x
= kzalloc(sizeof(*pl08x
), GFP_KERNEL
);
1975 /* Initialize memcpy engine */
1976 dma_cap_set(DMA_MEMCPY
, pl08x
->memcpy
.cap_mask
);
1977 pl08x
->memcpy
.dev
= &adev
->dev
;
1978 pl08x
->memcpy
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1979 pl08x
->memcpy
.device_free_chan_resources
= pl08x_free_chan_resources
;
1980 pl08x
->memcpy
.device_prep_dma_memcpy
= pl08x_prep_dma_memcpy
;
1981 pl08x
->memcpy
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1982 pl08x
->memcpy
.device_tx_status
= pl08x_dma_tx_status
;
1983 pl08x
->memcpy
.device_issue_pending
= pl08x_issue_pending
;
1984 pl08x
->memcpy
.device_control
= pl08x_control
;
1986 /* Initialize slave engine */
1987 dma_cap_set(DMA_SLAVE
, pl08x
->slave
.cap_mask
);
1988 pl08x
->slave
.dev
= &adev
->dev
;
1989 pl08x
->slave
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1990 pl08x
->slave
.device_free_chan_resources
= pl08x_free_chan_resources
;
1991 pl08x
->slave
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1992 pl08x
->slave
.device_tx_status
= pl08x_dma_tx_status
;
1993 pl08x
->slave
.device_issue_pending
= pl08x_issue_pending
;
1994 pl08x
->slave
.device_prep_slave_sg
= pl08x_prep_slave_sg
;
1995 pl08x
->slave
.device_control
= pl08x_control
;
1997 /* Get the platform data */
1998 pl08x
->pd
= dev_get_platdata(&adev
->dev
);
2000 dev_err(&adev
->dev
, "no platform data supplied\n");
2001 goto out_no_platdata
;
2004 /* Assign useful pointers to the driver state */
2008 /* By default, AHB1 only. If dualmaster, from platform */
2009 pl08x
->lli_buses
= PL08X_AHB1
;
2010 pl08x
->mem_buses
= PL08X_AHB1
;
2011 if (pl08x
->vd
->dualmaster
) {
2012 pl08x
->lli_buses
= pl08x
->pd
->lli_buses
;
2013 pl08x
->mem_buses
= pl08x
->pd
->mem_buses
;
2016 /* A DMA memory pool for LLIs, align on 1-byte boundary */
2017 pl08x
->pool
= dma_pool_create(DRIVER_NAME
, &pl08x
->adev
->dev
,
2018 PL08X_LLI_TSFR_SIZE
, PL08X_ALIGN
, 0);
2021 goto out_no_lli_pool
;
2024 pl08x
->base
= ioremap(adev
->res
.start
, resource_size(&adev
->res
));
2027 goto out_no_ioremap
;
2030 /* Turn on the PL08x */
2031 pl08x_ensure_on(pl08x
);
2033 /* Attach the interrupt handler */
2034 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
2035 writel(0x000000FF, pl08x
->base
+ PL080_TC_CLEAR
);
2037 ret
= request_irq(adev
->irq
[0], pl08x_irq
, IRQF_DISABLED
,
2038 DRIVER_NAME
, pl08x
);
2040 dev_err(&adev
->dev
, "%s failed to request interrupt %d\n",
2041 __func__
, adev
->irq
[0]);
2045 /* Initialize physical channels */
2046 pl08x
->phy_chans
= kzalloc((vd
->channels
* sizeof(*pl08x
->phy_chans
)),
2048 if (!pl08x
->phy_chans
) {
2049 dev_err(&adev
->dev
, "%s failed to allocate "
2050 "physical channel holders\n",
2052 goto out_no_phychans
;
2055 for (i
= 0; i
< vd
->channels
; i
++) {
2056 struct pl08x_phy_chan
*ch
= &pl08x
->phy_chans
[i
];
2059 ch
->base
= pl08x
->base
+ PL080_Cx_BASE(i
);
2060 spin_lock_init(&ch
->lock
);
2063 * Nomadik variants can have channels that are locked
2064 * down for the secure world only. Lock up these channels
2065 * by perpetually serving a dummy virtual channel.
2070 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
2071 if (val
& (PL080N_CONFIG_ITPROT
| PL080N_CONFIG_SECPROT
)) {
2072 dev_info(&adev
->dev
, "physical channel %d reserved for secure access only\n", i
);
2077 dev_dbg(&adev
->dev
, "physical channel %d is %s\n",
2078 i
, pl08x_phy_channel_busy(ch
) ? "BUSY" : "FREE");
2081 /* Register as many memcpy channels as there are physical channels */
2082 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->memcpy
,
2083 pl08x
->vd
->channels
, false);
2085 dev_warn(&pl08x
->adev
->dev
,
2086 "%s failed to enumerate memcpy channels - %d\n",
2090 pl08x
->memcpy
.chancnt
= ret
;
2092 /* Register slave channels */
2093 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->slave
,
2094 pl08x
->pd
->num_slave_channels
, true);
2096 dev_warn(&pl08x
->adev
->dev
,
2097 "%s failed to enumerate slave channels - %d\n",
2101 pl08x
->slave
.chancnt
= ret
;
2103 ret
= dma_async_device_register(&pl08x
->memcpy
);
2105 dev_warn(&pl08x
->adev
->dev
,
2106 "%s failed to register memcpy as an async device - %d\n",
2108 goto out_no_memcpy_reg
;
2111 ret
= dma_async_device_register(&pl08x
->slave
);
2113 dev_warn(&pl08x
->adev
->dev
,
2114 "%s failed to register slave as an async device - %d\n",
2116 goto out_no_slave_reg
;
2119 amba_set_drvdata(adev
, pl08x
);
2120 init_pl08x_debugfs(pl08x
);
2121 dev_info(&pl08x
->adev
->dev
, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2122 amba_part(adev
), amba_rev(adev
),
2123 (unsigned long long)adev
->res
.start
, adev
->irq
[0]);
2128 dma_async_device_unregister(&pl08x
->memcpy
);
2130 pl08x_free_virtual_channels(&pl08x
->slave
);
2132 pl08x_free_virtual_channels(&pl08x
->memcpy
);
2134 kfree(pl08x
->phy_chans
);
2136 free_irq(adev
->irq
[0], pl08x
);
2138 iounmap(pl08x
->base
);
2140 dma_pool_destroy(pl08x
->pool
);
2145 amba_release_regions(adev
);
2149 /* PL080 has 8 channels and the PL080 have just 2 */
2150 static struct vendor_data vendor_pl080
= {
2155 static struct vendor_data vendor_nomadik
= {
2161 static struct vendor_data vendor_pl081
= {
2163 .dualmaster
= false,
2166 static struct amba_id pl08x_ids
[] = {
2171 .data
= &vendor_pl080
,
2177 .data
= &vendor_pl081
,
2179 /* Nomadik 8815 PL080 variant */
2183 .data
= &vendor_nomadik
,
2188 MODULE_DEVICE_TABLE(amba
, pl08x_ids
);
2190 static struct amba_driver pl08x_amba_driver
= {
2191 .drv
.name
= DRIVER_NAME
,
2192 .id_table
= pl08x_ids
,
2193 .probe
= pl08x_probe
,
2196 static int __init
pl08x_init(void)
2199 retval
= amba_driver_register(&pl08x_amba_driver
);
2201 printk(KERN_WARNING DRIVER_NAME
2202 "failed to register as an AMBA device (%d)\n",
2206 subsys_initcall(pl08x_init
);