2 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
4 * Copyright (C) 2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
13 * The only Atmel DMA Controller that is not covered by this driver is the one
14 * found on AT91SAM9263.
17 #include <dt-bindings/dma/at91.h>
18 #include <linux/clk.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dmapool.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
27 #include <linux/of_device.h>
28 #include <linux/of_dma.h>
30 #include "at_hdmac_regs.h"
31 #include "dmaengine.h"
37 * at_hdmac : Name of the ATmel AHB DMA Controller
38 * at_dma_ / atdma : ATmel DMA controller entity related
39 * atc_ / atchan : ATmel DMA Channel entity related
42 #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
43 #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
44 |ATC_DIF(AT_DMA_MEM_IF))
45 #define ATC_DMA_BUSWIDTHS\
46 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
47 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
48 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
49 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
51 #define ATC_MAX_DSCR_TRIALS 10
54 * Initial number of descriptors to allocate for each channel. This could
55 * be increased during dma usage.
57 static unsigned int init_nr_desc_per_channel
= 64;
58 module_param(init_nr_desc_per_channel
, uint
, 0644);
59 MODULE_PARM_DESC(init_nr_desc_per_channel
,
60 "initial descriptors per channel (default: 64)");
64 static dma_cookie_t
atc_tx_submit(struct dma_async_tx_descriptor
*tx
);
65 static void atc_issue_pending(struct dma_chan
*chan
);
68 /*----------------------------------------------------------------------*/
70 static inline unsigned int atc_get_xfer_width(dma_addr_t src
, dma_addr_t dst
,
75 if (!((src
| dst
| len
) & 3))
77 else if (!((src
| dst
| len
) & 1))
85 static struct at_desc
*atc_first_active(struct at_dma_chan
*atchan
)
87 return list_first_entry(&atchan
->active_list
,
88 struct at_desc
, desc_node
);
91 static struct at_desc
*atc_first_queued(struct at_dma_chan
*atchan
)
93 return list_first_entry(&atchan
->queue
,
94 struct at_desc
, desc_node
);
98 * atc_alloc_descriptor - allocate and return an initialized descriptor
99 * @chan: the channel to allocate descriptors for
100 * @gfp_flags: GFP allocation flags
102 * Note: The ack-bit is positioned in the descriptor flag at creation time
103 * to make initial allocation more convenient. This bit will be cleared
104 * and control will be given to client at usage time (during
105 * preparation functions).
107 static struct at_desc
*atc_alloc_descriptor(struct dma_chan
*chan
,
110 struct at_desc
*desc
= NULL
;
111 struct at_dma
*atdma
= to_at_dma(chan
->device
);
114 desc
= dma_pool_alloc(atdma
->dma_desc_pool
, gfp_flags
, &phys
);
116 memset(desc
, 0, sizeof(struct at_desc
));
117 INIT_LIST_HEAD(&desc
->tx_list
);
118 dma_async_tx_descriptor_init(&desc
->txd
, chan
);
119 /* txd.flags will be overwritten in prep functions */
120 desc
->txd
.flags
= DMA_CTRL_ACK
;
121 desc
->txd
.tx_submit
= atc_tx_submit
;
122 desc
->txd
.phys
= phys
;
129 * atc_desc_get - get an unused descriptor from free_list
130 * @atchan: channel we want a new descriptor for
132 static struct at_desc
*atc_desc_get(struct at_dma_chan
*atchan
)
134 struct at_desc
*desc
, *_desc
;
135 struct at_desc
*ret
= NULL
;
140 spin_lock_irqsave(&atchan
->lock
, flags
);
141 list_for_each_entry_safe(desc
, _desc
, &atchan
->free_list
, desc_node
) {
143 if (async_tx_test_ack(&desc
->txd
)) {
144 list_del(&desc
->desc_node
);
148 dev_dbg(chan2dev(&atchan
->chan_common
),
149 "desc %p not ACKed\n", desc
);
151 spin_unlock_irqrestore(&atchan
->lock
, flags
);
152 dev_vdbg(chan2dev(&atchan
->chan_common
),
153 "scanned %u descriptors on freelist\n", i
);
155 /* no more descriptor available in initial pool: create one more */
157 ret
= atc_alloc_descriptor(&atchan
->chan_common
, GFP_ATOMIC
);
159 spin_lock_irqsave(&atchan
->lock
, flags
);
160 atchan
->descs_allocated
++;
161 spin_unlock_irqrestore(&atchan
->lock
, flags
);
163 dev_err(chan2dev(&atchan
->chan_common
),
164 "not enough descriptors available\n");
172 * atc_desc_put - move a descriptor, including any children, to the free list
173 * @atchan: channel we work on
174 * @desc: descriptor, at the head of a chain, to move to free list
176 static void atc_desc_put(struct at_dma_chan
*atchan
, struct at_desc
*desc
)
179 struct at_desc
*child
;
182 spin_lock_irqsave(&atchan
->lock
, flags
);
183 list_for_each_entry(child
, &desc
->tx_list
, desc_node
)
184 dev_vdbg(chan2dev(&atchan
->chan_common
),
185 "moving child desc %p to freelist\n",
187 list_splice_init(&desc
->tx_list
, &atchan
->free_list
);
188 dev_vdbg(chan2dev(&atchan
->chan_common
),
189 "moving desc %p to freelist\n", desc
);
190 list_add(&desc
->desc_node
, &atchan
->free_list
);
191 spin_unlock_irqrestore(&atchan
->lock
, flags
);
196 * atc_desc_chain - build chain adding a descriptor
197 * @first: address of first descriptor of the chain
198 * @prev: address of previous descriptor of the chain
199 * @desc: descriptor to queue
201 * Called from prep_* functions
203 static void atc_desc_chain(struct at_desc
**first
, struct at_desc
**prev
,
204 struct at_desc
*desc
)
209 /* inform the HW lli about chaining */
210 (*prev
)->lli
.dscr
= desc
->txd
.phys
;
211 /* insert the link descriptor to the LD ring */
212 list_add_tail(&desc
->desc_node
,
219 * atc_dostart - starts the DMA engine for real
220 * @atchan: the channel we want to start
221 * @first: first descriptor in the list we want to begin with
223 * Called with atchan->lock held and bh disabled
225 static void atc_dostart(struct at_dma_chan
*atchan
, struct at_desc
*first
)
227 struct at_dma
*atdma
= to_at_dma(atchan
->chan_common
.device
);
229 /* ASSERT: channel is idle */
230 if (atc_chan_is_enabled(atchan
)) {
231 dev_err(chan2dev(&atchan
->chan_common
),
232 "BUG: Attempted to start non-idle channel\n");
233 dev_err(chan2dev(&atchan
->chan_common
),
234 " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
235 channel_readl(atchan
, SADDR
),
236 channel_readl(atchan
, DADDR
),
237 channel_readl(atchan
, CTRLA
),
238 channel_readl(atchan
, CTRLB
),
239 channel_readl(atchan
, DSCR
));
241 /* The tasklet will hopefully advance the queue... */
245 vdbg_dump_regs(atchan
);
247 channel_writel(atchan
, SADDR
, 0);
248 channel_writel(atchan
, DADDR
, 0);
249 channel_writel(atchan
, CTRLA
, 0);
250 channel_writel(atchan
, CTRLB
, 0);
251 channel_writel(atchan
, DSCR
, first
->txd
.phys
);
252 channel_writel(atchan
, SPIP
, ATC_SPIP_HOLE(first
->src_hole
) |
253 ATC_SPIP_BOUNDARY(first
->boundary
));
254 channel_writel(atchan
, DPIP
, ATC_DPIP_HOLE(first
->dst_hole
) |
255 ATC_DPIP_BOUNDARY(first
->boundary
));
256 dma_writel(atdma
, CHER
, atchan
->mask
);
258 vdbg_dump_regs(atchan
);
262 * atc_get_desc_by_cookie - get the descriptor of a cookie
263 * @atchan: the DMA channel
264 * @cookie: the cookie to get the descriptor for
266 static struct at_desc
*atc_get_desc_by_cookie(struct at_dma_chan
*atchan
,
269 struct at_desc
*desc
, *_desc
;
271 list_for_each_entry_safe(desc
, _desc
, &atchan
->queue
, desc_node
) {
272 if (desc
->txd
.cookie
== cookie
)
276 list_for_each_entry_safe(desc
, _desc
, &atchan
->active_list
, desc_node
) {
277 if (desc
->txd
.cookie
== cookie
)
285 * atc_calc_bytes_left - calculates the number of bytes left according to the
286 * value read from CTRLA.
288 * @current_len: the number of bytes left before reading CTRLA
289 * @ctrla: the value of CTRLA
291 static inline int atc_calc_bytes_left(int current_len
, u32 ctrla
)
293 u32 btsize
= (ctrla
& ATC_BTSIZE_MAX
);
294 u32 src_width
= ATC_REG_TO_SRC_WIDTH(ctrla
);
297 * According to the datasheet, when reading the Control A Register
298 * (ctrla), the Buffer Transfer Size (btsize) bitfield refers to the
299 * number of transfers completed on the Source Interface.
300 * So btsize is always a number of source width transfers.
302 return current_len
- (btsize
<< src_width
);
306 * atc_get_bytes_left - get the number of bytes residue for a cookie
308 * @cookie: transaction identifier to check status of
310 static int atc_get_bytes_left(struct dma_chan
*chan
, dma_cookie_t cookie
)
312 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
313 struct at_desc
*desc_first
= atc_first_active(atchan
);
314 struct at_desc
*desc
;
316 u32 ctrla
, dscr
, trials
;
319 * If the cookie doesn't match to the currently running transfer then
320 * we can return the total length of the associated DMA transfer,
321 * because it is still queued.
323 desc
= atc_get_desc_by_cookie(atchan
, cookie
);
326 else if (desc
!= desc_first
)
327 return desc
->total_len
;
329 /* cookie matches to the currently running transfer */
330 ret
= desc_first
->total_len
;
332 if (desc_first
->lli
.dscr
) {
333 /* hardware linked list transfer */
336 * Calculate the residue by removing the length of the child
337 * descriptors already transferred from the total length.
338 * To get the current child descriptor we can use the value of
339 * the channel's DSCR register and compare it against the value
340 * of the hardware linked list structure of each child
343 * The CTRLA register provides us with the amount of data
344 * already read from the source for the current child
345 * descriptor. So we can compute a more accurate residue by also
346 * removing the number of bytes corresponding to this amount of
349 * However, the DSCR and CTRLA registers cannot be read both
350 * atomically. Hence a race condition may occur: the first read
351 * register may refer to one child descriptor whereas the second
352 * read may refer to a later child descriptor in the list
353 * because of the DMA transfer progression inbetween the two
356 * One solution could have been to pause the DMA transfer, read
357 * the DSCR and CTRLA then resume the DMA transfer. Nonetheless,
358 * this approach presents some drawbacks:
359 * - If the DMA transfer is paused, RX overruns or TX underruns
360 * are more likey to occur depending on the system latency.
361 * Taking the USART driver as an example, it uses a cyclic DMA
362 * transfer to read data from the Receive Holding Register
363 * (RHR) to avoid RX overruns since the RHR is not protected
364 * by any FIFO on most Atmel SoCs. So pausing the DMA transfer
365 * to compute the residue would break the USART driver design.
366 * - The atc_pause() function masks interrupts but we'd rather
367 * avoid to do so for system latency purpose.
369 * Then we'd rather use another solution: the DSCR is read a
370 * first time, the CTRLA is read in turn, next the DSCR is read
371 * a second time. If the two consecutive read values of the DSCR
372 * are the same then we assume both refers to the very same
373 * child descriptor as well as the CTRLA value read inbetween
374 * does. For cyclic tranfers, the assumption is that a full loop
376 * If the two DSCR values are different, we read again the CTRLA
377 * then the DSCR till two consecutive read values from DSCR are
378 * equal or till the maxium trials is reach.
379 * This algorithm is very unlikely not to find a stable value for
383 dscr
= channel_readl(atchan
, DSCR
);
384 rmb(); /* ensure DSCR is read before CTRLA */
385 ctrla
= channel_readl(atchan
, CTRLA
);
386 for (trials
= 0; trials
< ATC_MAX_DSCR_TRIALS
; ++trials
) {
389 rmb(); /* ensure DSCR is read after CTRLA */
390 new_dscr
= channel_readl(atchan
, DSCR
);
393 * If the DSCR register value has not changed inside the
394 * DMA controller since the previous read, we assume
395 * that both the dscr and ctrla values refers to the
396 * very same descriptor.
398 if (likely(new_dscr
== dscr
))
402 * DSCR has changed inside the DMA controller, so the
403 * previouly read value of CTRLA may refer to an already
404 * processed descriptor hence could be outdated.
405 * We need to update ctrla to match the current
409 rmb(); /* ensure DSCR is read before CTRLA */
410 ctrla
= channel_readl(atchan
, CTRLA
);
412 if (unlikely(trials
>= ATC_MAX_DSCR_TRIALS
))
415 /* for the first descriptor we can be more accurate */
416 if (desc_first
->lli
.dscr
== dscr
)
417 return atc_calc_bytes_left(ret
, ctrla
);
419 ret
-= desc_first
->len
;
420 list_for_each_entry(desc
, &desc_first
->tx_list
, desc_node
) {
421 if (desc
->lli
.dscr
== dscr
)
428 * For the current descriptor in the chain we can calculate
429 * the remaining bytes using the channel's register.
431 ret
= atc_calc_bytes_left(ret
, ctrla
);
433 /* single transfer */
434 ctrla
= channel_readl(atchan
, CTRLA
);
435 ret
= atc_calc_bytes_left(ret
, ctrla
);
442 * atc_chain_complete - finish work for one transaction chain
443 * @atchan: channel we work on
444 * @desc: descriptor at the head of the chain we want do complete
446 * Called with atchan->lock held and bh disabled */
448 atc_chain_complete(struct at_dma_chan
*atchan
, struct at_desc
*desc
)
450 struct dma_async_tx_descriptor
*txd
= &desc
->txd
;
451 struct at_dma
*atdma
= to_at_dma(atchan
->chan_common
.device
);
453 dev_vdbg(chan2dev(&atchan
->chan_common
),
454 "descriptor %u complete\n", txd
->cookie
);
456 /* mark the descriptor as complete for non cyclic cases only */
457 if (!atc_chan_is_cyclic(atchan
))
458 dma_cookie_complete(txd
);
460 /* If the transfer was a memset, free our temporary buffer */
462 dma_pool_free(atdma
->memset_pool
, desc
->memset_vaddr
,
464 desc
->memset
= false;
467 /* move children to free_list */
468 list_splice_init(&desc
->tx_list
, &atchan
->free_list
);
469 /* move myself to free_list */
470 list_move(&desc
->desc_node
, &atchan
->free_list
);
472 dma_descriptor_unmap(txd
);
473 /* for cyclic transfers,
474 * no need to replay callback function while stopping */
475 if (!atc_chan_is_cyclic(atchan
)) {
476 dma_async_tx_callback callback
= txd
->callback
;
477 void *param
= txd
->callback_param
;
480 * The API requires that no submissions are done from a
481 * callback, so we don't need to drop the lock here
487 dma_run_dependencies(txd
);
491 * atc_complete_all - finish work for all transactions
492 * @atchan: channel to complete transactions for
494 * Eventually submit queued descriptors if any
496 * Assume channel is idle while calling this function
497 * Called with atchan->lock held and bh disabled
499 static void atc_complete_all(struct at_dma_chan
*atchan
)
501 struct at_desc
*desc
, *_desc
;
504 dev_vdbg(chan2dev(&atchan
->chan_common
), "complete all\n");
507 * Submit queued descriptors ASAP, i.e. before we go through
508 * the completed ones.
510 if (!list_empty(&atchan
->queue
))
511 atc_dostart(atchan
, atc_first_queued(atchan
));
512 /* empty active_list now it is completed */
513 list_splice_init(&atchan
->active_list
, &list
);
514 /* empty queue list by moving descriptors (if any) to active_list */
515 list_splice_init(&atchan
->queue
, &atchan
->active_list
);
517 list_for_each_entry_safe(desc
, _desc
, &list
, desc_node
)
518 atc_chain_complete(atchan
, desc
);
522 * atc_advance_work - at the end of a transaction, move forward
523 * @atchan: channel where the transaction ended
525 * Called with atchan->lock held and bh disabled
527 static void atc_advance_work(struct at_dma_chan
*atchan
)
529 dev_vdbg(chan2dev(&atchan
->chan_common
), "advance_work\n");
531 if (atc_chan_is_enabled(atchan
))
534 if (list_empty(&atchan
->active_list
) ||
535 list_is_singular(&atchan
->active_list
)) {
536 atc_complete_all(atchan
);
538 atc_chain_complete(atchan
, atc_first_active(atchan
));
540 atc_dostart(atchan
, atc_first_active(atchan
));
546 * atc_handle_error - handle errors reported by DMA controller
547 * @atchan: channel where error occurs
549 * Called with atchan->lock held and bh disabled
551 static void atc_handle_error(struct at_dma_chan
*atchan
)
553 struct at_desc
*bad_desc
;
554 struct at_desc
*child
;
557 * The descriptor currently at the head of the active list is
558 * broked. Since we don't have any way to report errors, we'll
559 * just have to scream loudly and try to carry on.
561 bad_desc
= atc_first_active(atchan
);
562 list_del_init(&bad_desc
->desc_node
);
564 /* As we are stopped, take advantage to push queued descriptors
566 list_splice_init(&atchan
->queue
, atchan
->active_list
.prev
);
568 /* Try to restart the controller */
569 if (!list_empty(&atchan
->active_list
))
570 atc_dostart(atchan
, atc_first_active(atchan
));
573 * KERN_CRITICAL may seem harsh, but since this only happens
574 * when someone submits a bad physical address in a
575 * descriptor, we should consider ourselves lucky that the
576 * controller flagged an error instead of scribbling over
577 * random memory locations.
579 dev_crit(chan2dev(&atchan
->chan_common
),
580 "Bad descriptor submitted for DMA!\n");
581 dev_crit(chan2dev(&atchan
->chan_common
),
582 " cookie: %d\n", bad_desc
->txd
.cookie
);
583 atc_dump_lli(atchan
, &bad_desc
->lli
);
584 list_for_each_entry(child
, &bad_desc
->tx_list
, desc_node
)
585 atc_dump_lli(atchan
, &child
->lli
);
587 /* Pretend the descriptor completed successfully */
588 atc_chain_complete(atchan
, bad_desc
);
592 * atc_handle_cyclic - at the end of a period, run callback function
593 * @atchan: channel used for cyclic operations
595 * Called with atchan->lock held and bh disabled
597 static void atc_handle_cyclic(struct at_dma_chan
*atchan
)
599 struct at_desc
*first
= atc_first_active(atchan
);
600 struct dma_async_tx_descriptor
*txd
= &first
->txd
;
601 dma_async_tx_callback callback
= txd
->callback
;
602 void *param
= txd
->callback_param
;
604 dev_vdbg(chan2dev(&atchan
->chan_common
),
605 "new cyclic period llp 0x%08x\n",
606 channel_readl(atchan
, DSCR
));
612 /*-- IRQ & Tasklet ---------------------------------------------------*/
614 static void atc_tasklet(unsigned long data
)
616 struct at_dma_chan
*atchan
= (struct at_dma_chan
*)data
;
619 spin_lock_irqsave(&atchan
->lock
, flags
);
620 if (test_and_clear_bit(ATC_IS_ERROR
, &atchan
->status
))
621 atc_handle_error(atchan
);
622 else if (atc_chan_is_cyclic(atchan
))
623 atc_handle_cyclic(atchan
);
625 atc_advance_work(atchan
);
627 spin_unlock_irqrestore(&atchan
->lock
, flags
);
630 static irqreturn_t
at_dma_interrupt(int irq
, void *dev_id
)
632 struct at_dma
*atdma
= (struct at_dma
*)dev_id
;
633 struct at_dma_chan
*atchan
;
635 u32 status
, pending
, imr
;
639 imr
= dma_readl(atdma
, EBCIMR
);
640 status
= dma_readl(atdma
, EBCISR
);
641 pending
= status
& imr
;
646 dev_vdbg(atdma
->dma_common
.dev
,
647 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
648 status
, imr
, pending
);
650 for (i
= 0; i
< atdma
->dma_common
.chancnt
; i
++) {
651 atchan
= &atdma
->chan
[i
];
652 if (pending
& (AT_DMA_BTC(i
) | AT_DMA_ERR(i
))) {
653 if (pending
& AT_DMA_ERR(i
)) {
654 /* Disable channel on AHB error */
655 dma_writel(atdma
, CHDR
,
656 AT_DMA_RES(i
) | atchan
->mask
);
657 /* Give information to tasklet */
658 set_bit(ATC_IS_ERROR
, &atchan
->status
);
660 tasklet_schedule(&atchan
->tasklet
);
671 /*-- DMA Engine API --------------------------------------------------*/
674 * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
675 * @desc: descriptor at the head of the transaction chain
677 * Queue chain if DMA engine is working already
679 * Cookie increment and adding to active_list or queue must be atomic
681 static dma_cookie_t
atc_tx_submit(struct dma_async_tx_descriptor
*tx
)
683 struct at_desc
*desc
= txd_to_at_desc(tx
);
684 struct at_dma_chan
*atchan
= to_at_dma_chan(tx
->chan
);
688 spin_lock_irqsave(&atchan
->lock
, flags
);
689 cookie
= dma_cookie_assign(tx
);
691 if (list_empty(&atchan
->active_list
)) {
692 dev_vdbg(chan2dev(tx
->chan
), "tx_submit: started %u\n",
694 atc_dostart(atchan
, desc
);
695 list_add_tail(&desc
->desc_node
, &atchan
->active_list
);
697 dev_vdbg(chan2dev(tx
->chan
), "tx_submit: queued %u\n",
699 list_add_tail(&desc
->desc_node
, &atchan
->queue
);
702 spin_unlock_irqrestore(&atchan
->lock
, flags
);
708 * atc_prep_dma_interleaved - prepare memory to memory interleaved operation
709 * @chan: the channel to prepare operation on
710 * @xt: Interleaved transfer template
711 * @flags: tx descriptor status flags
713 static struct dma_async_tx_descriptor
*
714 atc_prep_dma_interleaved(struct dma_chan
*chan
,
715 struct dma_interleaved_template
*xt
,
718 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
719 struct data_chunk
*first
= xt
->sgl
;
720 struct at_desc
*desc
= NULL
;
728 if (unlikely(!xt
|| xt
->numf
!= 1 || !xt
->frame_size
))
731 dev_info(chan2dev(chan
),
732 "%s: src=0x%08x, dest=0x%08x, numf=%d, frame_size=%d, flags=0x%lx\n",
733 __func__
, xt
->src_start
, xt
->dst_start
, xt
->numf
,
734 xt
->frame_size
, flags
);
737 * The controller can only "skip" X bytes every Y bytes, so we
738 * need to make sure we are given a template that fit that
739 * description, ie a template with chunks that always have the
740 * same size, with the same ICGs.
742 for (i
= 0; i
< xt
->frame_size
; i
++) {
743 struct data_chunk
*chunk
= xt
->sgl
+ i
;
745 if ((chunk
->size
!= xt
->sgl
->size
) ||
746 (dmaengine_get_dst_icg(xt
, chunk
) != dmaengine_get_dst_icg(xt
, first
)) ||
747 (dmaengine_get_src_icg(xt
, chunk
) != dmaengine_get_src_icg(xt
, first
))) {
748 dev_err(chan2dev(chan
),
749 "%s: the controller can transfer only identical chunks\n",
757 dwidth
= atc_get_xfer_width(xt
->src_start
,
760 xfer_count
= len
>> dwidth
;
761 if (xfer_count
> ATC_BTSIZE_MAX
) {
762 dev_err(chan2dev(chan
), "%s: buffer is too big\n", __func__
);
766 ctrla
= ATC_SRC_WIDTH(dwidth
) |
767 ATC_DST_WIDTH(dwidth
);
769 ctrlb
= ATC_DEFAULT_CTRLB
| ATC_IEN
770 | ATC_SRC_ADDR_MODE_INCR
771 | ATC_DST_ADDR_MODE_INCR
776 /* create the transfer */
777 desc
= atc_desc_get(atchan
);
779 dev_err(chan2dev(chan
),
780 "%s: couldn't allocate our descriptor\n", __func__
);
784 desc
->lli
.saddr
= xt
->src_start
;
785 desc
->lli
.daddr
= xt
->dst_start
;
786 desc
->lli
.ctrla
= ctrla
| xfer_count
;
787 desc
->lli
.ctrlb
= ctrlb
;
789 desc
->boundary
= first
->size
>> dwidth
;
790 desc
->dst_hole
= (dmaengine_get_dst_icg(xt
, first
) >> dwidth
) + 1;
791 desc
->src_hole
= (dmaengine_get_src_icg(xt
, first
) >> dwidth
) + 1;
793 desc
->txd
.cookie
= -EBUSY
;
794 desc
->total_len
= desc
->len
= len
;
796 /* set end-of-link to the last link descriptor of list*/
799 desc
->txd
.flags
= flags
; /* client is in control of this ack */
805 * atc_prep_dma_memcpy - prepare a memcpy operation
806 * @chan: the channel to prepare operation on
807 * @dest: operation virtual destination address
808 * @src: operation virtual source address
809 * @len: operation length
810 * @flags: tx descriptor status flags
812 static struct dma_async_tx_descriptor
*
813 atc_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
814 size_t len
, unsigned long flags
)
816 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
817 struct at_desc
*desc
= NULL
;
818 struct at_desc
*first
= NULL
;
819 struct at_desc
*prev
= NULL
;
822 unsigned int src_width
;
823 unsigned int dst_width
;
827 dev_vdbg(chan2dev(chan
), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n",
828 dest
, src
, len
, flags
);
830 if (unlikely(!len
)) {
831 dev_dbg(chan2dev(chan
), "prep_dma_memcpy: length is zero!\n");
835 ctrlb
= ATC_DEFAULT_CTRLB
| ATC_IEN
836 | ATC_SRC_ADDR_MODE_INCR
837 | ATC_DST_ADDR_MODE_INCR
841 * We can be a lot more clever here, but this should take care
842 * of the most common optimization.
844 src_width
= dst_width
= atc_get_xfer_width(src
, dest
, len
);
846 ctrla
= ATC_SRC_WIDTH(src_width
) |
847 ATC_DST_WIDTH(dst_width
);
849 for (offset
= 0; offset
< len
; offset
+= xfer_count
<< src_width
) {
850 xfer_count
= min_t(size_t, (len
- offset
) >> src_width
,
853 desc
= atc_desc_get(atchan
);
857 desc
->lli
.saddr
= src
+ offset
;
858 desc
->lli
.daddr
= dest
+ offset
;
859 desc
->lli
.ctrla
= ctrla
| xfer_count
;
860 desc
->lli
.ctrlb
= ctrlb
;
862 desc
->txd
.cookie
= 0;
863 desc
->len
= xfer_count
<< src_width
;
865 atc_desc_chain(&first
, &prev
, desc
);
868 /* First descriptor of the chain embedds additional information */
869 first
->txd
.cookie
= -EBUSY
;
870 first
->total_len
= len
;
872 /* set end-of-link to the last link descriptor of list*/
875 first
->txd
.flags
= flags
; /* client is in control of this ack */
880 atc_desc_put(atchan
, first
);
885 * atc_prep_dma_memset - prepare a memcpy operation
886 * @chan: the channel to prepare operation on
887 * @dest: operation virtual destination address
888 * @value: value to set memory buffer to
889 * @len: operation length
890 * @flags: tx descriptor status flags
892 static struct dma_async_tx_descriptor
*
893 atc_prep_dma_memset(struct dma_chan
*chan
, dma_addr_t dest
, int value
,
894 size_t len
, unsigned long flags
)
896 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
897 struct at_dma
*atdma
= to_at_dma(chan
->device
);
898 struct at_desc
*desc
= NULL
;
903 dev_vdbg(chan2dev(chan
), "%s: d0x%x v0x%x l0x%zx f0x%lx\n", __func__
,
904 dest
, value
, len
, flags
);
906 if (unlikely(!len
)) {
907 dev_dbg(chan2dev(chan
), "%s: length is zero!\n", __func__
);
911 if (!is_dma_fill_aligned(chan
->device
, dest
, 0, len
)) {
912 dev_dbg(chan2dev(chan
), "%s: buffer is not aligned\n",
917 xfer_count
= len
>> 2;
918 if (xfer_count
> ATC_BTSIZE_MAX
) {
919 dev_err(chan2dev(chan
), "%s: buffer is too big\n",
924 ctrlb
= ATC_DEFAULT_CTRLB
| ATC_IEN
925 | ATC_SRC_ADDR_MODE_FIXED
926 | ATC_DST_ADDR_MODE_INCR
929 ctrla
= ATC_SRC_WIDTH(2) |
932 desc
= atc_desc_get(atchan
);
934 dev_err(chan2dev(chan
), "%s: can't get a descriptor\n",
939 desc
->memset_vaddr
= dma_pool_alloc(atdma
->memset_pool
, GFP_ATOMIC
,
940 &desc
->memset_paddr
);
941 if (!desc
->memset_vaddr
) {
942 dev_err(chan2dev(chan
), "%s: couldn't allocate buffer\n",
947 *desc
->memset_vaddr
= value
;
950 desc
->lli
.saddr
= desc
->memset_paddr
;
951 desc
->lli
.daddr
= dest
;
952 desc
->lli
.ctrla
= ctrla
| xfer_count
;
953 desc
->lli
.ctrlb
= ctrlb
;
955 desc
->txd
.cookie
= -EBUSY
;
957 desc
->total_len
= len
;
959 /* set end-of-link on the descriptor */
962 desc
->txd
.flags
= flags
;
967 atc_desc_put(atchan
, desc
);
973 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
975 * @sgl: scatterlist to transfer to/from
976 * @sg_len: number of entries in @scatterlist
977 * @direction: DMA direction
978 * @flags: tx descriptor status flags
979 * @context: transaction context (ignored)
981 static struct dma_async_tx_descriptor
*
982 atc_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
983 unsigned int sg_len
, enum dma_transfer_direction direction
,
984 unsigned long flags
, void *context
)
986 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
987 struct at_dma_slave
*atslave
= chan
->private;
988 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
989 struct at_desc
*first
= NULL
;
990 struct at_desc
*prev
= NULL
;
994 unsigned int reg_width
;
995 unsigned int mem_width
;
997 struct scatterlist
*sg
;
998 size_t total_len
= 0;
1000 dev_vdbg(chan2dev(chan
), "prep_slave_sg (%d): %s f0x%lx\n",
1002 direction
== DMA_MEM_TO_DEV
? "TO DEVICE" : "FROM DEVICE",
1005 if (unlikely(!atslave
|| !sg_len
)) {
1006 dev_dbg(chan2dev(chan
), "prep_slave_sg: sg length is zero!\n");
1010 ctrla
= ATC_SCSIZE(sconfig
->src_maxburst
)
1011 | ATC_DCSIZE(sconfig
->dst_maxburst
);
1014 switch (direction
) {
1015 case DMA_MEM_TO_DEV
:
1016 reg_width
= convert_buswidth(sconfig
->dst_addr_width
);
1017 ctrla
|= ATC_DST_WIDTH(reg_width
);
1018 ctrlb
|= ATC_DST_ADDR_MODE_FIXED
1019 | ATC_SRC_ADDR_MODE_INCR
1021 | ATC_SIF(atchan
->mem_if
) | ATC_DIF(atchan
->per_if
);
1022 reg
= sconfig
->dst_addr
;
1023 for_each_sg(sgl
, sg
, sg_len
, i
) {
1024 struct at_desc
*desc
;
1028 desc
= atc_desc_get(atchan
);
1032 mem
= sg_dma_address(sg
);
1033 len
= sg_dma_len(sg
);
1034 if (unlikely(!len
)) {
1035 dev_dbg(chan2dev(chan
),
1036 "prep_slave_sg: sg(%d) data length is zero\n", i
);
1040 if (unlikely(mem
& 3 || len
& 3))
1043 desc
->lli
.saddr
= mem
;
1044 desc
->lli
.daddr
= reg
;
1045 desc
->lli
.ctrla
= ctrla
1046 | ATC_SRC_WIDTH(mem_width
)
1048 desc
->lli
.ctrlb
= ctrlb
;
1051 atc_desc_chain(&first
, &prev
, desc
);
1055 case DMA_DEV_TO_MEM
:
1056 reg_width
= convert_buswidth(sconfig
->src_addr_width
);
1057 ctrla
|= ATC_SRC_WIDTH(reg_width
);
1058 ctrlb
|= ATC_DST_ADDR_MODE_INCR
1059 | ATC_SRC_ADDR_MODE_FIXED
1061 | ATC_SIF(atchan
->per_if
) | ATC_DIF(atchan
->mem_if
);
1063 reg
= sconfig
->src_addr
;
1064 for_each_sg(sgl
, sg
, sg_len
, i
) {
1065 struct at_desc
*desc
;
1069 desc
= atc_desc_get(atchan
);
1073 mem
= sg_dma_address(sg
);
1074 len
= sg_dma_len(sg
);
1075 if (unlikely(!len
)) {
1076 dev_dbg(chan2dev(chan
),
1077 "prep_slave_sg: sg(%d) data length is zero\n", i
);
1081 if (unlikely(mem
& 3 || len
& 3))
1084 desc
->lli
.saddr
= reg
;
1085 desc
->lli
.daddr
= mem
;
1086 desc
->lli
.ctrla
= ctrla
1087 | ATC_DST_WIDTH(mem_width
)
1089 desc
->lli
.ctrlb
= ctrlb
;
1092 atc_desc_chain(&first
, &prev
, desc
);
1100 /* set end-of-link to the last link descriptor of list*/
1103 /* First descriptor of the chain embedds additional information */
1104 first
->txd
.cookie
= -EBUSY
;
1105 first
->total_len
= total_len
;
1107 /* first link descriptor of list is responsible of flags */
1108 first
->txd
.flags
= flags
; /* client is in control of this ack */
1113 dev_err(chan2dev(chan
), "not enough descriptors available\n");
1115 atc_desc_put(atchan
, first
);
1120 * atc_prep_dma_sg - prepare memory to memory scather-gather operation
1121 * @chan: the channel to prepare operation on
1122 * @dst_sg: destination scatterlist
1123 * @dst_nents: number of destination scatterlist entries
1124 * @src_sg: source scatterlist
1125 * @src_nents: number of source scatterlist entries
1126 * @flags: tx descriptor status flags
1128 static struct dma_async_tx_descriptor
*
1129 atc_prep_dma_sg(struct dma_chan
*chan
,
1130 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
1131 struct scatterlist
*src_sg
, unsigned int src_nents
,
1132 unsigned long flags
)
1134 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1135 struct at_desc
*desc
= NULL
;
1136 struct at_desc
*first
= NULL
;
1137 struct at_desc
*prev
= NULL
;
1138 unsigned int src_width
;
1139 unsigned int dst_width
;
1143 size_t dst_len
= 0, src_len
= 0;
1144 dma_addr_t dst
= 0, src
= 0;
1145 size_t len
= 0, total_len
= 0;
1147 if (unlikely(dst_nents
== 0 || src_nents
== 0))
1150 if (unlikely(dst_sg
== NULL
|| src_sg
== NULL
))
1153 ctrlb
= ATC_DEFAULT_CTRLB
| ATC_IEN
1154 | ATC_SRC_ADDR_MODE_INCR
1155 | ATC_DST_ADDR_MODE_INCR
1159 * loop until there is either no more source or no more destination
1164 /* prepare the next transfer */
1167 /* no more destination scatterlist entries */
1168 if (!dst_sg
|| !dst_nents
)
1171 dst
= sg_dma_address(dst_sg
);
1172 dst_len
= sg_dma_len(dst_sg
);
1174 dst_sg
= sg_next(dst_sg
);
1180 /* no more source scatterlist entries */
1181 if (!src_sg
|| !src_nents
)
1184 src
= sg_dma_address(src_sg
);
1185 src_len
= sg_dma_len(src_sg
);
1187 src_sg
= sg_next(src_sg
);
1191 len
= min_t(size_t, src_len
, dst_len
);
1195 /* take care for the alignment */
1196 src_width
= dst_width
= atc_get_xfer_width(src
, dst
, len
);
1198 ctrla
= ATC_SRC_WIDTH(src_width
) |
1199 ATC_DST_WIDTH(dst_width
);
1202 * The number of transfers to set up refer to the source width
1203 * that depends on the alignment.
1205 xfer_count
= len
>> src_width
;
1206 if (xfer_count
> ATC_BTSIZE_MAX
) {
1207 xfer_count
= ATC_BTSIZE_MAX
;
1208 len
= ATC_BTSIZE_MAX
<< src_width
;
1211 /* create the transfer */
1212 desc
= atc_desc_get(atchan
);
1216 desc
->lli
.saddr
= src
;
1217 desc
->lli
.daddr
= dst
;
1218 desc
->lli
.ctrla
= ctrla
| xfer_count
;
1219 desc
->lli
.ctrlb
= ctrlb
;
1221 desc
->txd
.cookie
= 0;
1224 atc_desc_chain(&first
, &prev
, desc
);
1226 /* update the lengths and addresses for the next loop cycle */
1235 /* First descriptor of the chain embedds additional information */
1236 first
->txd
.cookie
= -EBUSY
;
1237 first
->total_len
= total_len
;
1239 /* set end-of-link to the last link descriptor of list*/
1242 first
->txd
.flags
= flags
; /* client is in control of this ack */
1247 atc_desc_put(atchan
, first
);
1252 * atc_dma_cyclic_check_values
1253 * Check for too big/unaligned periods and unaligned DMA buffer
1256 atc_dma_cyclic_check_values(unsigned int reg_width
, dma_addr_t buf_addr
,
1259 if (period_len
> (ATC_BTSIZE_MAX
<< reg_width
))
1261 if (unlikely(period_len
& ((1 << reg_width
) - 1)))
1263 if (unlikely(buf_addr
& ((1 << reg_width
) - 1)))
1273 * atc_dma_cyclic_fill_desc - Fill one period descriptor
1276 atc_dma_cyclic_fill_desc(struct dma_chan
*chan
, struct at_desc
*desc
,
1277 unsigned int period_index
, dma_addr_t buf_addr
,
1278 unsigned int reg_width
, size_t period_len
,
1279 enum dma_transfer_direction direction
)
1281 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1282 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
1285 /* prepare common CRTLA value */
1286 ctrla
= ATC_SCSIZE(sconfig
->src_maxburst
)
1287 | ATC_DCSIZE(sconfig
->dst_maxburst
)
1288 | ATC_DST_WIDTH(reg_width
)
1289 | ATC_SRC_WIDTH(reg_width
)
1290 | period_len
>> reg_width
;
1292 switch (direction
) {
1293 case DMA_MEM_TO_DEV
:
1294 desc
->lli
.saddr
= buf_addr
+ (period_len
* period_index
);
1295 desc
->lli
.daddr
= sconfig
->dst_addr
;
1296 desc
->lli
.ctrla
= ctrla
;
1297 desc
->lli
.ctrlb
= ATC_DST_ADDR_MODE_FIXED
1298 | ATC_SRC_ADDR_MODE_INCR
1300 | ATC_SIF(atchan
->mem_if
)
1301 | ATC_DIF(atchan
->per_if
);
1302 desc
->len
= period_len
;
1305 case DMA_DEV_TO_MEM
:
1306 desc
->lli
.saddr
= sconfig
->src_addr
;
1307 desc
->lli
.daddr
= buf_addr
+ (period_len
* period_index
);
1308 desc
->lli
.ctrla
= ctrla
;
1309 desc
->lli
.ctrlb
= ATC_DST_ADDR_MODE_INCR
1310 | ATC_SRC_ADDR_MODE_FIXED
1312 | ATC_SIF(atchan
->per_if
)
1313 | ATC_DIF(atchan
->mem_if
);
1314 desc
->len
= period_len
;
1325 * atc_prep_dma_cyclic - prepare the cyclic DMA transfer
1326 * @chan: the DMA channel to prepare
1327 * @buf_addr: physical DMA address where the buffer starts
1328 * @buf_len: total number of bytes for the entire buffer
1329 * @period_len: number of bytes for each period
1330 * @direction: transfer direction, to or from device
1331 * @flags: tx descriptor status flags
1333 static struct dma_async_tx_descriptor
*
1334 atc_prep_dma_cyclic(struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
1335 size_t period_len
, enum dma_transfer_direction direction
,
1336 unsigned long flags
)
1338 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1339 struct at_dma_slave
*atslave
= chan
->private;
1340 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
1341 struct at_desc
*first
= NULL
;
1342 struct at_desc
*prev
= NULL
;
1343 unsigned long was_cyclic
;
1344 unsigned int reg_width
;
1345 unsigned int periods
= buf_len
/ period_len
;
1348 dev_vdbg(chan2dev(chan
), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
1349 direction
== DMA_MEM_TO_DEV
? "TO DEVICE" : "FROM DEVICE",
1351 periods
, buf_len
, period_len
);
1353 if (unlikely(!atslave
|| !buf_len
|| !period_len
)) {
1354 dev_dbg(chan2dev(chan
), "prep_dma_cyclic: length is zero!\n");
1358 was_cyclic
= test_and_set_bit(ATC_IS_CYCLIC
, &atchan
->status
);
1360 dev_dbg(chan2dev(chan
), "prep_dma_cyclic: channel in use!\n");
1364 if (unlikely(!is_slave_direction(direction
)))
1367 if (sconfig
->direction
== DMA_MEM_TO_DEV
)
1368 reg_width
= convert_buswidth(sconfig
->dst_addr_width
);
1370 reg_width
= convert_buswidth(sconfig
->src_addr_width
);
1372 /* Check for too big/unaligned periods and unaligned DMA buffer */
1373 if (atc_dma_cyclic_check_values(reg_width
, buf_addr
, period_len
))
1376 /* build cyclic linked list */
1377 for (i
= 0; i
< periods
; i
++) {
1378 struct at_desc
*desc
;
1380 desc
= atc_desc_get(atchan
);
1384 if (atc_dma_cyclic_fill_desc(chan
, desc
, i
, buf_addr
,
1385 reg_width
, period_len
, direction
))
1388 atc_desc_chain(&first
, &prev
, desc
);
1391 /* lets make a cyclic list */
1392 prev
->lli
.dscr
= first
->txd
.phys
;
1394 /* First descriptor of the chain embedds additional information */
1395 first
->txd
.cookie
= -EBUSY
;
1396 first
->total_len
= buf_len
;
1401 dev_err(chan2dev(chan
), "not enough descriptors available\n");
1402 atc_desc_put(atchan
, first
);
1404 clear_bit(ATC_IS_CYCLIC
, &atchan
->status
);
1408 static int atc_config(struct dma_chan
*chan
,
1409 struct dma_slave_config
*sconfig
)
1411 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1413 dev_vdbg(chan2dev(chan
), "%s\n", __func__
);
1415 /* Check if it is chan is configured for slave transfers */
1419 memcpy(&atchan
->dma_sconfig
, sconfig
, sizeof(*sconfig
));
1421 convert_burst(&atchan
->dma_sconfig
.src_maxburst
);
1422 convert_burst(&atchan
->dma_sconfig
.dst_maxburst
);
1427 static int atc_pause(struct dma_chan
*chan
)
1429 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1430 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1431 int chan_id
= atchan
->chan_common
.chan_id
;
1432 unsigned long flags
;
1436 dev_vdbg(chan2dev(chan
), "%s\n", __func__
);
1438 spin_lock_irqsave(&atchan
->lock
, flags
);
1440 dma_writel(atdma
, CHER
, AT_DMA_SUSP(chan_id
));
1441 set_bit(ATC_IS_PAUSED
, &atchan
->status
);
1443 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1448 static int atc_resume(struct dma_chan
*chan
)
1450 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1451 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1452 int chan_id
= atchan
->chan_common
.chan_id
;
1453 unsigned long flags
;
1457 dev_vdbg(chan2dev(chan
), "%s\n", __func__
);
1459 if (!atc_chan_is_paused(atchan
))
1462 spin_lock_irqsave(&atchan
->lock
, flags
);
1464 dma_writel(atdma
, CHDR
, AT_DMA_RES(chan_id
));
1465 clear_bit(ATC_IS_PAUSED
, &atchan
->status
);
1467 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1472 static int atc_terminate_all(struct dma_chan
*chan
)
1474 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1475 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1476 int chan_id
= atchan
->chan_common
.chan_id
;
1477 struct at_desc
*desc
, *_desc
;
1478 unsigned long flags
;
1482 dev_vdbg(chan2dev(chan
), "%s\n", __func__
);
1485 * This is only called when something went wrong elsewhere, so
1486 * we don't really care about the data. Just disable the
1487 * channel. We still have to poll the channel enable bit due
1488 * to AHB/HSB limitations.
1490 spin_lock_irqsave(&atchan
->lock
, flags
);
1492 /* disabling channel: must also remove suspend state */
1493 dma_writel(atdma
, CHDR
, AT_DMA_RES(chan_id
) | atchan
->mask
);
1495 /* confirm that this channel is disabled */
1496 while (dma_readl(atdma
, CHSR
) & atchan
->mask
)
1499 /* active_list entries will end up before queued entries */
1500 list_splice_init(&atchan
->queue
, &list
);
1501 list_splice_init(&atchan
->active_list
, &list
);
1503 /* Flush all pending and queued descriptors */
1504 list_for_each_entry_safe(desc
, _desc
, &list
, desc_node
)
1505 atc_chain_complete(atchan
, desc
);
1507 clear_bit(ATC_IS_PAUSED
, &atchan
->status
);
1508 /* if channel dedicated to cyclic operations, free it */
1509 clear_bit(ATC_IS_CYCLIC
, &atchan
->status
);
1511 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1517 * atc_tx_status - poll for transaction completion
1518 * @chan: DMA channel
1519 * @cookie: transaction identifier to check status of
1520 * @txstate: if not %NULL updated with transaction state
1522 * If @txstate is passed in, upon return it reflect the driver
1523 * internal state and can be used with dma_async_is_complete() to check
1524 * the status of multiple cookies without re-checking hardware state.
1526 static enum dma_status
1527 atc_tx_status(struct dma_chan
*chan
,
1528 dma_cookie_t cookie
,
1529 struct dma_tx_state
*txstate
)
1531 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1532 unsigned long flags
;
1533 enum dma_status ret
;
1536 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1537 if (ret
== DMA_COMPLETE
)
1540 * There's no point calculating the residue if there's
1541 * no txstate to store the value.
1546 spin_lock_irqsave(&atchan
->lock
, flags
);
1548 /* Get number of bytes left in the active transactions */
1549 bytes
= atc_get_bytes_left(chan
, cookie
);
1551 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1553 if (unlikely(bytes
< 0)) {
1554 dev_vdbg(chan2dev(chan
), "get residual bytes error\n");
1557 dma_set_residue(txstate
, bytes
);
1560 dev_vdbg(chan2dev(chan
), "tx_status %d: cookie = %d residue = %d\n",
1561 ret
, cookie
, bytes
);
1567 * atc_issue_pending - try to finish work
1568 * @chan: target DMA channel
1570 static void atc_issue_pending(struct dma_chan
*chan
)
1572 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1573 unsigned long flags
;
1575 dev_vdbg(chan2dev(chan
), "issue_pending\n");
1577 /* Not needed for cyclic transfers */
1578 if (atc_chan_is_cyclic(atchan
))
1581 spin_lock_irqsave(&atchan
->lock
, flags
);
1582 atc_advance_work(atchan
);
1583 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1587 * atc_alloc_chan_resources - allocate resources for DMA channel
1588 * @chan: allocate descriptor resources for this channel
1589 * @client: current client requesting the channel be ready for requests
1591 * return - the number of allocated descriptors
1593 static int atc_alloc_chan_resources(struct dma_chan
*chan
)
1595 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1596 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1597 struct at_desc
*desc
;
1598 struct at_dma_slave
*atslave
;
1599 unsigned long flags
;
1602 LIST_HEAD(tmp_list
);
1604 dev_vdbg(chan2dev(chan
), "alloc_chan_resources\n");
1606 /* ASSERT: channel is idle */
1607 if (atc_chan_is_enabled(atchan
)) {
1608 dev_dbg(chan2dev(chan
), "DMA channel not idle ?\n");
1612 cfg
= ATC_DEFAULT_CFG
;
1614 atslave
= chan
->private;
1617 * We need controller-specific data to set up slave
1620 BUG_ON(!atslave
->dma_dev
|| atslave
->dma_dev
!= atdma
->dma_common
.dev
);
1622 /* if cfg configuration specified take it instead of default */
1627 /* have we already been set up?
1628 * reconfigure channel but no need to reallocate descriptors */
1629 if (!list_empty(&atchan
->free_list
))
1630 return atchan
->descs_allocated
;
1632 /* Allocate initial pool of descriptors */
1633 for (i
= 0; i
< init_nr_desc_per_channel
; i
++) {
1634 desc
= atc_alloc_descriptor(chan
, GFP_KERNEL
);
1636 dev_err(atdma
->dma_common
.dev
,
1637 "Only %d initial descriptors\n", i
);
1640 list_add_tail(&desc
->desc_node
, &tmp_list
);
1643 spin_lock_irqsave(&atchan
->lock
, flags
);
1644 atchan
->descs_allocated
= i
;
1645 list_splice(&tmp_list
, &atchan
->free_list
);
1646 dma_cookie_init(chan
);
1647 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1649 /* channel parameters */
1650 channel_writel(atchan
, CFG
, cfg
);
1652 dev_dbg(chan2dev(chan
),
1653 "alloc_chan_resources: allocated %d descriptors\n",
1654 atchan
->descs_allocated
);
1656 return atchan
->descs_allocated
;
1660 * atc_free_chan_resources - free all channel resources
1661 * @chan: DMA channel
1663 static void atc_free_chan_resources(struct dma_chan
*chan
)
1665 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1666 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1667 struct at_desc
*desc
, *_desc
;
1670 dev_dbg(chan2dev(chan
), "free_chan_resources: (descs allocated=%u)\n",
1671 atchan
->descs_allocated
);
1673 /* ASSERT: channel is idle */
1674 BUG_ON(!list_empty(&atchan
->active_list
));
1675 BUG_ON(!list_empty(&atchan
->queue
));
1676 BUG_ON(atc_chan_is_enabled(atchan
));
1678 list_for_each_entry_safe(desc
, _desc
, &atchan
->free_list
, desc_node
) {
1679 dev_vdbg(chan2dev(chan
), " freeing descriptor %p\n", desc
);
1680 list_del(&desc
->desc_node
);
1681 /* free link descriptor */
1682 dma_pool_free(atdma
->dma_desc_pool
, desc
, desc
->txd
.phys
);
1684 list_splice_init(&atchan
->free_list
, &list
);
1685 atchan
->descs_allocated
= 0;
1688 dev_vdbg(chan2dev(chan
), "free_chan_resources: done\n");
1692 static bool at_dma_filter(struct dma_chan
*chan
, void *slave
)
1694 struct at_dma_slave
*atslave
= slave
;
1696 if (atslave
->dma_dev
== chan
->device
->dev
) {
1697 chan
->private = atslave
;
1704 static struct dma_chan
*at_dma_xlate(struct of_phandle_args
*dma_spec
,
1705 struct of_dma
*of_dma
)
1707 struct dma_chan
*chan
;
1708 struct at_dma_chan
*atchan
;
1709 struct at_dma_slave
*atslave
;
1710 dma_cap_mask_t mask
;
1711 unsigned int per_id
;
1712 struct platform_device
*dmac_pdev
;
1714 if (dma_spec
->args_count
!= 2)
1717 dmac_pdev
= of_find_device_by_node(dma_spec
->np
);
1720 dma_cap_set(DMA_SLAVE
, mask
);
1722 atslave
= devm_kzalloc(&dmac_pdev
->dev
, sizeof(*atslave
), GFP_KERNEL
);
1726 atslave
->cfg
= ATC_DST_H2SEL_HW
| ATC_SRC_H2SEL_HW
;
1728 * We can fill both SRC_PER and DST_PER, one of these fields will be
1729 * ignored depending on DMA transfer direction.
1731 per_id
= dma_spec
->args
[1] & AT91_DMA_CFG_PER_ID_MASK
;
1732 atslave
->cfg
|= ATC_DST_PER_MSB(per_id
) | ATC_DST_PER(per_id
)
1733 | ATC_SRC_PER_MSB(per_id
) | ATC_SRC_PER(per_id
);
1735 * We have to translate the value we get from the device tree since
1736 * the half FIFO configuration value had to be 0 to keep backward
1739 switch (dma_spec
->args
[1] & AT91_DMA_CFG_FIFOCFG_MASK
) {
1740 case AT91_DMA_CFG_FIFOCFG_ALAP
:
1741 atslave
->cfg
|= ATC_FIFOCFG_LARGESTBURST
;
1743 case AT91_DMA_CFG_FIFOCFG_ASAP
:
1744 atslave
->cfg
|= ATC_FIFOCFG_ENOUGHSPACE
;
1746 case AT91_DMA_CFG_FIFOCFG_HALF
:
1748 atslave
->cfg
|= ATC_FIFOCFG_HALFFIFO
;
1750 atslave
->dma_dev
= &dmac_pdev
->dev
;
1752 chan
= dma_request_channel(mask
, at_dma_filter
, atslave
);
1756 atchan
= to_at_dma_chan(chan
);
1757 atchan
->per_if
= dma_spec
->args
[0] & 0xff;
1758 atchan
->mem_if
= (dma_spec
->args
[0] >> 16) & 0xff;
1763 static struct dma_chan
*at_dma_xlate(struct of_phandle_args
*dma_spec
,
1764 struct of_dma
*of_dma
)
1770 /*-- Module Management -----------------------------------------------*/
1772 /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
1773 static struct at_dma_platform_data at91sam9rl_config
= {
1776 static struct at_dma_platform_data at91sam9g45_config
= {
1780 #if defined(CONFIG_OF)
1781 static const struct of_device_id atmel_dma_dt_ids
[] = {
1783 .compatible
= "atmel,at91sam9rl-dma",
1784 .data
= &at91sam9rl_config
,
1786 .compatible
= "atmel,at91sam9g45-dma",
1787 .data
= &at91sam9g45_config
,
1793 MODULE_DEVICE_TABLE(of
, atmel_dma_dt_ids
);
1796 static const struct platform_device_id atdma_devtypes
[] = {
1798 .name
= "at91sam9rl_dma",
1799 .driver_data
= (unsigned long) &at91sam9rl_config
,
1801 .name
= "at91sam9g45_dma",
1802 .driver_data
= (unsigned long) &at91sam9g45_config
,
1808 static inline const struct at_dma_platform_data
* __init
at_dma_get_driver_data(
1809 struct platform_device
*pdev
)
1811 if (pdev
->dev
.of_node
) {
1812 const struct of_device_id
*match
;
1813 match
= of_match_node(atmel_dma_dt_ids
, pdev
->dev
.of_node
);
1818 return (struct at_dma_platform_data
*)
1819 platform_get_device_id(pdev
)->driver_data
;
1823 * at_dma_off - disable DMA controller
1824 * @atdma: the Atmel HDAMC device
1826 static void at_dma_off(struct at_dma
*atdma
)
1828 dma_writel(atdma
, EN
, 0);
1830 /* disable all interrupts */
1831 dma_writel(atdma
, EBCIDR
, -1L);
1833 /* confirm that all channels are disabled */
1834 while (dma_readl(atdma
, CHSR
) & atdma
->all_chan_mask
)
1838 static int __init
at_dma_probe(struct platform_device
*pdev
)
1840 struct resource
*io
;
1841 struct at_dma
*atdma
;
1846 const struct at_dma_platform_data
*plat_dat
;
1848 /* setup platform data for each SoC */
1849 dma_cap_set(DMA_MEMCPY
, at91sam9rl_config
.cap_mask
);
1850 dma_cap_set(DMA_SG
, at91sam9rl_config
.cap_mask
);
1851 dma_cap_set(DMA_INTERLEAVE
, at91sam9g45_config
.cap_mask
);
1852 dma_cap_set(DMA_MEMCPY
, at91sam9g45_config
.cap_mask
);
1853 dma_cap_set(DMA_MEMSET
, at91sam9g45_config
.cap_mask
);
1854 dma_cap_set(DMA_PRIVATE
, at91sam9g45_config
.cap_mask
);
1855 dma_cap_set(DMA_SLAVE
, at91sam9g45_config
.cap_mask
);
1856 dma_cap_set(DMA_SG
, at91sam9g45_config
.cap_mask
);
1858 /* get DMA parameters from controller type */
1859 plat_dat
= at_dma_get_driver_data(pdev
);
1863 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1867 irq
= platform_get_irq(pdev
, 0);
1871 size
= sizeof(struct at_dma
);
1872 size
+= plat_dat
->nr_channels
* sizeof(struct at_dma_chan
);
1873 atdma
= kzalloc(size
, GFP_KERNEL
);
1877 /* discover transaction capabilities */
1878 atdma
->dma_common
.cap_mask
= plat_dat
->cap_mask
;
1879 atdma
->all_chan_mask
= (1 << plat_dat
->nr_channels
) - 1;
1881 size
= resource_size(io
);
1882 if (!request_mem_region(io
->start
, size
, pdev
->dev
.driver
->name
)) {
1887 atdma
->regs
= ioremap(io
->start
, size
);
1893 atdma
->clk
= clk_get(&pdev
->dev
, "dma_clk");
1894 if (IS_ERR(atdma
->clk
)) {
1895 err
= PTR_ERR(atdma
->clk
);
1898 err
= clk_prepare_enable(atdma
->clk
);
1900 goto err_clk_prepare
;
1902 /* force dma off, just in case */
1905 err
= request_irq(irq
, at_dma_interrupt
, 0, "at_hdmac", atdma
);
1909 platform_set_drvdata(pdev
, atdma
);
1911 /* create a pool of consistent memory blocks for hardware descriptors */
1912 atdma
->dma_desc_pool
= dma_pool_create("at_hdmac_desc_pool",
1913 &pdev
->dev
, sizeof(struct at_desc
),
1914 4 /* word alignment */, 0);
1915 if (!atdma
->dma_desc_pool
) {
1916 dev_err(&pdev
->dev
, "No memory for descriptors dma pool\n");
1918 goto err_desc_pool_create
;
1921 /* create a pool of consistent memory blocks for memset blocks */
1922 atdma
->memset_pool
= dma_pool_create("at_hdmac_memset_pool",
1923 &pdev
->dev
, sizeof(int), 4, 0);
1924 if (!atdma
->memset_pool
) {
1925 dev_err(&pdev
->dev
, "No memory for memset dma pool\n");
1927 goto err_memset_pool_create
;
1930 /* clear any pending interrupt */
1931 while (dma_readl(atdma
, EBCISR
))
1934 /* initialize channels related values */
1935 INIT_LIST_HEAD(&atdma
->dma_common
.channels
);
1936 for (i
= 0; i
< plat_dat
->nr_channels
; i
++) {
1937 struct at_dma_chan
*atchan
= &atdma
->chan
[i
];
1939 atchan
->mem_if
= AT_DMA_MEM_IF
;
1940 atchan
->per_if
= AT_DMA_PER_IF
;
1941 atchan
->chan_common
.device
= &atdma
->dma_common
;
1942 dma_cookie_init(&atchan
->chan_common
);
1943 list_add_tail(&atchan
->chan_common
.device_node
,
1944 &atdma
->dma_common
.channels
);
1946 atchan
->ch_regs
= atdma
->regs
+ ch_regs(i
);
1947 spin_lock_init(&atchan
->lock
);
1948 atchan
->mask
= 1 << i
;
1950 INIT_LIST_HEAD(&atchan
->active_list
);
1951 INIT_LIST_HEAD(&atchan
->queue
);
1952 INIT_LIST_HEAD(&atchan
->free_list
);
1954 tasklet_init(&atchan
->tasklet
, atc_tasklet
,
1955 (unsigned long)atchan
);
1956 atc_enable_chan_irq(atdma
, i
);
1959 /* set base routines */
1960 atdma
->dma_common
.device_alloc_chan_resources
= atc_alloc_chan_resources
;
1961 atdma
->dma_common
.device_free_chan_resources
= atc_free_chan_resources
;
1962 atdma
->dma_common
.device_tx_status
= atc_tx_status
;
1963 atdma
->dma_common
.device_issue_pending
= atc_issue_pending
;
1964 atdma
->dma_common
.dev
= &pdev
->dev
;
1966 /* set prep routines based on capability */
1967 if (dma_has_cap(DMA_INTERLEAVE
, atdma
->dma_common
.cap_mask
))
1968 atdma
->dma_common
.device_prep_interleaved_dma
= atc_prep_dma_interleaved
;
1970 if (dma_has_cap(DMA_MEMCPY
, atdma
->dma_common
.cap_mask
))
1971 atdma
->dma_common
.device_prep_dma_memcpy
= atc_prep_dma_memcpy
;
1973 if (dma_has_cap(DMA_MEMSET
, atdma
->dma_common
.cap_mask
)) {
1974 atdma
->dma_common
.device_prep_dma_memset
= atc_prep_dma_memset
;
1975 atdma
->dma_common
.fill_align
= DMAENGINE_ALIGN_4_BYTES
;
1978 if (dma_has_cap(DMA_SLAVE
, atdma
->dma_common
.cap_mask
)) {
1979 atdma
->dma_common
.device_prep_slave_sg
= atc_prep_slave_sg
;
1980 /* controller can do slave DMA: can trigger cyclic transfers */
1981 dma_cap_set(DMA_CYCLIC
, atdma
->dma_common
.cap_mask
);
1982 atdma
->dma_common
.device_prep_dma_cyclic
= atc_prep_dma_cyclic
;
1983 atdma
->dma_common
.device_config
= atc_config
;
1984 atdma
->dma_common
.device_pause
= atc_pause
;
1985 atdma
->dma_common
.device_resume
= atc_resume
;
1986 atdma
->dma_common
.device_terminate_all
= atc_terminate_all
;
1987 atdma
->dma_common
.src_addr_widths
= ATC_DMA_BUSWIDTHS
;
1988 atdma
->dma_common
.dst_addr_widths
= ATC_DMA_BUSWIDTHS
;
1989 atdma
->dma_common
.directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
1990 atdma
->dma_common
.residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
1993 if (dma_has_cap(DMA_SG
, atdma
->dma_common
.cap_mask
))
1994 atdma
->dma_common
.device_prep_dma_sg
= atc_prep_dma_sg
;
1996 dma_writel(atdma
, EN
, AT_DMA_ENABLE
);
1998 dev_info(&pdev
->dev
, "Atmel AHB DMA Controller ( %s%s%s%s), %d channels\n",
1999 dma_has_cap(DMA_MEMCPY
, atdma
->dma_common
.cap_mask
) ? "cpy " : "",
2000 dma_has_cap(DMA_MEMSET
, atdma
->dma_common
.cap_mask
) ? "set " : "",
2001 dma_has_cap(DMA_SLAVE
, atdma
->dma_common
.cap_mask
) ? "slave " : "",
2002 dma_has_cap(DMA_SG
, atdma
->dma_common
.cap_mask
) ? "sg-cpy " : "",
2003 plat_dat
->nr_channels
);
2005 dma_async_device_register(&atdma
->dma_common
);
2008 * Do not return an error if the dmac node is not present in order to
2009 * not break the existing way of requesting channel with
2010 * dma_request_channel().
2012 if (pdev
->dev
.of_node
) {
2013 err
= of_dma_controller_register(pdev
->dev
.of_node
,
2014 at_dma_xlate
, atdma
);
2016 dev_err(&pdev
->dev
, "could not register of_dma_controller\n");
2017 goto err_of_dma_controller_register
;
2023 err_of_dma_controller_register
:
2024 dma_async_device_unregister(&atdma
->dma_common
);
2025 dma_pool_destroy(atdma
->memset_pool
);
2026 err_memset_pool_create
:
2027 dma_pool_destroy(atdma
->dma_desc_pool
);
2028 err_desc_pool_create
:
2029 free_irq(platform_get_irq(pdev
, 0), atdma
);
2031 clk_disable_unprepare(atdma
->clk
);
2033 clk_put(atdma
->clk
);
2035 iounmap(atdma
->regs
);
2038 release_mem_region(io
->start
, size
);
2044 static int at_dma_remove(struct platform_device
*pdev
)
2046 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
2047 struct dma_chan
*chan
, *_chan
;
2048 struct resource
*io
;
2051 dma_async_device_unregister(&atdma
->dma_common
);
2053 dma_pool_destroy(atdma
->memset_pool
);
2054 dma_pool_destroy(atdma
->dma_desc_pool
);
2055 free_irq(platform_get_irq(pdev
, 0), atdma
);
2057 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
2059 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
2061 /* Disable interrupts */
2062 atc_disable_chan_irq(atdma
, chan
->chan_id
);
2064 tasklet_kill(&atchan
->tasklet
);
2065 list_del(&chan
->device_node
);
2068 clk_disable_unprepare(atdma
->clk
);
2069 clk_put(atdma
->clk
);
2071 iounmap(atdma
->regs
);
2074 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2075 release_mem_region(io
->start
, resource_size(io
));
2082 static void at_dma_shutdown(struct platform_device
*pdev
)
2084 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
2086 at_dma_off(platform_get_drvdata(pdev
));
2087 clk_disable_unprepare(atdma
->clk
);
2090 static int at_dma_prepare(struct device
*dev
)
2092 struct platform_device
*pdev
= to_platform_device(dev
);
2093 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
2094 struct dma_chan
*chan
, *_chan
;
2096 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
2098 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
2099 /* wait for transaction completion (except in cyclic case) */
2100 if (atc_chan_is_enabled(atchan
) && !atc_chan_is_cyclic(atchan
))
2106 static void atc_suspend_cyclic(struct at_dma_chan
*atchan
)
2108 struct dma_chan
*chan
= &atchan
->chan_common
;
2110 /* Channel should be paused by user
2111 * do it anyway even if it is not done already */
2112 if (!atc_chan_is_paused(atchan
)) {
2113 dev_warn(chan2dev(chan
),
2114 "cyclic channel not paused, should be done by channel user\n");
2118 /* now preserve additional data for cyclic operations */
2119 /* next descriptor address in the cyclic list */
2120 atchan
->save_dscr
= channel_readl(atchan
, DSCR
);
2122 vdbg_dump_regs(atchan
);
2125 static int at_dma_suspend_noirq(struct device
*dev
)
2127 struct platform_device
*pdev
= to_platform_device(dev
);
2128 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
2129 struct dma_chan
*chan
, *_chan
;
2132 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
2134 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
2136 if (atc_chan_is_cyclic(atchan
))
2137 atc_suspend_cyclic(atchan
);
2138 atchan
->save_cfg
= channel_readl(atchan
, CFG
);
2140 atdma
->save_imr
= dma_readl(atdma
, EBCIMR
);
2142 /* disable DMA controller */
2144 clk_disable_unprepare(atdma
->clk
);
2148 static void atc_resume_cyclic(struct at_dma_chan
*atchan
)
2150 struct at_dma
*atdma
= to_at_dma(atchan
->chan_common
.device
);
2152 /* restore channel status for cyclic descriptors list:
2153 * next descriptor in the cyclic list at the time of suspend */
2154 channel_writel(atchan
, SADDR
, 0);
2155 channel_writel(atchan
, DADDR
, 0);
2156 channel_writel(atchan
, CTRLA
, 0);
2157 channel_writel(atchan
, CTRLB
, 0);
2158 channel_writel(atchan
, DSCR
, atchan
->save_dscr
);
2159 dma_writel(atdma
, CHER
, atchan
->mask
);
2161 /* channel pause status should be removed by channel user
2162 * We cannot take the initiative to do it here */
2164 vdbg_dump_regs(atchan
);
2167 static int at_dma_resume_noirq(struct device
*dev
)
2169 struct platform_device
*pdev
= to_platform_device(dev
);
2170 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
2171 struct dma_chan
*chan
, *_chan
;
2173 /* bring back DMA controller */
2174 clk_prepare_enable(atdma
->clk
);
2175 dma_writel(atdma
, EN
, AT_DMA_ENABLE
);
2177 /* clear any pending interrupt */
2178 while (dma_readl(atdma
, EBCISR
))
2181 /* restore saved data */
2182 dma_writel(atdma
, EBCIER
, atdma
->save_imr
);
2183 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
2185 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
2187 channel_writel(atchan
, CFG
, atchan
->save_cfg
);
2188 if (atc_chan_is_cyclic(atchan
))
2189 atc_resume_cyclic(atchan
);
2194 static const struct dev_pm_ops at_dma_dev_pm_ops
= {
2195 .prepare
= at_dma_prepare
,
2196 .suspend_noirq
= at_dma_suspend_noirq
,
2197 .resume_noirq
= at_dma_resume_noirq
,
2200 static struct platform_driver at_dma_driver
= {
2201 .remove
= at_dma_remove
,
2202 .shutdown
= at_dma_shutdown
,
2203 .id_table
= atdma_devtypes
,
2206 .pm
= &at_dma_dev_pm_ops
,
2207 .of_match_table
= of_match_ptr(atmel_dma_dt_ids
),
2211 static int __init
at_dma_init(void)
2213 return platform_driver_probe(&at_dma_driver
, at_dma_probe
);
2215 subsys_initcall(at_dma_init
);
2217 static void __exit
at_dma_exit(void)
2219 platform_driver_unregister(&at_dma_driver
);
2221 module_exit(at_dma_exit
);
2223 MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
2224 MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
2225 MODULE_LICENSE("GPL");
2226 MODULE_ALIAS("platform:at_hdmac");