2 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
4 * Copyright (C) 2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
13 * The only Atmel DMA Controller that is not covered by this driver is the one
14 * found on AT91SAM9263.
17 #include <linux/clk.h>
18 #include <linux/dmaengine.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmapool.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
26 #include <linux/of_device.h>
28 #include "at_hdmac_regs.h"
29 #include "dmaengine.h"
35 * at_hdmac : Name of the ATmel AHB DMA Controller
36 * at_dma_ / atdma : ATmel DMA controller entity related
37 * atc_ / atchan : ATmel DMA Channel entity related
40 #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
41 #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
42 |ATC_DIF(AT_DMA_MEM_IF))
45 * Initial number of descriptors to allocate for each channel. This could
46 * be increased during dma usage.
48 static unsigned int init_nr_desc_per_channel
= 64;
49 module_param(init_nr_desc_per_channel
, uint
, 0644);
50 MODULE_PARM_DESC(init_nr_desc_per_channel
,
51 "initial descriptors per channel (default: 64)");
55 static dma_cookie_t
atc_tx_submit(struct dma_async_tx_descriptor
*tx
);
58 /*----------------------------------------------------------------------*/
60 static struct at_desc
*atc_first_active(struct at_dma_chan
*atchan
)
62 return list_first_entry(&atchan
->active_list
,
63 struct at_desc
, desc_node
);
66 static struct at_desc
*atc_first_queued(struct at_dma_chan
*atchan
)
68 return list_first_entry(&atchan
->queue
,
69 struct at_desc
, desc_node
);
73 * atc_alloc_descriptor - allocate and return an initialized descriptor
74 * @chan: the channel to allocate descriptors for
75 * @gfp_flags: GFP allocation flags
77 * Note: The ack-bit is positioned in the descriptor flag at creation time
78 * to make initial allocation more convenient. This bit will be cleared
79 * and control will be given to client at usage time (during
80 * preparation functions).
82 static struct at_desc
*atc_alloc_descriptor(struct dma_chan
*chan
,
85 struct at_desc
*desc
= NULL
;
86 struct at_dma
*atdma
= to_at_dma(chan
->device
);
89 desc
= dma_pool_alloc(atdma
->dma_desc_pool
, gfp_flags
, &phys
);
91 memset(desc
, 0, sizeof(struct at_desc
));
92 INIT_LIST_HEAD(&desc
->tx_list
);
93 dma_async_tx_descriptor_init(&desc
->txd
, chan
);
94 /* txd.flags will be overwritten in prep functions */
95 desc
->txd
.flags
= DMA_CTRL_ACK
;
96 desc
->txd
.tx_submit
= atc_tx_submit
;
97 desc
->txd
.phys
= phys
;
104 * atc_desc_get - get an unused descriptor from free_list
105 * @atchan: channel we want a new descriptor for
107 static struct at_desc
*atc_desc_get(struct at_dma_chan
*atchan
)
109 struct at_desc
*desc
, *_desc
;
110 struct at_desc
*ret
= NULL
;
115 spin_lock_irqsave(&atchan
->lock
, flags
);
116 list_for_each_entry_safe(desc
, _desc
, &atchan
->free_list
, desc_node
) {
118 if (async_tx_test_ack(&desc
->txd
)) {
119 list_del(&desc
->desc_node
);
123 dev_dbg(chan2dev(&atchan
->chan_common
),
124 "desc %p not ACKed\n", desc
);
126 spin_unlock_irqrestore(&atchan
->lock
, flags
);
127 dev_vdbg(chan2dev(&atchan
->chan_common
),
128 "scanned %u descriptors on freelist\n", i
);
130 /* no more descriptor available in initial pool: create one more */
132 ret
= atc_alloc_descriptor(&atchan
->chan_common
, GFP_ATOMIC
);
134 spin_lock_irqsave(&atchan
->lock
, flags
);
135 atchan
->descs_allocated
++;
136 spin_unlock_irqrestore(&atchan
->lock
, flags
);
138 dev_err(chan2dev(&atchan
->chan_common
),
139 "not enough descriptors available\n");
147 * atc_desc_put - move a descriptor, including any children, to the free list
148 * @atchan: channel we work on
149 * @desc: descriptor, at the head of a chain, to move to free list
151 static void atc_desc_put(struct at_dma_chan
*atchan
, struct at_desc
*desc
)
154 struct at_desc
*child
;
157 spin_lock_irqsave(&atchan
->lock
, flags
);
158 list_for_each_entry(child
, &desc
->tx_list
, desc_node
)
159 dev_vdbg(chan2dev(&atchan
->chan_common
),
160 "moving child desc %p to freelist\n",
162 list_splice_init(&desc
->tx_list
, &atchan
->free_list
);
163 dev_vdbg(chan2dev(&atchan
->chan_common
),
164 "moving desc %p to freelist\n", desc
);
165 list_add(&desc
->desc_node
, &atchan
->free_list
);
166 spin_unlock_irqrestore(&atchan
->lock
, flags
);
171 * atc_desc_chain - build chain adding a descriptor
172 * @first: address of first descriptor of the chain
173 * @prev: address of previous descriptor of the chain
174 * @desc: descriptor to queue
176 * Called from prep_* functions
178 static void atc_desc_chain(struct at_desc
**first
, struct at_desc
**prev
,
179 struct at_desc
*desc
)
184 /* inform the HW lli about chaining */
185 (*prev
)->lli
.dscr
= desc
->txd
.phys
;
186 /* insert the link descriptor to the LD ring */
187 list_add_tail(&desc
->desc_node
,
194 * atc_dostart - starts the DMA engine for real
195 * @atchan: the channel we want to start
196 * @first: first descriptor in the list we want to begin with
198 * Called with atchan->lock held and bh disabled
200 static void atc_dostart(struct at_dma_chan
*atchan
, struct at_desc
*first
)
202 struct at_dma
*atdma
= to_at_dma(atchan
->chan_common
.device
);
204 /* ASSERT: channel is idle */
205 if (atc_chan_is_enabled(atchan
)) {
206 dev_err(chan2dev(&atchan
->chan_common
),
207 "BUG: Attempted to start non-idle channel\n");
208 dev_err(chan2dev(&atchan
->chan_common
),
209 " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
210 channel_readl(atchan
, SADDR
),
211 channel_readl(atchan
, DADDR
),
212 channel_readl(atchan
, CTRLA
),
213 channel_readl(atchan
, CTRLB
),
214 channel_readl(atchan
, DSCR
));
216 /* The tasklet will hopefully advance the queue... */
220 vdbg_dump_regs(atchan
);
222 channel_writel(atchan
, SADDR
, 0);
223 channel_writel(atchan
, DADDR
, 0);
224 channel_writel(atchan
, CTRLA
, 0);
225 channel_writel(atchan
, CTRLB
, 0);
226 channel_writel(atchan
, DSCR
, first
->txd
.phys
);
227 dma_writel(atdma
, CHER
, atchan
->mask
);
229 vdbg_dump_regs(atchan
);
233 * atc_chain_complete - finish work for one transaction chain
234 * @atchan: channel we work on
235 * @desc: descriptor at the head of the chain we want do complete
237 * Called with atchan->lock held and bh disabled */
239 atc_chain_complete(struct at_dma_chan
*atchan
, struct at_desc
*desc
)
241 struct dma_async_tx_descriptor
*txd
= &desc
->txd
;
243 dev_vdbg(chan2dev(&atchan
->chan_common
),
244 "descriptor %u complete\n", txd
->cookie
);
246 /* mark the descriptor as complete for non cyclic cases only */
247 if (!atc_chan_is_cyclic(atchan
))
248 dma_cookie_complete(txd
);
250 /* move children to free_list */
251 list_splice_init(&desc
->tx_list
, &atchan
->free_list
);
252 /* move myself to free_list */
253 list_move(&desc
->desc_node
, &atchan
->free_list
);
255 /* unmap dma addresses (not on slave channels) */
256 if (!atchan
->chan_common
.private) {
257 struct device
*parent
= chan2parent(&atchan
->chan_common
);
258 if (!(txd
->flags
& DMA_COMPL_SKIP_DEST_UNMAP
)) {
259 if (txd
->flags
& DMA_COMPL_DEST_UNMAP_SINGLE
)
260 dma_unmap_single(parent
,
262 desc
->len
, DMA_FROM_DEVICE
);
264 dma_unmap_page(parent
,
266 desc
->len
, DMA_FROM_DEVICE
);
268 if (!(txd
->flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
269 if (txd
->flags
& DMA_COMPL_SRC_UNMAP_SINGLE
)
270 dma_unmap_single(parent
,
272 desc
->len
, DMA_TO_DEVICE
);
274 dma_unmap_page(parent
,
276 desc
->len
, DMA_TO_DEVICE
);
280 /* for cyclic transfers,
281 * no need to replay callback function while stopping */
282 if (!atc_chan_is_cyclic(atchan
)) {
283 dma_async_tx_callback callback
= txd
->callback
;
284 void *param
= txd
->callback_param
;
287 * The API requires that no submissions are done from a
288 * callback, so we don't need to drop the lock here
294 dma_run_dependencies(txd
);
298 * atc_complete_all - finish work for all transactions
299 * @atchan: channel to complete transactions for
301 * Eventually submit queued descriptors if any
303 * Assume channel is idle while calling this function
304 * Called with atchan->lock held and bh disabled
306 static void atc_complete_all(struct at_dma_chan
*atchan
)
308 struct at_desc
*desc
, *_desc
;
311 dev_vdbg(chan2dev(&atchan
->chan_common
), "complete all\n");
314 * Submit queued descriptors ASAP, i.e. before we go through
315 * the completed ones.
317 if (!list_empty(&atchan
->queue
))
318 atc_dostart(atchan
, atc_first_queued(atchan
));
319 /* empty active_list now it is completed */
320 list_splice_init(&atchan
->active_list
, &list
);
321 /* empty queue list by moving descriptors (if any) to active_list */
322 list_splice_init(&atchan
->queue
, &atchan
->active_list
);
324 list_for_each_entry_safe(desc
, _desc
, &list
, desc_node
)
325 atc_chain_complete(atchan
, desc
);
329 * atc_cleanup_descriptors - cleanup up finished descriptors in active_list
330 * @atchan: channel to be cleaned up
332 * Called with atchan->lock held and bh disabled
334 static void atc_cleanup_descriptors(struct at_dma_chan
*atchan
)
336 struct at_desc
*desc
, *_desc
;
337 struct at_desc
*child
;
339 dev_vdbg(chan2dev(&atchan
->chan_common
), "cleanup descriptors\n");
341 list_for_each_entry_safe(desc
, _desc
, &atchan
->active_list
, desc_node
) {
342 if (!(desc
->lli
.ctrla
& ATC_DONE
))
343 /* This one is currently in progress */
346 list_for_each_entry(child
, &desc
->tx_list
, desc_node
)
347 if (!(child
->lli
.ctrla
& ATC_DONE
))
348 /* Currently in progress */
352 * No descriptors so far seem to be in progress, i.e.
353 * this chain must be done.
355 atc_chain_complete(atchan
, desc
);
360 * atc_advance_work - at the end of a transaction, move forward
361 * @atchan: channel where the transaction ended
363 * Called with atchan->lock held and bh disabled
365 static void atc_advance_work(struct at_dma_chan
*atchan
)
367 dev_vdbg(chan2dev(&atchan
->chan_common
), "advance_work\n");
369 if (atc_chan_is_enabled(atchan
))
372 if (list_empty(&atchan
->active_list
) ||
373 list_is_singular(&atchan
->active_list
)) {
374 atc_complete_all(atchan
);
376 atc_chain_complete(atchan
, atc_first_active(atchan
));
378 atc_dostart(atchan
, atc_first_active(atchan
));
384 * atc_handle_error - handle errors reported by DMA controller
385 * @atchan: channel where error occurs
387 * Called with atchan->lock held and bh disabled
389 static void atc_handle_error(struct at_dma_chan
*atchan
)
391 struct at_desc
*bad_desc
;
392 struct at_desc
*child
;
395 * The descriptor currently at the head of the active list is
396 * broked. Since we don't have any way to report errors, we'll
397 * just have to scream loudly and try to carry on.
399 bad_desc
= atc_first_active(atchan
);
400 list_del_init(&bad_desc
->desc_node
);
402 /* As we are stopped, take advantage to push queued descriptors
404 list_splice_init(&atchan
->queue
, atchan
->active_list
.prev
);
406 /* Try to restart the controller */
407 if (!list_empty(&atchan
->active_list
))
408 atc_dostart(atchan
, atc_first_active(atchan
));
411 * KERN_CRITICAL may seem harsh, but since this only happens
412 * when someone submits a bad physical address in a
413 * descriptor, we should consider ourselves lucky that the
414 * controller flagged an error instead of scribbling over
415 * random memory locations.
417 dev_crit(chan2dev(&atchan
->chan_common
),
418 "Bad descriptor submitted for DMA!\n");
419 dev_crit(chan2dev(&atchan
->chan_common
),
420 " cookie: %d\n", bad_desc
->txd
.cookie
);
421 atc_dump_lli(atchan
, &bad_desc
->lli
);
422 list_for_each_entry(child
, &bad_desc
->tx_list
, desc_node
)
423 atc_dump_lli(atchan
, &child
->lli
);
425 /* Pretend the descriptor completed successfully */
426 atc_chain_complete(atchan
, bad_desc
);
430 * atc_handle_cyclic - at the end of a period, run callback function
431 * @atchan: channel used for cyclic operations
433 * Called with atchan->lock held and bh disabled
435 static void atc_handle_cyclic(struct at_dma_chan
*atchan
)
437 struct at_desc
*first
= atc_first_active(atchan
);
438 struct dma_async_tx_descriptor
*txd
= &first
->txd
;
439 dma_async_tx_callback callback
= txd
->callback
;
440 void *param
= txd
->callback_param
;
442 dev_vdbg(chan2dev(&atchan
->chan_common
),
443 "new cyclic period llp 0x%08x\n",
444 channel_readl(atchan
, DSCR
));
450 /*-- IRQ & Tasklet ---------------------------------------------------*/
452 static void atc_tasklet(unsigned long data
)
454 struct at_dma_chan
*atchan
= (struct at_dma_chan
*)data
;
457 spin_lock_irqsave(&atchan
->lock
, flags
);
458 if (test_and_clear_bit(ATC_IS_ERROR
, &atchan
->status
))
459 atc_handle_error(atchan
);
460 else if (atc_chan_is_cyclic(atchan
))
461 atc_handle_cyclic(atchan
);
463 atc_advance_work(atchan
);
465 spin_unlock_irqrestore(&atchan
->lock
, flags
);
468 static irqreturn_t
at_dma_interrupt(int irq
, void *dev_id
)
470 struct at_dma
*atdma
= (struct at_dma
*)dev_id
;
471 struct at_dma_chan
*atchan
;
473 u32 status
, pending
, imr
;
477 imr
= dma_readl(atdma
, EBCIMR
);
478 status
= dma_readl(atdma
, EBCISR
);
479 pending
= status
& imr
;
484 dev_vdbg(atdma
->dma_common
.dev
,
485 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
486 status
, imr
, pending
);
488 for (i
= 0; i
< atdma
->dma_common
.chancnt
; i
++) {
489 atchan
= &atdma
->chan
[i
];
490 if (pending
& (AT_DMA_BTC(i
) | AT_DMA_ERR(i
))) {
491 if (pending
& AT_DMA_ERR(i
)) {
492 /* Disable channel on AHB error */
493 dma_writel(atdma
, CHDR
,
494 AT_DMA_RES(i
) | atchan
->mask
);
495 /* Give information to tasklet */
496 set_bit(ATC_IS_ERROR
, &atchan
->status
);
498 tasklet_schedule(&atchan
->tasklet
);
509 /*-- DMA Engine API --------------------------------------------------*/
512 * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
513 * @desc: descriptor at the head of the transaction chain
515 * Queue chain if DMA engine is working already
517 * Cookie increment and adding to active_list or queue must be atomic
519 static dma_cookie_t
atc_tx_submit(struct dma_async_tx_descriptor
*tx
)
521 struct at_desc
*desc
= txd_to_at_desc(tx
);
522 struct at_dma_chan
*atchan
= to_at_dma_chan(tx
->chan
);
526 spin_lock_irqsave(&atchan
->lock
, flags
);
527 cookie
= dma_cookie_assign(tx
);
529 if (list_empty(&atchan
->active_list
)) {
530 dev_vdbg(chan2dev(tx
->chan
), "tx_submit: started %u\n",
532 atc_dostart(atchan
, desc
);
533 list_add_tail(&desc
->desc_node
, &atchan
->active_list
);
535 dev_vdbg(chan2dev(tx
->chan
), "tx_submit: queued %u\n",
537 list_add_tail(&desc
->desc_node
, &atchan
->queue
);
540 spin_unlock_irqrestore(&atchan
->lock
, flags
);
546 * atc_prep_dma_memcpy - prepare a memcpy operation
547 * @chan: the channel to prepare operation on
548 * @dest: operation virtual destination address
549 * @src: operation virtual source address
550 * @len: operation length
551 * @flags: tx descriptor status flags
553 static struct dma_async_tx_descriptor
*
554 atc_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
555 size_t len
, unsigned long flags
)
557 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
558 struct at_desc
*desc
= NULL
;
559 struct at_desc
*first
= NULL
;
560 struct at_desc
*prev
= NULL
;
563 unsigned int src_width
;
564 unsigned int dst_width
;
568 dev_vdbg(chan2dev(chan
), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n",
569 dest
, src
, len
, flags
);
571 if (unlikely(!len
)) {
572 dev_dbg(chan2dev(chan
), "prep_dma_memcpy: length is zero!\n");
576 ctrlb
= ATC_DEFAULT_CTRLB
| ATC_IEN
577 | ATC_SRC_ADDR_MODE_INCR
578 | ATC_DST_ADDR_MODE_INCR
582 * We can be a lot more clever here, but this should take care
583 * of the most common optimization.
585 if (!((src
| dest
| len
) & 3)) {
586 ctrla
= ATC_SRC_WIDTH_WORD
| ATC_DST_WIDTH_WORD
;
587 src_width
= dst_width
= 2;
588 } else if (!((src
| dest
| len
) & 1)) {
589 ctrla
= ATC_SRC_WIDTH_HALFWORD
| ATC_DST_WIDTH_HALFWORD
;
590 src_width
= dst_width
= 1;
592 ctrla
= ATC_SRC_WIDTH_BYTE
| ATC_DST_WIDTH_BYTE
;
593 src_width
= dst_width
= 0;
596 for (offset
= 0; offset
< len
; offset
+= xfer_count
<< src_width
) {
597 xfer_count
= min_t(size_t, (len
- offset
) >> src_width
,
600 desc
= atc_desc_get(atchan
);
604 desc
->lli
.saddr
= src
+ offset
;
605 desc
->lli
.daddr
= dest
+ offset
;
606 desc
->lli
.ctrla
= ctrla
| xfer_count
;
607 desc
->lli
.ctrlb
= ctrlb
;
609 desc
->txd
.cookie
= 0;
611 atc_desc_chain(&first
, &prev
, desc
);
614 /* First descriptor of the chain embedds additional information */
615 first
->txd
.cookie
= -EBUSY
;
618 /* set end-of-link to the last link descriptor of list*/
621 first
->txd
.flags
= flags
; /* client is in control of this ack */
626 atc_desc_put(atchan
, first
);
632 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
634 * @sgl: scatterlist to transfer to/from
635 * @sg_len: number of entries in @scatterlist
636 * @direction: DMA direction
637 * @flags: tx descriptor status flags
638 * @context: transaction context (ignored)
640 static struct dma_async_tx_descriptor
*
641 atc_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
642 unsigned int sg_len
, enum dma_transfer_direction direction
,
643 unsigned long flags
, void *context
)
645 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
646 struct at_dma_slave
*atslave
= chan
->private;
647 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
648 struct at_desc
*first
= NULL
;
649 struct at_desc
*prev
= NULL
;
653 unsigned int reg_width
;
654 unsigned int mem_width
;
656 struct scatterlist
*sg
;
657 size_t total_len
= 0;
659 dev_vdbg(chan2dev(chan
), "prep_slave_sg (%d): %s f0x%lx\n",
661 direction
== DMA_MEM_TO_DEV
? "TO DEVICE" : "FROM DEVICE",
664 if (unlikely(!atslave
|| !sg_len
)) {
665 dev_dbg(chan2dev(chan
), "prep_slave_sg: sg length is zero!\n");
669 ctrla
= ATC_SCSIZE(sconfig
->src_maxburst
)
670 | ATC_DCSIZE(sconfig
->dst_maxburst
);
675 reg_width
= convert_buswidth(sconfig
->dst_addr_width
);
676 ctrla
|= ATC_DST_WIDTH(reg_width
);
677 ctrlb
|= ATC_DST_ADDR_MODE_FIXED
678 | ATC_SRC_ADDR_MODE_INCR
680 | ATC_SIF(AT_DMA_MEM_IF
) | ATC_DIF(AT_DMA_PER_IF
);
681 reg
= sconfig
->dst_addr
;
682 for_each_sg(sgl
, sg
, sg_len
, i
) {
683 struct at_desc
*desc
;
687 desc
= atc_desc_get(atchan
);
691 mem
= sg_dma_address(sg
);
692 len
= sg_dma_len(sg
);
693 if (unlikely(!len
)) {
694 dev_dbg(chan2dev(chan
),
695 "prep_slave_sg: sg(%d) data length is zero\n", i
);
699 if (unlikely(mem
& 3 || len
& 3))
702 desc
->lli
.saddr
= mem
;
703 desc
->lli
.daddr
= reg
;
704 desc
->lli
.ctrla
= ctrla
705 | ATC_SRC_WIDTH(mem_width
)
707 desc
->lli
.ctrlb
= ctrlb
;
709 atc_desc_chain(&first
, &prev
, desc
);
714 reg_width
= convert_buswidth(sconfig
->src_addr_width
);
715 ctrla
|= ATC_SRC_WIDTH(reg_width
);
716 ctrlb
|= ATC_DST_ADDR_MODE_INCR
717 | ATC_SRC_ADDR_MODE_FIXED
719 | ATC_SIF(AT_DMA_PER_IF
) | ATC_DIF(AT_DMA_MEM_IF
);
721 reg
= sconfig
->src_addr
;
722 for_each_sg(sgl
, sg
, sg_len
, i
) {
723 struct at_desc
*desc
;
727 desc
= atc_desc_get(atchan
);
731 mem
= sg_dma_address(sg
);
732 len
= sg_dma_len(sg
);
733 if (unlikely(!len
)) {
734 dev_dbg(chan2dev(chan
),
735 "prep_slave_sg: sg(%d) data length is zero\n", i
);
739 if (unlikely(mem
& 3 || len
& 3))
742 desc
->lli
.saddr
= reg
;
743 desc
->lli
.daddr
= mem
;
744 desc
->lli
.ctrla
= ctrla
745 | ATC_DST_WIDTH(mem_width
)
747 desc
->lli
.ctrlb
= ctrlb
;
749 atc_desc_chain(&first
, &prev
, desc
);
757 /* set end-of-link to the last link descriptor of list*/
760 /* First descriptor of the chain embedds additional information */
761 first
->txd
.cookie
= -EBUSY
;
762 first
->len
= total_len
;
764 /* first link descriptor of list is responsible of flags */
765 first
->txd
.flags
= flags
; /* client is in control of this ack */
770 dev_err(chan2dev(chan
), "not enough descriptors available\n");
772 atc_desc_put(atchan
, first
);
777 * atc_dma_cyclic_check_values
778 * Check for too big/unaligned periods and unaligned DMA buffer
781 atc_dma_cyclic_check_values(unsigned int reg_width
, dma_addr_t buf_addr
,
784 if (period_len
> (ATC_BTSIZE_MAX
<< reg_width
))
786 if (unlikely(period_len
& ((1 << reg_width
) - 1)))
788 if (unlikely(buf_addr
& ((1 << reg_width
) - 1)))
798 * atc_dma_cyclic_fill_desc - Fill one period descriptor
801 atc_dma_cyclic_fill_desc(struct dma_chan
*chan
, struct at_desc
*desc
,
802 unsigned int period_index
, dma_addr_t buf_addr
,
803 unsigned int reg_width
, size_t period_len
,
804 enum dma_transfer_direction direction
)
806 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
807 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
810 /* prepare common CRTLA value */
811 ctrla
= ATC_SCSIZE(sconfig
->src_maxburst
)
812 | ATC_DCSIZE(sconfig
->dst_maxburst
)
813 | ATC_DST_WIDTH(reg_width
)
814 | ATC_SRC_WIDTH(reg_width
)
815 | period_len
>> reg_width
;
819 desc
->lli
.saddr
= buf_addr
+ (period_len
* period_index
);
820 desc
->lli
.daddr
= sconfig
->dst_addr
;
821 desc
->lli
.ctrla
= ctrla
;
822 desc
->lli
.ctrlb
= ATC_DST_ADDR_MODE_FIXED
823 | ATC_SRC_ADDR_MODE_INCR
825 | ATC_SIF(AT_DMA_MEM_IF
)
826 | ATC_DIF(AT_DMA_PER_IF
);
830 desc
->lli
.saddr
= sconfig
->src_addr
;
831 desc
->lli
.daddr
= buf_addr
+ (period_len
* period_index
);
832 desc
->lli
.ctrla
= ctrla
;
833 desc
->lli
.ctrlb
= ATC_DST_ADDR_MODE_INCR
834 | ATC_SRC_ADDR_MODE_FIXED
836 | ATC_SIF(AT_DMA_PER_IF
)
837 | ATC_DIF(AT_DMA_MEM_IF
);
848 * atc_prep_dma_cyclic - prepare the cyclic DMA transfer
849 * @chan: the DMA channel to prepare
850 * @buf_addr: physical DMA address where the buffer starts
851 * @buf_len: total number of bytes for the entire buffer
852 * @period_len: number of bytes for each period
853 * @direction: transfer direction, to or from device
854 * @flags: tx descriptor status flags
855 * @context: transfer context (ignored)
857 static struct dma_async_tx_descriptor
*
858 atc_prep_dma_cyclic(struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
859 size_t period_len
, enum dma_transfer_direction direction
,
860 unsigned long flags
, void *context
)
862 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
863 struct at_dma_slave
*atslave
= chan
->private;
864 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
865 struct at_desc
*first
= NULL
;
866 struct at_desc
*prev
= NULL
;
867 unsigned long was_cyclic
;
868 unsigned int reg_width
;
869 unsigned int periods
= buf_len
/ period_len
;
872 dev_vdbg(chan2dev(chan
), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
873 direction
== DMA_MEM_TO_DEV
? "TO DEVICE" : "FROM DEVICE",
875 periods
, buf_len
, period_len
);
877 if (unlikely(!atslave
|| !buf_len
|| !period_len
)) {
878 dev_dbg(chan2dev(chan
), "prep_dma_cyclic: length is zero!\n");
882 was_cyclic
= test_and_set_bit(ATC_IS_CYCLIC
, &atchan
->status
);
884 dev_dbg(chan2dev(chan
), "prep_dma_cyclic: channel in use!\n");
888 if (unlikely(!is_slave_direction(direction
)))
891 if (sconfig
->direction
== DMA_MEM_TO_DEV
)
892 reg_width
= convert_buswidth(sconfig
->dst_addr_width
);
894 reg_width
= convert_buswidth(sconfig
->src_addr_width
);
896 /* Check for too big/unaligned periods and unaligned DMA buffer */
897 if (atc_dma_cyclic_check_values(reg_width
, buf_addr
, period_len
))
900 /* build cyclic linked list */
901 for (i
= 0; i
< periods
; i
++) {
902 struct at_desc
*desc
;
904 desc
= atc_desc_get(atchan
);
908 if (atc_dma_cyclic_fill_desc(chan
, desc
, i
, buf_addr
,
909 reg_width
, period_len
, direction
))
912 atc_desc_chain(&first
, &prev
, desc
);
915 /* lets make a cyclic list */
916 prev
->lli
.dscr
= first
->txd
.phys
;
918 /* First descriptor of the chain embedds additional information */
919 first
->txd
.cookie
= -EBUSY
;
920 first
->len
= buf_len
;
925 dev_err(chan2dev(chan
), "not enough descriptors available\n");
926 atc_desc_put(atchan
, first
);
928 clear_bit(ATC_IS_CYCLIC
, &atchan
->status
);
932 static int set_runtime_config(struct dma_chan
*chan
,
933 struct dma_slave_config
*sconfig
)
935 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
937 /* Check if it is chan is configured for slave transfers */
941 memcpy(&atchan
->dma_sconfig
, sconfig
, sizeof(*sconfig
));
943 convert_burst(&atchan
->dma_sconfig
.src_maxburst
);
944 convert_burst(&atchan
->dma_sconfig
.dst_maxburst
);
950 static int atc_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
953 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
954 struct at_dma
*atdma
= to_at_dma(chan
->device
);
955 int chan_id
= atchan
->chan_common
.chan_id
;
960 dev_vdbg(chan2dev(chan
), "atc_control (%d)\n", cmd
);
962 if (cmd
== DMA_PAUSE
) {
963 spin_lock_irqsave(&atchan
->lock
, flags
);
965 dma_writel(atdma
, CHER
, AT_DMA_SUSP(chan_id
));
966 set_bit(ATC_IS_PAUSED
, &atchan
->status
);
968 spin_unlock_irqrestore(&atchan
->lock
, flags
);
969 } else if (cmd
== DMA_RESUME
) {
970 if (!atc_chan_is_paused(atchan
))
973 spin_lock_irqsave(&atchan
->lock
, flags
);
975 dma_writel(atdma
, CHDR
, AT_DMA_RES(chan_id
));
976 clear_bit(ATC_IS_PAUSED
, &atchan
->status
);
978 spin_unlock_irqrestore(&atchan
->lock
, flags
);
979 } else if (cmd
== DMA_TERMINATE_ALL
) {
980 struct at_desc
*desc
, *_desc
;
982 * This is only called when something went wrong elsewhere, so
983 * we don't really care about the data. Just disable the
984 * channel. We still have to poll the channel enable bit due
985 * to AHB/HSB limitations.
987 spin_lock_irqsave(&atchan
->lock
, flags
);
989 /* disabling channel: must also remove suspend state */
990 dma_writel(atdma
, CHDR
, AT_DMA_RES(chan_id
) | atchan
->mask
);
992 /* confirm that this channel is disabled */
993 while (dma_readl(atdma
, CHSR
) & atchan
->mask
)
996 /* active_list entries will end up before queued entries */
997 list_splice_init(&atchan
->queue
, &list
);
998 list_splice_init(&atchan
->active_list
, &list
);
1000 /* Flush all pending and queued descriptors */
1001 list_for_each_entry_safe(desc
, _desc
, &list
, desc_node
)
1002 atc_chain_complete(atchan
, desc
);
1004 clear_bit(ATC_IS_PAUSED
, &atchan
->status
);
1005 /* if channel dedicated to cyclic operations, free it */
1006 clear_bit(ATC_IS_CYCLIC
, &atchan
->status
);
1008 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1009 } else if (cmd
== DMA_SLAVE_CONFIG
) {
1010 return set_runtime_config(chan
, (struct dma_slave_config
*)arg
);
1019 * atc_tx_status - poll for transaction completion
1020 * @chan: DMA channel
1021 * @cookie: transaction identifier to check status of
1022 * @txstate: if not %NULL updated with transaction state
1024 * If @txstate is passed in, upon return it reflect the driver
1025 * internal state and can be used with dma_async_is_complete() to check
1026 * the status of multiple cookies without re-checking hardware state.
1028 static enum dma_status
1029 atc_tx_status(struct dma_chan
*chan
,
1030 dma_cookie_t cookie
,
1031 struct dma_tx_state
*txstate
)
1033 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1034 dma_cookie_t last_used
;
1035 dma_cookie_t last_complete
;
1036 unsigned long flags
;
1037 enum dma_status ret
;
1039 spin_lock_irqsave(&atchan
->lock
, flags
);
1041 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1042 if (ret
!= DMA_SUCCESS
) {
1043 atc_cleanup_descriptors(atchan
);
1045 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1048 last_complete
= chan
->completed_cookie
;
1049 last_used
= chan
->cookie
;
1051 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1053 if (ret
!= DMA_SUCCESS
)
1054 dma_set_residue(txstate
, atc_first_active(atchan
)->len
);
1056 if (atc_chan_is_paused(atchan
))
1059 dev_vdbg(chan2dev(chan
), "tx_status %d: cookie = %d (d%d, u%d)\n",
1060 ret
, cookie
, last_complete
? last_complete
: 0,
1061 last_used
? last_used
: 0);
1067 * atc_issue_pending - try to finish work
1068 * @chan: target DMA channel
1070 static void atc_issue_pending(struct dma_chan
*chan
)
1072 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1073 unsigned long flags
;
1075 dev_vdbg(chan2dev(chan
), "issue_pending\n");
1077 /* Not needed for cyclic transfers */
1078 if (atc_chan_is_cyclic(atchan
))
1081 spin_lock_irqsave(&atchan
->lock
, flags
);
1082 atc_advance_work(atchan
);
1083 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1087 * atc_alloc_chan_resources - allocate resources for DMA channel
1088 * @chan: allocate descriptor resources for this channel
1089 * @client: current client requesting the channel be ready for requests
1091 * return - the number of allocated descriptors
1093 static int atc_alloc_chan_resources(struct dma_chan
*chan
)
1095 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1096 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1097 struct at_desc
*desc
;
1098 struct at_dma_slave
*atslave
;
1099 unsigned long flags
;
1102 LIST_HEAD(tmp_list
);
1104 dev_vdbg(chan2dev(chan
), "alloc_chan_resources\n");
1106 /* ASSERT: channel is idle */
1107 if (atc_chan_is_enabled(atchan
)) {
1108 dev_dbg(chan2dev(chan
), "DMA channel not idle ?\n");
1112 cfg
= ATC_DEFAULT_CFG
;
1114 atslave
= chan
->private;
1117 * We need controller-specific data to set up slave
1120 BUG_ON(!atslave
->dma_dev
|| atslave
->dma_dev
!= atdma
->dma_common
.dev
);
1122 /* if cfg configuration specified take it instad of default */
1127 /* have we already been set up?
1128 * reconfigure channel but no need to reallocate descriptors */
1129 if (!list_empty(&atchan
->free_list
))
1130 return atchan
->descs_allocated
;
1132 /* Allocate initial pool of descriptors */
1133 for (i
= 0; i
< init_nr_desc_per_channel
; i
++) {
1134 desc
= atc_alloc_descriptor(chan
, GFP_KERNEL
);
1136 dev_err(atdma
->dma_common
.dev
,
1137 "Only %d initial descriptors\n", i
);
1140 list_add_tail(&desc
->desc_node
, &tmp_list
);
1143 spin_lock_irqsave(&atchan
->lock
, flags
);
1144 atchan
->descs_allocated
= i
;
1145 list_splice(&tmp_list
, &atchan
->free_list
);
1146 dma_cookie_init(chan
);
1147 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1149 /* channel parameters */
1150 channel_writel(atchan
, CFG
, cfg
);
1152 dev_dbg(chan2dev(chan
),
1153 "alloc_chan_resources: allocated %d descriptors\n",
1154 atchan
->descs_allocated
);
1156 return atchan
->descs_allocated
;
1160 * atc_free_chan_resources - free all channel resources
1161 * @chan: DMA channel
1163 static void atc_free_chan_resources(struct dma_chan
*chan
)
1165 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1166 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1167 struct at_desc
*desc
, *_desc
;
1170 dev_dbg(chan2dev(chan
), "free_chan_resources: (descs allocated=%u)\n",
1171 atchan
->descs_allocated
);
1173 /* ASSERT: channel is idle */
1174 BUG_ON(!list_empty(&atchan
->active_list
));
1175 BUG_ON(!list_empty(&atchan
->queue
));
1176 BUG_ON(atc_chan_is_enabled(atchan
));
1178 list_for_each_entry_safe(desc
, _desc
, &atchan
->free_list
, desc_node
) {
1179 dev_vdbg(chan2dev(chan
), " freeing descriptor %p\n", desc
);
1180 list_del(&desc
->desc_node
);
1181 /* free link descriptor */
1182 dma_pool_free(atdma
->dma_desc_pool
, desc
, desc
->txd
.phys
);
1184 list_splice_init(&atchan
->free_list
, &list
);
1185 atchan
->descs_allocated
= 0;
1188 dev_vdbg(chan2dev(chan
), "free_chan_resources: done\n");
1192 /*-- Module Management -----------------------------------------------*/
1194 /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
1195 static struct at_dma_platform_data at91sam9rl_config
= {
1198 static struct at_dma_platform_data at91sam9g45_config
= {
1202 #if defined(CONFIG_OF)
1203 static const struct of_device_id atmel_dma_dt_ids
[] = {
1205 .compatible
= "atmel,at91sam9rl-dma",
1206 .data
= &at91sam9rl_config
,
1208 .compatible
= "atmel,at91sam9g45-dma",
1209 .data
= &at91sam9g45_config
,
1215 MODULE_DEVICE_TABLE(of
, atmel_dma_dt_ids
);
1218 static const struct platform_device_id atdma_devtypes
[] = {
1220 .name
= "at91sam9rl_dma",
1221 .driver_data
= (unsigned long) &at91sam9rl_config
,
1223 .name
= "at91sam9g45_dma",
1224 .driver_data
= (unsigned long) &at91sam9g45_config
,
1230 static inline const struct at_dma_platform_data
* __init
at_dma_get_driver_data(
1231 struct platform_device
*pdev
)
1233 if (pdev
->dev
.of_node
) {
1234 const struct of_device_id
*match
;
1235 match
= of_match_node(atmel_dma_dt_ids
, pdev
->dev
.of_node
);
1240 return (struct at_dma_platform_data
*)
1241 platform_get_device_id(pdev
)->driver_data
;
1245 * at_dma_off - disable DMA controller
1246 * @atdma: the Atmel HDAMC device
1248 static void at_dma_off(struct at_dma
*atdma
)
1250 dma_writel(atdma
, EN
, 0);
1252 /* disable all interrupts */
1253 dma_writel(atdma
, EBCIDR
, -1L);
1255 /* confirm that all channels are disabled */
1256 while (dma_readl(atdma
, CHSR
) & atdma
->all_chan_mask
)
1260 static int __init
at_dma_probe(struct platform_device
*pdev
)
1262 struct resource
*io
;
1263 struct at_dma
*atdma
;
1268 const struct at_dma_platform_data
*plat_dat
;
1270 /* setup platform data for each SoC */
1271 dma_cap_set(DMA_MEMCPY
, at91sam9rl_config
.cap_mask
);
1272 dma_cap_set(DMA_MEMCPY
, at91sam9g45_config
.cap_mask
);
1273 dma_cap_set(DMA_SLAVE
, at91sam9g45_config
.cap_mask
);
1275 /* get DMA parameters from controller type */
1276 plat_dat
= at_dma_get_driver_data(pdev
);
1280 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1284 irq
= platform_get_irq(pdev
, 0);
1288 size
= sizeof(struct at_dma
);
1289 size
+= plat_dat
->nr_channels
* sizeof(struct at_dma_chan
);
1290 atdma
= kzalloc(size
, GFP_KERNEL
);
1294 /* discover transaction capabilities */
1295 atdma
->dma_common
.cap_mask
= plat_dat
->cap_mask
;
1296 atdma
->all_chan_mask
= (1 << plat_dat
->nr_channels
) - 1;
1298 size
= resource_size(io
);
1299 if (!request_mem_region(io
->start
, size
, pdev
->dev
.driver
->name
)) {
1304 atdma
->regs
= ioremap(io
->start
, size
);
1310 atdma
->clk
= clk_get(&pdev
->dev
, "dma_clk");
1311 if (IS_ERR(atdma
->clk
)) {
1312 err
= PTR_ERR(atdma
->clk
);
1315 clk_enable(atdma
->clk
);
1317 /* force dma off, just in case */
1320 err
= request_irq(irq
, at_dma_interrupt
, 0, "at_hdmac", atdma
);
1324 platform_set_drvdata(pdev
, atdma
);
1326 /* create a pool of consistent memory blocks for hardware descriptors */
1327 atdma
->dma_desc_pool
= dma_pool_create("at_hdmac_desc_pool",
1328 &pdev
->dev
, sizeof(struct at_desc
),
1329 4 /* word alignment */, 0);
1330 if (!atdma
->dma_desc_pool
) {
1331 dev_err(&pdev
->dev
, "No memory for descriptors dma pool\n");
1333 goto err_pool_create
;
1336 /* clear any pending interrupt */
1337 while (dma_readl(atdma
, EBCISR
))
1340 /* initialize channels related values */
1341 INIT_LIST_HEAD(&atdma
->dma_common
.channels
);
1342 for (i
= 0; i
< plat_dat
->nr_channels
; i
++) {
1343 struct at_dma_chan
*atchan
= &atdma
->chan
[i
];
1345 atchan
->chan_common
.device
= &atdma
->dma_common
;
1346 dma_cookie_init(&atchan
->chan_common
);
1347 list_add_tail(&atchan
->chan_common
.device_node
,
1348 &atdma
->dma_common
.channels
);
1350 atchan
->ch_regs
= atdma
->regs
+ ch_regs(i
);
1351 spin_lock_init(&atchan
->lock
);
1352 atchan
->mask
= 1 << i
;
1354 INIT_LIST_HEAD(&atchan
->active_list
);
1355 INIT_LIST_HEAD(&atchan
->queue
);
1356 INIT_LIST_HEAD(&atchan
->free_list
);
1358 tasklet_init(&atchan
->tasklet
, atc_tasklet
,
1359 (unsigned long)atchan
);
1360 atc_enable_chan_irq(atdma
, i
);
1363 /* set base routines */
1364 atdma
->dma_common
.device_alloc_chan_resources
= atc_alloc_chan_resources
;
1365 atdma
->dma_common
.device_free_chan_resources
= atc_free_chan_resources
;
1366 atdma
->dma_common
.device_tx_status
= atc_tx_status
;
1367 atdma
->dma_common
.device_issue_pending
= atc_issue_pending
;
1368 atdma
->dma_common
.dev
= &pdev
->dev
;
1370 /* set prep routines based on capability */
1371 if (dma_has_cap(DMA_MEMCPY
, atdma
->dma_common
.cap_mask
))
1372 atdma
->dma_common
.device_prep_dma_memcpy
= atc_prep_dma_memcpy
;
1374 if (dma_has_cap(DMA_SLAVE
, atdma
->dma_common
.cap_mask
)) {
1375 atdma
->dma_common
.device_prep_slave_sg
= atc_prep_slave_sg
;
1376 /* controller can do slave DMA: can trigger cyclic transfers */
1377 dma_cap_set(DMA_CYCLIC
, atdma
->dma_common
.cap_mask
);
1378 atdma
->dma_common
.device_prep_dma_cyclic
= atc_prep_dma_cyclic
;
1379 atdma
->dma_common
.device_control
= atc_control
;
1382 dma_writel(atdma
, EN
, AT_DMA_ENABLE
);
1384 dev_info(&pdev
->dev
, "Atmel AHB DMA Controller ( %s%s), %d channels\n",
1385 dma_has_cap(DMA_MEMCPY
, atdma
->dma_common
.cap_mask
) ? "cpy " : "",
1386 dma_has_cap(DMA_SLAVE
, atdma
->dma_common
.cap_mask
) ? "slave " : "",
1387 plat_dat
->nr_channels
);
1389 dma_async_device_register(&atdma
->dma_common
);
1394 platform_set_drvdata(pdev
, NULL
);
1395 free_irq(platform_get_irq(pdev
, 0), atdma
);
1397 clk_disable(atdma
->clk
);
1398 clk_put(atdma
->clk
);
1400 iounmap(atdma
->regs
);
1403 release_mem_region(io
->start
, size
);
1409 static int __exit
at_dma_remove(struct platform_device
*pdev
)
1411 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1412 struct dma_chan
*chan
, *_chan
;
1413 struct resource
*io
;
1416 dma_async_device_unregister(&atdma
->dma_common
);
1418 dma_pool_destroy(atdma
->dma_desc_pool
);
1419 platform_set_drvdata(pdev
, NULL
);
1420 free_irq(platform_get_irq(pdev
, 0), atdma
);
1422 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
1424 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1426 /* Disable interrupts */
1427 atc_disable_chan_irq(atdma
, chan
->chan_id
);
1428 tasklet_disable(&atchan
->tasklet
);
1430 tasklet_kill(&atchan
->tasklet
);
1431 list_del(&chan
->device_node
);
1434 clk_disable(atdma
->clk
);
1435 clk_put(atdma
->clk
);
1437 iounmap(atdma
->regs
);
1440 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1441 release_mem_region(io
->start
, resource_size(io
));
1448 static void at_dma_shutdown(struct platform_device
*pdev
)
1450 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1452 at_dma_off(platform_get_drvdata(pdev
));
1453 clk_disable(atdma
->clk
);
1456 static int at_dma_prepare(struct device
*dev
)
1458 struct platform_device
*pdev
= to_platform_device(dev
);
1459 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1460 struct dma_chan
*chan
, *_chan
;
1462 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
1464 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1465 /* wait for transaction completion (except in cyclic case) */
1466 if (atc_chan_is_enabled(atchan
) && !atc_chan_is_cyclic(atchan
))
1472 static void atc_suspend_cyclic(struct at_dma_chan
*atchan
)
1474 struct dma_chan
*chan
= &atchan
->chan_common
;
1476 /* Channel should be paused by user
1477 * do it anyway even if it is not done already */
1478 if (!atc_chan_is_paused(atchan
)) {
1479 dev_warn(chan2dev(chan
),
1480 "cyclic channel not paused, should be done by channel user\n");
1481 atc_control(chan
, DMA_PAUSE
, 0);
1484 /* now preserve additional data for cyclic operations */
1485 /* next descriptor address in the cyclic list */
1486 atchan
->save_dscr
= channel_readl(atchan
, DSCR
);
1488 vdbg_dump_regs(atchan
);
1491 static int at_dma_suspend_noirq(struct device
*dev
)
1493 struct platform_device
*pdev
= to_platform_device(dev
);
1494 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1495 struct dma_chan
*chan
, *_chan
;
1498 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
1500 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1502 if (atc_chan_is_cyclic(atchan
))
1503 atc_suspend_cyclic(atchan
);
1504 atchan
->save_cfg
= channel_readl(atchan
, CFG
);
1506 atdma
->save_imr
= dma_readl(atdma
, EBCIMR
);
1508 /* disable DMA controller */
1510 clk_disable(atdma
->clk
);
1514 static void atc_resume_cyclic(struct at_dma_chan
*atchan
)
1516 struct at_dma
*atdma
= to_at_dma(atchan
->chan_common
.device
);
1518 /* restore channel status for cyclic descriptors list:
1519 * next descriptor in the cyclic list at the time of suspend */
1520 channel_writel(atchan
, SADDR
, 0);
1521 channel_writel(atchan
, DADDR
, 0);
1522 channel_writel(atchan
, CTRLA
, 0);
1523 channel_writel(atchan
, CTRLB
, 0);
1524 channel_writel(atchan
, DSCR
, atchan
->save_dscr
);
1525 dma_writel(atdma
, CHER
, atchan
->mask
);
1527 /* channel pause status should be removed by channel user
1528 * We cannot take the initiative to do it here */
1530 vdbg_dump_regs(atchan
);
1533 static int at_dma_resume_noirq(struct device
*dev
)
1535 struct platform_device
*pdev
= to_platform_device(dev
);
1536 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1537 struct dma_chan
*chan
, *_chan
;
1539 /* bring back DMA controller */
1540 clk_enable(atdma
->clk
);
1541 dma_writel(atdma
, EN
, AT_DMA_ENABLE
);
1543 /* clear any pending interrupt */
1544 while (dma_readl(atdma
, EBCISR
))
1547 /* restore saved data */
1548 dma_writel(atdma
, EBCIER
, atdma
->save_imr
);
1549 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
1551 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1553 channel_writel(atchan
, CFG
, atchan
->save_cfg
);
1554 if (atc_chan_is_cyclic(atchan
))
1555 atc_resume_cyclic(atchan
);
1560 static const struct dev_pm_ops at_dma_dev_pm_ops
= {
1561 .prepare
= at_dma_prepare
,
1562 .suspend_noirq
= at_dma_suspend_noirq
,
1563 .resume_noirq
= at_dma_resume_noirq
,
1566 static struct platform_driver at_dma_driver
= {
1567 .remove
= __exit_p(at_dma_remove
),
1568 .shutdown
= at_dma_shutdown
,
1569 .id_table
= atdma_devtypes
,
1572 .pm
= &at_dma_dev_pm_ops
,
1573 .of_match_table
= of_match_ptr(atmel_dma_dt_ids
),
1577 static int __init
at_dma_init(void)
1579 return platform_driver_probe(&at_dma_driver
, at_dma_probe
);
1581 subsys_initcall(at_dma_init
);
1583 static void __exit
at_dma_exit(void)
1585 platform_driver_unregister(&at_dma_driver
);
1587 module_exit(at_dma_exit
);
1589 MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
1590 MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
1591 MODULE_LICENSE("GPL");
1592 MODULE_ALIAS("platform:at_hdmac");