2 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
4 * Copyright (C) 2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
13 * The only Atmel DMA Controller that is not covered by this driver is the one
14 * found on AT91SAM9263.
17 #include <dt-bindings/dma/at91.h>
18 #include <linux/clk.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dmapool.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
27 #include <linux/of_device.h>
28 #include <linux/of_dma.h>
30 #include "at_hdmac_regs.h"
31 #include "dmaengine.h"
37 * at_hdmac : Name of the ATmel AHB DMA Controller
38 * at_dma_ / atdma : ATmel DMA controller entity related
39 * atc_ / atchan : ATmel DMA Channel entity related
42 #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
43 #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
44 |ATC_DIF(AT_DMA_MEM_IF))
45 #define ATC_DMA_BUSWIDTHS\
46 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
47 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
48 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
49 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
51 #define ATC_MAX_DSCR_TRIALS 10
54 * Initial number of descriptors to allocate for each channel. This could
55 * be increased during dma usage.
57 static unsigned int init_nr_desc_per_channel
= 64;
58 module_param(init_nr_desc_per_channel
, uint
, 0644);
59 MODULE_PARM_DESC(init_nr_desc_per_channel
,
60 "initial descriptors per channel (default: 64)");
64 static dma_cookie_t
atc_tx_submit(struct dma_async_tx_descriptor
*tx
);
65 static void atc_issue_pending(struct dma_chan
*chan
);
68 /*----------------------------------------------------------------------*/
70 static inline unsigned int atc_get_xfer_width(dma_addr_t src
, dma_addr_t dst
,
75 if (!((src
| dst
| len
) & 3))
77 else if (!((src
| dst
| len
) & 1))
85 static struct at_desc
*atc_first_active(struct at_dma_chan
*atchan
)
87 return list_first_entry(&atchan
->active_list
,
88 struct at_desc
, desc_node
);
91 static struct at_desc
*atc_first_queued(struct at_dma_chan
*atchan
)
93 return list_first_entry(&atchan
->queue
,
94 struct at_desc
, desc_node
);
98 * atc_alloc_descriptor - allocate and return an initialized descriptor
99 * @chan: the channel to allocate descriptors for
100 * @gfp_flags: GFP allocation flags
102 * Note: The ack-bit is positioned in the descriptor flag at creation time
103 * to make initial allocation more convenient. This bit will be cleared
104 * and control will be given to client at usage time (during
105 * preparation functions).
107 static struct at_desc
*atc_alloc_descriptor(struct dma_chan
*chan
,
110 struct at_desc
*desc
= NULL
;
111 struct at_dma
*atdma
= to_at_dma(chan
->device
);
114 desc
= dma_pool_alloc(atdma
->dma_desc_pool
, gfp_flags
, &phys
);
116 memset(desc
, 0, sizeof(struct at_desc
));
117 INIT_LIST_HEAD(&desc
->tx_list
);
118 dma_async_tx_descriptor_init(&desc
->txd
, chan
);
119 /* txd.flags will be overwritten in prep functions */
120 desc
->txd
.flags
= DMA_CTRL_ACK
;
121 desc
->txd
.tx_submit
= atc_tx_submit
;
122 desc
->txd
.phys
= phys
;
129 * atc_desc_get - get an unused descriptor from free_list
130 * @atchan: channel we want a new descriptor for
132 static struct at_desc
*atc_desc_get(struct at_dma_chan
*atchan
)
134 struct at_desc
*desc
, *_desc
;
135 struct at_desc
*ret
= NULL
;
140 spin_lock_irqsave(&atchan
->lock
, flags
);
141 list_for_each_entry_safe(desc
, _desc
, &atchan
->free_list
, desc_node
) {
143 if (async_tx_test_ack(&desc
->txd
)) {
144 list_del(&desc
->desc_node
);
148 dev_dbg(chan2dev(&atchan
->chan_common
),
149 "desc %p not ACKed\n", desc
);
151 spin_unlock_irqrestore(&atchan
->lock
, flags
);
152 dev_vdbg(chan2dev(&atchan
->chan_common
),
153 "scanned %u descriptors on freelist\n", i
);
155 /* no more descriptor available in initial pool: create one more */
157 ret
= atc_alloc_descriptor(&atchan
->chan_common
, GFP_ATOMIC
);
159 spin_lock_irqsave(&atchan
->lock
, flags
);
160 atchan
->descs_allocated
++;
161 spin_unlock_irqrestore(&atchan
->lock
, flags
);
163 dev_err(chan2dev(&atchan
->chan_common
),
164 "not enough descriptors available\n");
172 * atc_desc_put - move a descriptor, including any children, to the free list
173 * @atchan: channel we work on
174 * @desc: descriptor, at the head of a chain, to move to free list
176 static void atc_desc_put(struct at_dma_chan
*atchan
, struct at_desc
*desc
)
179 struct at_desc
*child
;
182 spin_lock_irqsave(&atchan
->lock
, flags
);
183 list_for_each_entry(child
, &desc
->tx_list
, desc_node
)
184 dev_vdbg(chan2dev(&atchan
->chan_common
),
185 "moving child desc %p to freelist\n",
187 list_splice_init(&desc
->tx_list
, &atchan
->free_list
);
188 dev_vdbg(chan2dev(&atchan
->chan_common
),
189 "moving desc %p to freelist\n", desc
);
190 list_add(&desc
->desc_node
, &atchan
->free_list
);
191 spin_unlock_irqrestore(&atchan
->lock
, flags
);
196 * atc_desc_chain - build chain adding a descriptor
197 * @first: address of first descriptor of the chain
198 * @prev: address of previous descriptor of the chain
199 * @desc: descriptor to queue
201 * Called from prep_* functions
203 static void atc_desc_chain(struct at_desc
**first
, struct at_desc
**prev
,
204 struct at_desc
*desc
)
209 /* inform the HW lli about chaining */
210 (*prev
)->lli
.dscr
= desc
->txd
.phys
;
211 /* insert the link descriptor to the LD ring */
212 list_add_tail(&desc
->desc_node
,
219 * atc_dostart - starts the DMA engine for real
220 * @atchan: the channel we want to start
221 * @first: first descriptor in the list we want to begin with
223 * Called with atchan->lock held and bh disabled
225 static void atc_dostart(struct at_dma_chan
*atchan
, struct at_desc
*first
)
227 struct at_dma
*atdma
= to_at_dma(atchan
->chan_common
.device
);
229 /* ASSERT: channel is idle */
230 if (atc_chan_is_enabled(atchan
)) {
231 dev_err(chan2dev(&atchan
->chan_common
),
232 "BUG: Attempted to start non-idle channel\n");
233 dev_err(chan2dev(&atchan
->chan_common
),
234 " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
235 channel_readl(atchan
, SADDR
),
236 channel_readl(atchan
, DADDR
),
237 channel_readl(atchan
, CTRLA
),
238 channel_readl(atchan
, CTRLB
),
239 channel_readl(atchan
, DSCR
));
241 /* The tasklet will hopefully advance the queue... */
245 vdbg_dump_regs(atchan
);
247 channel_writel(atchan
, SADDR
, 0);
248 channel_writel(atchan
, DADDR
, 0);
249 channel_writel(atchan
, CTRLA
, 0);
250 channel_writel(atchan
, CTRLB
, 0);
251 channel_writel(atchan
, DSCR
, first
->txd
.phys
);
252 channel_writel(atchan
, SPIP
, ATC_SPIP_HOLE(first
->src_hole
) |
253 ATC_SPIP_BOUNDARY(first
->boundary
));
254 channel_writel(atchan
, DPIP
, ATC_DPIP_HOLE(first
->dst_hole
) |
255 ATC_DPIP_BOUNDARY(first
->boundary
));
256 dma_writel(atdma
, CHER
, atchan
->mask
);
258 vdbg_dump_regs(atchan
);
262 * atc_get_desc_by_cookie - get the descriptor of a cookie
263 * @atchan: the DMA channel
264 * @cookie: the cookie to get the descriptor for
266 static struct at_desc
*atc_get_desc_by_cookie(struct at_dma_chan
*atchan
,
269 struct at_desc
*desc
, *_desc
;
271 list_for_each_entry_safe(desc
, _desc
, &atchan
->queue
, desc_node
) {
272 if (desc
->txd
.cookie
== cookie
)
276 list_for_each_entry_safe(desc
, _desc
, &atchan
->active_list
, desc_node
) {
277 if (desc
->txd
.cookie
== cookie
)
285 * atc_calc_bytes_left - calculates the number of bytes left according to the
286 * value read from CTRLA.
288 * @current_len: the number of bytes left before reading CTRLA
289 * @ctrla: the value of CTRLA
291 static inline int atc_calc_bytes_left(int current_len
, u32 ctrla
)
293 u32 btsize
= (ctrla
& ATC_BTSIZE_MAX
);
294 u32 src_width
= ATC_REG_TO_SRC_WIDTH(ctrla
);
297 * According to the datasheet, when reading the Control A Register
298 * (ctrla), the Buffer Transfer Size (btsize) bitfield refers to the
299 * number of transfers completed on the Source Interface.
300 * So btsize is always a number of source width transfers.
302 return current_len
- (btsize
<< src_width
);
306 * atc_get_bytes_left - get the number of bytes residue for a cookie
308 * @cookie: transaction identifier to check status of
310 static int atc_get_bytes_left(struct dma_chan
*chan
, dma_cookie_t cookie
)
312 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
313 struct at_desc
*desc_first
= atc_first_active(atchan
);
314 struct at_desc
*desc
;
316 u32 ctrla
, dscr
, trials
;
319 * If the cookie doesn't match to the currently running transfer then
320 * we can return the total length of the associated DMA transfer,
321 * because it is still queued.
323 desc
= atc_get_desc_by_cookie(atchan
, cookie
);
326 else if (desc
!= desc_first
)
327 return desc
->total_len
;
329 /* cookie matches to the currently running transfer */
330 ret
= desc_first
->total_len
;
332 if (desc_first
->lli
.dscr
) {
333 /* hardware linked list transfer */
336 * Calculate the residue by removing the length of the child
337 * descriptors already transferred from the total length.
338 * To get the current child descriptor we can use the value of
339 * the channel's DSCR register and compare it against the value
340 * of the hardware linked list structure of each child
343 * The CTRLA register provides us with the amount of data
344 * already read from the source for the current child
345 * descriptor. So we can compute a more accurate residue by also
346 * removing the number of bytes corresponding to this amount of
349 * However, the DSCR and CTRLA registers cannot be read both
350 * atomically. Hence a race condition may occur: the first read
351 * register may refer to one child descriptor whereas the second
352 * read may refer to a later child descriptor in the list
353 * because of the DMA transfer progression inbetween the two
356 * One solution could have been to pause the DMA transfer, read
357 * the DSCR and CTRLA then resume the DMA transfer. Nonetheless,
358 * this approach presents some drawbacks:
359 * - If the DMA transfer is paused, RX overruns or TX underruns
360 * are more likey to occur depending on the system latency.
361 * Taking the USART driver as an example, it uses a cyclic DMA
362 * transfer to read data from the Receive Holding Register
363 * (RHR) to avoid RX overruns since the RHR is not protected
364 * by any FIFO on most Atmel SoCs. So pausing the DMA transfer
365 * to compute the residue would break the USART driver design.
366 * - The atc_pause() function masks interrupts but we'd rather
367 * avoid to do so for system latency purpose.
369 * Then we'd rather use another solution: the DSCR is read a
370 * first time, the CTRLA is read in turn, next the DSCR is read
371 * a second time. If the two consecutive read values of the DSCR
372 * are the same then we assume both refers to the very same
373 * child descriptor as well as the CTRLA value read inbetween
374 * does. For cyclic tranfers, the assumption is that a full loop
376 * If the two DSCR values are different, we read again the CTRLA
377 * then the DSCR till two consecutive read values from DSCR are
378 * equal or till the maxium trials is reach.
379 * This algorithm is very unlikely not to find a stable value for
383 dscr
= channel_readl(atchan
, DSCR
);
384 rmb(); /* ensure DSCR is read before CTRLA */
385 ctrla
= channel_readl(atchan
, CTRLA
);
386 for (trials
= 0; trials
< ATC_MAX_DSCR_TRIALS
; ++trials
) {
389 rmb(); /* ensure DSCR is read after CTRLA */
390 new_dscr
= channel_readl(atchan
, DSCR
);
393 * If the DSCR register value has not changed inside the
394 * DMA controller since the previous read, we assume
395 * that both the dscr and ctrla values refers to the
396 * very same descriptor.
398 if (likely(new_dscr
== dscr
))
402 * DSCR has changed inside the DMA controller, so the
403 * previouly read value of CTRLA may refer to an already
404 * processed descriptor hence could be outdated.
405 * We need to update ctrla to match the current
409 rmb(); /* ensure DSCR is read before CTRLA */
410 ctrla
= channel_readl(atchan
, CTRLA
);
412 if (unlikely(trials
>= ATC_MAX_DSCR_TRIALS
))
415 /* for the first descriptor we can be more accurate */
416 if (desc_first
->lli
.dscr
== dscr
)
417 return atc_calc_bytes_left(ret
, ctrla
);
419 ret
-= desc_first
->len
;
420 list_for_each_entry(desc
, &desc_first
->tx_list
, desc_node
) {
421 if (desc
->lli
.dscr
== dscr
)
428 * For the current descriptor in the chain we can calculate
429 * the remaining bytes using the channel's register.
431 ret
= atc_calc_bytes_left(ret
, ctrla
);
433 /* single transfer */
434 ctrla
= channel_readl(atchan
, CTRLA
);
435 ret
= atc_calc_bytes_left(ret
, ctrla
);
442 * atc_chain_complete - finish work for one transaction chain
443 * @atchan: channel we work on
444 * @desc: descriptor at the head of the chain we want do complete
446 * Called with atchan->lock held and bh disabled */
448 atc_chain_complete(struct at_dma_chan
*atchan
, struct at_desc
*desc
)
450 struct dma_async_tx_descriptor
*txd
= &desc
->txd
;
452 dev_vdbg(chan2dev(&atchan
->chan_common
),
453 "descriptor %u complete\n", txd
->cookie
);
455 /* mark the descriptor as complete for non cyclic cases only */
456 if (!atc_chan_is_cyclic(atchan
))
457 dma_cookie_complete(txd
);
459 /* move children to free_list */
460 list_splice_init(&desc
->tx_list
, &atchan
->free_list
);
461 /* move myself to free_list */
462 list_move(&desc
->desc_node
, &atchan
->free_list
);
464 dma_descriptor_unmap(txd
);
465 /* for cyclic transfers,
466 * no need to replay callback function while stopping */
467 if (!atc_chan_is_cyclic(atchan
)) {
468 dma_async_tx_callback callback
= txd
->callback
;
469 void *param
= txd
->callback_param
;
472 * The API requires that no submissions are done from a
473 * callback, so we don't need to drop the lock here
479 dma_run_dependencies(txd
);
483 * atc_complete_all - finish work for all transactions
484 * @atchan: channel to complete transactions for
486 * Eventually submit queued descriptors if any
488 * Assume channel is idle while calling this function
489 * Called with atchan->lock held and bh disabled
491 static void atc_complete_all(struct at_dma_chan
*atchan
)
493 struct at_desc
*desc
, *_desc
;
496 dev_vdbg(chan2dev(&atchan
->chan_common
), "complete all\n");
499 * Submit queued descriptors ASAP, i.e. before we go through
500 * the completed ones.
502 if (!list_empty(&atchan
->queue
))
503 atc_dostart(atchan
, atc_first_queued(atchan
));
504 /* empty active_list now it is completed */
505 list_splice_init(&atchan
->active_list
, &list
);
506 /* empty queue list by moving descriptors (if any) to active_list */
507 list_splice_init(&atchan
->queue
, &atchan
->active_list
);
509 list_for_each_entry_safe(desc
, _desc
, &list
, desc_node
)
510 atc_chain_complete(atchan
, desc
);
514 * atc_advance_work - at the end of a transaction, move forward
515 * @atchan: channel where the transaction ended
517 * Called with atchan->lock held and bh disabled
519 static void atc_advance_work(struct at_dma_chan
*atchan
)
521 dev_vdbg(chan2dev(&atchan
->chan_common
), "advance_work\n");
523 if (atc_chan_is_enabled(atchan
))
526 if (list_empty(&atchan
->active_list
) ||
527 list_is_singular(&atchan
->active_list
)) {
528 atc_complete_all(atchan
);
530 atc_chain_complete(atchan
, atc_first_active(atchan
));
532 atc_dostart(atchan
, atc_first_active(atchan
));
538 * atc_handle_error - handle errors reported by DMA controller
539 * @atchan: channel where error occurs
541 * Called with atchan->lock held and bh disabled
543 static void atc_handle_error(struct at_dma_chan
*atchan
)
545 struct at_desc
*bad_desc
;
546 struct at_desc
*child
;
549 * The descriptor currently at the head of the active list is
550 * broked. Since we don't have any way to report errors, we'll
551 * just have to scream loudly and try to carry on.
553 bad_desc
= atc_first_active(atchan
);
554 list_del_init(&bad_desc
->desc_node
);
556 /* As we are stopped, take advantage to push queued descriptors
558 list_splice_init(&atchan
->queue
, atchan
->active_list
.prev
);
560 /* Try to restart the controller */
561 if (!list_empty(&atchan
->active_list
))
562 atc_dostart(atchan
, atc_first_active(atchan
));
565 * KERN_CRITICAL may seem harsh, but since this only happens
566 * when someone submits a bad physical address in a
567 * descriptor, we should consider ourselves lucky that the
568 * controller flagged an error instead of scribbling over
569 * random memory locations.
571 dev_crit(chan2dev(&atchan
->chan_common
),
572 "Bad descriptor submitted for DMA!\n");
573 dev_crit(chan2dev(&atchan
->chan_common
),
574 " cookie: %d\n", bad_desc
->txd
.cookie
);
575 atc_dump_lli(atchan
, &bad_desc
->lli
);
576 list_for_each_entry(child
, &bad_desc
->tx_list
, desc_node
)
577 atc_dump_lli(atchan
, &child
->lli
);
579 /* Pretend the descriptor completed successfully */
580 atc_chain_complete(atchan
, bad_desc
);
584 * atc_handle_cyclic - at the end of a period, run callback function
585 * @atchan: channel used for cyclic operations
587 * Called with atchan->lock held and bh disabled
589 static void atc_handle_cyclic(struct at_dma_chan
*atchan
)
591 struct at_desc
*first
= atc_first_active(atchan
);
592 struct dma_async_tx_descriptor
*txd
= &first
->txd
;
593 dma_async_tx_callback callback
= txd
->callback
;
594 void *param
= txd
->callback_param
;
596 dev_vdbg(chan2dev(&atchan
->chan_common
),
597 "new cyclic period llp 0x%08x\n",
598 channel_readl(atchan
, DSCR
));
604 /*-- IRQ & Tasklet ---------------------------------------------------*/
606 static void atc_tasklet(unsigned long data
)
608 struct at_dma_chan
*atchan
= (struct at_dma_chan
*)data
;
611 spin_lock_irqsave(&atchan
->lock
, flags
);
612 if (test_and_clear_bit(ATC_IS_ERROR
, &atchan
->status
))
613 atc_handle_error(atchan
);
614 else if (atc_chan_is_cyclic(atchan
))
615 atc_handle_cyclic(atchan
);
617 atc_advance_work(atchan
);
619 spin_unlock_irqrestore(&atchan
->lock
, flags
);
622 static irqreturn_t
at_dma_interrupt(int irq
, void *dev_id
)
624 struct at_dma
*atdma
= (struct at_dma
*)dev_id
;
625 struct at_dma_chan
*atchan
;
627 u32 status
, pending
, imr
;
631 imr
= dma_readl(atdma
, EBCIMR
);
632 status
= dma_readl(atdma
, EBCISR
);
633 pending
= status
& imr
;
638 dev_vdbg(atdma
->dma_common
.dev
,
639 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
640 status
, imr
, pending
);
642 for (i
= 0; i
< atdma
->dma_common
.chancnt
; i
++) {
643 atchan
= &atdma
->chan
[i
];
644 if (pending
& (AT_DMA_BTC(i
) | AT_DMA_ERR(i
))) {
645 if (pending
& AT_DMA_ERR(i
)) {
646 /* Disable channel on AHB error */
647 dma_writel(atdma
, CHDR
,
648 AT_DMA_RES(i
) | atchan
->mask
);
649 /* Give information to tasklet */
650 set_bit(ATC_IS_ERROR
, &atchan
->status
);
652 tasklet_schedule(&atchan
->tasklet
);
663 /*-- DMA Engine API --------------------------------------------------*/
666 * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
667 * @desc: descriptor at the head of the transaction chain
669 * Queue chain if DMA engine is working already
671 * Cookie increment and adding to active_list or queue must be atomic
673 static dma_cookie_t
atc_tx_submit(struct dma_async_tx_descriptor
*tx
)
675 struct at_desc
*desc
= txd_to_at_desc(tx
);
676 struct at_dma_chan
*atchan
= to_at_dma_chan(tx
->chan
);
680 spin_lock_irqsave(&atchan
->lock
, flags
);
681 cookie
= dma_cookie_assign(tx
);
683 if (list_empty(&atchan
->active_list
)) {
684 dev_vdbg(chan2dev(tx
->chan
), "tx_submit: started %u\n",
686 atc_dostart(atchan
, desc
);
687 list_add_tail(&desc
->desc_node
, &atchan
->active_list
);
689 dev_vdbg(chan2dev(tx
->chan
), "tx_submit: queued %u\n",
691 list_add_tail(&desc
->desc_node
, &atchan
->queue
);
694 spin_unlock_irqrestore(&atchan
->lock
, flags
);
700 * atc_prep_dma_interleaved - prepare memory to memory interleaved operation
701 * @chan: the channel to prepare operation on
702 * @xt: Interleaved transfer template
703 * @flags: tx descriptor status flags
705 static struct dma_async_tx_descriptor
*
706 atc_prep_dma_interleaved(struct dma_chan
*chan
,
707 struct dma_interleaved_template
*xt
,
710 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
711 struct data_chunk
*first
= xt
->sgl
;
712 struct at_desc
*desc
= NULL
;
720 dev_info(chan2dev(chan
),
721 "%s: src=0x%08x, dest=0x%08x, numf=%d, frame_size=%d, flags=0x%lx\n",
722 __func__
, xt
->src_start
, xt
->dst_start
, xt
->numf
,
723 xt
->frame_size
, flags
);
725 if (unlikely(!xt
|| xt
->numf
!= 1 || !xt
->frame_size
))
729 * The controller can only "skip" X bytes every Y bytes, so we
730 * need to make sure we are given a template that fit that
731 * description, ie a template with chunks that always have the
732 * same size, with the same ICGs.
734 for (i
= 0; i
< xt
->frame_size
; i
++) {
735 struct data_chunk
*chunk
= xt
->sgl
+ i
;
737 if ((chunk
->size
!= xt
->sgl
->size
) ||
738 (dmaengine_get_dst_icg(xt
, chunk
) != dmaengine_get_dst_icg(xt
, first
)) ||
739 (dmaengine_get_src_icg(xt
, chunk
) != dmaengine_get_src_icg(xt
, first
))) {
740 dev_err(chan2dev(chan
),
741 "%s: the controller can transfer only identical chunks\n",
749 dwidth
= atc_get_xfer_width(xt
->src_start
,
752 xfer_count
= len
>> dwidth
;
753 if (xfer_count
> ATC_BTSIZE_MAX
) {
754 dev_err(chan2dev(chan
), "%s: buffer is too big\n", __func__
);
758 ctrla
= ATC_SRC_WIDTH(dwidth
) |
759 ATC_DST_WIDTH(dwidth
);
761 ctrlb
= ATC_DEFAULT_CTRLB
| ATC_IEN
762 | ATC_SRC_ADDR_MODE_INCR
763 | ATC_DST_ADDR_MODE_INCR
768 /* create the transfer */
769 desc
= atc_desc_get(atchan
);
771 dev_err(chan2dev(chan
),
772 "%s: couldn't allocate our descriptor\n", __func__
);
776 desc
->lli
.saddr
= xt
->src_start
;
777 desc
->lli
.daddr
= xt
->dst_start
;
778 desc
->lli
.ctrla
= ctrla
| xfer_count
;
779 desc
->lli
.ctrlb
= ctrlb
;
781 desc
->boundary
= first
->size
>> dwidth
;
782 desc
->dst_hole
= (dmaengine_get_dst_icg(xt
, first
) >> dwidth
) + 1;
783 desc
->src_hole
= (dmaengine_get_src_icg(xt
, first
) >> dwidth
) + 1;
785 desc
->txd
.cookie
= -EBUSY
;
786 desc
->total_len
= desc
->len
= len
;
788 /* set end-of-link to the last link descriptor of list*/
791 desc
->txd
.flags
= flags
; /* client is in control of this ack */
797 * atc_prep_dma_memcpy - prepare a memcpy operation
798 * @chan: the channel to prepare operation on
799 * @dest: operation virtual destination address
800 * @src: operation virtual source address
801 * @len: operation length
802 * @flags: tx descriptor status flags
804 static struct dma_async_tx_descriptor
*
805 atc_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
806 size_t len
, unsigned long flags
)
808 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
809 struct at_desc
*desc
= NULL
;
810 struct at_desc
*first
= NULL
;
811 struct at_desc
*prev
= NULL
;
814 unsigned int src_width
;
815 unsigned int dst_width
;
819 dev_vdbg(chan2dev(chan
), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n",
820 dest
, src
, len
, flags
);
822 if (unlikely(!len
)) {
823 dev_dbg(chan2dev(chan
), "prep_dma_memcpy: length is zero!\n");
827 ctrlb
= ATC_DEFAULT_CTRLB
| ATC_IEN
828 | ATC_SRC_ADDR_MODE_INCR
829 | ATC_DST_ADDR_MODE_INCR
833 * We can be a lot more clever here, but this should take care
834 * of the most common optimization.
836 src_width
= dst_width
= atc_get_xfer_width(src
, dest
, len
);
838 ctrla
= ATC_SRC_WIDTH(src_width
) |
839 ATC_DST_WIDTH(dst_width
);
841 for (offset
= 0; offset
< len
; offset
+= xfer_count
<< src_width
) {
842 xfer_count
= min_t(size_t, (len
- offset
) >> src_width
,
845 desc
= atc_desc_get(atchan
);
849 desc
->lli
.saddr
= src
+ offset
;
850 desc
->lli
.daddr
= dest
+ offset
;
851 desc
->lli
.ctrla
= ctrla
| xfer_count
;
852 desc
->lli
.ctrlb
= ctrlb
;
854 desc
->txd
.cookie
= 0;
855 desc
->len
= xfer_count
<< src_width
;
857 atc_desc_chain(&first
, &prev
, desc
);
860 /* First descriptor of the chain embedds additional information */
861 first
->txd
.cookie
= -EBUSY
;
862 first
->total_len
= len
;
864 /* set end-of-link to the last link descriptor of list*/
867 first
->txd
.flags
= flags
; /* client is in control of this ack */
872 atc_desc_put(atchan
, first
);
878 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
880 * @sgl: scatterlist to transfer to/from
881 * @sg_len: number of entries in @scatterlist
882 * @direction: DMA direction
883 * @flags: tx descriptor status flags
884 * @context: transaction context (ignored)
886 static struct dma_async_tx_descriptor
*
887 atc_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
888 unsigned int sg_len
, enum dma_transfer_direction direction
,
889 unsigned long flags
, void *context
)
891 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
892 struct at_dma_slave
*atslave
= chan
->private;
893 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
894 struct at_desc
*first
= NULL
;
895 struct at_desc
*prev
= NULL
;
899 unsigned int reg_width
;
900 unsigned int mem_width
;
902 struct scatterlist
*sg
;
903 size_t total_len
= 0;
905 dev_vdbg(chan2dev(chan
), "prep_slave_sg (%d): %s f0x%lx\n",
907 direction
== DMA_MEM_TO_DEV
? "TO DEVICE" : "FROM DEVICE",
910 if (unlikely(!atslave
|| !sg_len
)) {
911 dev_dbg(chan2dev(chan
), "prep_slave_sg: sg length is zero!\n");
915 ctrla
= ATC_SCSIZE(sconfig
->src_maxburst
)
916 | ATC_DCSIZE(sconfig
->dst_maxburst
);
921 reg_width
= convert_buswidth(sconfig
->dst_addr_width
);
922 ctrla
|= ATC_DST_WIDTH(reg_width
);
923 ctrlb
|= ATC_DST_ADDR_MODE_FIXED
924 | ATC_SRC_ADDR_MODE_INCR
926 | ATC_SIF(atchan
->mem_if
) | ATC_DIF(atchan
->per_if
);
927 reg
= sconfig
->dst_addr
;
928 for_each_sg(sgl
, sg
, sg_len
, i
) {
929 struct at_desc
*desc
;
933 desc
= atc_desc_get(atchan
);
937 mem
= sg_dma_address(sg
);
938 len
= sg_dma_len(sg
);
939 if (unlikely(!len
)) {
940 dev_dbg(chan2dev(chan
),
941 "prep_slave_sg: sg(%d) data length is zero\n", i
);
945 if (unlikely(mem
& 3 || len
& 3))
948 desc
->lli
.saddr
= mem
;
949 desc
->lli
.daddr
= reg
;
950 desc
->lli
.ctrla
= ctrla
951 | ATC_SRC_WIDTH(mem_width
)
953 desc
->lli
.ctrlb
= ctrlb
;
956 atc_desc_chain(&first
, &prev
, desc
);
961 reg_width
= convert_buswidth(sconfig
->src_addr_width
);
962 ctrla
|= ATC_SRC_WIDTH(reg_width
);
963 ctrlb
|= ATC_DST_ADDR_MODE_INCR
964 | ATC_SRC_ADDR_MODE_FIXED
966 | ATC_SIF(atchan
->per_if
) | ATC_DIF(atchan
->mem_if
);
968 reg
= sconfig
->src_addr
;
969 for_each_sg(sgl
, sg
, sg_len
, i
) {
970 struct at_desc
*desc
;
974 desc
= atc_desc_get(atchan
);
978 mem
= sg_dma_address(sg
);
979 len
= sg_dma_len(sg
);
980 if (unlikely(!len
)) {
981 dev_dbg(chan2dev(chan
),
982 "prep_slave_sg: sg(%d) data length is zero\n", i
);
986 if (unlikely(mem
& 3 || len
& 3))
989 desc
->lli
.saddr
= reg
;
990 desc
->lli
.daddr
= mem
;
991 desc
->lli
.ctrla
= ctrla
992 | ATC_DST_WIDTH(mem_width
)
994 desc
->lli
.ctrlb
= ctrlb
;
997 atc_desc_chain(&first
, &prev
, desc
);
1005 /* set end-of-link to the last link descriptor of list*/
1008 /* First descriptor of the chain embedds additional information */
1009 first
->txd
.cookie
= -EBUSY
;
1010 first
->total_len
= total_len
;
1012 /* first link descriptor of list is responsible of flags */
1013 first
->txd
.flags
= flags
; /* client is in control of this ack */
1018 dev_err(chan2dev(chan
), "not enough descriptors available\n");
1020 atc_desc_put(atchan
, first
);
1025 * atc_prep_dma_sg - prepare memory to memory scather-gather operation
1026 * @chan: the channel to prepare operation on
1027 * @dst_sg: destination scatterlist
1028 * @dst_nents: number of destination scatterlist entries
1029 * @src_sg: source scatterlist
1030 * @src_nents: number of source scatterlist entries
1031 * @flags: tx descriptor status flags
1033 static struct dma_async_tx_descriptor
*
1034 atc_prep_dma_sg(struct dma_chan
*chan
,
1035 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
1036 struct scatterlist
*src_sg
, unsigned int src_nents
,
1037 unsigned long flags
)
1039 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1040 struct at_desc
*desc
= NULL
;
1041 struct at_desc
*first
= NULL
;
1042 struct at_desc
*prev
= NULL
;
1043 unsigned int src_width
;
1044 unsigned int dst_width
;
1048 size_t dst_len
= 0, src_len
= 0;
1049 dma_addr_t dst
= 0, src
= 0;
1050 size_t len
= 0, total_len
= 0;
1052 if (unlikely(dst_nents
== 0 || src_nents
== 0))
1055 if (unlikely(dst_sg
== NULL
|| src_sg
== NULL
))
1058 ctrlb
= ATC_DEFAULT_CTRLB
| ATC_IEN
1059 | ATC_SRC_ADDR_MODE_INCR
1060 | ATC_DST_ADDR_MODE_INCR
1064 * loop until there is either no more source or no more destination
1069 /* prepare the next transfer */
1072 /* no more destination scatterlist entries */
1073 if (!dst_sg
|| !dst_nents
)
1076 dst
= sg_dma_address(dst_sg
);
1077 dst_len
= sg_dma_len(dst_sg
);
1079 dst_sg
= sg_next(dst_sg
);
1085 /* no more source scatterlist entries */
1086 if (!src_sg
|| !src_nents
)
1089 src
= sg_dma_address(src_sg
);
1090 src_len
= sg_dma_len(src_sg
);
1092 src_sg
= sg_next(src_sg
);
1096 len
= min_t(size_t, src_len
, dst_len
);
1100 /* take care for the alignment */
1101 src_width
= dst_width
= atc_get_xfer_width(src
, dst
, len
);
1103 ctrla
= ATC_SRC_WIDTH(src_width
) |
1104 ATC_DST_WIDTH(dst_width
);
1107 * The number of transfers to set up refer to the source width
1108 * that depends on the alignment.
1110 xfer_count
= len
>> src_width
;
1111 if (xfer_count
> ATC_BTSIZE_MAX
) {
1112 xfer_count
= ATC_BTSIZE_MAX
;
1113 len
= ATC_BTSIZE_MAX
<< src_width
;
1116 /* create the transfer */
1117 desc
= atc_desc_get(atchan
);
1121 desc
->lli
.saddr
= src
;
1122 desc
->lli
.daddr
= dst
;
1123 desc
->lli
.ctrla
= ctrla
| xfer_count
;
1124 desc
->lli
.ctrlb
= ctrlb
;
1126 desc
->txd
.cookie
= 0;
1129 atc_desc_chain(&first
, &prev
, desc
);
1131 /* update the lengths and addresses for the next loop cycle */
1140 /* First descriptor of the chain embedds additional information */
1141 first
->txd
.cookie
= -EBUSY
;
1142 first
->total_len
= total_len
;
1144 /* set end-of-link to the last link descriptor of list*/
1147 first
->txd
.flags
= flags
; /* client is in control of this ack */
1152 atc_desc_put(atchan
, first
);
1157 * atc_dma_cyclic_check_values
1158 * Check for too big/unaligned periods and unaligned DMA buffer
1161 atc_dma_cyclic_check_values(unsigned int reg_width
, dma_addr_t buf_addr
,
1164 if (period_len
> (ATC_BTSIZE_MAX
<< reg_width
))
1166 if (unlikely(period_len
& ((1 << reg_width
) - 1)))
1168 if (unlikely(buf_addr
& ((1 << reg_width
) - 1)))
1178 * atc_dma_cyclic_fill_desc - Fill one period descriptor
1181 atc_dma_cyclic_fill_desc(struct dma_chan
*chan
, struct at_desc
*desc
,
1182 unsigned int period_index
, dma_addr_t buf_addr
,
1183 unsigned int reg_width
, size_t period_len
,
1184 enum dma_transfer_direction direction
)
1186 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1187 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
1190 /* prepare common CRTLA value */
1191 ctrla
= ATC_SCSIZE(sconfig
->src_maxburst
)
1192 | ATC_DCSIZE(sconfig
->dst_maxburst
)
1193 | ATC_DST_WIDTH(reg_width
)
1194 | ATC_SRC_WIDTH(reg_width
)
1195 | period_len
>> reg_width
;
1197 switch (direction
) {
1198 case DMA_MEM_TO_DEV
:
1199 desc
->lli
.saddr
= buf_addr
+ (period_len
* period_index
);
1200 desc
->lli
.daddr
= sconfig
->dst_addr
;
1201 desc
->lli
.ctrla
= ctrla
;
1202 desc
->lli
.ctrlb
= ATC_DST_ADDR_MODE_FIXED
1203 | ATC_SRC_ADDR_MODE_INCR
1205 | ATC_SIF(atchan
->mem_if
)
1206 | ATC_DIF(atchan
->per_if
);
1207 desc
->len
= period_len
;
1210 case DMA_DEV_TO_MEM
:
1211 desc
->lli
.saddr
= sconfig
->src_addr
;
1212 desc
->lli
.daddr
= buf_addr
+ (period_len
* period_index
);
1213 desc
->lli
.ctrla
= ctrla
;
1214 desc
->lli
.ctrlb
= ATC_DST_ADDR_MODE_INCR
1215 | ATC_SRC_ADDR_MODE_FIXED
1217 | ATC_SIF(atchan
->per_if
)
1218 | ATC_DIF(atchan
->mem_if
);
1219 desc
->len
= period_len
;
1230 * atc_prep_dma_cyclic - prepare the cyclic DMA transfer
1231 * @chan: the DMA channel to prepare
1232 * @buf_addr: physical DMA address where the buffer starts
1233 * @buf_len: total number of bytes for the entire buffer
1234 * @period_len: number of bytes for each period
1235 * @direction: transfer direction, to or from device
1236 * @flags: tx descriptor status flags
1238 static struct dma_async_tx_descriptor
*
1239 atc_prep_dma_cyclic(struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
1240 size_t period_len
, enum dma_transfer_direction direction
,
1241 unsigned long flags
)
1243 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1244 struct at_dma_slave
*atslave
= chan
->private;
1245 struct dma_slave_config
*sconfig
= &atchan
->dma_sconfig
;
1246 struct at_desc
*first
= NULL
;
1247 struct at_desc
*prev
= NULL
;
1248 unsigned long was_cyclic
;
1249 unsigned int reg_width
;
1250 unsigned int periods
= buf_len
/ period_len
;
1253 dev_vdbg(chan2dev(chan
), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
1254 direction
== DMA_MEM_TO_DEV
? "TO DEVICE" : "FROM DEVICE",
1256 periods
, buf_len
, period_len
);
1258 if (unlikely(!atslave
|| !buf_len
|| !period_len
)) {
1259 dev_dbg(chan2dev(chan
), "prep_dma_cyclic: length is zero!\n");
1263 was_cyclic
= test_and_set_bit(ATC_IS_CYCLIC
, &atchan
->status
);
1265 dev_dbg(chan2dev(chan
), "prep_dma_cyclic: channel in use!\n");
1269 if (unlikely(!is_slave_direction(direction
)))
1272 if (sconfig
->direction
== DMA_MEM_TO_DEV
)
1273 reg_width
= convert_buswidth(sconfig
->dst_addr_width
);
1275 reg_width
= convert_buswidth(sconfig
->src_addr_width
);
1277 /* Check for too big/unaligned periods and unaligned DMA buffer */
1278 if (atc_dma_cyclic_check_values(reg_width
, buf_addr
, period_len
))
1281 /* build cyclic linked list */
1282 for (i
= 0; i
< periods
; i
++) {
1283 struct at_desc
*desc
;
1285 desc
= atc_desc_get(atchan
);
1289 if (atc_dma_cyclic_fill_desc(chan
, desc
, i
, buf_addr
,
1290 reg_width
, period_len
, direction
))
1293 atc_desc_chain(&first
, &prev
, desc
);
1296 /* lets make a cyclic list */
1297 prev
->lli
.dscr
= first
->txd
.phys
;
1299 /* First descriptor of the chain embedds additional information */
1300 first
->txd
.cookie
= -EBUSY
;
1301 first
->total_len
= buf_len
;
1306 dev_err(chan2dev(chan
), "not enough descriptors available\n");
1307 atc_desc_put(atchan
, first
);
1309 clear_bit(ATC_IS_CYCLIC
, &atchan
->status
);
1313 static int atc_config(struct dma_chan
*chan
,
1314 struct dma_slave_config
*sconfig
)
1316 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1318 dev_vdbg(chan2dev(chan
), "%s\n", __func__
);
1320 /* Check if it is chan is configured for slave transfers */
1324 memcpy(&atchan
->dma_sconfig
, sconfig
, sizeof(*sconfig
));
1326 convert_burst(&atchan
->dma_sconfig
.src_maxburst
);
1327 convert_burst(&atchan
->dma_sconfig
.dst_maxburst
);
1332 static int atc_pause(struct dma_chan
*chan
)
1334 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1335 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1336 int chan_id
= atchan
->chan_common
.chan_id
;
1337 unsigned long flags
;
1341 dev_vdbg(chan2dev(chan
), "%s\n", __func__
);
1343 spin_lock_irqsave(&atchan
->lock
, flags
);
1345 dma_writel(atdma
, CHER
, AT_DMA_SUSP(chan_id
));
1346 set_bit(ATC_IS_PAUSED
, &atchan
->status
);
1348 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1353 static int atc_resume(struct dma_chan
*chan
)
1355 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1356 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1357 int chan_id
= atchan
->chan_common
.chan_id
;
1358 unsigned long flags
;
1362 dev_vdbg(chan2dev(chan
), "%s\n", __func__
);
1364 if (!atc_chan_is_paused(atchan
))
1367 spin_lock_irqsave(&atchan
->lock
, flags
);
1369 dma_writel(atdma
, CHDR
, AT_DMA_RES(chan_id
));
1370 clear_bit(ATC_IS_PAUSED
, &atchan
->status
);
1372 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1377 static int atc_terminate_all(struct dma_chan
*chan
)
1379 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1380 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1381 int chan_id
= atchan
->chan_common
.chan_id
;
1382 struct at_desc
*desc
, *_desc
;
1383 unsigned long flags
;
1387 dev_vdbg(chan2dev(chan
), "%s\n", __func__
);
1390 * This is only called when something went wrong elsewhere, so
1391 * we don't really care about the data. Just disable the
1392 * channel. We still have to poll the channel enable bit due
1393 * to AHB/HSB limitations.
1395 spin_lock_irqsave(&atchan
->lock
, flags
);
1397 /* disabling channel: must also remove suspend state */
1398 dma_writel(atdma
, CHDR
, AT_DMA_RES(chan_id
) | atchan
->mask
);
1400 /* confirm that this channel is disabled */
1401 while (dma_readl(atdma
, CHSR
) & atchan
->mask
)
1404 /* active_list entries will end up before queued entries */
1405 list_splice_init(&atchan
->queue
, &list
);
1406 list_splice_init(&atchan
->active_list
, &list
);
1408 /* Flush all pending and queued descriptors */
1409 list_for_each_entry_safe(desc
, _desc
, &list
, desc_node
)
1410 atc_chain_complete(atchan
, desc
);
1412 clear_bit(ATC_IS_PAUSED
, &atchan
->status
);
1413 /* if channel dedicated to cyclic operations, free it */
1414 clear_bit(ATC_IS_CYCLIC
, &atchan
->status
);
1416 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1422 * atc_tx_status - poll for transaction completion
1423 * @chan: DMA channel
1424 * @cookie: transaction identifier to check status of
1425 * @txstate: if not %NULL updated with transaction state
1427 * If @txstate is passed in, upon return it reflect the driver
1428 * internal state and can be used with dma_async_is_complete() to check
1429 * the status of multiple cookies without re-checking hardware state.
1431 static enum dma_status
1432 atc_tx_status(struct dma_chan
*chan
,
1433 dma_cookie_t cookie
,
1434 struct dma_tx_state
*txstate
)
1436 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1437 unsigned long flags
;
1438 enum dma_status ret
;
1441 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1442 if (ret
== DMA_COMPLETE
)
1445 * There's no point calculating the residue if there's
1446 * no txstate to store the value.
1451 spin_lock_irqsave(&atchan
->lock
, flags
);
1453 /* Get number of bytes left in the active transactions */
1454 bytes
= atc_get_bytes_left(chan
, cookie
);
1456 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1458 if (unlikely(bytes
< 0)) {
1459 dev_vdbg(chan2dev(chan
), "get residual bytes error\n");
1462 dma_set_residue(txstate
, bytes
);
1465 dev_vdbg(chan2dev(chan
), "tx_status %d: cookie = %d residue = %d\n",
1466 ret
, cookie
, bytes
);
1472 * atc_issue_pending - try to finish work
1473 * @chan: target DMA channel
1475 static void atc_issue_pending(struct dma_chan
*chan
)
1477 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1478 unsigned long flags
;
1480 dev_vdbg(chan2dev(chan
), "issue_pending\n");
1482 /* Not needed for cyclic transfers */
1483 if (atc_chan_is_cyclic(atchan
))
1486 spin_lock_irqsave(&atchan
->lock
, flags
);
1487 atc_advance_work(atchan
);
1488 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1492 * atc_alloc_chan_resources - allocate resources for DMA channel
1493 * @chan: allocate descriptor resources for this channel
1494 * @client: current client requesting the channel be ready for requests
1496 * return - the number of allocated descriptors
1498 static int atc_alloc_chan_resources(struct dma_chan
*chan
)
1500 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1501 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1502 struct at_desc
*desc
;
1503 struct at_dma_slave
*atslave
;
1504 unsigned long flags
;
1507 LIST_HEAD(tmp_list
);
1509 dev_vdbg(chan2dev(chan
), "alloc_chan_resources\n");
1511 /* ASSERT: channel is idle */
1512 if (atc_chan_is_enabled(atchan
)) {
1513 dev_dbg(chan2dev(chan
), "DMA channel not idle ?\n");
1517 cfg
= ATC_DEFAULT_CFG
;
1519 atslave
= chan
->private;
1522 * We need controller-specific data to set up slave
1525 BUG_ON(!atslave
->dma_dev
|| atslave
->dma_dev
!= atdma
->dma_common
.dev
);
1527 /* if cfg configuration specified take it instead of default */
1532 /* have we already been set up?
1533 * reconfigure channel but no need to reallocate descriptors */
1534 if (!list_empty(&atchan
->free_list
))
1535 return atchan
->descs_allocated
;
1537 /* Allocate initial pool of descriptors */
1538 for (i
= 0; i
< init_nr_desc_per_channel
; i
++) {
1539 desc
= atc_alloc_descriptor(chan
, GFP_KERNEL
);
1541 dev_err(atdma
->dma_common
.dev
,
1542 "Only %d initial descriptors\n", i
);
1545 list_add_tail(&desc
->desc_node
, &tmp_list
);
1548 spin_lock_irqsave(&atchan
->lock
, flags
);
1549 atchan
->descs_allocated
= i
;
1550 list_splice(&tmp_list
, &atchan
->free_list
);
1551 dma_cookie_init(chan
);
1552 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1554 /* channel parameters */
1555 channel_writel(atchan
, CFG
, cfg
);
1557 dev_dbg(chan2dev(chan
),
1558 "alloc_chan_resources: allocated %d descriptors\n",
1559 atchan
->descs_allocated
);
1561 return atchan
->descs_allocated
;
1565 * atc_free_chan_resources - free all channel resources
1566 * @chan: DMA channel
1568 static void atc_free_chan_resources(struct dma_chan
*chan
)
1570 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1571 struct at_dma
*atdma
= to_at_dma(chan
->device
);
1572 struct at_desc
*desc
, *_desc
;
1575 dev_dbg(chan2dev(chan
), "free_chan_resources: (descs allocated=%u)\n",
1576 atchan
->descs_allocated
);
1578 /* ASSERT: channel is idle */
1579 BUG_ON(!list_empty(&atchan
->active_list
));
1580 BUG_ON(!list_empty(&atchan
->queue
));
1581 BUG_ON(atc_chan_is_enabled(atchan
));
1583 list_for_each_entry_safe(desc
, _desc
, &atchan
->free_list
, desc_node
) {
1584 dev_vdbg(chan2dev(chan
), " freeing descriptor %p\n", desc
);
1585 list_del(&desc
->desc_node
);
1586 /* free link descriptor */
1587 dma_pool_free(atdma
->dma_desc_pool
, desc
, desc
->txd
.phys
);
1589 list_splice_init(&atchan
->free_list
, &list
);
1590 atchan
->descs_allocated
= 0;
1593 dev_vdbg(chan2dev(chan
), "free_chan_resources: done\n");
1597 static bool at_dma_filter(struct dma_chan
*chan
, void *slave
)
1599 struct at_dma_slave
*atslave
= slave
;
1601 if (atslave
->dma_dev
== chan
->device
->dev
) {
1602 chan
->private = atslave
;
1609 static struct dma_chan
*at_dma_xlate(struct of_phandle_args
*dma_spec
,
1610 struct of_dma
*of_dma
)
1612 struct dma_chan
*chan
;
1613 struct at_dma_chan
*atchan
;
1614 struct at_dma_slave
*atslave
;
1615 dma_cap_mask_t mask
;
1616 unsigned int per_id
;
1617 struct platform_device
*dmac_pdev
;
1619 if (dma_spec
->args_count
!= 2)
1622 dmac_pdev
= of_find_device_by_node(dma_spec
->np
);
1625 dma_cap_set(DMA_SLAVE
, mask
);
1627 atslave
= devm_kzalloc(&dmac_pdev
->dev
, sizeof(*atslave
), GFP_KERNEL
);
1631 atslave
->cfg
= ATC_DST_H2SEL_HW
| ATC_SRC_H2SEL_HW
;
1633 * We can fill both SRC_PER and DST_PER, one of these fields will be
1634 * ignored depending on DMA transfer direction.
1636 per_id
= dma_spec
->args
[1] & AT91_DMA_CFG_PER_ID_MASK
;
1637 atslave
->cfg
|= ATC_DST_PER_MSB(per_id
) | ATC_DST_PER(per_id
)
1638 | ATC_SRC_PER_MSB(per_id
) | ATC_SRC_PER(per_id
);
1640 * We have to translate the value we get from the device tree since
1641 * the half FIFO configuration value had to be 0 to keep backward
1644 switch (dma_spec
->args
[1] & AT91_DMA_CFG_FIFOCFG_MASK
) {
1645 case AT91_DMA_CFG_FIFOCFG_ALAP
:
1646 atslave
->cfg
|= ATC_FIFOCFG_LARGESTBURST
;
1648 case AT91_DMA_CFG_FIFOCFG_ASAP
:
1649 atslave
->cfg
|= ATC_FIFOCFG_ENOUGHSPACE
;
1651 case AT91_DMA_CFG_FIFOCFG_HALF
:
1653 atslave
->cfg
|= ATC_FIFOCFG_HALFFIFO
;
1655 atslave
->dma_dev
= &dmac_pdev
->dev
;
1657 chan
= dma_request_channel(mask
, at_dma_filter
, atslave
);
1661 atchan
= to_at_dma_chan(chan
);
1662 atchan
->per_if
= dma_spec
->args
[0] & 0xff;
1663 atchan
->mem_if
= (dma_spec
->args
[0] >> 16) & 0xff;
1668 static struct dma_chan
*at_dma_xlate(struct of_phandle_args
*dma_spec
,
1669 struct of_dma
*of_dma
)
1675 /*-- Module Management -----------------------------------------------*/
1677 /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
1678 static struct at_dma_platform_data at91sam9rl_config
= {
1681 static struct at_dma_platform_data at91sam9g45_config
= {
1685 #if defined(CONFIG_OF)
1686 static const struct of_device_id atmel_dma_dt_ids
[] = {
1688 .compatible
= "atmel,at91sam9rl-dma",
1689 .data
= &at91sam9rl_config
,
1691 .compatible
= "atmel,at91sam9g45-dma",
1692 .data
= &at91sam9g45_config
,
1698 MODULE_DEVICE_TABLE(of
, atmel_dma_dt_ids
);
1701 static const struct platform_device_id atdma_devtypes
[] = {
1703 .name
= "at91sam9rl_dma",
1704 .driver_data
= (unsigned long) &at91sam9rl_config
,
1706 .name
= "at91sam9g45_dma",
1707 .driver_data
= (unsigned long) &at91sam9g45_config
,
1713 static inline const struct at_dma_platform_data
* __init
at_dma_get_driver_data(
1714 struct platform_device
*pdev
)
1716 if (pdev
->dev
.of_node
) {
1717 const struct of_device_id
*match
;
1718 match
= of_match_node(atmel_dma_dt_ids
, pdev
->dev
.of_node
);
1723 return (struct at_dma_platform_data
*)
1724 platform_get_device_id(pdev
)->driver_data
;
1728 * at_dma_off - disable DMA controller
1729 * @atdma: the Atmel HDAMC device
1731 static void at_dma_off(struct at_dma
*atdma
)
1733 dma_writel(atdma
, EN
, 0);
1735 /* disable all interrupts */
1736 dma_writel(atdma
, EBCIDR
, -1L);
1738 /* confirm that all channels are disabled */
1739 while (dma_readl(atdma
, CHSR
) & atdma
->all_chan_mask
)
1743 static int __init
at_dma_probe(struct platform_device
*pdev
)
1745 struct resource
*io
;
1746 struct at_dma
*atdma
;
1751 const struct at_dma_platform_data
*plat_dat
;
1753 /* setup platform data for each SoC */
1754 dma_cap_set(DMA_MEMCPY
, at91sam9rl_config
.cap_mask
);
1755 dma_cap_set(DMA_SG
, at91sam9rl_config
.cap_mask
);
1756 dma_cap_set(DMA_INTERLEAVE
, at91sam9g45_config
.cap_mask
);
1757 dma_cap_set(DMA_MEMCPY
, at91sam9g45_config
.cap_mask
);
1758 dma_cap_set(DMA_SLAVE
, at91sam9g45_config
.cap_mask
);
1759 dma_cap_set(DMA_SG
, at91sam9g45_config
.cap_mask
);
1761 /* get DMA parameters from controller type */
1762 plat_dat
= at_dma_get_driver_data(pdev
);
1766 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1770 irq
= platform_get_irq(pdev
, 0);
1774 size
= sizeof(struct at_dma
);
1775 size
+= plat_dat
->nr_channels
* sizeof(struct at_dma_chan
);
1776 atdma
= kzalloc(size
, GFP_KERNEL
);
1780 /* discover transaction capabilities */
1781 atdma
->dma_common
.cap_mask
= plat_dat
->cap_mask
;
1782 atdma
->all_chan_mask
= (1 << plat_dat
->nr_channels
) - 1;
1784 size
= resource_size(io
);
1785 if (!request_mem_region(io
->start
, size
, pdev
->dev
.driver
->name
)) {
1790 atdma
->regs
= ioremap(io
->start
, size
);
1796 atdma
->clk
= clk_get(&pdev
->dev
, "dma_clk");
1797 if (IS_ERR(atdma
->clk
)) {
1798 err
= PTR_ERR(atdma
->clk
);
1801 err
= clk_prepare_enable(atdma
->clk
);
1803 goto err_clk_prepare
;
1805 /* force dma off, just in case */
1808 err
= request_irq(irq
, at_dma_interrupt
, 0, "at_hdmac", atdma
);
1812 platform_set_drvdata(pdev
, atdma
);
1814 /* create a pool of consistent memory blocks for hardware descriptors */
1815 atdma
->dma_desc_pool
= dma_pool_create("at_hdmac_desc_pool",
1816 &pdev
->dev
, sizeof(struct at_desc
),
1817 4 /* word alignment */, 0);
1818 if (!atdma
->dma_desc_pool
) {
1819 dev_err(&pdev
->dev
, "No memory for descriptors dma pool\n");
1821 goto err_pool_create
;
1824 /* clear any pending interrupt */
1825 while (dma_readl(atdma
, EBCISR
))
1828 /* initialize channels related values */
1829 INIT_LIST_HEAD(&atdma
->dma_common
.channels
);
1830 for (i
= 0; i
< plat_dat
->nr_channels
; i
++) {
1831 struct at_dma_chan
*atchan
= &atdma
->chan
[i
];
1833 atchan
->mem_if
= AT_DMA_MEM_IF
;
1834 atchan
->per_if
= AT_DMA_PER_IF
;
1835 atchan
->chan_common
.device
= &atdma
->dma_common
;
1836 dma_cookie_init(&atchan
->chan_common
);
1837 list_add_tail(&atchan
->chan_common
.device_node
,
1838 &atdma
->dma_common
.channels
);
1840 atchan
->ch_regs
= atdma
->regs
+ ch_regs(i
);
1841 spin_lock_init(&atchan
->lock
);
1842 atchan
->mask
= 1 << i
;
1844 INIT_LIST_HEAD(&atchan
->active_list
);
1845 INIT_LIST_HEAD(&atchan
->queue
);
1846 INIT_LIST_HEAD(&atchan
->free_list
);
1848 tasklet_init(&atchan
->tasklet
, atc_tasklet
,
1849 (unsigned long)atchan
);
1850 atc_enable_chan_irq(atdma
, i
);
1853 /* set base routines */
1854 atdma
->dma_common
.device_alloc_chan_resources
= atc_alloc_chan_resources
;
1855 atdma
->dma_common
.device_free_chan_resources
= atc_free_chan_resources
;
1856 atdma
->dma_common
.device_tx_status
= atc_tx_status
;
1857 atdma
->dma_common
.device_issue_pending
= atc_issue_pending
;
1858 atdma
->dma_common
.dev
= &pdev
->dev
;
1860 /* set prep routines based on capability */
1861 if (dma_has_cap(DMA_INTERLEAVE
, atdma
->dma_common
.cap_mask
))
1862 atdma
->dma_common
.device_prep_interleaved_dma
= atc_prep_dma_interleaved
;
1864 if (dma_has_cap(DMA_MEMCPY
, atdma
->dma_common
.cap_mask
))
1865 atdma
->dma_common
.device_prep_dma_memcpy
= atc_prep_dma_memcpy
;
1867 if (dma_has_cap(DMA_SLAVE
, atdma
->dma_common
.cap_mask
)) {
1868 atdma
->dma_common
.device_prep_slave_sg
= atc_prep_slave_sg
;
1869 /* controller can do slave DMA: can trigger cyclic transfers */
1870 dma_cap_set(DMA_CYCLIC
, atdma
->dma_common
.cap_mask
);
1871 atdma
->dma_common
.device_prep_dma_cyclic
= atc_prep_dma_cyclic
;
1872 atdma
->dma_common
.device_config
= atc_config
;
1873 atdma
->dma_common
.device_pause
= atc_pause
;
1874 atdma
->dma_common
.device_resume
= atc_resume
;
1875 atdma
->dma_common
.device_terminate_all
= atc_terminate_all
;
1876 atdma
->dma_common
.src_addr_widths
= ATC_DMA_BUSWIDTHS
;
1877 atdma
->dma_common
.dst_addr_widths
= ATC_DMA_BUSWIDTHS
;
1878 atdma
->dma_common
.directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
1879 atdma
->dma_common
.residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
1882 if (dma_has_cap(DMA_SG
, atdma
->dma_common
.cap_mask
))
1883 atdma
->dma_common
.device_prep_dma_sg
= atc_prep_dma_sg
;
1885 dma_writel(atdma
, EN
, AT_DMA_ENABLE
);
1887 dev_info(&pdev
->dev
, "Atmel AHB DMA Controller ( %s%s%s), %d channels\n",
1888 dma_has_cap(DMA_MEMCPY
, atdma
->dma_common
.cap_mask
) ? "cpy " : "",
1889 dma_has_cap(DMA_SLAVE
, atdma
->dma_common
.cap_mask
) ? "slave " : "",
1890 dma_has_cap(DMA_SG
, atdma
->dma_common
.cap_mask
) ? "sg-cpy " : "",
1891 plat_dat
->nr_channels
);
1893 dma_async_device_register(&atdma
->dma_common
);
1896 * Do not return an error if the dmac node is not present in order to
1897 * not break the existing way of requesting channel with
1898 * dma_request_channel().
1900 if (pdev
->dev
.of_node
) {
1901 err
= of_dma_controller_register(pdev
->dev
.of_node
,
1902 at_dma_xlate
, atdma
);
1904 dev_err(&pdev
->dev
, "could not register of_dma_controller\n");
1905 goto err_of_dma_controller_register
;
1911 err_of_dma_controller_register
:
1912 dma_async_device_unregister(&atdma
->dma_common
);
1913 dma_pool_destroy(atdma
->dma_desc_pool
);
1915 free_irq(platform_get_irq(pdev
, 0), atdma
);
1917 clk_disable_unprepare(atdma
->clk
);
1919 clk_put(atdma
->clk
);
1921 iounmap(atdma
->regs
);
1924 release_mem_region(io
->start
, size
);
1930 static int at_dma_remove(struct platform_device
*pdev
)
1932 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1933 struct dma_chan
*chan
, *_chan
;
1934 struct resource
*io
;
1937 dma_async_device_unregister(&atdma
->dma_common
);
1939 dma_pool_destroy(atdma
->dma_desc_pool
);
1940 free_irq(platform_get_irq(pdev
, 0), atdma
);
1942 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
1944 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1946 /* Disable interrupts */
1947 atc_disable_chan_irq(atdma
, chan
->chan_id
);
1949 tasklet_kill(&atchan
->tasklet
);
1950 list_del(&chan
->device_node
);
1953 clk_disable_unprepare(atdma
->clk
);
1954 clk_put(atdma
->clk
);
1956 iounmap(atdma
->regs
);
1959 io
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1960 release_mem_region(io
->start
, resource_size(io
));
1967 static void at_dma_shutdown(struct platform_device
*pdev
)
1969 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1971 at_dma_off(platform_get_drvdata(pdev
));
1972 clk_disable_unprepare(atdma
->clk
);
1975 static int at_dma_prepare(struct device
*dev
)
1977 struct platform_device
*pdev
= to_platform_device(dev
);
1978 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
1979 struct dma_chan
*chan
, *_chan
;
1981 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
1983 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
1984 /* wait for transaction completion (except in cyclic case) */
1985 if (atc_chan_is_enabled(atchan
) && !atc_chan_is_cyclic(atchan
))
1991 static void atc_suspend_cyclic(struct at_dma_chan
*atchan
)
1993 struct dma_chan
*chan
= &atchan
->chan_common
;
1995 /* Channel should be paused by user
1996 * do it anyway even if it is not done already */
1997 if (!atc_chan_is_paused(atchan
)) {
1998 dev_warn(chan2dev(chan
),
1999 "cyclic channel not paused, should be done by channel user\n");
2003 /* now preserve additional data for cyclic operations */
2004 /* next descriptor address in the cyclic list */
2005 atchan
->save_dscr
= channel_readl(atchan
, DSCR
);
2007 vdbg_dump_regs(atchan
);
2010 static int at_dma_suspend_noirq(struct device
*dev
)
2012 struct platform_device
*pdev
= to_platform_device(dev
);
2013 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
2014 struct dma_chan
*chan
, *_chan
;
2017 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
2019 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
2021 if (atc_chan_is_cyclic(atchan
))
2022 atc_suspend_cyclic(atchan
);
2023 atchan
->save_cfg
= channel_readl(atchan
, CFG
);
2025 atdma
->save_imr
= dma_readl(atdma
, EBCIMR
);
2027 /* disable DMA controller */
2029 clk_disable_unprepare(atdma
->clk
);
2033 static void atc_resume_cyclic(struct at_dma_chan
*atchan
)
2035 struct at_dma
*atdma
= to_at_dma(atchan
->chan_common
.device
);
2037 /* restore channel status for cyclic descriptors list:
2038 * next descriptor in the cyclic list at the time of suspend */
2039 channel_writel(atchan
, SADDR
, 0);
2040 channel_writel(atchan
, DADDR
, 0);
2041 channel_writel(atchan
, CTRLA
, 0);
2042 channel_writel(atchan
, CTRLB
, 0);
2043 channel_writel(atchan
, DSCR
, atchan
->save_dscr
);
2044 dma_writel(atdma
, CHER
, atchan
->mask
);
2046 /* channel pause status should be removed by channel user
2047 * We cannot take the initiative to do it here */
2049 vdbg_dump_regs(atchan
);
2052 static int at_dma_resume_noirq(struct device
*dev
)
2054 struct platform_device
*pdev
= to_platform_device(dev
);
2055 struct at_dma
*atdma
= platform_get_drvdata(pdev
);
2056 struct dma_chan
*chan
, *_chan
;
2058 /* bring back DMA controller */
2059 clk_prepare_enable(atdma
->clk
);
2060 dma_writel(atdma
, EN
, AT_DMA_ENABLE
);
2062 /* clear any pending interrupt */
2063 while (dma_readl(atdma
, EBCISR
))
2066 /* restore saved data */
2067 dma_writel(atdma
, EBCIER
, atdma
->save_imr
);
2068 list_for_each_entry_safe(chan
, _chan
, &atdma
->dma_common
.channels
,
2070 struct at_dma_chan
*atchan
= to_at_dma_chan(chan
);
2072 channel_writel(atchan
, CFG
, atchan
->save_cfg
);
2073 if (atc_chan_is_cyclic(atchan
))
2074 atc_resume_cyclic(atchan
);
2079 static const struct dev_pm_ops at_dma_dev_pm_ops
= {
2080 .prepare
= at_dma_prepare
,
2081 .suspend_noirq
= at_dma_suspend_noirq
,
2082 .resume_noirq
= at_dma_resume_noirq
,
2085 static struct platform_driver at_dma_driver
= {
2086 .remove
= at_dma_remove
,
2087 .shutdown
= at_dma_shutdown
,
2088 .id_table
= atdma_devtypes
,
2091 .pm
= &at_dma_dev_pm_ops
,
2092 .of_match_table
= of_match_ptr(atmel_dma_dt_ids
),
2096 static int __init
at_dma_init(void)
2098 return platform_driver_probe(&at_dma_driver
, at_dma_probe
);
2100 subsys_initcall(at_dma_init
);
2102 static void __exit
at_dma_exit(void)
2104 platform_driver_unregister(&at_dma_driver
);
2106 module_exit(at_dma_exit
);
2108 MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
2109 MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
2110 MODULE_LICENSE("GPL");
2111 MODULE_ALIAS("platform:at_hdmac");