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FIRMWARE: bcm47xx_nvram: Fix module license.
[deliverable/linux.git] / drivers / dma / at_xdmac.c
1 /*
2 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
3 *
4 * Copyright (C) 2014 Atmel Corporation
5 *
6 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <asm/barrier.h>
22 #include <dt-bindings/dma/at91.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dmapool.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/kernel.h>
29 #include <linux/list.h>
30 #include <linux/module.h>
31 #include <linux/of_dma.h>
32 #include <linux/of_platform.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm.h>
35
36 #include "dmaengine.h"
37
38 /* Global registers */
39 #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
40 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
41 #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
42 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
43 #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
44 #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
45 #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
46 #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
47 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
48 #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
49 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
50 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
51 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
52 #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
53 #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
54 #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
55 #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
56 #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
57 #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
58 #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
59 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
60
61 /* Channel relative registers offsets */
62 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
63 #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
64 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
65 #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
66 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
67 #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
68 #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
69 #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
70 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
71 #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
72 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
73 #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
74 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
75 #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
76 #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
77 #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
78 #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
79 #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
80 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
81 #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
82 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
83 #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
84 #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
85 #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
86 #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
87 #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
88 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
89 #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
90 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
91 #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
92 #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
93 #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
94 #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
95 #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
96 #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
97 #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
98 #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
99 #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
100 #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
101 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
102 #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
103 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
104 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
106 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
107 #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
108 #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
109 #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
110 #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
111 #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
112 #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
113 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
114 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
115 #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
116 #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
117 #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
118 #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
119 #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
120 #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
121 #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
122 #define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
123 #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
124 #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
125 #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
126 #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
127 #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
128 #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
129 #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
130 #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
131 #define AT_XDMAC_CC_DWIDTH_OFFSET 11
132 #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
133 #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
134 #define AT_XDMAC_CC_DWIDTH_BYTE 0x0
135 #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
136 #define AT_XDMAC_CC_DWIDTH_WORD 0x2
137 #define AT_XDMAC_CC_DWIDTH_DWORD 0x3
138 #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
139 #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
140 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
141 #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
142 #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
143 #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
144 #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
145 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
146 #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
147 #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
148 #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
149 #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
150 #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
151 #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
152 #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
153 #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
154 #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
155 #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
156 #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
157 #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
158 #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
159 #define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */
160 #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
161 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
162 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
163
164 #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
165
166 /* Microblock control members */
167 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
168 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
169 #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
170 #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
171 #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
172 #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
173 #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
174 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
175
176 #define AT_XDMAC_MAX_CHAN 0x20
177 #define AT_XDMAC_MAX_CSIZE 16 /* 16 data */
178 #define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */
179
180 #define AT_XDMAC_DMA_BUSWIDTHS\
181 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
182 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
183 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
184 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
185 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
186
187 enum atc_status {
188 AT_XDMAC_CHAN_IS_CYCLIC = 0,
189 AT_XDMAC_CHAN_IS_PAUSED,
190 };
191
192 /* ----- Channels ----- */
193 struct at_xdmac_chan {
194 struct dma_chan chan;
195 void __iomem *ch_regs;
196 u32 mask; /* Channel Mask */
197 u32 cfg; /* Channel Configuration Register */
198 u8 perid; /* Peripheral ID */
199 u8 perif; /* Peripheral Interface */
200 u8 memif; /* Memory Interface */
201 u32 save_cc;
202 u32 save_cim;
203 u32 save_cnda;
204 u32 save_cndc;
205 unsigned long status;
206 struct tasklet_struct tasklet;
207 struct dma_slave_config sconfig;
208
209 spinlock_t lock;
210
211 struct list_head xfers_list;
212 struct list_head free_descs_list;
213 };
214
215
216 /* ----- Controller ----- */
217 struct at_xdmac {
218 struct dma_device dma;
219 void __iomem *regs;
220 int irq;
221 struct clk *clk;
222 u32 save_gim;
223 u32 save_gs;
224 struct dma_pool *at_xdmac_desc_pool;
225 struct at_xdmac_chan chan[0];
226 };
227
228
229 /* ----- Descriptors ----- */
230
231 /* Linked List Descriptor */
232 struct at_xdmac_lld {
233 dma_addr_t mbr_nda; /* Next Descriptor Member */
234 u32 mbr_ubc; /* Microblock Control Member */
235 dma_addr_t mbr_sa; /* Source Address Member */
236 dma_addr_t mbr_da; /* Destination Address Member */
237 u32 mbr_cfg; /* Configuration Register */
238 u32 mbr_bc; /* Block Control Register */
239 u32 mbr_ds; /* Data Stride Register */
240 u32 mbr_sus; /* Source Microblock Stride Register */
241 u32 mbr_dus; /* Destination Microblock Stride Register */
242 };
243
244
245 struct at_xdmac_desc {
246 struct at_xdmac_lld lld;
247 enum dma_transfer_direction direction;
248 struct dma_async_tx_descriptor tx_dma_desc;
249 struct list_head desc_node;
250 /* Following members are only used by the first descriptor */
251 bool active_xfer;
252 unsigned int xfer_size;
253 struct list_head descs_list;
254 struct list_head xfer_node;
255 };
256
257 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
258 {
259 return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
260 }
261
262 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
263 #define at_xdmac_write(atxdmac, reg, value) \
264 writel_relaxed((value), (atxdmac)->regs + (reg))
265
266 #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
267 #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
268
269 static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
270 {
271 return container_of(dchan, struct at_xdmac_chan, chan);
272 }
273
274 static struct device *chan2dev(struct dma_chan *chan)
275 {
276 return &chan->dev->device;
277 }
278
279 static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
280 {
281 return container_of(ddev, struct at_xdmac, dma);
282 }
283
284 static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
285 {
286 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
287 }
288
289 static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
290 {
291 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
292 }
293
294 static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
295 {
296 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
297 }
298
299 static inline int at_xdmac_csize(u32 maxburst)
300 {
301 int csize;
302
303 csize = ffs(maxburst) - 1;
304 if (csize > 4)
305 csize = -EINVAL;
306
307 return csize;
308 };
309
310 static inline u8 at_xdmac_get_dwidth(u32 cfg)
311 {
312 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
313 };
314
315 static unsigned int init_nr_desc_per_channel = 64;
316 module_param(init_nr_desc_per_channel, uint, 0644);
317 MODULE_PARM_DESC(init_nr_desc_per_channel,
318 "initial descriptors per channel (default: 64)");
319
320
321 static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
322 {
323 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
324 }
325
326 static void at_xdmac_off(struct at_xdmac *atxdmac)
327 {
328 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
329
330 /* Wait that all chans are disabled. */
331 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
332 cpu_relax();
333
334 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
335 }
336
337 /* Call with lock hold. */
338 static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
339 struct at_xdmac_desc *first)
340 {
341 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
342 u32 reg;
343
344 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
345
346 if (at_xdmac_chan_is_enabled(atchan))
347 return;
348
349 /* Set transfer as active to not try to start it again. */
350 first->active_xfer = true;
351
352 /* Tell xdmac where to get the first descriptor. */
353 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
354 | AT_XDMAC_CNDA_NDAIF(atchan->memif);
355 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
356
357 /*
358 * When doing non cyclic transfer we need to use the next
359 * descriptor view 2 since some fields of the configuration register
360 * depend on transfer size and src/dest addresses.
361 */
362 if (at_xdmac_chan_is_cyclic(atchan))
363 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
364 else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3)
365 reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
366 else
367 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
368 /*
369 * Even if the register will be updated from the configuration in the
370 * descriptor when using view 2 or higher, the PROT bit won't be set
371 * properly. This bit can be modified only by using the channel
372 * configuration register.
373 */
374 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
375
376 reg |= AT_XDMAC_CNDC_NDDUP
377 | AT_XDMAC_CNDC_NDSUP
378 | AT_XDMAC_CNDC_NDE;
379 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
380
381 dev_vdbg(chan2dev(&atchan->chan),
382 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
383 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
384 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
385 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
386 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
387 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
388 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
389
390 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
391 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE;
392 /*
393 * There is no end of list when doing cyclic dma, we need to get
394 * an interrupt after each periods.
395 */
396 if (at_xdmac_chan_is_cyclic(atchan))
397 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
398 reg | AT_XDMAC_CIE_BIE);
399 else
400 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
401 reg | AT_XDMAC_CIE_LIE);
402 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
403 dev_vdbg(chan2dev(&atchan->chan),
404 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
405 wmb();
406 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
407
408 dev_vdbg(chan2dev(&atchan->chan),
409 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
410 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
411 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
412 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
413 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
414 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
415 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
416
417 }
418
419 static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
420 {
421 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
422 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
423 dma_cookie_t cookie;
424 unsigned long irqflags;
425
426 spin_lock_irqsave(&atchan->lock, irqflags);
427 cookie = dma_cookie_assign(tx);
428
429 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
430 __func__, atchan, desc);
431 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
432 if (list_is_singular(&atchan->xfers_list))
433 at_xdmac_start_xfer(atchan, desc);
434
435 spin_unlock_irqrestore(&atchan->lock, irqflags);
436 return cookie;
437 }
438
439 static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
440 gfp_t gfp_flags)
441 {
442 struct at_xdmac_desc *desc;
443 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
444 dma_addr_t phys;
445
446 desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
447 if (desc) {
448 memset(desc, 0, sizeof(*desc));
449 INIT_LIST_HEAD(&desc->descs_list);
450 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
451 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
452 desc->tx_dma_desc.phys = phys;
453 }
454
455 return desc;
456 }
457
458 /* Call must be protected by lock. */
459 static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
460 {
461 struct at_xdmac_desc *desc;
462
463 if (list_empty(&atchan->free_descs_list)) {
464 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
465 } else {
466 desc = list_first_entry(&atchan->free_descs_list,
467 struct at_xdmac_desc, desc_node);
468 list_del(&desc->desc_node);
469 desc->active_xfer = false;
470 }
471
472 return desc;
473 }
474
475 static void at_xdmac_queue_desc(struct dma_chan *chan,
476 struct at_xdmac_desc *prev,
477 struct at_xdmac_desc *desc)
478 {
479 if (!prev || !desc)
480 return;
481
482 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
483 prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE;
484
485 dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
486 __func__, prev, &prev->lld.mbr_nda);
487 }
488
489 static inline void at_xdmac_increment_block_count(struct dma_chan *chan,
490 struct at_xdmac_desc *desc)
491 {
492 if (!desc)
493 return;
494
495 desc->lld.mbr_bc++;
496
497 dev_dbg(chan2dev(chan),
498 "%s: incrementing the block count of the desc 0x%p\n",
499 __func__, desc);
500 }
501
502 static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
503 struct of_dma *of_dma)
504 {
505 struct at_xdmac *atxdmac = of_dma->of_dma_data;
506 struct at_xdmac_chan *atchan;
507 struct dma_chan *chan;
508 struct device *dev = atxdmac->dma.dev;
509
510 if (dma_spec->args_count != 1) {
511 dev_err(dev, "dma phandler args: bad number of args\n");
512 return NULL;
513 }
514
515 chan = dma_get_any_slave_channel(&atxdmac->dma);
516 if (!chan) {
517 dev_err(dev, "can't get a dma channel\n");
518 return NULL;
519 }
520
521 atchan = to_at_xdmac_chan(chan);
522 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
523 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
524 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
525 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
526 atchan->memif, atchan->perif, atchan->perid);
527
528 return chan;
529 }
530
531 static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
532 enum dma_transfer_direction direction)
533 {
534 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
535 int csize, dwidth;
536
537 if (direction == DMA_DEV_TO_MEM) {
538 atchan->cfg =
539 AT91_XDMAC_DT_PERID(atchan->perid)
540 | AT_XDMAC_CC_DAM_INCREMENTED_AM
541 | AT_XDMAC_CC_SAM_FIXED_AM
542 | AT_XDMAC_CC_DIF(atchan->memif)
543 | AT_XDMAC_CC_SIF(atchan->perif)
544 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
545 | AT_XDMAC_CC_DSYNC_PER2MEM
546 | AT_XDMAC_CC_MBSIZE_SIXTEEN
547 | AT_XDMAC_CC_TYPE_PER_TRAN;
548 csize = ffs(atchan->sconfig.src_maxburst) - 1;
549 if (csize < 0) {
550 dev_err(chan2dev(chan), "invalid src maxburst value\n");
551 return -EINVAL;
552 }
553 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
554 dwidth = ffs(atchan->sconfig.src_addr_width) - 1;
555 if (dwidth < 0) {
556 dev_err(chan2dev(chan), "invalid src addr width value\n");
557 return -EINVAL;
558 }
559 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
560 } else if (direction == DMA_MEM_TO_DEV) {
561 atchan->cfg =
562 AT91_XDMAC_DT_PERID(atchan->perid)
563 | AT_XDMAC_CC_DAM_FIXED_AM
564 | AT_XDMAC_CC_SAM_INCREMENTED_AM
565 | AT_XDMAC_CC_DIF(atchan->perif)
566 | AT_XDMAC_CC_SIF(atchan->memif)
567 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
568 | AT_XDMAC_CC_DSYNC_MEM2PER
569 | AT_XDMAC_CC_MBSIZE_SIXTEEN
570 | AT_XDMAC_CC_TYPE_PER_TRAN;
571 csize = ffs(atchan->sconfig.dst_maxburst) - 1;
572 if (csize < 0) {
573 dev_err(chan2dev(chan), "invalid src maxburst value\n");
574 return -EINVAL;
575 }
576 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
577 dwidth = ffs(atchan->sconfig.dst_addr_width) - 1;
578 if (dwidth < 0) {
579 dev_err(chan2dev(chan), "invalid dst addr width value\n");
580 return -EINVAL;
581 }
582 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
583 }
584
585 dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg);
586
587 return 0;
588 }
589
590 /*
591 * Only check that maxburst and addr width values are supported by the
592 * the controller but not that the configuration is good to perform the
593 * transfer since we don't know the direction at this stage.
594 */
595 static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig)
596 {
597 if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE)
598 || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE))
599 return -EINVAL;
600
601 if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH)
602 || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH))
603 return -EINVAL;
604
605 return 0;
606 }
607
608 static int at_xdmac_set_slave_config(struct dma_chan *chan,
609 struct dma_slave_config *sconfig)
610 {
611 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
612
613 if (at_xdmac_check_slave_config(sconfig)) {
614 dev_err(chan2dev(chan), "invalid slave configuration\n");
615 return -EINVAL;
616 }
617
618 memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig));
619
620 return 0;
621 }
622
623 static struct dma_async_tx_descriptor *
624 at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
625 unsigned int sg_len, enum dma_transfer_direction direction,
626 unsigned long flags, void *context)
627 {
628 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
629 struct at_xdmac_desc *first = NULL, *prev = NULL;
630 struct scatterlist *sg;
631 int i;
632 unsigned int xfer_size = 0;
633 unsigned long irqflags;
634 struct dma_async_tx_descriptor *ret = NULL;
635
636 if (!sgl)
637 return NULL;
638
639 if (!is_slave_direction(direction)) {
640 dev_err(chan2dev(chan), "invalid DMA direction\n");
641 return NULL;
642 }
643
644 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
645 __func__, sg_len,
646 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
647 flags);
648
649 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
650 spin_lock_irqsave(&atchan->lock, irqflags);
651
652 if (at_xdmac_compute_chan_conf(chan, direction))
653 goto spin_unlock;
654
655 /* Prepare descriptors. */
656 for_each_sg(sgl, sg, sg_len, i) {
657 struct at_xdmac_desc *desc = NULL;
658 u32 len, mem, dwidth, fixed_dwidth;
659
660 len = sg_dma_len(sg);
661 mem = sg_dma_address(sg);
662 if (unlikely(!len)) {
663 dev_err(chan2dev(chan), "sg data length is zero\n");
664 goto spin_unlock;
665 }
666 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
667 __func__, i, len, mem);
668
669 desc = at_xdmac_get_desc(atchan);
670 if (!desc) {
671 dev_err(chan2dev(chan), "can't get descriptor\n");
672 if (first)
673 list_splice_init(&first->descs_list, &atchan->free_descs_list);
674 goto spin_unlock;
675 }
676
677 /* Linked list descriptor setup. */
678 if (direction == DMA_DEV_TO_MEM) {
679 desc->lld.mbr_sa = atchan->sconfig.src_addr;
680 desc->lld.mbr_da = mem;
681 } else {
682 desc->lld.mbr_sa = mem;
683 desc->lld.mbr_da = atchan->sconfig.dst_addr;
684 }
685 dwidth = at_xdmac_get_dwidth(atchan->cfg);
686 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
687 ? dwidth
688 : AT_XDMAC_CC_DWIDTH_BYTE;
689 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
690 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
691 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
692 | (len >> fixed_dwidth); /* microblock length */
693 desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |
694 AT_XDMAC_CC_DWIDTH(fixed_dwidth);
695 dev_dbg(chan2dev(chan),
696 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
697 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
698
699 /* Chain lld. */
700 if (prev)
701 at_xdmac_queue_desc(chan, prev, desc);
702
703 prev = desc;
704 if (!first)
705 first = desc;
706
707 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
708 __func__, desc, first);
709 list_add_tail(&desc->desc_node, &first->descs_list);
710 xfer_size += len;
711 }
712
713
714 first->tx_dma_desc.flags = flags;
715 first->xfer_size = xfer_size;
716 first->direction = direction;
717 ret = &first->tx_dma_desc;
718
719 spin_unlock:
720 spin_unlock_irqrestore(&atchan->lock, irqflags);
721 return ret;
722 }
723
724 static struct dma_async_tx_descriptor *
725 at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
726 size_t buf_len, size_t period_len,
727 enum dma_transfer_direction direction,
728 unsigned long flags)
729 {
730 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
731 struct at_xdmac_desc *first = NULL, *prev = NULL;
732 unsigned int periods = buf_len / period_len;
733 int i;
734 unsigned long irqflags;
735
736 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
737 __func__, &buf_addr, buf_len, period_len,
738 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
739
740 if (!is_slave_direction(direction)) {
741 dev_err(chan2dev(chan), "invalid DMA direction\n");
742 return NULL;
743 }
744
745 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
746 dev_err(chan2dev(chan), "channel currently used\n");
747 return NULL;
748 }
749
750 if (at_xdmac_compute_chan_conf(chan, direction))
751 return NULL;
752
753 for (i = 0; i < periods; i++) {
754 struct at_xdmac_desc *desc = NULL;
755
756 spin_lock_irqsave(&atchan->lock, irqflags);
757 desc = at_xdmac_get_desc(atchan);
758 if (!desc) {
759 dev_err(chan2dev(chan), "can't get descriptor\n");
760 if (first)
761 list_splice_init(&first->descs_list, &atchan->free_descs_list);
762 spin_unlock_irqrestore(&atchan->lock, irqflags);
763 return NULL;
764 }
765 spin_unlock_irqrestore(&atchan->lock, irqflags);
766 dev_dbg(chan2dev(chan),
767 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
768 __func__, desc, &desc->tx_dma_desc.phys);
769
770 if (direction == DMA_DEV_TO_MEM) {
771 desc->lld.mbr_sa = atchan->sconfig.src_addr;
772 desc->lld.mbr_da = buf_addr + i * period_len;
773 } else {
774 desc->lld.mbr_sa = buf_addr + i * period_len;
775 desc->lld.mbr_da = atchan->sconfig.dst_addr;
776 }
777 desc->lld.mbr_cfg = atchan->cfg;
778 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
779 | AT_XDMAC_MBR_UBC_NDEN
780 | AT_XDMAC_MBR_UBC_NSEN
781 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
782
783 dev_dbg(chan2dev(chan),
784 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
785 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
786
787 /* Chain lld. */
788 if (prev)
789 at_xdmac_queue_desc(chan, prev, desc);
790
791 prev = desc;
792 if (!first)
793 first = desc;
794
795 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
796 __func__, desc, first);
797 list_add_tail(&desc->desc_node, &first->descs_list);
798 }
799
800 prev->lld.mbr_nda = first->tx_dma_desc.phys;
801 dev_dbg(chan2dev(chan),
802 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
803 __func__, prev, &prev->lld.mbr_nda);
804 first->tx_dma_desc.flags = flags;
805 first->xfer_size = buf_len;
806 first->direction = direction;
807
808 return &first->tx_dma_desc;
809 }
810
811 static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr)
812 {
813 u32 width;
814
815 /*
816 * Check address alignment to select the greater data width we
817 * can use.
818 *
819 * Some XDMAC implementations don't provide dword transfer, in
820 * this case selecting dword has the same behavior as
821 * selecting word transfers.
822 */
823 if (!(addr & 7)) {
824 width = AT_XDMAC_CC_DWIDTH_DWORD;
825 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
826 } else if (!(addr & 3)) {
827 width = AT_XDMAC_CC_DWIDTH_WORD;
828 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
829 } else if (!(addr & 1)) {
830 width = AT_XDMAC_CC_DWIDTH_HALFWORD;
831 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
832 } else {
833 width = AT_XDMAC_CC_DWIDTH_BYTE;
834 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
835 }
836
837 return width;
838 }
839
840 static struct at_xdmac_desc *
841 at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
842 struct at_xdmac_chan *atchan,
843 struct at_xdmac_desc *prev,
844 dma_addr_t src, dma_addr_t dst,
845 struct dma_interleaved_template *xt,
846 struct data_chunk *chunk)
847 {
848 struct at_xdmac_desc *desc;
849 u32 dwidth;
850 unsigned long flags;
851 size_t ublen;
852 /*
853 * WARNING: The channel configuration is set here since there is no
854 * dmaengine_slave_config call in this case. Moreover we don't know the
855 * direction, it involves we can't dynamically set the source and dest
856 * interface so we have to use the same one. Only interface 0 allows EBI
857 * access. Hopefully we can access DDR through both ports (at least on
858 * SAMA5D4x), so we can use the same interface for source and dest,
859 * that solves the fact we don't know the direction.
860 */
861 u32 chan_cc = AT_XDMAC_CC_DIF(0)
862 | AT_XDMAC_CC_SIF(0)
863 | AT_XDMAC_CC_MBSIZE_SIXTEEN
864 | AT_XDMAC_CC_TYPE_MEM_TRAN;
865
866 dwidth = at_xdmac_align_width(chan, src | dst | chunk->size);
867 if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
868 dev_dbg(chan2dev(chan),
869 "%s: chunk too big (%d, max size %lu)...\n",
870 __func__, chunk->size,
871 AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth);
872 return NULL;
873 }
874
875 if (prev)
876 dev_dbg(chan2dev(chan),
877 "Adding items at the end of desc 0x%p\n", prev);
878
879 if (xt->src_inc) {
880 if (xt->src_sgl)
881 chan_cc |= AT_XDMAC_CC_SAM_UBS_DS_AM;
882 else
883 chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM;
884 }
885
886 if (xt->dst_inc) {
887 if (xt->dst_sgl)
888 chan_cc |= AT_XDMAC_CC_DAM_UBS_DS_AM;
889 else
890 chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM;
891 }
892
893 spin_lock_irqsave(&atchan->lock, flags);
894 desc = at_xdmac_get_desc(atchan);
895 spin_unlock_irqrestore(&atchan->lock, flags);
896 if (!desc) {
897 dev_err(chan2dev(chan), "can't get descriptor\n");
898 return NULL;
899 }
900
901 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
902
903 ublen = chunk->size >> dwidth;
904
905 desc->lld.mbr_sa = src;
906 desc->lld.mbr_da = dst;
907 desc->lld.mbr_sus = dmaengine_get_src_icg(xt, chunk);
908 desc->lld.mbr_dus = dmaengine_get_dst_icg(xt, chunk);
909
910 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
911 | AT_XDMAC_MBR_UBC_NDEN
912 | AT_XDMAC_MBR_UBC_NSEN
913 | ublen;
914 desc->lld.mbr_cfg = chan_cc;
915
916 dev_dbg(chan2dev(chan),
917 "%s: lld: mbr_sa=0x%08x, mbr_da=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
918 __func__, desc->lld.mbr_sa, desc->lld.mbr_da,
919 desc->lld.mbr_ubc, desc->lld.mbr_cfg);
920
921 /* Chain lld. */
922 if (prev)
923 at_xdmac_queue_desc(chan, prev, desc);
924
925 return desc;
926 }
927
928 static struct dma_async_tx_descriptor *
929 at_xdmac_prep_interleaved(struct dma_chan *chan,
930 struct dma_interleaved_template *xt,
931 unsigned long flags)
932 {
933 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
934 struct at_xdmac_desc *prev = NULL, *first = NULL;
935 struct data_chunk *chunk, *prev_chunk = NULL;
936 dma_addr_t dst_addr, src_addr;
937 size_t dst_skip, src_skip, len = 0;
938 size_t prev_dst_icg = 0, prev_src_icg = 0;
939 int i;
940
941 if (!xt || (xt->numf != 1) || (xt->dir != DMA_MEM_TO_MEM))
942 return NULL;
943
944 dev_dbg(chan2dev(chan), "%s: src=0x%08x, dest=0x%08x, numf=%d, frame_size=%d, flags=0x%lx\n",
945 __func__, xt->src_start, xt->dst_start, xt->numf,
946 xt->frame_size, flags);
947
948 src_addr = xt->src_start;
949 dst_addr = xt->dst_start;
950
951 for (i = 0; i < xt->frame_size; i++) {
952 struct at_xdmac_desc *desc;
953 size_t src_icg, dst_icg;
954
955 chunk = xt->sgl + i;
956
957 dst_icg = dmaengine_get_dst_icg(xt, chunk);
958 src_icg = dmaengine_get_src_icg(xt, chunk);
959
960 src_skip = chunk->size + src_icg;
961 dst_skip = chunk->size + dst_icg;
962
963 dev_dbg(chan2dev(chan),
964 "%s: chunk size=%d, src icg=%d, dst icg=%d\n",
965 __func__, chunk->size, src_icg, dst_icg);
966
967 /*
968 * Handle the case where we just have the same
969 * transfer to setup, we can just increase the
970 * block number and reuse the same descriptor.
971 */
972 if (prev_chunk && prev &&
973 (prev_chunk->size == chunk->size) &&
974 (prev_src_icg == src_icg) &&
975 (prev_dst_icg == dst_icg)) {
976 dev_dbg(chan2dev(chan),
977 "%s: same configuration that the previous chunk, merging the descriptors...\n",
978 __func__);
979 at_xdmac_increment_block_count(chan, prev);
980 continue;
981 }
982
983 desc = at_xdmac_interleaved_queue_desc(chan, atchan,
984 prev,
985 src_addr, dst_addr,
986 xt, chunk);
987 if (!desc) {
988 list_splice_init(&first->descs_list,
989 &atchan->free_descs_list);
990 return NULL;
991 }
992
993 if (!first)
994 first = desc;
995
996 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
997 __func__, desc, first);
998 list_add_tail(&desc->desc_node, &first->descs_list);
999
1000 if (xt->src_sgl)
1001 src_addr += src_skip;
1002
1003 if (xt->dst_sgl)
1004 dst_addr += dst_skip;
1005
1006 len += chunk->size;
1007 prev_chunk = chunk;
1008 prev_dst_icg = dst_icg;
1009 prev_src_icg = src_icg;
1010 prev = desc;
1011 }
1012
1013 first->tx_dma_desc.cookie = -EBUSY;
1014 first->tx_dma_desc.flags = flags;
1015 first->xfer_size = len;
1016
1017 return &first->tx_dma_desc;
1018 }
1019
1020 static struct dma_async_tx_descriptor *
1021 at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1022 size_t len, unsigned long flags)
1023 {
1024 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1025 struct at_xdmac_desc *first = NULL, *prev = NULL;
1026 size_t remaining_size = len, xfer_size = 0, ublen;
1027 dma_addr_t src_addr = src, dst_addr = dest;
1028 u32 dwidth;
1029 /*
1030 * WARNING: We don't know the direction, it involves we can't
1031 * dynamically set the source and dest interface so we have to use the
1032 * same one. Only interface 0 allows EBI access. Hopefully we can
1033 * access DDR through both ports (at least on SAMA5D4x), so we can use
1034 * the same interface for source and dest, that solves the fact we
1035 * don't know the direction.
1036 */
1037 u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
1038 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1039 | AT_XDMAC_CC_DIF(0)
1040 | AT_XDMAC_CC_SIF(0)
1041 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1042 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1043 unsigned long irqflags;
1044
1045 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
1046 __func__, &src, &dest, len, flags);
1047
1048 if (unlikely(!len))
1049 return NULL;
1050
1051 dwidth = at_xdmac_align_width(chan, src_addr | dst_addr);
1052
1053 /* Prepare descriptors. */
1054 while (remaining_size) {
1055 struct at_xdmac_desc *desc = NULL;
1056
1057 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
1058
1059 spin_lock_irqsave(&atchan->lock, irqflags);
1060 desc = at_xdmac_get_desc(atchan);
1061 spin_unlock_irqrestore(&atchan->lock, irqflags);
1062 if (!desc) {
1063 dev_err(chan2dev(chan), "can't get descriptor\n");
1064 if (first)
1065 list_splice_init(&first->descs_list, &atchan->free_descs_list);
1066 return NULL;
1067 }
1068
1069 /* Update src and dest addresses. */
1070 src_addr += xfer_size;
1071 dst_addr += xfer_size;
1072
1073 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
1074 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
1075 else
1076 xfer_size = remaining_size;
1077
1078 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
1079
1080 /* Check remaining length and change data width if needed. */
1081 dwidth = at_xdmac_align_width(chan,
1082 src_addr | dst_addr | xfer_size);
1083 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1084
1085 ublen = xfer_size >> dwidth;
1086 remaining_size -= xfer_size;
1087
1088 desc->lld.mbr_sa = src_addr;
1089 desc->lld.mbr_da = dst_addr;
1090 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
1091 | AT_XDMAC_MBR_UBC_NDEN
1092 | AT_XDMAC_MBR_UBC_NSEN
1093 | ublen;
1094 desc->lld.mbr_cfg = chan_cc;
1095
1096 dev_dbg(chan2dev(chan),
1097 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1098 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
1099
1100 /* Chain lld. */
1101 if (prev)
1102 at_xdmac_queue_desc(chan, prev, desc);
1103
1104 prev = desc;
1105 if (!first)
1106 first = desc;
1107
1108 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1109 __func__, desc, first);
1110 list_add_tail(&desc->desc_node, &first->descs_list);
1111 }
1112
1113 first->tx_dma_desc.flags = flags;
1114 first->xfer_size = len;
1115
1116 return &first->tx_dma_desc;
1117 }
1118
1119 static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
1120 struct at_xdmac_chan *atchan,
1121 dma_addr_t dst_addr,
1122 size_t len,
1123 int value)
1124 {
1125 struct at_xdmac_desc *desc;
1126 unsigned long flags;
1127 size_t ublen;
1128 u32 dwidth;
1129 /*
1130 * WARNING: The channel configuration is set here since there is no
1131 * dmaengine_slave_config call in this case. Moreover we don't know the
1132 * direction, it involves we can't dynamically set the source and dest
1133 * interface so we have to use the same one. Only interface 0 allows EBI
1134 * access. Hopefully we can access DDR through both ports (at least on
1135 * SAMA5D4x), so we can use the same interface for source and dest,
1136 * that solves the fact we don't know the direction.
1137 */
1138 u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
1139 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1140 | AT_XDMAC_CC_DIF(0)
1141 | AT_XDMAC_CC_SIF(0)
1142 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1143 | AT_XDMAC_CC_MEMSET_HW_MODE
1144 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1145
1146 dwidth = at_xdmac_align_width(chan, dst_addr);
1147
1148 if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
1149 dev_err(chan2dev(chan),
1150 "%s: Transfer too large, aborting...\n",
1151 __func__);
1152 return NULL;
1153 }
1154
1155 spin_lock_irqsave(&atchan->lock, flags);
1156 desc = at_xdmac_get_desc(atchan);
1157 spin_unlock_irqrestore(&atchan->lock, flags);
1158 if (!desc) {
1159 dev_err(chan2dev(chan), "can't get descriptor\n");
1160 return NULL;
1161 }
1162
1163 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1164
1165 ublen = len >> dwidth;
1166
1167 desc->lld.mbr_da = dst_addr;
1168 desc->lld.mbr_ds = value;
1169 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
1170 | AT_XDMAC_MBR_UBC_NDEN
1171 | AT_XDMAC_MBR_UBC_NSEN
1172 | ublen;
1173 desc->lld.mbr_cfg = chan_cc;
1174
1175 dev_dbg(chan2dev(chan),
1176 "%s: lld: mbr_da=0x%08x, mbr_ds=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1177 __func__, desc->lld.mbr_da, desc->lld.mbr_ds, desc->lld.mbr_ubc,
1178 desc->lld.mbr_cfg);
1179
1180 return desc;
1181 }
1182
1183 struct dma_async_tx_descriptor *
1184 at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
1185 size_t len, unsigned long flags)
1186 {
1187 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1188 struct at_xdmac_desc *desc;
1189
1190 dev_dbg(chan2dev(chan), "%s: dest=0x%08x, len=%d, pattern=0x%x, flags=0x%lx\n",
1191 __func__, dest, len, value, flags);
1192
1193 if (unlikely(!len))
1194 return NULL;
1195
1196 desc = at_xdmac_memset_create_desc(chan, atchan, dest, len, value);
1197 list_add_tail(&desc->desc_node, &desc->descs_list);
1198
1199 desc->tx_dma_desc.cookie = -EBUSY;
1200 desc->tx_dma_desc.flags = flags;
1201 desc->xfer_size = len;
1202
1203 return &desc->tx_dma_desc;
1204 }
1205
1206 static enum dma_status
1207 at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1208 struct dma_tx_state *txstate)
1209 {
1210 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1211 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1212 struct at_xdmac_desc *desc, *_desc;
1213 struct list_head *descs_list;
1214 enum dma_status ret;
1215 int residue;
1216 u32 cur_nda, mask, value;
1217 u8 dwidth = 0;
1218 unsigned long flags;
1219
1220 ret = dma_cookie_status(chan, cookie, txstate);
1221 if (ret == DMA_COMPLETE)
1222 return ret;
1223
1224 if (!txstate)
1225 return ret;
1226
1227 spin_lock_irqsave(&atchan->lock, flags);
1228
1229 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1230
1231 /*
1232 * If the transfer has not been started yet, don't need to compute the
1233 * residue, it's the transfer length.
1234 */
1235 if (!desc->active_xfer) {
1236 dma_set_residue(txstate, desc->xfer_size);
1237 goto spin_unlock;
1238 }
1239
1240 residue = desc->xfer_size;
1241 /*
1242 * Flush FIFO: only relevant when the transfer is source peripheral
1243 * synchronized.
1244 */
1245 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
1246 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
1247 if ((desc->lld.mbr_cfg & mask) == value) {
1248 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
1249 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1250 cpu_relax();
1251 }
1252
1253 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1254 /*
1255 * Remove size of all microblocks already transferred and the current
1256 * one. Then add the remaining size to transfer of the current
1257 * microblock.
1258 */
1259 descs_list = &desc->descs_list;
1260 list_for_each_entry_safe(desc, _desc, descs_list, desc_node) {
1261 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
1262 residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth;
1263 if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda)
1264 break;
1265 }
1266 residue += at_xdmac_chan_read(atchan, AT_XDMAC_CUBC) << dwidth;
1267
1268 dma_set_residue(txstate, residue);
1269
1270 dev_dbg(chan2dev(chan),
1271 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
1272 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
1273
1274 spin_unlock:
1275 spin_unlock_irqrestore(&atchan->lock, flags);
1276 return ret;
1277 }
1278
1279 /* Call must be protected by lock. */
1280 static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan,
1281 struct at_xdmac_desc *desc)
1282 {
1283 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1284
1285 /*
1286 * Remove the transfer from the transfer list then move the transfer
1287 * descriptors into the free descriptors list.
1288 */
1289 list_del(&desc->xfer_node);
1290 list_splice_init(&desc->descs_list, &atchan->free_descs_list);
1291 }
1292
1293 static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
1294 {
1295 struct at_xdmac_desc *desc;
1296 unsigned long flags;
1297
1298 spin_lock_irqsave(&atchan->lock, flags);
1299
1300 /*
1301 * If channel is enabled, do nothing, advance_work will be triggered
1302 * after the interruption.
1303 */
1304 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) {
1305 desc = list_first_entry(&atchan->xfers_list,
1306 struct at_xdmac_desc,
1307 xfer_node);
1308 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1309 if (!desc->active_xfer)
1310 at_xdmac_start_xfer(atchan, desc);
1311 }
1312
1313 spin_unlock_irqrestore(&atchan->lock, flags);
1314 }
1315
1316 static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
1317 {
1318 struct at_xdmac_desc *desc;
1319 struct dma_async_tx_descriptor *txd;
1320
1321 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1322 txd = &desc->tx_dma_desc;
1323
1324 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1325 txd->callback(txd->callback_param);
1326 }
1327
1328 static void at_xdmac_tasklet(unsigned long data)
1329 {
1330 struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data;
1331 struct at_xdmac_desc *desc;
1332 u32 error_mask;
1333
1334 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n",
1335 __func__, atchan->status);
1336
1337 error_mask = AT_XDMAC_CIS_RBEIS
1338 | AT_XDMAC_CIS_WBEIS
1339 | AT_XDMAC_CIS_ROIS;
1340
1341 if (at_xdmac_chan_is_cyclic(atchan)) {
1342 at_xdmac_handle_cyclic(atchan);
1343 } else if ((atchan->status & AT_XDMAC_CIS_LIS)
1344 || (atchan->status & error_mask)) {
1345 struct dma_async_tx_descriptor *txd;
1346
1347 if (atchan->status & AT_XDMAC_CIS_RBEIS)
1348 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1349 if (atchan->status & AT_XDMAC_CIS_WBEIS)
1350 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1351 if (atchan->status & AT_XDMAC_CIS_ROIS)
1352 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1353
1354 spin_lock_bh(&atchan->lock);
1355 desc = list_first_entry(&atchan->xfers_list,
1356 struct at_xdmac_desc,
1357 xfer_node);
1358 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1359 BUG_ON(!desc->active_xfer);
1360
1361 txd = &desc->tx_dma_desc;
1362
1363 at_xdmac_remove_xfer(atchan, desc);
1364 spin_unlock_bh(&atchan->lock);
1365
1366 if (!at_xdmac_chan_is_cyclic(atchan)) {
1367 dma_cookie_complete(txd);
1368 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1369 txd->callback(txd->callback_param);
1370 }
1371
1372 dma_run_dependencies(txd);
1373
1374 at_xdmac_advance_work(atchan);
1375 }
1376 }
1377
1378 static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1379 {
1380 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1381 struct at_xdmac_chan *atchan;
1382 u32 imr, status, pending;
1383 u32 chan_imr, chan_status;
1384 int i, ret = IRQ_NONE;
1385
1386 do {
1387 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1388 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1389 pending = status & imr;
1390
1391 dev_vdbg(atxdmac->dma.dev,
1392 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1393 __func__, status, imr, pending);
1394
1395 if (!pending)
1396 break;
1397
1398 /* We have to find which channel has generated the interrupt. */
1399 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1400 if (!((1 << i) & pending))
1401 continue;
1402
1403 atchan = &atxdmac->chan[i];
1404 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1405 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1406 atchan->status = chan_status & chan_imr;
1407 dev_vdbg(atxdmac->dma.dev,
1408 "%s: chan%d: imr=0x%x, status=0x%x\n",
1409 __func__, i, chan_imr, chan_status);
1410 dev_vdbg(chan2dev(&atchan->chan),
1411 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1412 __func__,
1413 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1414 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1415 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1416 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1417 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1418 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1419
1420 if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1421 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1422
1423 tasklet_schedule(&atchan->tasklet);
1424 ret = IRQ_HANDLED;
1425 }
1426
1427 } while (pending);
1428
1429 return ret;
1430 }
1431
1432 static void at_xdmac_issue_pending(struct dma_chan *chan)
1433 {
1434 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1435
1436 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1437
1438 if (!at_xdmac_chan_is_cyclic(atchan))
1439 at_xdmac_advance_work(atchan);
1440
1441 return;
1442 }
1443
1444 static int at_xdmac_device_config(struct dma_chan *chan,
1445 struct dma_slave_config *config)
1446 {
1447 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1448 int ret;
1449 unsigned long flags;
1450
1451 dev_dbg(chan2dev(chan), "%s\n", __func__);
1452
1453 spin_lock_irqsave(&atchan->lock, flags);
1454 ret = at_xdmac_set_slave_config(chan, config);
1455 spin_unlock_irqrestore(&atchan->lock, flags);
1456
1457 return ret;
1458 }
1459
1460 static int at_xdmac_device_pause(struct dma_chan *chan)
1461 {
1462 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1463 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1464 unsigned long flags;
1465
1466 dev_dbg(chan2dev(chan), "%s\n", __func__);
1467
1468 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1469 return 0;
1470
1471 spin_lock_irqsave(&atchan->lock, flags);
1472 at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
1473 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1474 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1475 cpu_relax();
1476 spin_unlock_irqrestore(&atchan->lock, flags);
1477
1478 return 0;
1479 }
1480
1481 static int at_xdmac_device_resume(struct dma_chan *chan)
1482 {
1483 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1484 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1485 unsigned long flags;
1486
1487 dev_dbg(chan2dev(chan), "%s\n", __func__);
1488
1489 spin_lock_irqsave(&atchan->lock, flags);
1490 if (!at_xdmac_chan_is_paused(atchan)) {
1491 spin_unlock_irqrestore(&atchan->lock, flags);
1492 return 0;
1493 }
1494
1495 at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
1496 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1497 spin_unlock_irqrestore(&atchan->lock, flags);
1498
1499 return 0;
1500 }
1501
1502 static int at_xdmac_device_terminate_all(struct dma_chan *chan)
1503 {
1504 struct at_xdmac_desc *desc, *_desc;
1505 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1506 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1507 unsigned long flags;
1508
1509 dev_dbg(chan2dev(chan), "%s\n", __func__);
1510
1511 spin_lock_irqsave(&atchan->lock, flags);
1512 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1513 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1514 cpu_relax();
1515
1516 /* Cancel all pending transfers. */
1517 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node)
1518 at_xdmac_remove_xfer(atchan, desc);
1519
1520 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
1521 spin_unlock_irqrestore(&atchan->lock, flags);
1522
1523 return 0;
1524 }
1525
1526 static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1527 {
1528 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1529 struct at_xdmac_desc *desc;
1530 int i;
1531 unsigned long flags;
1532
1533 spin_lock_irqsave(&atchan->lock, flags);
1534
1535 if (at_xdmac_chan_is_enabled(atchan)) {
1536 dev_err(chan2dev(chan),
1537 "can't allocate channel resources (channel enabled)\n");
1538 i = -EIO;
1539 goto spin_unlock;
1540 }
1541
1542 if (!list_empty(&atchan->free_descs_list)) {
1543 dev_err(chan2dev(chan),
1544 "can't allocate channel resources (channel not free from a previous use)\n");
1545 i = -EIO;
1546 goto spin_unlock;
1547 }
1548
1549 for (i = 0; i < init_nr_desc_per_channel; i++) {
1550 desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC);
1551 if (!desc) {
1552 dev_warn(chan2dev(chan),
1553 "only %d descriptors have been allocated\n", i);
1554 break;
1555 }
1556 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1557 }
1558
1559 dma_cookie_init(chan);
1560
1561 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1562
1563 spin_unlock:
1564 spin_unlock_irqrestore(&atchan->lock, flags);
1565 return i;
1566 }
1567
1568 static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1569 {
1570 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1571 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1572 struct at_xdmac_desc *desc, *_desc;
1573
1574 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1575 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1576 list_del(&desc->desc_node);
1577 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1578 }
1579
1580 return;
1581 }
1582
1583 #ifdef CONFIG_PM
1584 static int atmel_xdmac_prepare(struct device *dev)
1585 {
1586 struct platform_device *pdev = to_platform_device(dev);
1587 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1588 struct dma_chan *chan, *_chan;
1589
1590 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1591 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1592
1593 /* Wait for transfer completion, except in cyclic case. */
1594 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1595 return -EAGAIN;
1596 }
1597 return 0;
1598 }
1599 #else
1600 # define atmel_xdmac_prepare NULL
1601 #endif
1602
1603 #ifdef CONFIG_PM_SLEEP
1604 static int atmel_xdmac_suspend(struct device *dev)
1605 {
1606 struct platform_device *pdev = to_platform_device(dev);
1607 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1608 struct dma_chan *chan, *_chan;
1609
1610 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1611 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1612
1613 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
1614 if (at_xdmac_chan_is_cyclic(atchan)) {
1615 if (!at_xdmac_chan_is_paused(atchan))
1616 at_xdmac_device_pause(chan);
1617 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1618 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1619 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1620 }
1621 }
1622 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1623
1624 at_xdmac_off(atxdmac);
1625 clk_disable_unprepare(atxdmac->clk);
1626 return 0;
1627 }
1628
1629 static int atmel_xdmac_resume(struct device *dev)
1630 {
1631 struct platform_device *pdev = to_platform_device(dev);
1632 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1633 struct at_xdmac_chan *atchan;
1634 struct dma_chan *chan, *_chan;
1635 int i;
1636
1637 clk_prepare_enable(atxdmac->clk);
1638
1639 /* Clear pending interrupts. */
1640 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1641 atchan = &atxdmac->chan[i];
1642 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1643 cpu_relax();
1644 }
1645
1646 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
1647 at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs);
1648 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1649 atchan = to_at_xdmac_chan(chan);
1650 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
1651 if (at_xdmac_chan_is_cyclic(atchan)) {
1652 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
1653 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
1654 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
1655 wmb();
1656 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
1657 }
1658 }
1659 return 0;
1660 }
1661 #endif /* CONFIG_PM_SLEEP */
1662
1663 static int at_xdmac_probe(struct platform_device *pdev)
1664 {
1665 struct resource *res;
1666 struct at_xdmac *atxdmac;
1667 int irq, size, nr_channels, i, ret;
1668 void __iomem *base;
1669 u32 reg;
1670
1671 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1672 if (!res)
1673 return -EINVAL;
1674
1675 irq = platform_get_irq(pdev, 0);
1676 if (irq < 0)
1677 return irq;
1678
1679 base = devm_ioremap_resource(&pdev->dev, res);
1680 if (IS_ERR(base))
1681 return PTR_ERR(base);
1682
1683 /*
1684 * Read number of xdmac channels, read helper function can't be used
1685 * since atxdmac is not yet allocated and we need to know the number
1686 * of channels to do the allocation.
1687 */
1688 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
1689 nr_channels = AT_XDMAC_NB_CH(reg);
1690 if (nr_channels > AT_XDMAC_MAX_CHAN) {
1691 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
1692 nr_channels);
1693 return -EINVAL;
1694 }
1695
1696 size = sizeof(*atxdmac);
1697 size += nr_channels * sizeof(struct at_xdmac_chan);
1698 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1699 if (!atxdmac) {
1700 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
1701 return -ENOMEM;
1702 }
1703
1704 atxdmac->regs = base;
1705 atxdmac->irq = irq;
1706
1707 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
1708 if (IS_ERR(atxdmac->clk)) {
1709 dev_err(&pdev->dev, "can't get dma_clk\n");
1710 return PTR_ERR(atxdmac->clk);
1711 }
1712
1713 /* Do not use dev res to prevent races with tasklet */
1714 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
1715 if (ret) {
1716 dev_err(&pdev->dev, "can't request irq\n");
1717 return ret;
1718 }
1719
1720 ret = clk_prepare_enable(atxdmac->clk);
1721 if (ret) {
1722 dev_err(&pdev->dev, "can't prepare or enable clock\n");
1723 goto err_free_irq;
1724 }
1725
1726 atxdmac->at_xdmac_desc_pool =
1727 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1728 sizeof(struct at_xdmac_desc), 4, 0);
1729 if (!atxdmac->at_xdmac_desc_pool) {
1730 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
1731 ret = -ENOMEM;
1732 goto err_clk_disable;
1733 }
1734
1735 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
1736 dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask);
1737 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
1738 dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask);
1739 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
1740 /*
1741 * Without DMA_PRIVATE the driver is not able to allocate more than
1742 * one channel, second allocation fails in private_candidate.
1743 */
1744 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
1745 atxdmac->dma.dev = &pdev->dev;
1746 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
1747 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
1748 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
1749 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
1750 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
1751 atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved;
1752 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
1753 atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset;
1754 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
1755 atxdmac->dma.device_config = at_xdmac_device_config;
1756 atxdmac->dma.device_pause = at_xdmac_device_pause;
1757 atxdmac->dma.device_resume = at_xdmac_device_resume;
1758 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
1759 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1760 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1761 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1762 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1763
1764 /* Disable all chans and interrupts. */
1765 at_xdmac_off(atxdmac);
1766
1767 /* Init channels. */
1768 INIT_LIST_HEAD(&atxdmac->dma.channels);
1769 for (i = 0; i < nr_channels; i++) {
1770 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1771
1772 atchan->chan.device = &atxdmac->dma;
1773 list_add_tail(&atchan->chan.device_node,
1774 &atxdmac->dma.channels);
1775
1776 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
1777 atchan->mask = 1 << i;
1778
1779 spin_lock_init(&atchan->lock);
1780 INIT_LIST_HEAD(&atchan->xfers_list);
1781 INIT_LIST_HEAD(&atchan->free_descs_list);
1782 tasklet_init(&atchan->tasklet, at_xdmac_tasklet,
1783 (unsigned long)atchan);
1784
1785 /* Clear pending interrupts. */
1786 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1787 cpu_relax();
1788 }
1789 platform_set_drvdata(pdev, atxdmac);
1790
1791 ret = dma_async_device_register(&atxdmac->dma);
1792 if (ret) {
1793 dev_err(&pdev->dev, "fail to register DMA engine device\n");
1794 goto err_clk_disable;
1795 }
1796
1797 ret = of_dma_controller_register(pdev->dev.of_node,
1798 at_xdmac_xlate, atxdmac);
1799 if (ret) {
1800 dev_err(&pdev->dev, "could not register of dma controller\n");
1801 goto err_dma_unregister;
1802 }
1803
1804 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
1805 nr_channels, atxdmac->regs);
1806
1807 return 0;
1808
1809 err_dma_unregister:
1810 dma_async_device_unregister(&atxdmac->dma);
1811 err_clk_disable:
1812 clk_disable_unprepare(atxdmac->clk);
1813 err_free_irq:
1814 free_irq(atxdmac->irq, atxdmac->dma.dev);
1815 return ret;
1816 }
1817
1818 static int at_xdmac_remove(struct platform_device *pdev)
1819 {
1820 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
1821 int i;
1822
1823 at_xdmac_off(atxdmac);
1824 of_dma_controller_free(pdev->dev.of_node);
1825 dma_async_device_unregister(&atxdmac->dma);
1826 clk_disable_unprepare(atxdmac->clk);
1827
1828 synchronize_irq(atxdmac->irq);
1829
1830 free_irq(atxdmac->irq, atxdmac->dma.dev);
1831
1832 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1833 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1834
1835 tasklet_kill(&atchan->tasklet);
1836 at_xdmac_free_chan_resources(&atchan->chan);
1837 }
1838
1839 return 0;
1840 }
1841
1842 static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
1843 .prepare = atmel_xdmac_prepare,
1844 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
1845 };
1846
1847 static const struct of_device_id atmel_xdmac_dt_ids[] = {
1848 {
1849 .compatible = "atmel,sama5d4-dma",
1850 }, {
1851 /* sentinel */
1852 }
1853 };
1854 MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
1855
1856 static struct platform_driver at_xdmac_driver = {
1857 .probe = at_xdmac_probe,
1858 .remove = at_xdmac_remove,
1859 .driver = {
1860 .name = "at_xdmac",
1861 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
1862 .pm = &atmel_xdmac_dev_pm_ops,
1863 }
1864 };
1865
1866 static int __init at_xdmac_init(void)
1867 {
1868 return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe);
1869 }
1870 subsys_initcall(at_xdmac_init);
1871
1872 MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
1873 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
1874 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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