2 * TI EDMA DMA engine driver
4 * Copyright 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/edma.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/list.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
28 #include <linux/of_dma.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_address.h>
31 #include <linux/of_device.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/platform_data/edma.h>
36 #include "dmaengine.h"
39 /* Offsets matching "struct edmacc_param" */
42 #define PARM_A_B_CNT 0x08
44 #define PARM_SRC_DST_BIDX 0x10
45 #define PARM_LINK_BCNTRLD 0x14
46 #define PARM_SRC_DST_CIDX 0x18
47 #define PARM_CCNT 0x1c
49 #define PARM_SIZE 0x20
51 /* Offsets for EDMA CC global channel registers and their shadows */
52 #define SH_ER 0x00 /* 64 bits */
53 #define SH_ECR 0x08 /* 64 bits */
54 #define SH_ESR 0x10 /* 64 bits */
55 #define SH_CER 0x18 /* 64 bits */
56 #define SH_EER 0x20 /* 64 bits */
57 #define SH_EECR 0x28 /* 64 bits */
58 #define SH_EESR 0x30 /* 64 bits */
59 #define SH_SER 0x38 /* 64 bits */
60 #define SH_SECR 0x40 /* 64 bits */
61 #define SH_IER 0x50 /* 64 bits */
62 #define SH_IECR 0x58 /* 64 bits */
63 #define SH_IESR 0x60 /* 64 bits */
64 #define SH_IPR 0x68 /* 64 bits */
65 #define SH_ICR 0x70 /* 64 bits */
75 /* Offsets for EDMA CC global registers */
76 #define EDMA_REV 0x0000
77 #define EDMA_CCCFG 0x0004
78 #define EDMA_QCHMAP 0x0200 /* 8 registers */
79 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
80 #define EDMA_QDMAQNUM 0x0260
81 #define EDMA_QUETCMAP 0x0280
82 #define EDMA_QUEPRI 0x0284
83 #define EDMA_EMR 0x0300 /* 64 bits */
84 #define EDMA_EMCR 0x0308 /* 64 bits */
85 #define EDMA_QEMR 0x0310
86 #define EDMA_QEMCR 0x0314
87 #define EDMA_CCERR 0x0318
88 #define EDMA_CCERRCLR 0x031c
89 #define EDMA_EEVAL 0x0320
90 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
91 #define EDMA_QRAE 0x0380 /* 4 registers */
92 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
93 #define EDMA_QSTAT 0x0600 /* 2 registers */
94 #define EDMA_QWMTHRA 0x0620
95 #define EDMA_QWMTHRB 0x0624
96 #define EDMA_CCSTAT 0x0640
98 #define EDMA_M 0x1000 /* global channel registers */
99 #define EDMA_ECR 0x1008
100 #define EDMA_ECRH 0x100C
101 #define EDMA_SHADOW0 0x2000 /* 4 shadow regions */
102 #define EDMA_PARM 0x4000 /* PaRAM entries */
104 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
106 #define EDMA_DCHMAP 0x0100 /* 64 registers */
109 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
110 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
111 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
112 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
113 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
114 #define CHMAP_EXIST BIT(24)
117 * Max of 20 segments per channel to conserve PaRAM slots
118 * Also note that MAX_NR_SG should be atleast the no.of periods
119 * that are required for ASoC, otherwise DMA prep calls will
120 * fail. Today davinci-pcm is the only user of this driver and
121 * requires atleast 17 slots, so we setup the default to 20.
124 #define EDMA_MAX_SLOTS MAX_NR_SG
125 #define EDMA_DESCRIPTORS 16
127 #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
128 #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
129 #define EDMA_CONT_PARAMS_ANY 1001
130 #define EDMA_CONT_PARAMS_FIXED_EXACT 1002
131 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
133 /* PaRAM slots are laid out like this */
134 struct edmacc_param
{
145 /* fields in edmacc_param.opt */
148 #define SYNCDIM BIT(2)
149 #define STATIC BIT(3)
150 #define EDMA_FWID (0x07 << 8)
151 #define TCCMODE BIT(11)
152 #define EDMA_TCC(t) ((t) << 12)
153 #define TCINTEN BIT(20)
154 #define ITCINTEN BIT(21)
155 #define TCCHEN BIT(22)
156 #define ITCCHEN BIT(23)
161 struct edmacc_param param
;
165 struct virt_dma_desc vdesc
;
166 struct list_head node
;
167 enum dma_transfer_direction direction
;
171 struct edma_chan
*echan
;
175 * The following 4 elements are used for residue accounting.
177 * - processed_stat: the number of SG elements we have traversed
178 * so far to cover accounting. This is updated directly to processed
179 * during edma_callback and is always <= processed, because processed
180 * refers to the number of pending transfer (programmed to EDMA
181 * controller), where as processed_stat tracks number of transfers
182 * accounted for so far.
184 * - residue: The amount of bytes we have left to transfer for this desc
186 * - residue_stat: The residue in bytes of data we have covered
187 * so far for accounting. This is updated directly to residue
188 * during callbacks to keep it current.
190 * - sg_len: Tracks the length of the current intermediate transfer,
191 * this is required to update the residue during intermediate transfer
192 * completion callback.
199 struct edma_pset pset
[0];
205 struct device_node
*node
;
210 struct virt_dma_chan vchan
;
211 struct list_head node
;
212 struct edma_desc
*edesc
;
218 int slot
[EDMA_MAX_SLOTS
];
220 struct dma_slave_config cfg
;
225 struct edma_soc_info
*info
;
230 /* eDMA3 resource information */
231 unsigned num_channels
;
232 unsigned num_qchannels
;
237 enum dma_event_q default_queue
;
240 * The slot_inuse bit for each PaRAM slot is clear unless the slot is
241 * in use by Linux or if it is allocated to be used by DSP.
243 unsigned long *slot_inuse
;
245 struct dma_device dma_slave
;
246 struct dma_device
*dma_memcpy
;
247 struct edma_chan
*slave_chans
;
248 struct edma_tc
*tc_list
;
252 /* dummy param set used to (re)initialize parameter RAM slots */
253 static const struct edmacc_param dummy_paramset
= {
254 .link_bcntrld
= 0xffff,
258 #define EDMA_BINDING_LEGACY 0
259 #define EDMA_BINDING_TPCC 1
260 static const struct of_device_id edma_of_ids
[] = {
262 .compatible
= "ti,edma3",
263 .data
= (void *)EDMA_BINDING_LEGACY
,
266 .compatible
= "ti,edma3-tpcc",
267 .data
= (void *)EDMA_BINDING_TPCC
,
272 static const struct of_device_id edma_tptc_of_ids
[] = {
273 { .compatible
= "ti,edma3-tptc", },
277 static inline unsigned int edma_read(struct edma_cc
*ecc
, int offset
)
279 return (unsigned int)__raw_readl(ecc
->base
+ offset
);
282 static inline void edma_write(struct edma_cc
*ecc
, int offset
, int val
)
284 __raw_writel(val
, ecc
->base
+ offset
);
287 static inline void edma_modify(struct edma_cc
*ecc
, int offset
, unsigned and,
290 unsigned val
= edma_read(ecc
, offset
);
294 edma_write(ecc
, offset
, val
);
297 static inline void edma_and(struct edma_cc
*ecc
, int offset
, unsigned and)
299 unsigned val
= edma_read(ecc
, offset
);
302 edma_write(ecc
, offset
, val
);
305 static inline void edma_or(struct edma_cc
*ecc
, int offset
, unsigned or)
307 unsigned val
= edma_read(ecc
, offset
);
310 edma_write(ecc
, offset
, val
);
313 static inline unsigned int edma_read_array(struct edma_cc
*ecc
, int offset
,
316 return edma_read(ecc
, offset
+ (i
<< 2));
319 static inline void edma_write_array(struct edma_cc
*ecc
, int offset
, int i
,
322 edma_write(ecc
, offset
+ (i
<< 2), val
);
325 static inline void edma_modify_array(struct edma_cc
*ecc
, int offset
, int i
,
326 unsigned and, unsigned or)
328 edma_modify(ecc
, offset
+ (i
<< 2), and, or);
331 static inline void edma_or_array(struct edma_cc
*ecc
, int offset
, int i
,
334 edma_or(ecc
, offset
+ (i
<< 2), or);
337 static inline void edma_or_array2(struct edma_cc
*ecc
, int offset
, int i
, int j
,
340 edma_or(ecc
, offset
+ ((i
* 2 + j
) << 2), or);
343 static inline void edma_write_array2(struct edma_cc
*ecc
, int offset
, int i
,
346 edma_write(ecc
, offset
+ ((i
* 2 + j
) << 2), val
);
349 static inline unsigned int edma_shadow0_read(struct edma_cc
*ecc
, int offset
)
351 return edma_read(ecc
, EDMA_SHADOW0
+ offset
);
354 static inline unsigned int edma_shadow0_read_array(struct edma_cc
*ecc
,
357 return edma_read(ecc
, EDMA_SHADOW0
+ offset
+ (i
<< 2));
360 static inline void edma_shadow0_write(struct edma_cc
*ecc
, int offset
,
363 edma_write(ecc
, EDMA_SHADOW0
+ offset
, val
);
366 static inline void edma_shadow0_write_array(struct edma_cc
*ecc
, int offset
,
369 edma_write(ecc
, EDMA_SHADOW0
+ offset
+ (i
<< 2), val
);
372 static inline unsigned int edma_param_read(struct edma_cc
*ecc
, int offset
,
375 return edma_read(ecc
, EDMA_PARM
+ offset
+ (param_no
<< 5));
378 static inline void edma_param_write(struct edma_cc
*ecc
, int offset
,
379 int param_no
, unsigned val
)
381 edma_write(ecc
, EDMA_PARM
+ offset
+ (param_no
<< 5), val
);
384 static inline void edma_param_modify(struct edma_cc
*ecc
, int offset
,
385 int param_no
, unsigned and, unsigned or)
387 edma_modify(ecc
, EDMA_PARM
+ offset
+ (param_no
<< 5), and, or);
390 static inline void edma_param_and(struct edma_cc
*ecc
, int offset
, int param_no
,
393 edma_and(ecc
, EDMA_PARM
+ offset
+ (param_no
<< 5), and);
396 static inline void edma_param_or(struct edma_cc
*ecc
, int offset
, int param_no
,
399 edma_or(ecc
, EDMA_PARM
+ offset
+ (param_no
<< 5), or);
402 static inline void set_bits(int offset
, int len
, unsigned long *p
)
404 for (; len
> 0; len
--)
405 set_bit(offset
+ (len
- 1), p
);
408 static inline void clear_bits(int offset
, int len
, unsigned long *p
)
410 for (; len
> 0; len
--)
411 clear_bit(offset
+ (len
- 1), p
);
414 static void edma_assign_priority_to_queue(struct edma_cc
*ecc
, int queue_no
,
417 int bit
= queue_no
* 4;
419 edma_modify(ecc
, EDMA_QUEPRI
, ~(0x7 << bit
), ((priority
& 0x7) << bit
));
422 static void edma_set_chmap(struct edma_chan
*echan
, int slot
)
424 struct edma_cc
*ecc
= echan
->ecc
;
425 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
427 if (ecc
->chmap_exist
) {
428 slot
= EDMA_CHAN_SLOT(slot
);
429 edma_write_array(ecc
, EDMA_DCHMAP
, channel
, (slot
<< 5));
433 static void edma_setup_interrupt(struct edma_chan
*echan
, bool enable
)
435 struct edma_cc
*ecc
= echan
->ecc
;
436 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
439 edma_shadow0_write_array(ecc
, SH_ICR
, channel
>> 5,
440 BIT(channel
& 0x1f));
441 edma_shadow0_write_array(ecc
, SH_IESR
, channel
>> 5,
442 BIT(channel
& 0x1f));
444 edma_shadow0_write_array(ecc
, SH_IECR
, channel
>> 5,
445 BIT(channel
& 0x1f));
450 * paRAM slot management functions
452 static void edma_write_slot(struct edma_cc
*ecc
, unsigned slot
,
453 const struct edmacc_param
*param
)
455 slot
= EDMA_CHAN_SLOT(slot
);
456 if (slot
>= ecc
->num_slots
)
458 memcpy_toio(ecc
->base
+ PARM_OFFSET(slot
), param
, PARM_SIZE
);
461 static void edma_read_slot(struct edma_cc
*ecc
, unsigned slot
,
462 struct edmacc_param
*param
)
464 slot
= EDMA_CHAN_SLOT(slot
);
465 if (slot
>= ecc
->num_slots
)
467 memcpy_fromio(param
, ecc
->base
+ PARM_OFFSET(slot
), PARM_SIZE
);
471 * edma_alloc_slot - allocate DMA parameter RAM
472 * @ecc: pointer to edma_cc struct
473 * @slot: specific slot to allocate; negative for "any unused slot"
475 * This allocates a parameter RAM slot, initializing it to hold a
476 * dummy transfer. Slots allocated using this routine have not been
477 * mapped to a hardware DMA channel, and will normally be used by
478 * linking to them from a slot associated with a DMA channel.
480 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
481 * slots may be allocated on behalf of DSP firmware.
483 * Returns the number of the slot, else negative errno.
485 static int edma_alloc_slot(struct edma_cc
*ecc
, int slot
)
488 slot
= EDMA_CHAN_SLOT(slot
);
489 /* Requesting entry paRAM slot for a HW triggered channel. */
490 if (ecc
->chmap_exist
&& slot
< ecc
->num_channels
)
491 slot
= EDMA_SLOT_ANY
;
495 if (ecc
->chmap_exist
)
498 slot
= ecc
->num_channels
;
500 slot
= find_next_zero_bit(ecc
->slot_inuse
,
503 if (slot
== ecc
->num_slots
)
505 if (!test_and_set_bit(slot
, ecc
->slot_inuse
))
508 } else if (slot
>= ecc
->num_slots
) {
510 } else if (test_and_set_bit(slot
, ecc
->slot_inuse
)) {
514 edma_write_slot(ecc
, slot
, &dummy_paramset
);
516 return EDMA_CTLR_CHAN(ecc
->id
, slot
);
519 static void edma_free_slot(struct edma_cc
*ecc
, unsigned slot
)
521 slot
= EDMA_CHAN_SLOT(slot
);
522 if (slot
>= ecc
->num_slots
)
525 edma_write_slot(ecc
, slot
, &dummy_paramset
);
526 clear_bit(slot
, ecc
->slot_inuse
);
530 * edma_link - link one parameter RAM slot to another
531 * @ecc: pointer to edma_cc struct
532 * @from: parameter RAM slot originating the link
533 * @to: parameter RAM slot which is the link target
535 * The originating slot should not be part of any active DMA transfer.
537 static void edma_link(struct edma_cc
*ecc
, unsigned from
, unsigned to
)
539 if (unlikely(EDMA_CTLR(from
) != EDMA_CTLR(to
)))
540 dev_warn(ecc
->dev
, "Ignoring eDMA instance for linking\n");
542 from
= EDMA_CHAN_SLOT(from
);
543 to
= EDMA_CHAN_SLOT(to
);
544 if (from
>= ecc
->num_slots
|| to
>= ecc
->num_slots
)
547 edma_param_modify(ecc
, PARM_LINK_BCNTRLD
, from
, 0xffff0000,
552 * edma_get_position - returns the current transfer point
553 * @ecc: pointer to edma_cc struct
554 * @slot: parameter RAM slot being examined
555 * @dst: true selects the dest position, false the source
557 * Returns the position of the current active slot
559 static dma_addr_t
edma_get_position(struct edma_cc
*ecc
, unsigned slot
,
564 slot
= EDMA_CHAN_SLOT(slot
);
565 offs
= PARM_OFFSET(slot
);
566 offs
+= dst
? PARM_DST
: PARM_SRC
;
568 return edma_read(ecc
, offs
);
572 * Channels with event associations will be triggered by their hardware
573 * events, and channels without such associations will be triggered by
574 * software. (At this writing there is no interface for using software
575 * triggers except with channels that don't support hardware triggers.)
577 static void edma_start(struct edma_chan
*echan
)
579 struct edma_cc
*ecc
= echan
->ecc
;
580 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
581 int j
= (channel
>> 5);
582 unsigned int mask
= BIT(channel
& 0x1f);
584 if (!echan
->hw_triggered
) {
585 /* EDMA channels without event association */
586 dev_dbg(ecc
->dev
, "ESR%d %08x\n", j
,
587 edma_shadow0_read_array(ecc
, SH_ESR
, j
));
588 edma_shadow0_write_array(ecc
, SH_ESR
, j
, mask
);
590 /* EDMA channel with event association */
591 dev_dbg(ecc
->dev
, "ER%d %08x\n", j
,
592 edma_shadow0_read_array(ecc
, SH_ER
, j
));
593 /* Clear any pending event or error */
594 edma_write_array(ecc
, EDMA_ECR
, j
, mask
);
595 edma_write_array(ecc
, EDMA_EMCR
, j
, mask
);
597 edma_shadow0_write_array(ecc
, SH_SECR
, j
, mask
);
598 edma_shadow0_write_array(ecc
, SH_EESR
, j
, mask
);
599 dev_dbg(ecc
->dev
, "EER%d %08x\n", j
,
600 edma_shadow0_read_array(ecc
, SH_EER
, j
));
604 static void edma_stop(struct edma_chan
*echan
)
606 struct edma_cc
*ecc
= echan
->ecc
;
607 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
608 int j
= (channel
>> 5);
609 unsigned int mask
= BIT(channel
& 0x1f);
611 edma_shadow0_write_array(ecc
, SH_EECR
, j
, mask
);
612 edma_shadow0_write_array(ecc
, SH_ECR
, j
, mask
);
613 edma_shadow0_write_array(ecc
, SH_SECR
, j
, mask
);
614 edma_write_array(ecc
, EDMA_EMCR
, j
, mask
);
616 /* clear possibly pending completion interrupt */
617 edma_shadow0_write_array(ecc
, SH_ICR
, j
, mask
);
619 dev_dbg(ecc
->dev
, "EER%d %08x\n", j
,
620 edma_shadow0_read_array(ecc
, SH_EER
, j
));
622 /* REVISIT: consider guarding against inappropriate event
623 * chaining by overwriting with dummy_paramset.
628 * Temporarily disable EDMA hardware events on the specified channel,
629 * preventing them from triggering new transfers
631 static void edma_pause(struct edma_chan
*echan
)
633 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
634 unsigned int mask
= BIT(channel
& 0x1f);
636 edma_shadow0_write_array(echan
->ecc
, SH_EECR
, channel
>> 5, mask
);
639 /* Re-enable EDMA hardware events on the specified channel. */
640 static void edma_resume(struct edma_chan
*echan
)
642 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
643 unsigned int mask
= BIT(channel
& 0x1f);
645 edma_shadow0_write_array(echan
->ecc
, SH_EESR
, channel
>> 5, mask
);
648 static void edma_trigger_channel(struct edma_chan
*echan
)
650 struct edma_cc
*ecc
= echan
->ecc
;
651 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
652 unsigned int mask
= BIT(channel
& 0x1f);
654 edma_shadow0_write_array(ecc
, SH_ESR
, (channel
>> 5), mask
);
656 dev_dbg(ecc
->dev
, "ESR%d %08x\n", (channel
>> 5),
657 edma_shadow0_read_array(ecc
, SH_ESR
, (channel
>> 5)));
660 static void edma_clean_channel(struct edma_chan
*echan
)
662 struct edma_cc
*ecc
= echan
->ecc
;
663 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
664 int j
= (channel
>> 5);
665 unsigned int mask
= BIT(channel
& 0x1f);
667 dev_dbg(ecc
->dev
, "EMR%d %08x\n", j
, edma_read_array(ecc
, EDMA_EMR
, j
));
668 edma_shadow0_write_array(ecc
, SH_ECR
, j
, mask
);
669 /* Clear the corresponding EMR bits */
670 edma_write_array(ecc
, EDMA_EMCR
, j
, mask
);
672 edma_shadow0_write_array(ecc
, SH_SECR
, j
, mask
);
673 edma_write(ecc
, EDMA_CCERRCLR
, BIT(16) | BIT(1) | BIT(0));
676 /* Move channel to a specific event queue */
677 static void edma_assign_channel_eventq(struct edma_chan
*echan
,
678 enum dma_event_q eventq_no
)
680 struct edma_cc
*ecc
= echan
->ecc
;
681 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
682 int bit
= (channel
& 0x7) * 4;
684 /* default to low priority queue */
685 if (eventq_no
== EVENTQ_DEFAULT
)
686 eventq_no
= ecc
->default_queue
;
687 if (eventq_no
>= ecc
->num_tc
)
691 edma_modify_array(ecc
, EDMA_DMAQNUM
, (channel
>> 3), ~(0x7 << bit
),
695 static int edma_alloc_channel(struct edma_chan
*echan
,
696 enum dma_event_q eventq_no
)
698 struct edma_cc
*ecc
= echan
->ecc
;
699 int channel
= EDMA_CHAN_SLOT(echan
->ch_num
);
701 /* ensure access through shadow region 0 */
702 edma_or_array2(ecc
, EDMA_DRAE
, 0, channel
>> 5, BIT(channel
& 0x1f));
704 /* ensure no events are pending */
707 edma_setup_interrupt(echan
, true);
709 edma_assign_channel_eventq(echan
, eventq_no
);
714 static void edma_free_channel(struct edma_chan
*echan
)
716 /* ensure no events are pending */
718 /* REVISIT should probably take out of shadow region 0 */
719 edma_setup_interrupt(echan
, false);
722 static inline struct edma_cc
*to_edma_cc(struct dma_device
*d
)
724 return container_of(d
, struct edma_cc
, dma_slave
);
727 static inline struct edma_chan
*to_edma_chan(struct dma_chan
*c
)
729 return container_of(c
, struct edma_chan
, vchan
.chan
);
732 static inline struct edma_desc
*to_edma_desc(struct dma_async_tx_descriptor
*tx
)
734 return container_of(tx
, struct edma_desc
, vdesc
.tx
);
737 static void edma_desc_free(struct virt_dma_desc
*vdesc
)
739 kfree(container_of(vdesc
, struct edma_desc
, vdesc
));
742 /* Dispatch a queued descriptor to the controller (caller holds lock) */
743 static void edma_execute(struct edma_chan
*echan
)
745 struct edma_cc
*ecc
= echan
->ecc
;
746 struct virt_dma_desc
*vdesc
;
747 struct edma_desc
*edesc
;
748 struct device
*dev
= echan
->vchan
.chan
.device
->dev
;
749 int i
, j
, left
, nslots
;
752 /* Setup is needed for the first transfer */
753 vdesc
= vchan_next_desc(&echan
->vchan
);
756 list_del(&vdesc
->node
);
757 echan
->edesc
= to_edma_desc(&vdesc
->tx
);
760 edesc
= echan
->edesc
;
762 /* Find out how many left */
763 left
= edesc
->pset_nr
- edesc
->processed
;
764 nslots
= min(MAX_NR_SG
, left
);
767 /* Write descriptor PaRAM set(s) */
768 for (i
= 0; i
< nslots
; i
++) {
769 j
= i
+ edesc
->processed
;
770 edma_write_slot(ecc
, echan
->slot
[i
], &edesc
->pset
[j
].param
);
771 edesc
->sg_len
+= edesc
->pset
[j
].len
;
784 j
, echan
->ch_num
, echan
->slot
[i
],
785 edesc
->pset
[j
].param
.opt
,
786 edesc
->pset
[j
].param
.src
,
787 edesc
->pset
[j
].param
.dst
,
788 edesc
->pset
[j
].param
.a_b_cnt
,
789 edesc
->pset
[j
].param
.ccnt
,
790 edesc
->pset
[j
].param
.src_dst_bidx
,
791 edesc
->pset
[j
].param
.src_dst_cidx
,
792 edesc
->pset
[j
].param
.link_bcntrld
);
793 /* Link to the previous slot if not the last set */
794 if (i
!= (nslots
- 1))
795 edma_link(ecc
, echan
->slot
[i
], echan
->slot
[i
+ 1]);
798 edesc
->processed
+= nslots
;
801 * If this is either the last set in a set of SG-list transactions
802 * then setup a link to the dummy slot, this results in all future
803 * events being absorbed and that's OK because we're done
805 if (edesc
->processed
== edesc
->pset_nr
) {
807 edma_link(ecc
, echan
->slot
[nslots
- 1], echan
->slot
[1]);
809 edma_link(ecc
, echan
->slot
[nslots
- 1],
810 echan
->ecc
->dummy_slot
);
815 * This happens due to setup times between intermediate
816 * transfers in long SG lists which have to be broken up into
817 * transfers of MAX_NR_SG
819 dev_dbg(dev
, "missed event on channel %d\n", echan
->ch_num
);
820 edma_clean_channel(echan
);
823 edma_trigger_channel(echan
);
825 } else if (edesc
->processed
<= MAX_NR_SG
) {
826 dev_dbg(dev
, "first transfer starting on channel %d\n",
830 dev_dbg(dev
, "chan: %d: completed %d elements, resuming\n",
831 echan
->ch_num
, edesc
->processed
);
836 static int edma_terminate_all(struct dma_chan
*chan
)
838 struct edma_chan
*echan
= to_edma_chan(chan
);
842 spin_lock_irqsave(&echan
->vchan
.lock
, flags
);
845 * Stop DMA activity: we assume the callback will not be called
846 * after edma_dma() returns (even if it does, it will see
847 * echan->edesc is NULL and exit.)
851 /* Move the cyclic channel back to default queue */
852 if (!echan
->tc
&& echan
->edesc
->cyclic
)
853 edma_assign_channel_eventq(echan
, EVENTQ_DEFAULT
);
855 * free the running request descriptor
856 * since it is not in any of the vdesc lists
858 edma_desc_free(&echan
->edesc
->vdesc
);
862 vchan_get_all_descriptors(&echan
->vchan
, &head
);
863 spin_unlock_irqrestore(&echan
->vchan
.lock
, flags
);
864 vchan_dma_desc_free_list(&echan
->vchan
, &head
);
869 static void edma_synchronize(struct dma_chan
*chan
)
871 struct edma_chan
*echan
= to_edma_chan(chan
);
873 vchan_synchronize(&echan
->vchan
);
876 static int edma_slave_config(struct dma_chan
*chan
,
877 struct dma_slave_config
*cfg
)
879 struct edma_chan
*echan
= to_edma_chan(chan
);
881 if (cfg
->src_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
||
882 cfg
->dst_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
)
885 memcpy(&echan
->cfg
, cfg
, sizeof(echan
->cfg
));
890 static int edma_dma_pause(struct dma_chan
*chan
)
892 struct edma_chan
*echan
= to_edma_chan(chan
);
901 static int edma_dma_resume(struct dma_chan
*chan
)
903 struct edma_chan
*echan
= to_edma_chan(chan
);
910 * A PaRAM set configuration abstraction used by other modes
911 * @chan: Channel who's PaRAM set we're configuring
912 * @pset: PaRAM set to initialize and setup.
913 * @src_addr: Source address of the DMA
914 * @dst_addr: Destination address of the DMA
915 * @burst: In units of dev_width, how much to send
916 * @dev_width: How much is the dev_width
917 * @dma_length: Total length of the DMA transfer
918 * @direction: Direction of the transfer
920 static int edma_config_pset(struct dma_chan
*chan
, struct edma_pset
*epset
,
921 dma_addr_t src_addr
, dma_addr_t dst_addr
, u32 burst
,
922 unsigned int acnt
, unsigned int dma_length
,
923 enum dma_transfer_direction direction
)
925 struct edma_chan
*echan
= to_edma_chan(chan
);
926 struct device
*dev
= chan
->device
->dev
;
927 struct edmacc_param
*param
= &epset
->param
;
928 int bcnt
, ccnt
, cidx
;
929 int src_bidx
, dst_bidx
, src_cidx
, dst_cidx
;
932 /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
936 * If the maxburst is equal to the fifo width, use
937 * A-synced transfers. This allows for large contiguous
938 * buffer transfers using only one PaRAM set.
942 * For the A-sync case, bcnt and ccnt are the remainder
943 * and quotient respectively of the division of:
944 * (dma_length / acnt) by (SZ_64K -1). This is so
945 * that in case bcnt over flows, we have ccnt to use.
946 * Note: In A-sync tranfer only, bcntrld is used, but it
947 * only applies for sg_dma_len(sg) >= SZ_64K.
948 * In this case, the best way adopted is- bccnt for the
949 * first frame will be the remainder below. Then for
950 * every successive frame, bcnt will be SZ_64K-1. This
951 * is assured as bcntrld = 0xffff in end of function.
954 ccnt
= dma_length
/ acnt
/ (SZ_64K
- 1);
955 bcnt
= dma_length
/ acnt
- ccnt
* (SZ_64K
- 1);
957 * If bcnt is non-zero, we have a remainder and hence an
958 * extra frame to transfer, so increment ccnt.
967 * If maxburst is greater than the fifo address_width,
968 * use AB-synced transfers where A count is the fifo
969 * address_width and B count is the maxburst. In this
970 * case, we are limited to transfers of C count frames
971 * of (address_width * maxburst) where C count is limited
972 * to SZ_64K-1. This places an upper bound on the length
973 * of an SG segment that can be handled.
977 ccnt
= dma_length
/ (acnt
* bcnt
);
978 if (ccnt
> (SZ_64K
- 1)) {
979 dev_err(dev
, "Exceeded max SG segment size\n");
985 epset
->len
= dma_length
;
987 if (direction
== DMA_MEM_TO_DEV
) {
992 epset
->addr
= src_addr
;
993 } else if (direction
== DMA_DEV_TO_MEM
) {
998 epset
->addr
= dst_addr
;
999 } else if (direction
== DMA_MEM_TO_MEM
) {
1005 dev_err(dev
, "%s: direction not implemented yet\n", __func__
);
1009 param
->opt
= EDMA_TCC(EDMA_CHAN_SLOT(echan
->ch_num
));
1010 /* Configure A or AB synchronized transfers */
1012 param
->opt
|= SYNCDIM
;
1014 param
->src
= src_addr
;
1015 param
->dst
= dst_addr
;
1017 param
->src_dst_bidx
= (dst_bidx
<< 16) | src_bidx
;
1018 param
->src_dst_cidx
= (dst_cidx
<< 16) | src_cidx
;
1020 param
->a_b_cnt
= bcnt
<< 16 | acnt
;
1023 * Only time when (bcntrld) auto reload is required is for
1024 * A-sync case, and in this case, a requirement of reload value
1025 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
1026 * and then later will be populated by edma_execute.
1028 param
->link_bcntrld
= 0xffffffff;
1032 static struct dma_async_tx_descriptor
*edma_prep_slave_sg(
1033 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1034 unsigned int sg_len
, enum dma_transfer_direction direction
,
1035 unsigned long tx_flags
, void *context
)
1037 struct edma_chan
*echan
= to_edma_chan(chan
);
1038 struct device
*dev
= chan
->device
->dev
;
1039 struct edma_desc
*edesc
;
1040 dma_addr_t src_addr
= 0, dst_addr
= 0;
1041 enum dma_slave_buswidth dev_width
;
1043 struct scatterlist
*sg
;
1046 if (unlikely(!echan
|| !sgl
|| !sg_len
))
1049 if (direction
== DMA_DEV_TO_MEM
) {
1050 src_addr
= echan
->cfg
.src_addr
;
1051 dev_width
= echan
->cfg
.src_addr_width
;
1052 burst
= echan
->cfg
.src_maxburst
;
1053 } else if (direction
== DMA_MEM_TO_DEV
) {
1054 dst_addr
= echan
->cfg
.dst_addr
;
1055 dev_width
= echan
->cfg
.dst_addr_width
;
1056 burst
= echan
->cfg
.dst_maxburst
;
1058 dev_err(dev
, "%s: bad direction: %d\n", __func__
, direction
);
1062 if (dev_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
) {
1063 dev_err(dev
, "%s: Undefined slave buswidth\n", __func__
);
1067 edesc
= kzalloc(sizeof(*edesc
) + sg_len
* sizeof(edesc
->pset
[0]),
1070 dev_err(dev
, "%s: Failed to allocate a descriptor\n", __func__
);
1074 edesc
->pset_nr
= sg_len
;
1076 edesc
->direction
= direction
;
1077 edesc
->echan
= echan
;
1079 /* Allocate a PaRAM slot, if needed */
1080 nslots
= min_t(unsigned, MAX_NR_SG
, sg_len
);
1082 for (i
= 0; i
< nslots
; i
++) {
1083 if (echan
->slot
[i
] < 0) {
1085 edma_alloc_slot(echan
->ecc
, EDMA_SLOT_ANY
);
1086 if (echan
->slot
[i
] < 0) {
1088 dev_err(dev
, "%s: Failed to allocate slot\n",
1095 /* Configure PaRAM sets for each SG */
1096 for_each_sg(sgl
, sg
, sg_len
, i
) {
1097 /* Get address for each SG */
1098 if (direction
== DMA_DEV_TO_MEM
)
1099 dst_addr
= sg_dma_address(sg
);
1101 src_addr
= sg_dma_address(sg
);
1103 ret
= edma_config_pset(chan
, &edesc
->pset
[i
], src_addr
,
1104 dst_addr
, burst
, dev_width
,
1105 sg_dma_len(sg
), direction
);
1111 edesc
->absync
= ret
;
1112 edesc
->residue
+= sg_dma_len(sg
);
1114 /* If this is the last in a current SG set of transactions,
1115 enable interrupts so that next set is processed */
1116 if (!((i
+1) % MAX_NR_SG
))
1117 edesc
->pset
[i
].param
.opt
|= TCINTEN
;
1119 /* If this is the last set, enable completion interrupt flag */
1120 if (i
== sg_len
- 1)
1121 edesc
->pset
[i
].param
.opt
|= TCINTEN
;
1123 edesc
->residue_stat
= edesc
->residue
;
1125 return vchan_tx_prep(&echan
->vchan
, &edesc
->vdesc
, tx_flags
);
1128 static struct dma_async_tx_descriptor
*edma_prep_dma_memcpy(
1129 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1130 size_t len
, unsigned long tx_flags
)
1133 struct edma_desc
*edesc
;
1134 struct device
*dev
= chan
->device
->dev
;
1135 struct edma_chan
*echan
= to_edma_chan(chan
);
1136 unsigned int width
, pset_len
;
1138 if (unlikely(!echan
|| !len
))
1143 * Transfer size less than 64K can be handled with one paRAM
1144 * slot and with one burst.
1152 * Transfer size bigger than 64K will be handled with maximum of
1154 * slot1: (full_length / 32767) times 32767 bytes bursts.
1155 * ACNT = 32767, length1: (full_length / 32767) * 32767
1156 * slot2: the remaining amount of data after slot1.
1157 * ACNT = full_length - length1, length2 = ACNT
1159 * When the full_length is multibple of 32767 one slot can be
1160 * used to complete the transfer.
1163 pset_len
= rounddown(len
, width
);
1164 /* One slot is enough for lengths multiple of (SZ_32K -1) */
1165 if (unlikely(pset_len
== len
))
1171 edesc
= kzalloc(sizeof(*edesc
) + nslots
* sizeof(edesc
->pset
[0]),
1174 dev_dbg(dev
, "Failed to allocate a descriptor\n");
1178 edesc
->pset_nr
= nslots
;
1179 edesc
->residue
= edesc
->residue_stat
= len
;
1180 edesc
->direction
= DMA_MEM_TO_MEM
;
1181 edesc
->echan
= echan
;
1183 ret
= edma_config_pset(chan
, &edesc
->pset
[0], src
, dest
, 1,
1184 width
, pset_len
, DMA_MEM_TO_MEM
);
1190 edesc
->absync
= ret
;
1192 edesc
->pset
[0].param
.opt
|= ITCCHEN
;
1194 /* Enable transfer complete interrupt */
1195 edesc
->pset
[0].param
.opt
|= TCINTEN
;
1197 /* Enable transfer complete chaining for the first slot */
1198 edesc
->pset
[0].param
.opt
|= TCCHEN
;
1200 if (echan
->slot
[1] < 0) {
1201 echan
->slot
[1] = edma_alloc_slot(echan
->ecc
,
1203 if (echan
->slot
[1] < 0) {
1205 dev_err(dev
, "%s: Failed to allocate slot\n",
1212 pset_len
= width
= len
% (SZ_32K
- 1);
1214 ret
= edma_config_pset(chan
, &edesc
->pset
[1], src
, dest
, 1,
1215 width
, pset_len
, DMA_MEM_TO_MEM
);
1221 edesc
->pset
[1].param
.opt
|= ITCCHEN
;
1222 edesc
->pset
[1].param
.opt
|= TCINTEN
;
1225 return vchan_tx_prep(&echan
->vchan
, &edesc
->vdesc
, tx_flags
);
1228 static struct dma_async_tx_descriptor
*edma_prep_dma_cyclic(
1229 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
1230 size_t period_len
, enum dma_transfer_direction direction
,
1231 unsigned long tx_flags
)
1233 struct edma_chan
*echan
= to_edma_chan(chan
);
1234 struct device
*dev
= chan
->device
->dev
;
1235 struct edma_desc
*edesc
;
1236 dma_addr_t src_addr
, dst_addr
;
1237 enum dma_slave_buswidth dev_width
;
1241 if (unlikely(!echan
|| !buf_len
|| !period_len
))
1244 if (direction
== DMA_DEV_TO_MEM
) {
1245 src_addr
= echan
->cfg
.src_addr
;
1246 dst_addr
= buf_addr
;
1247 dev_width
= echan
->cfg
.src_addr_width
;
1248 burst
= echan
->cfg
.src_maxburst
;
1249 } else if (direction
== DMA_MEM_TO_DEV
) {
1250 src_addr
= buf_addr
;
1251 dst_addr
= echan
->cfg
.dst_addr
;
1252 dev_width
= echan
->cfg
.dst_addr_width
;
1253 burst
= echan
->cfg
.dst_maxburst
;
1255 dev_err(dev
, "%s: bad direction: %d\n", __func__
, direction
);
1259 if (dev_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
) {
1260 dev_err(dev
, "%s: Undefined slave buswidth\n", __func__
);
1264 if (unlikely(buf_len
% period_len
)) {
1265 dev_err(dev
, "Period should be multiple of Buffer length\n");
1269 nslots
= (buf_len
/ period_len
) + 1;
1272 * Cyclic DMA users such as audio cannot tolerate delays introduced
1273 * by cases where the number of periods is more than the maximum
1274 * number of SGs the EDMA driver can handle at a time. For DMA types
1275 * such as Slave SGs, such delays are tolerable and synchronized,
1276 * but the synchronization is difficult to achieve with Cyclic and
1277 * cannot be guaranteed, so we error out early.
1279 if (nslots
> MAX_NR_SG
)
1282 edesc
= kzalloc(sizeof(*edesc
) + nslots
* sizeof(edesc
->pset
[0]),
1285 dev_err(dev
, "%s: Failed to allocate a descriptor\n", __func__
);
1290 edesc
->pset_nr
= nslots
;
1291 edesc
->residue
= edesc
->residue_stat
= buf_len
;
1292 edesc
->direction
= direction
;
1293 edesc
->echan
= echan
;
1295 dev_dbg(dev
, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1296 __func__
, echan
->ch_num
, nslots
, period_len
, buf_len
);
1298 for (i
= 0; i
< nslots
; i
++) {
1299 /* Allocate a PaRAM slot, if needed */
1300 if (echan
->slot
[i
] < 0) {
1302 edma_alloc_slot(echan
->ecc
, EDMA_SLOT_ANY
);
1303 if (echan
->slot
[i
] < 0) {
1305 dev_err(dev
, "%s: Failed to allocate slot\n",
1311 if (i
== nslots
- 1) {
1312 memcpy(&edesc
->pset
[i
], &edesc
->pset
[0],
1313 sizeof(edesc
->pset
[0]));
1317 ret
= edma_config_pset(chan
, &edesc
->pset
[i
], src_addr
,
1318 dst_addr
, burst
, dev_width
, period_len
,
1325 if (direction
== DMA_DEV_TO_MEM
)
1326 dst_addr
+= period_len
;
1328 src_addr
+= period_len
;
1330 dev_vdbg(dev
, "%s: Configure period %d of buf:\n", __func__
, i
);
1343 i
, echan
->ch_num
, echan
->slot
[i
],
1344 edesc
->pset
[i
].param
.opt
,
1345 edesc
->pset
[i
].param
.src
,
1346 edesc
->pset
[i
].param
.dst
,
1347 edesc
->pset
[i
].param
.a_b_cnt
,
1348 edesc
->pset
[i
].param
.ccnt
,
1349 edesc
->pset
[i
].param
.src_dst_bidx
,
1350 edesc
->pset
[i
].param
.src_dst_cidx
,
1351 edesc
->pset
[i
].param
.link_bcntrld
);
1353 edesc
->absync
= ret
;
1356 * Enable period interrupt only if it is requested
1358 if (tx_flags
& DMA_PREP_INTERRUPT
)
1359 edesc
->pset
[i
].param
.opt
|= TCINTEN
;
1362 /* Place the cyclic channel to highest priority queue */
1364 edma_assign_channel_eventq(echan
, EVENTQ_0
);
1366 return vchan_tx_prep(&echan
->vchan
, &edesc
->vdesc
, tx_flags
);
1369 static void edma_completion_handler(struct edma_chan
*echan
)
1371 struct device
*dev
= echan
->vchan
.chan
.device
->dev
;
1372 struct edma_desc
*edesc
= echan
->edesc
;
1377 spin_lock(&echan
->vchan
.lock
);
1378 if (edesc
->cyclic
) {
1379 vchan_cyclic_callback(&edesc
->vdesc
);
1380 spin_unlock(&echan
->vchan
.lock
);
1382 } else if (edesc
->processed
== edesc
->pset_nr
) {
1385 vchan_cookie_complete(&edesc
->vdesc
);
1386 echan
->edesc
= NULL
;
1388 dev_dbg(dev
, "Transfer completed on channel %d\n",
1391 dev_dbg(dev
, "Sub transfer completed on channel %d\n",
1396 /* Update statistics for tx_status */
1397 edesc
->residue
-= edesc
->sg_len
;
1398 edesc
->residue_stat
= edesc
->residue
;
1399 edesc
->processed_stat
= edesc
->processed
;
1401 edma_execute(echan
);
1403 spin_unlock(&echan
->vchan
.lock
);
1406 /* eDMA interrupt handler */
1407 static irqreturn_t
dma_irq_handler(int irq
, void *data
)
1409 struct edma_cc
*ecc
= data
;
1419 dev_vdbg(ecc
->dev
, "dma_irq_handler\n");
1421 sh_ipr
= edma_shadow0_read_array(ecc
, SH_IPR
, 0);
1423 sh_ipr
= edma_shadow0_read_array(ecc
, SH_IPR
, 1);
1426 sh_ier
= edma_shadow0_read_array(ecc
, SH_IER
, 1);
1429 sh_ier
= edma_shadow0_read_array(ecc
, SH_IER
, 0);
1437 slot
= __ffs(sh_ipr
);
1438 sh_ipr
&= ~(BIT(slot
));
1440 if (sh_ier
& BIT(slot
)) {
1441 channel
= (bank
<< 5) | slot
;
1442 /* Clear the corresponding IPR bits */
1443 edma_shadow0_write_array(ecc
, SH_ICR
, bank
, BIT(slot
));
1444 edma_completion_handler(&ecc
->slave_chans
[channel
]);
1448 edma_shadow0_write(ecc
, SH_IEVAL
, 1);
1452 static void edma_error_handler(struct edma_chan
*echan
)
1454 struct edma_cc
*ecc
= echan
->ecc
;
1455 struct device
*dev
= echan
->vchan
.chan
.device
->dev
;
1456 struct edmacc_param p
;
1461 spin_lock(&echan
->vchan
.lock
);
1463 edma_read_slot(ecc
, echan
->slot
[0], &p
);
1465 * Issue later based on missed flag which will be sure
1467 * (1) we finished transmitting an intermediate slot and
1468 * edma_execute is coming up.
1469 * (2) or we finished current transfer and issue will
1470 * call edma_execute.
1472 * Important note: issuing can be dangerous here and
1473 * lead to some nasty recursion when we are in a NULL
1474 * slot. So we avoid doing so and set the missed flag.
1476 if (p
.a_b_cnt
== 0 && p
.ccnt
== 0) {
1477 dev_dbg(dev
, "Error on null slot, setting miss\n");
1481 * The slot is already programmed but the event got
1482 * missed, so its safe to issue it here.
1484 dev_dbg(dev
, "Missed event, TRIGGERING\n");
1485 edma_clean_channel(echan
);
1488 edma_trigger_channel(echan
);
1490 spin_unlock(&echan
->vchan
.lock
);
1493 static inline bool edma_error_pending(struct edma_cc
*ecc
)
1495 if (edma_read_array(ecc
, EDMA_EMR
, 0) ||
1496 edma_read_array(ecc
, EDMA_EMR
, 1) ||
1497 edma_read(ecc
, EDMA_QEMR
) || edma_read(ecc
, EDMA_CCERR
))
1503 /* eDMA error interrupt handler */
1504 static irqreturn_t
dma_ccerr_handler(int irq
, void *data
)
1506 struct edma_cc
*ecc
= data
;
1509 unsigned int cnt
= 0;
1516 dev_vdbg(ecc
->dev
, "dma_ccerr_handler\n");
1518 if (!edma_error_pending(ecc
))
1522 /* Event missed register(s) */
1523 for (j
= 0; j
< 2; j
++) {
1526 val
= edma_read_array(ecc
, EDMA_EMR
, j
);
1530 dev_dbg(ecc
->dev
, "EMR%d 0x%08x\n", j
, val
);
1532 for (i
= find_next_bit(&emr
, 32, 0); i
< 32;
1533 i
= find_next_bit(&emr
, 32, i
+ 1)) {
1534 int k
= (j
<< 5) + i
;
1536 /* Clear the corresponding EMR bits */
1537 edma_write_array(ecc
, EDMA_EMCR
, j
, BIT(i
));
1539 edma_shadow0_write_array(ecc
, SH_SECR
, j
,
1541 edma_error_handler(&ecc
->slave_chans
[k
]);
1545 val
= edma_read(ecc
, EDMA_QEMR
);
1547 dev_dbg(ecc
->dev
, "QEMR 0x%02x\n", val
);
1548 /* Not reported, just clear the interrupt reason. */
1549 edma_write(ecc
, EDMA_QEMCR
, val
);
1550 edma_shadow0_write(ecc
, SH_QSECR
, val
);
1553 val
= edma_read(ecc
, EDMA_CCERR
);
1555 dev_warn(ecc
->dev
, "CCERR 0x%08x\n", val
);
1556 /* Not reported, just clear the interrupt reason. */
1557 edma_write(ecc
, EDMA_CCERRCLR
, val
);
1560 if (!edma_error_pending(ecc
))
1566 edma_write(ecc
, EDMA_EEVAL
, 1);
1570 static void edma_tc_set_pm_state(struct edma_tc
*tc
, bool enable
)
1572 struct platform_device
*tc_pdev
;
1575 if (!IS_ENABLED(CONFIG_OF
) || !tc
)
1578 tc_pdev
= of_find_device_by_node(tc
->node
);
1580 pr_err("%s: TPTC device is not found\n", __func__
);
1583 if (!pm_runtime_enabled(&tc_pdev
->dev
))
1584 pm_runtime_enable(&tc_pdev
->dev
);
1587 ret
= pm_runtime_get_sync(&tc_pdev
->dev
);
1589 ret
= pm_runtime_put_sync(&tc_pdev
->dev
);
1592 pr_err("%s: pm_runtime_%s_sync() failed for %s\n", __func__
,
1593 enable
? "get" : "put", dev_name(&tc_pdev
->dev
));
1596 /* Alloc channel resources */
1597 static int edma_alloc_chan_resources(struct dma_chan
*chan
)
1599 struct edma_chan
*echan
= to_edma_chan(chan
);
1600 struct edma_cc
*ecc
= echan
->ecc
;
1601 struct device
*dev
= ecc
->dev
;
1602 enum dma_event_q eventq_no
= EVENTQ_DEFAULT
;
1606 eventq_no
= echan
->tc
->id
;
1607 } else if (ecc
->tc_list
) {
1608 /* memcpy channel */
1609 echan
->tc
= &ecc
->tc_list
[ecc
->info
->default_queue
];
1610 eventq_no
= echan
->tc
->id
;
1613 ret
= edma_alloc_channel(echan
, eventq_no
);
1617 echan
->slot
[0] = edma_alloc_slot(ecc
, echan
->ch_num
);
1618 if (echan
->slot
[0] < 0) {
1619 dev_err(dev
, "Entry slot allocation failed for channel %u\n",
1620 EDMA_CHAN_SLOT(echan
->ch_num
));
1624 /* Set up channel -> slot mapping for the entry slot */
1625 edma_set_chmap(echan
, echan
->slot
[0]);
1626 echan
->alloced
= true;
1628 dev_dbg(dev
, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
1629 EDMA_CHAN_SLOT(echan
->ch_num
), chan
->chan_id
,
1630 echan
->hw_triggered
? "HW" : "SW");
1632 edma_tc_set_pm_state(echan
->tc
, true);
1637 edma_free_channel(echan
);
1641 /* Free channel resources */
1642 static void edma_free_chan_resources(struct dma_chan
*chan
)
1644 struct edma_chan
*echan
= to_edma_chan(chan
);
1645 struct device
*dev
= echan
->ecc
->dev
;
1648 /* Terminate transfers */
1651 vchan_free_chan_resources(&echan
->vchan
);
1653 /* Free EDMA PaRAM slots */
1654 for (i
= 0; i
< EDMA_MAX_SLOTS
; i
++) {
1655 if (echan
->slot
[i
] >= 0) {
1656 edma_free_slot(echan
->ecc
, echan
->slot
[i
]);
1657 echan
->slot
[i
] = -1;
1661 /* Set entry slot to the dummy slot */
1662 edma_set_chmap(echan
, echan
->ecc
->dummy_slot
);
1664 /* Free EDMA channel */
1665 if (echan
->alloced
) {
1666 edma_free_channel(echan
);
1667 echan
->alloced
= false;
1670 edma_tc_set_pm_state(echan
->tc
, false);
1672 echan
->hw_triggered
= false;
1674 dev_dbg(dev
, "Free eDMA channel %d for virt channel %d\n",
1675 EDMA_CHAN_SLOT(echan
->ch_num
), chan
->chan_id
);
1678 /* Send pending descriptor to hardware */
1679 static void edma_issue_pending(struct dma_chan
*chan
)
1681 struct edma_chan
*echan
= to_edma_chan(chan
);
1682 unsigned long flags
;
1684 spin_lock_irqsave(&echan
->vchan
.lock
, flags
);
1685 if (vchan_issue_pending(&echan
->vchan
) && !echan
->edesc
)
1686 edma_execute(echan
);
1687 spin_unlock_irqrestore(&echan
->vchan
.lock
, flags
);
1690 static u32
edma_residue(struct edma_desc
*edesc
)
1692 bool dst
= edesc
->direction
== DMA_DEV_TO_MEM
;
1693 struct edma_pset
*pset
= edesc
->pset
;
1694 dma_addr_t done
, pos
;
1698 * We always read the dst/src position from the first RamPar
1699 * pset. That's the one which is active now.
1701 pos
= edma_get_position(edesc
->echan
->ecc
, edesc
->echan
->slot
[0], dst
);
1704 * Cyclic is simple. Just subtract pset[0].addr from pos.
1706 * We never update edesc->residue in the cyclic case, so we
1707 * can tell the remaining room to the end of the circular
1710 if (edesc
->cyclic
) {
1711 done
= pos
- pset
->addr
;
1712 edesc
->residue_stat
= edesc
->residue
- done
;
1713 return edesc
->residue_stat
;
1717 * For SG operation we catch up with the last processed
1720 pset
+= edesc
->processed_stat
;
1722 for (i
= edesc
->processed_stat
; i
< edesc
->processed
; i
++, pset
++) {
1724 * If we are inside this pset address range, we know
1725 * this is the active one. Get the current delta and
1726 * stop walking the psets.
1728 if (pos
>= pset
->addr
&& pos
< pset
->addr
+ pset
->len
)
1729 return edesc
->residue_stat
- (pos
- pset
->addr
);
1731 /* Otherwise mark it done and update residue_stat. */
1732 edesc
->processed_stat
++;
1733 edesc
->residue_stat
-= pset
->len
;
1735 return edesc
->residue_stat
;
1738 /* Check request completion status */
1739 static enum dma_status
edma_tx_status(struct dma_chan
*chan
,
1740 dma_cookie_t cookie
,
1741 struct dma_tx_state
*txstate
)
1743 struct edma_chan
*echan
= to_edma_chan(chan
);
1744 struct virt_dma_desc
*vdesc
;
1745 enum dma_status ret
;
1746 unsigned long flags
;
1748 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1749 if (ret
== DMA_COMPLETE
|| !txstate
)
1752 spin_lock_irqsave(&echan
->vchan
.lock
, flags
);
1753 if (echan
->edesc
&& echan
->edesc
->vdesc
.tx
.cookie
== cookie
)
1754 txstate
->residue
= edma_residue(echan
->edesc
);
1755 else if ((vdesc
= vchan_find_desc(&echan
->vchan
, cookie
)))
1756 txstate
->residue
= to_edma_desc(&vdesc
->tx
)->residue
;
1757 spin_unlock_irqrestore(&echan
->vchan
.lock
, flags
);
1762 static bool edma_is_memcpy_channel(int ch_num
, s32
*memcpy_channels
)
1764 if (!memcpy_channels
)
1766 while (*memcpy_channels
!= -1) {
1767 if (*memcpy_channels
== ch_num
)
1774 #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1775 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1776 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
1777 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1779 static void edma_dma_init(struct edma_cc
*ecc
, bool legacy_mode
)
1781 struct dma_device
*s_ddev
= &ecc
->dma_slave
;
1782 struct dma_device
*m_ddev
= NULL
;
1783 s32
*memcpy_channels
= ecc
->info
->memcpy_channels
;
1786 dma_cap_zero(s_ddev
->cap_mask
);
1787 dma_cap_set(DMA_SLAVE
, s_ddev
->cap_mask
);
1788 dma_cap_set(DMA_CYCLIC
, s_ddev
->cap_mask
);
1789 if (ecc
->legacy_mode
&& !memcpy_channels
) {
1791 "Legacy memcpy is enabled, things might not work\n");
1793 dma_cap_set(DMA_MEMCPY
, s_ddev
->cap_mask
);
1794 s_ddev
->device_prep_dma_memcpy
= edma_prep_dma_memcpy
;
1795 s_ddev
->directions
= BIT(DMA_MEM_TO_MEM
);
1798 s_ddev
->device_prep_slave_sg
= edma_prep_slave_sg
;
1799 s_ddev
->device_prep_dma_cyclic
= edma_prep_dma_cyclic
;
1800 s_ddev
->device_alloc_chan_resources
= edma_alloc_chan_resources
;
1801 s_ddev
->device_free_chan_resources
= edma_free_chan_resources
;
1802 s_ddev
->device_issue_pending
= edma_issue_pending
;
1803 s_ddev
->device_tx_status
= edma_tx_status
;
1804 s_ddev
->device_config
= edma_slave_config
;
1805 s_ddev
->device_pause
= edma_dma_pause
;
1806 s_ddev
->device_resume
= edma_dma_resume
;
1807 s_ddev
->device_terminate_all
= edma_terminate_all
;
1808 s_ddev
->device_synchronize
= edma_synchronize
;
1810 s_ddev
->src_addr_widths
= EDMA_DMA_BUSWIDTHS
;
1811 s_ddev
->dst_addr_widths
= EDMA_DMA_BUSWIDTHS
;
1812 s_ddev
->directions
|= (BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
));
1813 s_ddev
->residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
1815 s_ddev
->dev
= ecc
->dev
;
1816 INIT_LIST_HEAD(&s_ddev
->channels
);
1818 if (memcpy_channels
) {
1819 m_ddev
= devm_kzalloc(ecc
->dev
, sizeof(*m_ddev
), GFP_KERNEL
);
1820 ecc
->dma_memcpy
= m_ddev
;
1822 dma_cap_zero(m_ddev
->cap_mask
);
1823 dma_cap_set(DMA_MEMCPY
, m_ddev
->cap_mask
);
1825 m_ddev
->device_prep_dma_memcpy
= edma_prep_dma_memcpy
;
1826 m_ddev
->device_alloc_chan_resources
= edma_alloc_chan_resources
;
1827 m_ddev
->device_free_chan_resources
= edma_free_chan_resources
;
1828 m_ddev
->device_issue_pending
= edma_issue_pending
;
1829 m_ddev
->device_tx_status
= edma_tx_status
;
1830 m_ddev
->device_config
= edma_slave_config
;
1831 m_ddev
->device_pause
= edma_dma_pause
;
1832 m_ddev
->device_resume
= edma_dma_resume
;
1833 m_ddev
->device_terminate_all
= edma_terminate_all
;
1834 m_ddev
->device_synchronize
= edma_synchronize
;
1836 m_ddev
->src_addr_widths
= EDMA_DMA_BUSWIDTHS
;
1837 m_ddev
->dst_addr_widths
= EDMA_DMA_BUSWIDTHS
;
1838 m_ddev
->directions
= BIT(DMA_MEM_TO_MEM
);
1839 m_ddev
->residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
1841 m_ddev
->dev
= ecc
->dev
;
1842 INIT_LIST_HEAD(&m_ddev
->channels
);
1843 } else if (!ecc
->legacy_mode
) {
1844 dev_info(ecc
->dev
, "memcpy is disabled\n");
1847 for (i
= 0; i
< ecc
->num_channels
; i
++) {
1848 struct edma_chan
*echan
= &ecc
->slave_chans
[i
];
1849 echan
->ch_num
= EDMA_CTLR_CHAN(ecc
->id
, i
);
1851 echan
->vchan
.desc_free
= edma_desc_free
;
1853 if (m_ddev
&& edma_is_memcpy_channel(i
, memcpy_channels
))
1854 vchan_init(&echan
->vchan
, m_ddev
);
1856 vchan_init(&echan
->vchan
, s_ddev
);
1858 INIT_LIST_HEAD(&echan
->node
);
1859 for (j
= 0; j
< EDMA_MAX_SLOTS
; j
++)
1860 echan
->slot
[j
] = -1;
1864 static int edma_setup_from_hw(struct device
*dev
, struct edma_soc_info
*pdata
,
1865 struct edma_cc
*ecc
)
1869 s8 (*queue_priority_map
)[2];
1871 /* Decode the eDMA3 configuration from CCCFG register */
1872 cccfg
= edma_read(ecc
, EDMA_CCCFG
);
1874 value
= GET_NUM_REGN(cccfg
);
1875 ecc
->num_region
= BIT(value
);
1877 value
= GET_NUM_DMACH(cccfg
);
1878 ecc
->num_channels
= BIT(value
+ 1);
1880 value
= GET_NUM_QDMACH(cccfg
);
1881 ecc
->num_qchannels
= value
* 2;
1883 value
= GET_NUM_PAENTRY(cccfg
);
1884 ecc
->num_slots
= BIT(value
+ 4);
1886 value
= GET_NUM_EVQUE(cccfg
);
1887 ecc
->num_tc
= value
+ 1;
1889 ecc
->chmap_exist
= (cccfg
& CHMAP_EXIST
) ? true : false;
1891 dev_dbg(dev
, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg
);
1892 dev_dbg(dev
, "num_region: %u\n", ecc
->num_region
);
1893 dev_dbg(dev
, "num_channels: %u\n", ecc
->num_channels
);
1894 dev_dbg(dev
, "num_qchannels: %u\n", ecc
->num_qchannels
);
1895 dev_dbg(dev
, "num_slots: %u\n", ecc
->num_slots
);
1896 dev_dbg(dev
, "num_tc: %u\n", ecc
->num_tc
);
1897 dev_dbg(dev
, "chmap_exist: %s\n", ecc
->chmap_exist
? "yes" : "no");
1899 /* Nothing need to be done if queue priority is provided */
1900 if (pdata
->queue_priority_mapping
)
1904 * Configure TC/queue priority as follows:
1909 * The meaning of priority numbers: 0 highest priority, 7 lowest
1910 * priority. So Q0 is the highest priority queue and the last queue has
1911 * the lowest priority.
1913 queue_priority_map
= devm_kcalloc(dev
, ecc
->num_tc
+ 1, sizeof(s8
),
1915 if (!queue_priority_map
)
1918 for (i
= 0; i
< ecc
->num_tc
; i
++) {
1919 queue_priority_map
[i
][0] = i
;
1920 queue_priority_map
[i
][1] = i
;
1922 queue_priority_map
[i
][0] = -1;
1923 queue_priority_map
[i
][1] = -1;
1925 pdata
->queue_priority_mapping
= queue_priority_map
;
1926 /* Default queue has the lowest priority */
1927 pdata
->default_queue
= i
- 1;
1932 #if IS_ENABLED(CONFIG_OF)
1933 static int edma_xbar_event_map(struct device
*dev
, struct edma_soc_info
*pdata
,
1936 const char pname
[] = "ti,edma-xbar-event-map";
1937 struct resource res
;
1939 s16 (*xbar_chans
)[2];
1940 size_t nelm
= sz
/ sizeof(s16
);
1941 u32 shift
, offset
, mux
;
1944 xbar_chans
= devm_kcalloc(dev
, nelm
+ 2, sizeof(s16
), GFP_KERNEL
);
1948 ret
= of_address_to_resource(dev
->of_node
, 1, &res
);
1952 xbar
= devm_ioremap(dev
, res
.start
, resource_size(&res
));
1956 ret
= of_property_read_u16_array(dev
->of_node
, pname
, (u16
*)xbar_chans
,
1961 /* Invalidate last entry for the other user of this mess */
1963 xbar_chans
[nelm
][0] = -1;
1964 xbar_chans
[nelm
][1] = -1;
1966 for (i
= 0; i
< nelm
; i
++) {
1967 shift
= (xbar_chans
[i
][1] & 0x03) << 3;
1968 offset
= xbar_chans
[i
][1] & 0xfffffffc;
1969 mux
= readl(xbar
+ offset
);
1970 mux
&= ~(0xff << shift
);
1971 mux
|= xbar_chans
[i
][0] << shift
;
1972 writel(mux
, (xbar
+ offset
));
1975 pdata
->xbar_chans
= (const s16 (*)[2]) xbar_chans
;
1979 static struct edma_soc_info
*edma_setup_info_from_dt(struct device
*dev
,
1982 struct edma_soc_info
*info
;
1983 struct property
*prop
;
1987 info
= devm_kzalloc(dev
, sizeof(struct edma_soc_info
), GFP_KERNEL
);
1989 return ERR_PTR(-ENOMEM
);
1992 prop
= of_find_property(dev
->of_node
, "ti,edma-xbar-event-map",
1995 ret
= edma_xbar_event_map(dev
, info
, sz
);
1997 return ERR_PTR(ret
);
2002 /* Get the list of channels allocated to be used for memcpy */
2003 prop
= of_find_property(dev
->of_node
, "ti,edma-memcpy-channels", &sz
);
2005 const char pname
[] = "ti,edma-memcpy-channels";
2006 size_t nelm
= sz
/ sizeof(s32
);
2009 memcpy_ch
= devm_kcalloc(dev
, nelm
+ 1, sizeof(s32
),
2012 return ERR_PTR(-ENOMEM
);
2014 ret
= of_property_read_u32_array(dev
->of_node
, pname
,
2015 (u32
*)memcpy_ch
, nelm
);
2017 return ERR_PTR(ret
);
2019 memcpy_ch
[nelm
] = -1;
2020 info
->memcpy_channels
= memcpy_ch
;
2023 prop
= of_find_property(dev
->of_node
, "ti,edma-reserved-slot-ranges",
2026 const char pname
[] = "ti,edma-reserved-slot-ranges";
2028 s16 (*rsv_slots
)[2];
2029 size_t nelm
= sz
/ sizeof(*tmp
);
2030 struct edma_rsv_info
*rsv_info
;
2036 tmp
= kcalloc(nelm
, sizeof(*tmp
), GFP_KERNEL
);
2038 return ERR_PTR(-ENOMEM
);
2040 rsv_info
= devm_kzalloc(dev
, sizeof(*rsv_info
), GFP_KERNEL
);
2043 return ERR_PTR(-ENOMEM
);
2046 rsv_slots
= devm_kcalloc(dev
, nelm
+ 1, sizeof(*rsv_slots
),
2050 return ERR_PTR(-ENOMEM
);
2053 ret
= of_property_read_u32_array(dev
->of_node
, pname
,
2054 (u32
*)tmp
, nelm
* 2);
2057 return ERR_PTR(ret
);
2060 for (i
= 0; i
< nelm
; i
++) {
2061 rsv_slots
[i
][0] = tmp
[i
][0];
2062 rsv_slots
[i
][1] = tmp
[i
][1];
2064 rsv_slots
[nelm
][0] = -1;
2065 rsv_slots
[nelm
][1] = -1;
2067 info
->rsv
= rsv_info
;
2068 info
->rsv
->rsv_slots
= (const s16 (*)[2])rsv_slots
;
2076 static struct dma_chan
*of_edma_xlate(struct of_phandle_args
*dma_spec
,
2077 struct of_dma
*ofdma
)
2079 struct edma_cc
*ecc
= ofdma
->of_dma_data
;
2080 struct dma_chan
*chan
= NULL
;
2081 struct edma_chan
*echan
;
2084 if (!ecc
|| dma_spec
->args_count
< 1)
2087 for (i
= 0; i
< ecc
->num_channels
; i
++) {
2088 echan
= &ecc
->slave_chans
[i
];
2089 if (echan
->ch_num
== dma_spec
->args
[0]) {
2090 chan
= &echan
->vchan
.chan
;
2098 if (echan
->ecc
->legacy_mode
&& dma_spec
->args_count
== 1)
2101 if (!echan
->ecc
->legacy_mode
&& dma_spec
->args_count
== 2 &&
2102 dma_spec
->args
[1] < echan
->ecc
->num_tc
) {
2103 echan
->tc
= &echan
->ecc
->tc_list
[dma_spec
->args
[1]];
2109 /* The channel is going to be used as HW synchronized */
2110 echan
->hw_triggered
= true;
2111 return dma_get_slave_channel(chan
);
2114 static struct edma_soc_info
*edma_setup_info_from_dt(struct device
*dev
,
2117 return ERR_PTR(-EINVAL
);
2120 static struct dma_chan
*of_edma_xlate(struct of_phandle_args
*dma_spec
,
2121 struct of_dma
*ofdma
)
2127 static int edma_probe(struct platform_device
*pdev
)
2129 struct edma_soc_info
*info
= pdev
->dev
.platform_data
;
2130 s8 (*queue_priority_mapping
)[2];
2132 const s16 (*rsv_slots
)[2];
2133 const s16 (*xbar_chans
)[2];
2136 struct resource
*mem
;
2137 struct device_node
*node
= pdev
->dev
.of_node
;
2138 struct device
*dev
= &pdev
->dev
;
2139 struct edma_cc
*ecc
;
2140 bool legacy_mode
= true;
2144 const struct of_device_id
*match
;
2146 match
= of_match_node(edma_of_ids
, node
);
2147 if (match
&& (u32
)match
->data
== EDMA_BINDING_TPCC
)
2148 legacy_mode
= false;
2150 info
= edma_setup_info_from_dt(dev
, legacy_mode
);
2152 dev_err(dev
, "failed to get DT data\n");
2153 return PTR_ERR(info
);
2160 pm_runtime_enable(dev
);
2161 ret
= pm_runtime_get_sync(dev
);
2163 dev_err(dev
, "pm_runtime_get_sync() failed\n");
2167 ret
= dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(32));
2171 ecc
= devm_kzalloc(dev
, sizeof(*ecc
), GFP_KERNEL
);
2173 dev_err(dev
, "Can't allocate controller\n");
2179 ecc
->legacy_mode
= legacy_mode
;
2180 /* When booting with DT the pdev->id is -1 */
2184 mem
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "edma3_cc");
2186 dev_dbg(dev
, "mem resource not found, using index 0\n");
2187 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2189 dev_err(dev
, "no mem resource?\n");
2193 ecc
->base
= devm_ioremap_resource(dev
, mem
);
2194 if (IS_ERR(ecc
->base
))
2195 return PTR_ERR(ecc
->base
);
2197 platform_set_drvdata(pdev
, ecc
);
2199 /* Get eDMA3 configuration from IP */
2200 ret
= edma_setup_from_hw(dev
, info
, ecc
);
2204 /* Allocate memory based on the information we got from the IP */
2205 ecc
->slave_chans
= devm_kcalloc(dev
, ecc
->num_channels
,
2206 sizeof(*ecc
->slave_chans
), GFP_KERNEL
);
2207 if (!ecc
->slave_chans
)
2210 ecc
->slot_inuse
= devm_kcalloc(dev
, BITS_TO_LONGS(ecc
->num_slots
),
2211 sizeof(unsigned long), GFP_KERNEL
);
2212 if (!ecc
->slot_inuse
)
2215 ecc
->default_queue
= info
->default_queue
;
2217 for (i
= 0; i
< ecc
->num_slots
; i
++)
2218 edma_write_slot(ecc
, i
, &dummy_paramset
);
2221 /* Set the reserved slots in inuse list */
2222 rsv_slots
= info
->rsv
->rsv_slots
;
2224 for (i
= 0; rsv_slots
[i
][0] != -1; i
++) {
2225 off
= rsv_slots
[i
][0];
2226 ln
= rsv_slots
[i
][1];
2227 set_bits(off
, ln
, ecc
->slot_inuse
);
2232 /* Clear the xbar mapped channels in unused list */
2233 xbar_chans
= info
->xbar_chans
;
2235 for (i
= 0; xbar_chans
[i
][1] != -1; i
++) {
2236 off
= xbar_chans
[i
][1];
2240 irq
= platform_get_irq_byname(pdev
, "edma3_ccint");
2241 if (irq
< 0 && node
)
2242 irq
= irq_of_parse_and_map(node
, 0);
2245 irq_name
= devm_kasprintf(dev
, GFP_KERNEL
, "%s_ccint",
2247 ret
= devm_request_irq(dev
, irq
, dma_irq_handler
, 0, irq_name
,
2250 dev_err(dev
, "CCINT (%d) failed --> %d\n", irq
, ret
);
2255 irq
= platform_get_irq_byname(pdev
, "edma3_ccerrint");
2256 if (irq
< 0 && node
)
2257 irq
= irq_of_parse_and_map(node
, 2);
2260 irq_name
= devm_kasprintf(dev
, GFP_KERNEL
, "%s_ccerrint",
2262 ret
= devm_request_irq(dev
, irq
, dma_ccerr_handler
, 0, irq_name
,
2265 dev_err(dev
, "CCERRINT (%d) failed --> %d\n", irq
, ret
);
2270 ecc
->dummy_slot
= edma_alloc_slot(ecc
, EDMA_SLOT_ANY
);
2271 if (ecc
->dummy_slot
< 0) {
2272 dev_err(dev
, "Can't allocate PaRAM dummy slot\n");
2273 return ecc
->dummy_slot
;
2276 queue_priority_mapping
= info
->queue_priority_mapping
;
2278 if (!ecc
->legacy_mode
) {
2279 int lowest_priority
= 0;
2280 struct of_phandle_args tc_args
;
2282 ecc
->tc_list
= devm_kcalloc(dev
, ecc
->num_tc
,
2283 sizeof(*ecc
->tc_list
), GFP_KERNEL
);
2288 ret
= of_parse_phandle_with_fixed_args(node
, "ti,tptcs",
2290 if (ret
|| i
== ecc
->num_tc
)
2293 ecc
->tc_list
[i
].node
= tc_args
.np
;
2294 ecc
->tc_list
[i
].id
= i
;
2295 queue_priority_mapping
[i
][1] = tc_args
.args
[0];
2296 if (queue_priority_mapping
[i
][1] > lowest_priority
) {
2297 lowest_priority
= queue_priority_mapping
[i
][1];
2298 info
->default_queue
= i
;
2303 /* Event queue priority mapping */
2304 for (i
= 0; queue_priority_mapping
[i
][0] != -1; i
++)
2305 edma_assign_priority_to_queue(ecc
, queue_priority_mapping
[i
][0],
2306 queue_priority_mapping
[i
][1]);
2308 for (i
= 0; i
< ecc
->num_region
; i
++) {
2309 edma_write_array2(ecc
, EDMA_DRAE
, i
, 0, 0x0);
2310 edma_write_array2(ecc
, EDMA_DRAE
, i
, 1, 0x0);
2311 edma_write_array(ecc
, EDMA_QRAE
, i
, 0x0);
2315 /* Init the dma device and channels */
2316 edma_dma_init(ecc
, legacy_mode
);
2318 for (i
= 0; i
< ecc
->num_channels
; i
++) {
2319 /* Assign all channels to the default queue */
2320 edma_assign_channel_eventq(&ecc
->slave_chans
[i
],
2321 info
->default_queue
);
2322 /* Set entry slot to the dummy slot */
2323 edma_set_chmap(&ecc
->slave_chans
[i
], ecc
->dummy_slot
);
2326 ecc
->dma_slave
.filter
.map
= info
->slave_map
;
2327 ecc
->dma_slave
.filter
.mapcnt
= info
->slavecnt
;
2328 ecc
->dma_slave
.filter
.fn
= edma_filter_fn
;
2330 ret
= dma_async_device_register(&ecc
->dma_slave
);
2332 dev_err(dev
, "slave ddev registration failed (%d)\n", ret
);
2336 if (ecc
->dma_memcpy
) {
2337 ret
= dma_async_device_register(ecc
->dma_memcpy
);
2339 dev_err(dev
, "memcpy ddev registration failed (%d)\n",
2341 dma_async_device_unregister(&ecc
->dma_slave
);
2347 of_dma_controller_register(node
, of_edma_xlate
, ecc
);
2349 dev_info(dev
, "TI EDMA DMA engine driver\n");
2354 edma_free_slot(ecc
, ecc
->dummy_slot
);
2358 static int edma_remove(struct platform_device
*pdev
)
2360 struct device
*dev
= &pdev
->dev
;
2361 struct edma_cc
*ecc
= dev_get_drvdata(dev
);
2364 of_dma_controller_free(dev
->of_node
);
2365 dma_async_device_unregister(&ecc
->dma_slave
);
2366 if (ecc
->dma_memcpy
)
2367 dma_async_device_unregister(ecc
->dma_memcpy
);
2368 edma_free_slot(ecc
, ecc
->dummy_slot
);
2373 #ifdef CONFIG_PM_SLEEP
2374 static int edma_pm_suspend(struct device
*dev
)
2376 struct edma_cc
*ecc
= dev_get_drvdata(dev
);
2377 struct edma_chan
*echan
= ecc
->slave_chans
;
2380 for (i
= 0; i
< ecc
->num_channels
; i
++) {
2381 if (echan
[i
].alloced
) {
2382 edma_setup_interrupt(&echan
[i
], false);
2383 edma_tc_set_pm_state(echan
[i
].tc
, false);
2390 static int edma_pm_resume(struct device
*dev
)
2392 struct edma_cc
*ecc
= dev_get_drvdata(dev
);
2393 struct edma_chan
*echan
= ecc
->slave_chans
;
2395 s8 (*queue_priority_mapping
)[2];
2397 queue_priority_mapping
= ecc
->info
->queue_priority_mapping
;
2399 /* Event queue priority mapping */
2400 for (i
= 0; queue_priority_mapping
[i
][0] != -1; i
++)
2401 edma_assign_priority_to_queue(ecc
, queue_priority_mapping
[i
][0],
2402 queue_priority_mapping
[i
][1]);
2404 for (i
= 0; i
< ecc
->num_channels
; i
++) {
2405 if (echan
[i
].alloced
) {
2406 /* ensure access through shadow region 0 */
2407 edma_or_array2(ecc
, EDMA_DRAE
, 0, i
>> 5,
2410 edma_setup_interrupt(&echan
[i
], true);
2412 /* Set up channel -> slot mapping for the entry slot */
2413 edma_set_chmap(&echan
[i
], echan
[i
].slot
[0]);
2415 edma_tc_set_pm_state(echan
[i
].tc
, true);
2423 static const struct dev_pm_ops edma_pm_ops
= {
2424 SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend
, edma_pm_resume
)
2427 static struct platform_driver edma_driver
= {
2428 .probe
= edma_probe
,
2429 .remove
= edma_remove
,
2433 .of_match_table
= edma_of_ids
,
2437 static int edma_tptc_probe(struct platform_device
*pdev
)
2442 static struct platform_driver edma_tptc_driver
= {
2443 .probe
= edma_tptc_probe
,
2445 .name
= "edma3-tptc",
2446 .of_match_table
= edma_tptc_of_ids
,
2450 bool edma_filter_fn(struct dma_chan
*chan
, void *param
)
2454 if (chan
->device
->dev
->driver
== &edma_driver
.driver
) {
2455 struct edma_chan
*echan
= to_edma_chan(chan
);
2456 unsigned ch_req
= *(unsigned *)param
;
2457 if (ch_req
== echan
->ch_num
) {
2458 /* The channel is going to be used as HW synchronized */
2459 echan
->hw_triggered
= true;
2465 EXPORT_SYMBOL(edma_filter_fn
);
2467 static int edma_init(void)
2471 ret
= platform_driver_register(&edma_tptc_driver
);
2475 return platform_driver_register(&edma_driver
);
2477 subsys_initcall(edma_init
);
2479 static void __exit
edma_exit(void)
2481 platform_driver_unregister(&edma_driver
);
2482 platform_driver_unregister(&edma_tptc_driver
);
2484 module_exit(edma_exit
);
2486 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
2487 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
2488 MODULE_LICENSE("GPL v2");