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[deliverable/linux.git] / drivers / dma / edma.c
1 /*
2 * TI EDMA DMA engine driver
3 *
4 * Copyright 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/edma.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/list.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/of.h>
28 #include <linux/of_dma.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_address.h>
31 #include <linux/of_device.h>
32 #include <linux/pm_runtime.h>
33
34 #include <linux/platform_data/edma.h>
35
36 #include "dmaengine.h"
37 #include "virt-dma.h"
38
39 /* Offsets matching "struct edmacc_param" */
40 #define PARM_OPT 0x00
41 #define PARM_SRC 0x04
42 #define PARM_A_B_CNT 0x08
43 #define PARM_DST 0x0c
44 #define PARM_SRC_DST_BIDX 0x10
45 #define PARM_LINK_BCNTRLD 0x14
46 #define PARM_SRC_DST_CIDX 0x18
47 #define PARM_CCNT 0x1c
48
49 #define PARM_SIZE 0x20
50
51 /* Offsets for EDMA CC global channel registers and their shadows */
52 #define SH_ER 0x00 /* 64 bits */
53 #define SH_ECR 0x08 /* 64 bits */
54 #define SH_ESR 0x10 /* 64 bits */
55 #define SH_CER 0x18 /* 64 bits */
56 #define SH_EER 0x20 /* 64 bits */
57 #define SH_EECR 0x28 /* 64 bits */
58 #define SH_EESR 0x30 /* 64 bits */
59 #define SH_SER 0x38 /* 64 bits */
60 #define SH_SECR 0x40 /* 64 bits */
61 #define SH_IER 0x50 /* 64 bits */
62 #define SH_IECR 0x58 /* 64 bits */
63 #define SH_IESR 0x60 /* 64 bits */
64 #define SH_IPR 0x68 /* 64 bits */
65 #define SH_ICR 0x70 /* 64 bits */
66 #define SH_IEVAL 0x78
67 #define SH_QER 0x80
68 #define SH_QEER 0x84
69 #define SH_QEECR 0x88
70 #define SH_QEESR 0x8c
71 #define SH_QSER 0x90
72 #define SH_QSECR 0x94
73 #define SH_SIZE 0x200
74
75 /* Offsets for EDMA CC global registers */
76 #define EDMA_REV 0x0000
77 #define EDMA_CCCFG 0x0004
78 #define EDMA_QCHMAP 0x0200 /* 8 registers */
79 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
80 #define EDMA_QDMAQNUM 0x0260
81 #define EDMA_QUETCMAP 0x0280
82 #define EDMA_QUEPRI 0x0284
83 #define EDMA_EMR 0x0300 /* 64 bits */
84 #define EDMA_EMCR 0x0308 /* 64 bits */
85 #define EDMA_QEMR 0x0310
86 #define EDMA_QEMCR 0x0314
87 #define EDMA_CCERR 0x0318
88 #define EDMA_CCERRCLR 0x031c
89 #define EDMA_EEVAL 0x0320
90 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
91 #define EDMA_QRAE 0x0380 /* 4 registers */
92 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
93 #define EDMA_QSTAT 0x0600 /* 2 registers */
94 #define EDMA_QWMTHRA 0x0620
95 #define EDMA_QWMTHRB 0x0624
96 #define EDMA_CCSTAT 0x0640
97
98 #define EDMA_M 0x1000 /* global channel registers */
99 #define EDMA_ECR 0x1008
100 #define EDMA_ECRH 0x100C
101 #define EDMA_SHADOW0 0x2000 /* 4 shadow regions */
102 #define EDMA_PARM 0x4000 /* PaRAM entries */
103
104 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
105
106 #define EDMA_DCHMAP 0x0100 /* 64 registers */
107
108 /* CCCFG register */
109 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
110 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
111 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
112 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
113 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
114 #define CHMAP_EXIST BIT(24)
115
116 /* CCSTAT register */
117 #define EDMA_CCSTAT_ACTV BIT(4)
118
119 /*
120 * Max of 20 segments per channel to conserve PaRAM slots
121 * Also note that MAX_NR_SG should be atleast the no.of periods
122 * that are required for ASoC, otherwise DMA prep calls will
123 * fail. Today davinci-pcm is the only user of this driver and
124 * requires atleast 17 slots, so we setup the default to 20.
125 */
126 #define MAX_NR_SG 20
127 #define EDMA_MAX_SLOTS MAX_NR_SG
128 #define EDMA_DESCRIPTORS 16
129
130 #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
131 #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
132 #define EDMA_CONT_PARAMS_ANY 1001
133 #define EDMA_CONT_PARAMS_FIXED_EXACT 1002
134 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
135
136 /* PaRAM slots are laid out like this */
137 struct edmacc_param {
138 u32 opt;
139 u32 src;
140 u32 a_b_cnt;
141 u32 dst;
142 u32 src_dst_bidx;
143 u32 link_bcntrld;
144 u32 src_dst_cidx;
145 u32 ccnt;
146 } __packed;
147
148 /* fields in edmacc_param.opt */
149 #define SAM BIT(0)
150 #define DAM BIT(1)
151 #define SYNCDIM BIT(2)
152 #define STATIC BIT(3)
153 #define EDMA_FWID (0x07 << 8)
154 #define TCCMODE BIT(11)
155 #define EDMA_TCC(t) ((t) << 12)
156 #define TCINTEN BIT(20)
157 #define ITCINTEN BIT(21)
158 #define TCCHEN BIT(22)
159 #define ITCCHEN BIT(23)
160
161 struct edma_pset {
162 u32 len;
163 dma_addr_t addr;
164 struct edmacc_param param;
165 };
166
167 struct edma_desc {
168 struct virt_dma_desc vdesc;
169 struct list_head node;
170 enum dma_transfer_direction direction;
171 int cyclic;
172 int absync;
173 int pset_nr;
174 struct edma_chan *echan;
175 int processed;
176
177 /*
178 * The following 4 elements are used for residue accounting.
179 *
180 * - processed_stat: the number of SG elements we have traversed
181 * so far to cover accounting. This is updated directly to processed
182 * during edma_callback and is always <= processed, because processed
183 * refers to the number of pending transfer (programmed to EDMA
184 * controller), where as processed_stat tracks number of transfers
185 * accounted for so far.
186 *
187 * - residue: The amount of bytes we have left to transfer for this desc
188 *
189 * - residue_stat: The residue in bytes of data we have covered
190 * so far for accounting. This is updated directly to residue
191 * during callbacks to keep it current.
192 *
193 * - sg_len: Tracks the length of the current intermediate transfer,
194 * this is required to update the residue during intermediate transfer
195 * completion callback.
196 */
197 int processed_stat;
198 u32 sg_len;
199 u32 residue;
200 u32 residue_stat;
201
202 struct edma_pset pset[0];
203 };
204
205 struct edma_cc;
206
207 struct edma_tc {
208 struct device_node *node;
209 u16 id;
210 };
211
212 struct edma_chan {
213 struct virt_dma_chan vchan;
214 struct list_head node;
215 struct edma_desc *edesc;
216 struct edma_cc *ecc;
217 struct edma_tc *tc;
218 int ch_num;
219 bool alloced;
220 bool hw_triggered;
221 int slot[EDMA_MAX_SLOTS];
222 int missed;
223 struct dma_slave_config cfg;
224 };
225
226 struct edma_cc {
227 struct device *dev;
228 struct edma_soc_info *info;
229 void __iomem *base;
230 int id;
231 bool legacy_mode;
232
233 /* eDMA3 resource information */
234 unsigned num_channels;
235 unsigned num_qchannels;
236 unsigned num_region;
237 unsigned num_slots;
238 unsigned num_tc;
239 bool chmap_exist;
240 enum dma_event_q default_queue;
241
242 /*
243 * The slot_inuse bit for each PaRAM slot is clear unless the slot is
244 * in use by Linux or if it is allocated to be used by DSP.
245 */
246 unsigned long *slot_inuse;
247
248 struct dma_device dma_slave;
249 struct dma_device *dma_memcpy;
250 struct edma_chan *slave_chans;
251 struct edma_tc *tc_list;
252 int dummy_slot;
253 };
254
255 /* dummy param set used to (re)initialize parameter RAM slots */
256 static const struct edmacc_param dummy_paramset = {
257 .link_bcntrld = 0xffff,
258 .ccnt = 1,
259 };
260
261 #define EDMA_BINDING_LEGACY 0
262 #define EDMA_BINDING_TPCC 1
263 static const struct of_device_id edma_of_ids[] = {
264 {
265 .compatible = "ti,edma3",
266 .data = (void *)EDMA_BINDING_LEGACY,
267 },
268 {
269 .compatible = "ti,edma3-tpcc",
270 .data = (void *)EDMA_BINDING_TPCC,
271 },
272 {}
273 };
274
275 static const struct of_device_id edma_tptc_of_ids[] = {
276 { .compatible = "ti,edma3-tptc", },
277 {}
278 };
279
280 static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
281 {
282 return (unsigned int)__raw_readl(ecc->base + offset);
283 }
284
285 static inline void edma_write(struct edma_cc *ecc, int offset, int val)
286 {
287 __raw_writel(val, ecc->base + offset);
288 }
289
290 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
291 unsigned or)
292 {
293 unsigned val = edma_read(ecc, offset);
294
295 val &= and;
296 val |= or;
297 edma_write(ecc, offset, val);
298 }
299
300 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
301 {
302 unsigned val = edma_read(ecc, offset);
303
304 val &= and;
305 edma_write(ecc, offset, val);
306 }
307
308 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
309 {
310 unsigned val = edma_read(ecc, offset);
311
312 val |= or;
313 edma_write(ecc, offset, val);
314 }
315
316 static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
317 int i)
318 {
319 return edma_read(ecc, offset + (i << 2));
320 }
321
322 static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
323 unsigned val)
324 {
325 edma_write(ecc, offset + (i << 2), val);
326 }
327
328 static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
329 unsigned and, unsigned or)
330 {
331 edma_modify(ecc, offset + (i << 2), and, or);
332 }
333
334 static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
335 unsigned or)
336 {
337 edma_or(ecc, offset + (i << 2), or);
338 }
339
340 static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
341 unsigned or)
342 {
343 edma_or(ecc, offset + ((i * 2 + j) << 2), or);
344 }
345
346 static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
347 int j, unsigned val)
348 {
349 edma_write(ecc, offset + ((i * 2 + j) << 2), val);
350 }
351
352 static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
353 {
354 return edma_read(ecc, EDMA_SHADOW0 + offset);
355 }
356
357 static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
358 int offset, int i)
359 {
360 return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
361 }
362
363 static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
364 unsigned val)
365 {
366 edma_write(ecc, EDMA_SHADOW0 + offset, val);
367 }
368
369 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
370 int i, unsigned val)
371 {
372 edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
373 }
374
375 static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset,
376 int param_no)
377 {
378 return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
379 }
380
381 static inline void edma_param_write(struct edma_cc *ecc, int offset,
382 int param_no, unsigned val)
383 {
384 edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
385 }
386
387 static inline void edma_param_modify(struct edma_cc *ecc, int offset,
388 int param_no, unsigned and, unsigned or)
389 {
390 edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
391 }
392
393 static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no,
394 unsigned and)
395 {
396 edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
397 }
398
399 static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no,
400 unsigned or)
401 {
402 edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
403 }
404
405 static inline void set_bits(int offset, int len, unsigned long *p)
406 {
407 for (; len > 0; len--)
408 set_bit(offset + (len - 1), p);
409 }
410
411 static inline void clear_bits(int offset, int len, unsigned long *p)
412 {
413 for (; len > 0; len--)
414 clear_bit(offset + (len - 1), p);
415 }
416
417 static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
418 int priority)
419 {
420 int bit = queue_no * 4;
421
422 edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
423 }
424
425 static void edma_set_chmap(struct edma_chan *echan, int slot)
426 {
427 struct edma_cc *ecc = echan->ecc;
428 int channel = EDMA_CHAN_SLOT(echan->ch_num);
429
430 if (ecc->chmap_exist) {
431 slot = EDMA_CHAN_SLOT(slot);
432 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
433 }
434 }
435
436 static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
437 {
438 struct edma_cc *ecc = echan->ecc;
439 int channel = EDMA_CHAN_SLOT(echan->ch_num);
440
441 if (enable) {
442 edma_shadow0_write_array(ecc, SH_ICR, channel >> 5,
443 BIT(channel & 0x1f));
444 edma_shadow0_write_array(ecc, SH_IESR, channel >> 5,
445 BIT(channel & 0x1f));
446 } else {
447 edma_shadow0_write_array(ecc, SH_IECR, channel >> 5,
448 BIT(channel & 0x1f));
449 }
450 }
451
452 /*
453 * paRAM slot management functions
454 */
455 static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
456 const struct edmacc_param *param)
457 {
458 slot = EDMA_CHAN_SLOT(slot);
459 if (slot >= ecc->num_slots)
460 return;
461 memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
462 }
463
464 static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
465 struct edmacc_param *param)
466 {
467 slot = EDMA_CHAN_SLOT(slot);
468 if (slot >= ecc->num_slots)
469 return;
470 memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
471 }
472
473 /**
474 * edma_alloc_slot - allocate DMA parameter RAM
475 * @ecc: pointer to edma_cc struct
476 * @slot: specific slot to allocate; negative for "any unused slot"
477 *
478 * This allocates a parameter RAM slot, initializing it to hold a
479 * dummy transfer. Slots allocated using this routine have not been
480 * mapped to a hardware DMA channel, and will normally be used by
481 * linking to them from a slot associated with a DMA channel.
482 *
483 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
484 * slots may be allocated on behalf of DSP firmware.
485 *
486 * Returns the number of the slot, else negative errno.
487 */
488 static int edma_alloc_slot(struct edma_cc *ecc, int slot)
489 {
490 if (slot >= 0) {
491 slot = EDMA_CHAN_SLOT(slot);
492 /* Requesting entry paRAM slot for a HW triggered channel. */
493 if (ecc->chmap_exist && slot < ecc->num_channels)
494 slot = EDMA_SLOT_ANY;
495 }
496
497 if (slot < 0) {
498 if (ecc->chmap_exist)
499 slot = 0;
500 else
501 slot = ecc->num_channels;
502 for (;;) {
503 slot = find_next_zero_bit(ecc->slot_inuse,
504 ecc->num_slots,
505 slot);
506 if (slot == ecc->num_slots)
507 return -ENOMEM;
508 if (!test_and_set_bit(slot, ecc->slot_inuse))
509 break;
510 }
511 } else if (slot >= ecc->num_slots) {
512 return -EINVAL;
513 } else if (test_and_set_bit(slot, ecc->slot_inuse)) {
514 return -EBUSY;
515 }
516
517 edma_write_slot(ecc, slot, &dummy_paramset);
518
519 return EDMA_CTLR_CHAN(ecc->id, slot);
520 }
521
522 static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
523 {
524 slot = EDMA_CHAN_SLOT(slot);
525 if (slot >= ecc->num_slots)
526 return;
527
528 edma_write_slot(ecc, slot, &dummy_paramset);
529 clear_bit(slot, ecc->slot_inuse);
530 }
531
532 /**
533 * edma_link - link one parameter RAM slot to another
534 * @ecc: pointer to edma_cc struct
535 * @from: parameter RAM slot originating the link
536 * @to: parameter RAM slot which is the link target
537 *
538 * The originating slot should not be part of any active DMA transfer.
539 */
540 static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
541 {
542 if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
543 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");
544
545 from = EDMA_CHAN_SLOT(from);
546 to = EDMA_CHAN_SLOT(to);
547 if (from >= ecc->num_slots || to >= ecc->num_slots)
548 return;
549
550 edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
551 PARM_OFFSET(to));
552 }
553
554 /**
555 * edma_get_position - returns the current transfer point
556 * @ecc: pointer to edma_cc struct
557 * @slot: parameter RAM slot being examined
558 * @dst: true selects the dest position, false the source
559 *
560 * Returns the position of the current active slot
561 */
562 static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
563 bool dst)
564 {
565 u32 offs;
566
567 slot = EDMA_CHAN_SLOT(slot);
568 offs = PARM_OFFSET(slot);
569 offs += dst ? PARM_DST : PARM_SRC;
570
571 return edma_read(ecc, offs);
572 }
573
574 /*
575 * Channels with event associations will be triggered by their hardware
576 * events, and channels without such associations will be triggered by
577 * software. (At this writing there is no interface for using software
578 * triggers except with channels that don't support hardware triggers.)
579 */
580 static void edma_start(struct edma_chan *echan)
581 {
582 struct edma_cc *ecc = echan->ecc;
583 int channel = EDMA_CHAN_SLOT(echan->ch_num);
584 int j = (channel >> 5);
585 unsigned int mask = BIT(channel & 0x1f);
586
587 if (!echan->hw_triggered) {
588 /* EDMA channels without event association */
589 dev_dbg(ecc->dev, "ESR%d %08x\n", j,
590 edma_shadow0_read_array(ecc, SH_ESR, j));
591 edma_shadow0_write_array(ecc, SH_ESR, j, mask);
592 } else {
593 /* EDMA channel with event association */
594 dev_dbg(ecc->dev, "ER%d %08x\n", j,
595 edma_shadow0_read_array(ecc, SH_ER, j));
596 /* Clear any pending event or error */
597 edma_write_array(ecc, EDMA_ECR, j, mask);
598 edma_write_array(ecc, EDMA_EMCR, j, mask);
599 /* Clear any SER */
600 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
601 edma_shadow0_write_array(ecc, SH_EESR, j, mask);
602 dev_dbg(ecc->dev, "EER%d %08x\n", j,
603 edma_shadow0_read_array(ecc, SH_EER, j));
604 }
605 }
606
607 static void edma_stop(struct edma_chan *echan)
608 {
609 struct edma_cc *ecc = echan->ecc;
610 int channel = EDMA_CHAN_SLOT(echan->ch_num);
611 int j = (channel >> 5);
612 unsigned int mask = BIT(channel & 0x1f);
613
614 edma_shadow0_write_array(ecc, SH_EECR, j, mask);
615 edma_shadow0_write_array(ecc, SH_ECR, j, mask);
616 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
617 edma_write_array(ecc, EDMA_EMCR, j, mask);
618
619 /* clear possibly pending completion interrupt */
620 edma_shadow0_write_array(ecc, SH_ICR, j, mask);
621
622 dev_dbg(ecc->dev, "EER%d %08x\n", j,
623 edma_shadow0_read_array(ecc, SH_EER, j));
624
625 /* REVISIT: consider guarding against inappropriate event
626 * chaining by overwriting with dummy_paramset.
627 */
628 }
629
630 /*
631 * Temporarily disable EDMA hardware events on the specified channel,
632 * preventing them from triggering new transfers
633 */
634 static void edma_pause(struct edma_chan *echan)
635 {
636 int channel = EDMA_CHAN_SLOT(echan->ch_num);
637 unsigned int mask = BIT(channel & 0x1f);
638
639 edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask);
640 }
641
642 /* Re-enable EDMA hardware events on the specified channel. */
643 static void edma_resume(struct edma_chan *echan)
644 {
645 int channel = EDMA_CHAN_SLOT(echan->ch_num);
646 unsigned int mask = BIT(channel & 0x1f);
647
648 edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask);
649 }
650
651 static void edma_trigger_channel(struct edma_chan *echan)
652 {
653 struct edma_cc *ecc = echan->ecc;
654 int channel = EDMA_CHAN_SLOT(echan->ch_num);
655 unsigned int mask = BIT(channel & 0x1f);
656
657 edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
658
659 dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
660 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
661 }
662
663 static void edma_clean_channel(struct edma_chan *echan)
664 {
665 struct edma_cc *ecc = echan->ecc;
666 int channel = EDMA_CHAN_SLOT(echan->ch_num);
667 int j = (channel >> 5);
668 unsigned int mask = BIT(channel & 0x1f);
669
670 dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j));
671 edma_shadow0_write_array(ecc, SH_ECR, j, mask);
672 /* Clear the corresponding EMR bits */
673 edma_write_array(ecc, EDMA_EMCR, j, mask);
674 /* Clear any SER */
675 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
676 edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
677 }
678
679 /* Move channel to a specific event queue */
680 static void edma_assign_channel_eventq(struct edma_chan *echan,
681 enum dma_event_q eventq_no)
682 {
683 struct edma_cc *ecc = echan->ecc;
684 int channel = EDMA_CHAN_SLOT(echan->ch_num);
685 int bit = (channel & 0x7) * 4;
686
687 /* default to low priority queue */
688 if (eventq_no == EVENTQ_DEFAULT)
689 eventq_no = ecc->default_queue;
690 if (eventq_no >= ecc->num_tc)
691 return;
692
693 eventq_no &= 7;
694 edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
695 eventq_no << bit);
696 }
697
698 static int edma_alloc_channel(struct edma_chan *echan,
699 enum dma_event_q eventq_no)
700 {
701 struct edma_cc *ecc = echan->ecc;
702 int channel = EDMA_CHAN_SLOT(echan->ch_num);
703
704 /* ensure access through shadow region 0 */
705 edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
706
707 /* ensure no events are pending */
708 edma_stop(echan);
709
710 edma_setup_interrupt(echan, true);
711
712 edma_assign_channel_eventq(echan, eventq_no);
713
714 return 0;
715 }
716
717 static void edma_free_channel(struct edma_chan *echan)
718 {
719 /* ensure no events are pending */
720 edma_stop(echan);
721 /* REVISIT should probably take out of shadow region 0 */
722 edma_setup_interrupt(echan, false);
723 }
724
725 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
726 {
727 return container_of(d, struct edma_cc, dma_slave);
728 }
729
730 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
731 {
732 return container_of(c, struct edma_chan, vchan.chan);
733 }
734
735 static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
736 {
737 return container_of(tx, struct edma_desc, vdesc.tx);
738 }
739
740 static void edma_desc_free(struct virt_dma_desc *vdesc)
741 {
742 kfree(container_of(vdesc, struct edma_desc, vdesc));
743 }
744
745 /* Dispatch a queued descriptor to the controller (caller holds lock) */
746 static void edma_execute(struct edma_chan *echan)
747 {
748 struct edma_cc *ecc = echan->ecc;
749 struct virt_dma_desc *vdesc;
750 struct edma_desc *edesc;
751 struct device *dev = echan->vchan.chan.device->dev;
752 int i, j, left, nslots;
753
754 if (!echan->edesc) {
755 /* Setup is needed for the first transfer */
756 vdesc = vchan_next_desc(&echan->vchan);
757 if (!vdesc)
758 return;
759 list_del(&vdesc->node);
760 echan->edesc = to_edma_desc(&vdesc->tx);
761 }
762
763 edesc = echan->edesc;
764
765 /* Find out how many left */
766 left = edesc->pset_nr - edesc->processed;
767 nslots = min(MAX_NR_SG, left);
768 edesc->sg_len = 0;
769
770 /* Write descriptor PaRAM set(s) */
771 for (i = 0; i < nslots; i++) {
772 j = i + edesc->processed;
773 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
774 edesc->sg_len += edesc->pset[j].len;
775 dev_vdbg(dev,
776 "\n pset[%d]:\n"
777 " chnum\t%d\n"
778 " slot\t%d\n"
779 " opt\t%08x\n"
780 " src\t%08x\n"
781 " dst\t%08x\n"
782 " abcnt\t%08x\n"
783 " ccnt\t%08x\n"
784 " bidx\t%08x\n"
785 " cidx\t%08x\n"
786 " lkrld\t%08x\n",
787 j, echan->ch_num, echan->slot[i],
788 edesc->pset[j].param.opt,
789 edesc->pset[j].param.src,
790 edesc->pset[j].param.dst,
791 edesc->pset[j].param.a_b_cnt,
792 edesc->pset[j].param.ccnt,
793 edesc->pset[j].param.src_dst_bidx,
794 edesc->pset[j].param.src_dst_cidx,
795 edesc->pset[j].param.link_bcntrld);
796 /* Link to the previous slot if not the last set */
797 if (i != (nslots - 1))
798 edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
799 }
800
801 edesc->processed += nslots;
802
803 /*
804 * If this is either the last set in a set of SG-list transactions
805 * then setup a link to the dummy slot, this results in all future
806 * events being absorbed and that's OK because we're done
807 */
808 if (edesc->processed == edesc->pset_nr) {
809 if (edesc->cyclic)
810 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
811 else
812 edma_link(ecc, echan->slot[nslots - 1],
813 echan->ecc->dummy_slot);
814 }
815
816 if (echan->missed) {
817 /*
818 * This happens due to setup times between intermediate
819 * transfers in long SG lists which have to be broken up into
820 * transfers of MAX_NR_SG
821 */
822 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
823 edma_clean_channel(echan);
824 edma_stop(echan);
825 edma_start(echan);
826 edma_trigger_channel(echan);
827 echan->missed = 0;
828 } else if (edesc->processed <= MAX_NR_SG) {
829 dev_dbg(dev, "first transfer starting on channel %d\n",
830 echan->ch_num);
831 edma_start(echan);
832 } else {
833 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
834 echan->ch_num, edesc->processed);
835 edma_resume(echan);
836 }
837 }
838
839 static int edma_terminate_all(struct dma_chan *chan)
840 {
841 struct edma_chan *echan = to_edma_chan(chan);
842 unsigned long flags;
843 LIST_HEAD(head);
844
845 spin_lock_irqsave(&echan->vchan.lock, flags);
846
847 /*
848 * Stop DMA activity: we assume the callback will not be called
849 * after edma_dma() returns (even if it does, it will see
850 * echan->edesc is NULL and exit.)
851 */
852 if (echan->edesc) {
853 edma_stop(echan);
854 /* Move the cyclic channel back to default queue */
855 if (!echan->tc && echan->edesc->cyclic)
856 edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
857 /*
858 * free the running request descriptor
859 * since it is not in any of the vdesc lists
860 */
861 edma_desc_free(&echan->edesc->vdesc);
862 echan->edesc = NULL;
863 }
864
865 vchan_get_all_descriptors(&echan->vchan, &head);
866 spin_unlock_irqrestore(&echan->vchan.lock, flags);
867 vchan_dma_desc_free_list(&echan->vchan, &head);
868
869 return 0;
870 }
871
872 static void edma_synchronize(struct dma_chan *chan)
873 {
874 struct edma_chan *echan = to_edma_chan(chan);
875
876 vchan_synchronize(&echan->vchan);
877 }
878
879 static int edma_slave_config(struct dma_chan *chan,
880 struct dma_slave_config *cfg)
881 {
882 struct edma_chan *echan = to_edma_chan(chan);
883
884 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
885 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
886 return -EINVAL;
887
888 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
889
890 return 0;
891 }
892
893 static int edma_dma_pause(struct dma_chan *chan)
894 {
895 struct edma_chan *echan = to_edma_chan(chan);
896
897 if (!echan->edesc)
898 return -EINVAL;
899
900 edma_pause(echan);
901 return 0;
902 }
903
904 static int edma_dma_resume(struct dma_chan *chan)
905 {
906 struct edma_chan *echan = to_edma_chan(chan);
907
908 edma_resume(echan);
909 return 0;
910 }
911
912 /*
913 * A PaRAM set configuration abstraction used by other modes
914 * @chan: Channel who's PaRAM set we're configuring
915 * @pset: PaRAM set to initialize and setup.
916 * @src_addr: Source address of the DMA
917 * @dst_addr: Destination address of the DMA
918 * @burst: In units of dev_width, how much to send
919 * @dev_width: How much is the dev_width
920 * @dma_length: Total length of the DMA transfer
921 * @direction: Direction of the transfer
922 */
923 static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
924 dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
925 unsigned int acnt, unsigned int dma_length,
926 enum dma_transfer_direction direction)
927 {
928 struct edma_chan *echan = to_edma_chan(chan);
929 struct device *dev = chan->device->dev;
930 struct edmacc_param *param = &epset->param;
931 int bcnt, ccnt, cidx;
932 int src_bidx, dst_bidx, src_cidx, dst_cidx;
933 int absync;
934
935 /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
936 if (!burst)
937 burst = 1;
938 /*
939 * If the maxburst is equal to the fifo width, use
940 * A-synced transfers. This allows for large contiguous
941 * buffer transfers using only one PaRAM set.
942 */
943 if (burst == 1) {
944 /*
945 * For the A-sync case, bcnt and ccnt are the remainder
946 * and quotient respectively of the division of:
947 * (dma_length / acnt) by (SZ_64K -1). This is so
948 * that in case bcnt over flows, we have ccnt to use.
949 * Note: In A-sync tranfer only, bcntrld is used, but it
950 * only applies for sg_dma_len(sg) >= SZ_64K.
951 * In this case, the best way adopted is- bccnt for the
952 * first frame will be the remainder below. Then for
953 * every successive frame, bcnt will be SZ_64K-1. This
954 * is assured as bcntrld = 0xffff in end of function.
955 */
956 absync = false;
957 ccnt = dma_length / acnt / (SZ_64K - 1);
958 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
959 /*
960 * If bcnt is non-zero, we have a remainder and hence an
961 * extra frame to transfer, so increment ccnt.
962 */
963 if (bcnt)
964 ccnt++;
965 else
966 bcnt = SZ_64K - 1;
967 cidx = acnt;
968 } else {
969 /*
970 * If maxburst is greater than the fifo address_width,
971 * use AB-synced transfers where A count is the fifo
972 * address_width and B count is the maxburst. In this
973 * case, we are limited to transfers of C count frames
974 * of (address_width * maxburst) where C count is limited
975 * to SZ_64K-1. This places an upper bound on the length
976 * of an SG segment that can be handled.
977 */
978 absync = true;
979 bcnt = burst;
980 ccnt = dma_length / (acnt * bcnt);
981 if (ccnt > (SZ_64K - 1)) {
982 dev_err(dev, "Exceeded max SG segment size\n");
983 return -EINVAL;
984 }
985 cidx = acnt * bcnt;
986 }
987
988 epset->len = dma_length;
989
990 if (direction == DMA_MEM_TO_DEV) {
991 src_bidx = acnt;
992 src_cidx = cidx;
993 dst_bidx = 0;
994 dst_cidx = 0;
995 epset->addr = src_addr;
996 } else if (direction == DMA_DEV_TO_MEM) {
997 src_bidx = 0;
998 src_cidx = 0;
999 dst_bidx = acnt;
1000 dst_cidx = cidx;
1001 epset->addr = dst_addr;
1002 } else if (direction == DMA_MEM_TO_MEM) {
1003 src_bidx = acnt;
1004 src_cidx = cidx;
1005 dst_bidx = acnt;
1006 dst_cidx = cidx;
1007 } else {
1008 dev_err(dev, "%s: direction not implemented yet\n", __func__);
1009 return -EINVAL;
1010 }
1011
1012 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1013 /* Configure A or AB synchronized transfers */
1014 if (absync)
1015 param->opt |= SYNCDIM;
1016
1017 param->src = src_addr;
1018 param->dst = dst_addr;
1019
1020 param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
1021 param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
1022
1023 param->a_b_cnt = bcnt << 16 | acnt;
1024 param->ccnt = ccnt;
1025 /*
1026 * Only time when (bcntrld) auto reload is required is for
1027 * A-sync case, and in this case, a requirement of reload value
1028 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
1029 * and then later will be populated by edma_execute.
1030 */
1031 param->link_bcntrld = 0xffffffff;
1032 return absync;
1033 }
1034
1035 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
1036 struct dma_chan *chan, struct scatterlist *sgl,
1037 unsigned int sg_len, enum dma_transfer_direction direction,
1038 unsigned long tx_flags, void *context)
1039 {
1040 struct edma_chan *echan = to_edma_chan(chan);
1041 struct device *dev = chan->device->dev;
1042 struct edma_desc *edesc;
1043 dma_addr_t src_addr = 0, dst_addr = 0;
1044 enum dma_slave_buswidth dev_width;
1045 u32 burst;
1046 struct scatterlist *sg;
1047 int i, nslots, ret;
1048
1049 if (unlikely(!echan || !sgl || !sg_len))
1050 return NULL;
1051
1052 if (direction == DMA_DEV_TO_MEM) {
1053 src_addr = echan->cfg.src_addr;
1054 dev_width = echan->cfg.src_addr_width;
1055 burst = echan->cfg.src_maxburst;
1056 } else if (direction == DMA_MEM_TO_DEV) {
1057 dst_addr = echan->cfg.dst_addr;
1058 dev_width = echan->cfg.dst_addr_width;
1059 burst = echan->cfg.dst_maxburst;
1060 } else {
1061 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1062 return NULL;
1063 }
1064
1065 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1066 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1067 return NULL;
1068 }
1069
1070 edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]),
1071 GFP_ATOMIC);
1072 if (!edesc)
1073 return NULL;
1074
1075 edesc->pset_nr = sg_len;
1076 edesc->residue = 0;
1077 edesc->direction = direction;
1078 edesc->echan = echan;
1079
1080 /* Allocate a PaRAM slot, if needed */
1081 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
1082
1083 for (i = 0; i < nslots; i++) {
1084 if (echan->slot[i] < 0) {
1085 echan->slot[i] =
1086 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1087 if (echan->slot[i] < 0) {
1088 kfree(edesc);
1089 dev_err(dev, "%s: Failed to allocate slot\n",
1090 __func__);
1091 return NULL;
1092 }
1093 }
1094 }
1095
1096 /* Configure PaRAM sets for each SG */
1097 for_each_sg(sgl, sg, sg_len, i) {
1098 /* Get address for each SG */
1099 if (direction == DMA_DEV_TO_MEM)
1100 dst_addr = sg_dma_address(sg);
1101 else
1102 src_addr = sg_dma_address(sg);
1103
1104 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1105 dst_addr, burst, dev_width,
1106 sg_dma_len(sg), direction);
1107 if (ret < 0) {
1108 kfree(edesc);
1109 return NULL;
1110 }
1111
1112 edesc->absync = ret;
1113 edesc->residue += sg_dma_len(sg);
1114
1115 if (i == sg_len - 1)
1116 /* Enable completion interrupt */
1117 edesc->pset[i].param.opt |= TCINTEN;
1118 else if (!((i+1) % MAX_NR_SG))
1119 /*
1120 * Enable early completion interrupt for the
1121 * intermediateset. In this case the driver will be
1122 * notified when the paRAM set is submitted to TC. This
1123 * will allow more time to set up the next set of slots.
1124 */
1125 edesc->pset[i].param.opt |= (TCINTEN | TCCMODE);
1126 }
1127 edesc->residue_stat = edesc->residue;
1128
1129 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1130 }
1131
1132 static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
1133 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1134 size_t len, unsigned long tx_flags)
1135 {
1136 int ret, nslots;
1137 struct edma_desc *edesc;
1138 struct device *dev = chan->device->dev;
1139 struct edma_chan *echan = to_edma_chan(chan);
1140 unsigned int width, pset_len;
1141
1142 if (unlikely(!echan || !len))
1143 return NULL;
1144
1145 if (len < SZ_64K) {
1146 /*
1147 * Transfer size less than 64K can be handled with one paRAM
1148 * slot and with one burst.
1149 * ACNT = length
1150 */
1151 width = len;
1152 pset_len = len;
1153 nslots = 1;
1154 } else {
1155 /*
1156 * Transfer size bigger than 64K will be handled with maximum of
1157 * two paRAM slots.
1158 * slot1: (full_length / 32767) times 32767 bytes bursts.
1159 * ACNT = 32767, length1: (full_length / 32767) * 32767
1160 * slot2: the remaining amount of data after slot1.
1161 * ACNT = full_length - length1, length2 = ACNT
1162 *
1163 * When the full_length is multibple of 32767 one slot can be
1164 * used to complete the transfer.
1165 */
1166 width = SZ_32K - 1;
1167 pset_len = rounddown(len, width);
1168 /* One slot is enough for lengths multiple of (SZ_32K -1) */
1169 if (unlikely(pset_len == len))
1170 nslots = 1;
1171 else
1172 nslots = 2;
1173 }
1174
1175 edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1176 GFP_ATOMIC);
1177 if (!edesc)
1178 return NULL;
1179
1180 edesc->pset_nr = nslots;
1181 edesc->residue = edesc->residue_stat = len;
1182 edesc->direction = DMA_MEM_TO_MEM;
1183 edesc->echan = echan;
1184
1185 ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
1186 width, pset_len, DMA_MEM_TO_MEM);
1187 if (ret < 0) {
1188 kfree(edesc);
1189 return NULL;
1190 }
1191
1192 edesc->absync = ret;
1193
1194 edesc->pset[0].param.opt |= ITCCHEN;
1195 if (nslots == 1) {
1196 /* Enable transfer complete interrupt */
1197 edesc->pset[0].param.opt |= TCINTEN;
1198 } else {
1199 /* Enable transfer complete chaining for the first slot */
1200 edesc->pset[0].param.opt |= TCCHEN;
1201
1202 if (echan->slot[1] < 0) {
1203 echan->slot[1] = edma_alloc_slot(echan->ecc,
1204 EDMA_SLOT_ANY);
1205 if (echan->slot[1] < 0) {
1206 kfree(edesc);
1207 dev_err(dev, "%s: Failed to allocate slot\n",
1208 __func__);
1209 return NULL;
1210 }
1211 }
1212 dest += pset_len;
1213 src += pset_len;
1214 pset_len = width = len % (SZ_32K - 1);
1215
1216 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1,
1217 width, pset_len, DMA_MEM_TO_MEM);
1218 if (ret < 0) {
1219 kfree(edesc);
1220 return NULL;
1221 }
1222
1223 edesc->pset[1].param.opt |= ITCCHEN;
1224 edesc->pset[1].param.opt |= TCINTEN;
1225 }
1226
1227 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1228 }
1229
1230 static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
1231 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1232 size_t period_len, enum dma_transfer_direction direction,
1233 unsigned long tx_flags)
1234 {
1235 struct edma_chan *echan = to_edma_chan(chan);
1236 struct device *dev = chan->device->dev;
1237 struct edma_desc *edesc;
1238 dma_addr_t src_addr, dst_addr;
1239 enum dma_slave_buswidth dev_width;
1240 bool use_intermediate = false;
1241 u32 burst;
1242 int i, ret, nslots;
1243
1244 if (unlikely(!echan || !buf_len || !period_len))
1245 return NULL;
1246
1247 if (direction == DMA_DEV_TO_MEM) {
1248 src_addr = echan->cfg.src_addr;
1249 dst_addr = buf_addr;
1250 dev_width = echan->cfg.src_addr_width;
1251 burst = echan->cfg.src_maxburst;
1252 } else if (direction == DMA_MEM_TO_DEV) {
1253 src_addr = buf_addr;
1254 dst_addr = echan->cfg.dst_addr;
1255 dev_width = echan->cfg.dst_addr_width;
1256 burst = echan->cfg.dst_maxburst;
1257 } else {
1258 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1259 return NULL;
1260 }
1261
1262 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1263 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1264 return NULL;
1265 }
1266
1267 if (unlikely(buf_len % period_len)) {
1268 dev_err(dev, "Period should be multiple of Buffer length\n");
1269 return NULL;
1270 }
1271
1272 nslots = (buf_len / period_len) + 1;
1273
1274 /*
1275 * Cyclic DMA users such as audio cannot tolerate delays introduced
1276 * by cases where the number of periods is more than the maximum
1277 * number of SGs the EDMA driver can handle at a time. For DMA types
1278 * such as Slave SGs, such delays are tolerable and synchronized,
1279 * but the synchronization is difficult to achieve with Cyclic and
1280 * cannot be guaranteed, so we error out early.
1281 */
1282 if (nslots > MAX_NR_SG) {
1283 /*
1284 * If the burst and period sizes are the same, we can put
1285 * the full buffer into a single period and activate
1286 * intermediate interrupts. This will produce interrupts
1287 * after each burst, which is also after each desired period.
1288 */
1289 if (burst == period_len) {
1290 period_len = buf_len;
1291 nslots = 2;
1292 use_intermediate = true;
1293 } else {
1294 return NULL;
1295 }
1296 }
1297
1298 edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1299 GFP_ATOMIC);
1300 if (!edesc)
1301 return NULL;
1302
1303 edesc->cyclic = 1;
1304 edesc->pset_nr = nslots;
1305 edesc->residue = edesc->residue_stat = buf_len;
1306 edesc->direction = direction;
1307 edesc->echan = echan;
1308
1309 dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1310 __func__, echan->ch_num, nslots, period_len, buf_len);
1311
1312 for (i = 0; i < nslots; i++) {
1313 /* Allocate a PaRAM slot, if needed */
1314 if (echan->slot[i] < 0) {
1315 echan->slot[i] =
1316 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1317 if (echan->slot[i] < 0) {
1318 kfree(edesc);
1319 dev_err(dev, "%s: Failed to allocate slot\n",
1320 __func__);
1321 return NULL;
1322 }
1323 }
1324
1325 if (i == nslots - 1) {
1326 memcpy(&edesc->pset[i], &edesc->pset[0],
1327 sizeof(edesc->pset[0]));
1328 break;
1329 }
1330
1331 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1332 dst_addr, burst, dev_width, period_len,
1333 direction);
1334 if (ret < 0) {
1335 kfree(edesc);
1336 return NULL;
1337 }
1338
1339 if (direction == DMA_DEV_TO_MEM)
1340 dst_addr += period_len;
1341 else
1342 src_addr += period_len;
1343
1344 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
1345 dev_vdbg(dev,
1346 "\n pset[%d]:\n"
1347 " chnum\t%d\n"
1348 " slot\t%d\n"
1349 " opt\t%08x\n"
1350 " src\t%08x\n"
1351 " dst\t%08x\n"
1352 " abcnt\t%08x\n"
1353 " ccnt\t%08x\n"
1354 " bidx\t%08x\n"
1355 " cidx\t%08x\n"
1356 " lkrld\t%08x\n",
1357 i, echan->ch_num, echan->slot[i],
1358 edesc->pset[i].param.opt,
1359 edesc->pset[i].param.src,
1360 edesc->pset[i].param.dst,
1361 edesc->pset[i].param.a_b_cnt,
1362 edesc->pset[i].param.ccnt,
1363 edesc->pset[i].param.src_dst_bidx,
1364 edesc->pset[i].param.src_dst_cidx,
1365 edesc->pset[i].param.link_bcntrld);
1366
1367 edesc->absync = ret;
1368
1369 /*
1370 * Enable period interrupt only if it is requested
1371 */
1372 if (tx_flags & DMA_PREP_INTERRUPT) {
1373 edesc->pset[i].param.opt |= TCINTEN;
1374
1375 /* Also enable intermediate interrupts if necessary */
1376 if (use_intermediate)
1377 edesc->pset[i].param.opt |= ITCINTEN;
1378 }
1379 }
1380
1381 /* Place the cyclic channel to highest priority queue */
1382 if (!echan->tc)
1383 edma_assign_channel_eventq(echan, EVENTQ_0);
1384
1385 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1386 }
1387
1388 static void edma_completion_handler(struct edma_chan *echan)
1389 {
1390 struct device *dev = echan->vchan.chan.device->dev;
1391 struct edma_desc *edesc;
1392
1393 spin_lock(&echan->vchan.lock);
1394 edesc = echan->edesc;
1395 if (edesc) {
1396 if (edesc->cyclic) {
1397 vchan_cyclic_callback(&edesc->vdesc);
1398 spin_unlock(&echan->vchan.lock);
1399 return;
1400 } else if (edesc->processed == edesc->pset_nr) {
1401 edesc->residue = 0;
1402 edma_stop(echan);
1403 vchan_cookie_complete(&edesc->vdesc);
1404 echan->edesc = NULL;
1405
1406 dev_dbg(dev, "Transfer completed on channel %d\n",
1407 echan->ch_num);
1408 } else {
1409 dev_dbg(dev, "Sub transfer completed on channel %d\n",
1410 echan->ch_num);
1411
1412 edma_pause(echan);
1413
1414 /* Update statistics for tx_status */
1415 edesc->residue -= edesc->sg_len;
1416 edesc->residue_stat = edesc->residue;
1417 edesc->processed_stat = edesc->processed;
1418 }
1419 edma_execute(echan);
1420 }
1421
1422 spin_unlock(&echan->vchan.lock);
1423 }
1424
1425 /* eDMA interrupt handler */
1426 static irqreturn_t dma_irq_handler(int irq, void *data)
1427 {
1428 struct edma_cc *ecc = data;
1429 int ctlr;
1430 u32 sh_ier;
1431 u32 sh_ipr;
1432 u32 bank;
1433
1434 ctlr = ecc->id;
1435 if (ctlr < 0)
1436 return IRQ_NONE;
1437
1438 dev_vdbg(ecc->dev, "dma_irq_handler\n");
1439
1440 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
1441 if (!sh_ipr) {
1442 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
1443 if (!sh_ipr)
1444 return IRQ_NONE;
1445 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
1446 bank = 1;
1447 } else {
1448 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
1449 bank = 0;
1450 }
1451
1452 do {
1453 u32 slot;
1454 u32 channel;
1455
1456 slot = __ffs(sh_ipr);
1457 sh_ipr &= ~(BIT(slot));
1458
1459 if (sh_ier & BIT(slot)) {
1460 channel = (bank << 5) | slot;
1461 /* Clear the corresponding IPR bits */
1462 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
1463 edma_completion_handler(&ecc->slave_chans[channel]);
1464 }
1465 } while (sh_ipr);
1466
1467 edma_shadow0_write(ecc, SH_IEVAL, 1);
1468 return IRQ_HANDLED;
1469 }
1470
1471 static void edma_error_handler(struct edma_chan *echan)
1472 {
1473 struct edma_cc *ecc = echan->ecc;
1474 struct device *dev = echan->vchan.chan.device->dev;
1475 struct edmacc_param p;
1476
1477 if (!echan->edesc)
1478 return;
1479
1480 spin_lock(&echan->vchan.lock);
1481
1482 edma_read_slot(ecc, echan->slot[0], &p);
1483 /*
1484 * Issue later based on missed flag which will be sure
1485 * to happen as:
1486 * (1) we finished transmitting an intermediate slot and
1487 * edma_execute is coming up.
1488 * (2) or we finished current transfer and issue will
1489 * call edma_execute.
1490 *
1491 * Important note: issuing can be dangerous here and
1492 * lead to some nasty recursion when we are in a NULL
1493 * slot. So we avoid doing so and set the missed flag.
1494 */
1495 if (p.a_b_cnt == 0 && p.ccnt == 0) {
1496 dev_dbg(dev, "Error on null slot, setting miss\n");
1497 echan->missed = 1;
1498 } else {
1499 /*
1500 * The slot is already programmed but the event got
1501 * missed, so its safe to issue it here.
1502 */
1503 dev_dbg(dev, "Missed event, TRIGGERING\n");
1504 edma_clean_channel(echan);
1505 edma_stop(echan);
1506 edma_start(echan);
1507 edma_trigger_channel(echan);
1508 }
1509 spin_unlock(&echan->vchan.lock);
1510 }
1511
1512 static inline bool edma_error_pending(struct edma_cc *ecc)
1513 {
1514 if (edma_read_array(ecc, EDMA_EMR, 0) ||
1515 edma_read_array(ecc, EDMA_EMR, 1) ||
1516 edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
1517 return true;
1518
1519 return false;
1520 }
1521
1522 /* eDMA error interrupt handler */
1523 static irqreturn_t dma_ccerr_handler(int irq, void *data)
1524 {
1525 struct edma_cc *ecc = data;
1526 int i, j;
1527 int ctlr;
1528 unsigned int cnt = 0;
1529 unsigned int val;
1530
1531 ctlr = ecc->id;
1532 if (ctlr < 0)
1533 return IRQ_NONE;
1534
1535 dev_vdbg(ecc->dev, "dma_ccerr_handler\n");
1536
1537 if (!edma_error_pending(ecc)) {
1538 /*
1539 * The registers indicate no pending error event but the irq
1540 * handler has been called.
1541 * Ask eDMA to re-evaluate the error registers.
1542 */
1543 dev_err(ecc->dev, "%s: Error interrupt without error event!\n",
1544 __func__);
1545 edma_write(ecc, EDMA_EEVAL, 1);
1546 return IRQ_NONE;
1547 }
1548
1549 while (1) {
1550 /* Event missed register(s) */
1551 for (j = 0; j < 2; j++) {
1552 unsigned long emr;
1553
1554 val = edma_read_array(ecc, EDMA_EMR, j);
1555 if (!val)
1556 continue;
1557
1558 dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
1559 emr = val;
1560 for (i = find_next_bit(&emr, 32, 0); i < 32;
1561 i = find_next_bit(&emr, 32, i + 1)) {
1562 int k = (j << 5) + i;
1563
1564 /* Clear the corresponding EMR bits */
1565 edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
1566 /* Clear any SER */
1567 edma_shadow0_write_array(ecc, SH_SECR, j,
1568 BIT(i));
1569 edma_error_handler(&ecc->slave_chans[k]);
1570 }
1571 }
1572
1573 val = edma_read(ecc, EDMA_QEMR);
1574 if (val) {
1575 dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
1576 /* Not reported, just clear the interrupt reason. */
1577 edma_write(ecc, EDMA_QEMCR, val);
1578 edma_shadow0_write(ecc, SH_QSECR, val);
1579 }
1580
1581 val = edma_read(ecc, EDMA_CCERR);
1582 if (val) {
1583 dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
1584 /* Not reported, just clear the interrupt reason. */
1585 edma_write(ecc, EDMA_CCERRCLR, val);
1586 }
1587
1588 if (!edma_error_pending(ecc))
1589 break;
1590 cnt++;
1591 if (cnt > 10)
1592 break;
1593 }
1594 edma_write(ecc, EDMA_EEVAL, 1);
1595 return IRQ_HANDLED;
1596 }
1597
1598 /* Alloc channel resources */
1599 static int edma_alloc_chan_resources(struct dma_chan *chan)
1600 {
1601 struct edma_chan *echan = to_edma_chan(chan);
1602 struct edma_cc *ecc = echan->ecc;
1603 struct device *dev = ecc->dev;
1604 enum dma_event_q eventq_no = EVENTQ_DEFAULT;
1605 int ret;
1606
1607 if (echan->tc) {
1608 eventq_no = echan->tc->id;
1609 } else if (ecc->tc_list) {
1610 /* memcpy channel */
1611 echan->tc = &ecc->tc_list[ecc->info->default_queue];
1612 eventq_no = echan->tc->id;
1613 }
1614
1615 ret = edma_alloc_channel(echan, eventq_no);
1616 if (ret)
1617 return ret;
1618
1619 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num);
1620 if (echan->slot[0] < 0) {
1621 dev_err(dev, "Entry slot allocation failed for channel %u\n",
1622 EDMA_CHAN_SLOT(echan->ch_num));
1623 goto err_slot;
1624 }
1625
1626 /* Set up channel -> slot mapping for the entry slot */
1627 edma_set_chmap(echan, echan->slot[0]);
1628 echan->alloced = true;
1629
1630 dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
1631 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
1632 echan->hw_triggered ? "HW" : "SW");
1633
1634 return 0;
1635
1636 err_slot:
1637 edma_free_channel(echan);
1638 return ret;
1639 }
1640
1641 /* Free channel resources */
1642 static void edma_free_chan_resources(struct dma_chan *chan)
1643 {
1644 struct edma_chan *echan = to_edma_chan(chan);
1645 struct device *dev = echan->ecc->dev;
1646 int i;
1647
1648 /* Terminate transfers */
1649 edma_stop(echan);
1650
1651 vchan_free_chan_resources(&echan->vchan);
1652
1653 /* Free EDMA PaRAM slots */
1654 for (i = 0; i < EDMA_MAX_SLOTS; i++) {
1655 if (echan->slot[i] >= 0) {
1656 edma_free_slot(echan->ecc, echan->slot[i]);
1657 echan->slot[i] = -1;
1658 }
1659 }
1660
1661 /* Set entry slot to the dummy slot */
1662 edma_set_chmap(echan, echan->ecc->dummy_slot);
1663
1664 /* Free EDMA channel */
1665 if (echan->alloced) {
1666 edma_free_channel(echan);
1667 echan->alloced = false;
1668 }
1669
1670 echan->tc = NULL;
1671 echan->hw_triggered = false;
1672
1673 dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n",
1674 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id);
1675 }
1676
1677 /* Send pending descriptor to hardware */
1678 static void edma_issue_pending(struct dma_chan *chan)
1679 {
1680 struct edma_chan *echan = to_edma_chan(chan);
1681 unsigned long flags;
1682
1683 spin_lock_irqsave(&echan->vchan.lock, flags);
1684 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
1685 edma_execute(echan);
1686 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1687 }
1688
1689 /*
1690 * This limit exists to avoid a possible infinite loop when waiting for proof
1691 * that a particular transfer is completed. This limit can be hit if there
1692 * are large bursts to/from slow devices or the CPU is never able to catch
1693 * the DMA hardware idle. On an AM335x transfering 48 bytes from the UART
1694 * RX-FIFO, as many as 55 loops have been seen.
1695 */
1696 #define EDMA_MAX_TR_WAIT_LOOPS 1000
1697
1698 static u32 edma_residue(struct edma_desc *edesc)
1699 {
1700 bool dst = edesc->direction == DMA_DEV_TO_MEM;
1701 int loop_count = EDMA_MAX_TR_WAIT_LOOPS;
1702 struct edma_chan *echan = edesc->echan;
1703 struct edma_pset *pset = edesc->pset;
1704 dma_addr_t done, pos;
1705 int i;
1706
1707 /*
1708 * We always read the dst/src position from the first RamPar
1709 * pset. That's the one which is active now.
1710 */
1711 pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1712
1713 /*
1714 * "pos" may represent a transfer request that is still being
1715 * processed by the EDMACC or EDMATC. We will busy wait until
1716 * any one of the situations occurs:
1717 * 1. the DMA hardware is idle
1718 * 2. a new transfer request is setup
1719 * 3. we hit the loop limit
1720 */
1721 while (edma_read(echan->ecc, EDMA_CCSTAT) & EDMA_CCSTAT_ACTV) {
1722 /* check if a new transfer request is setup */
1723 if (edma_get_position(echan->ecc,
1724 echan->slot[0], dst) != pos) {
1725 break;
1726 }
1727
1728 if (!--loop_count) {
1729 dev_dbg_ratelimited(echan->vchan.chan.device->dev,
1730 "%s: timeout waiting for PaRAM update\n",
1731 __func__);
1732 break;
1733 }
1734
1735 cpu_relax();
1736 }
1737
1738 /*
1739 * Cyclic is simple. Just subtract pset[0].addr from pos.
1740 *
1741 * We never update edesc->residue in the cyclic case, so we
1742 * can tell the remaining room to the end of the circular
1743 * buffer.
1744 */
1745 if (edesc->cyclic) {
1746 done = pos - pset->addr;
1747 edesc->residue_stat = edesc->residue - done;
1748 return edesc->residue_stat;
1749 }
1750
1751 /*
1752 * For SG operation we catch up with the last processed
1753 * status.
1754 */
1755 pset += edesc->processed_stat;
1756
1757 for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
1758 /*
1759 * If we are inside this pset address range, we know
1760 * this is the active one. Get the current delta and
1761 * stop walking the psets.
1762 */
1763 if (pos >= pset->addr && pos < pset->addr + pset->len)
1764 return edesc->residue_stat - (pos - pset->addr);
1765
1766 /* Otherwise mark it done and update residue_stat. */
1767 edesc->processed_stat++;
1768 edesc->residue_stat -= pset->len;
1769 }
1770 return edesc->residue_stat;
1771 }
1772
1773 /* Check request completion status */
1774 static enum dma_status edma_tx_status(struct dma_chan *chan,
1775 dma_cookie_t cookie,
1776 struct dma_tx_state *txstate)
1777 {
1778 struct edma_chan *echan = to_edma_chan(chan);
1779 struct virt_dma_desc *vdesc;
1780 enum dma_status ret;
1781 unsigned long flags;
1782
1783 ret = dma_cookie_status(chan, cookie, txstate);
1784 if (ret == DMA_COMPLETE || !txstate)
1785 return ret;
1786
1787 spin_lock_irqsave(&echan->vchan.lock, flags);
1788 if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
1789 txstate->residue = edma_residue(echan->edesc);
1790 else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
1791 txstate->residue = to_edma_desc(&vdesc->tx)->residue;
1792 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1793
1794 return ret;
1795 }
1796
1797 static bool edma_is_memcpy_channel(int ch_num, s32 *memcpy_channels)
1798 {
1799 if (!memcpy_channels)
1800 return false;
1801 while (*memcpy_channels != -1) {
1802 if (*memcpy_channels == ch_num)
1803 return true;
1804 memcpy_channels++;
1805 }
1806 return false;
1807 }
1808
1809 #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1810 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1811 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
1812 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1813
1814 static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode)
1815 {
1816 struct dma_device *s_ddev = &ecc->dma_slave;
1817 struct dma_device *m_ddev = NULL;
1818 s32 *memcpy_channels = ecc->info->memcpy_channels;
1819 int i, j;
1820
1821 dma_cap_zero(s_ddev->cap_mask);
1822 dma_cap_set(DMA_SLAVE, s_ddev->cap_mask);
1823 dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask);
1824 if (ecc->legacy_mode && !memcpy_channels) {
1825 dev_warn(ecc->dev,
1826 "Legacy memcpy is enabled, things might not work\n");
1827
1828 dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask);
1829 s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1830 s_ddev->directions = BIT(DMA_MEM_TO_MEM);
1831 }
1832
1833 s_ddev->device_prep_slave_sg = edma_prep_slave_sg;
1834 s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic;
1835 s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1836 s_ddev->device_free_chan_resources = edma_free_chan_resources;
1837 s_ddev->device_issue_pending = edma_issue_pending;
1838 s_ddev->device_tx_status = edma_tx_status;
1839 s_ddev->device_config = edma_slave_config;
1840 s_ddev->device_pause = edma_dma_pause;
1841 s_ddev->device_resume = edma_dma_resume;
1842 s_ddev->device_terminate_all = edma_terminate_all;
1843 s_ddev->device_synchronize = edma_synchronize;
1844
1845 s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1846 s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1847 s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV));
1848 s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1849
1850 s_ddev->dev = ecc->dev;
1851 INIT_LIST_HEAD(&s_ddev->channels);
1852
1853 if (memcpy_channels) {
1854 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL);
1855 ecc->dma_memcpy = m_ddev;
1856
1857 dma_cap_zero(m_ddev->cap_mask);
1858 dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask);
1859
1860 m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1861 m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1862 m_ddev->device_free_chan_resources = edma_free_chan_resources;
1863 m_ddev->device_issue_pending = edma_issue_pending;
1864 m_ddev->device_tx_status = edma_tx_status;
1865 m_ddev->device_config = edma_slave_config;
1866 m_ddev->device_pause = edma_dma_pause;
1867 m_ddev->device_resume = edma_dma_resume;
1868 m_ddev->device_terminate_all = edma_terminate_all;
1869 m_ddev->device_synchronize = edma_synchronize;
1870
1871 m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1872 m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1873 m_ddev->directions = BIT(DMA_MEM_TO_MEM);
1874 m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1875
1876 m_ddev->dev = ecc->dev;
1877 INIT_LIST_HEAD(&m_ddev->channels);
1878 } else if (!ecc->legacy_mode) {
1879 dev_info(ecc->dev, "memcpy is disabled\n");
1880 }
1881
1882 for (i = 0; i < ecc->num_channels; i++) {
1883 struct edma_chan *echan = &ecc->slave_chans[i];
1884 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
1885 echan->ecc = ecc;
1886 echan->vchan.desc_free = edma_desc_free;
1887
1888 if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels))
1889 vchan_init(&echan->vchan, m_ddev);
1890 else
1891 vchan_init(&echan->vchan, s_ddev);
1892
1893 INIT_LIST_HEAD(&echan->node);
1894 for (j = 0; j < EDMA_MAX_SLOTS; j++)
1895 echan->slot[j] = -1;
1896 }
1897 }
1898
1899 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1900 struct edma_cc *ecc)
1901 {
1902 int i;
1903 u32 value, cccfg;
1904 s8 (*queue_priority_map)[2];
1905
1906 /* Decode the eDMA3 configuration from CCCFG register */
1907 cccfg = edma_read(ecc, EDMA_CCCFG);
1908
1909 value = GET_NUM_REGN(cccfg);
1910 ecc->num_region = BIT(value);
1911
1912 value = GET_NUM_DMACH(cccfg);
1913 ecc->num_channels = BIT(value + 1);
1914
1915 value = GET_NUM_QDMACH(cccfg);
1916 ecc->num_qchannels = value * 2;
1917
1918 value = GET_NUM_PAENTRY(cccfg);
1919 ecc->num_slots = BIT(value + 4);
1920
1921 value = GET_NUM_EVQUE(cccfg);
1922 ecc->num_tc = value + 1;
1923
1924 ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
1925
1926 dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
1927 dev_dbg(dev, "num_region: %u\n", ecc->num_region);
1928 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
1929 dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
1930 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
1931 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
1932 dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
1933
1934 /* Nothing need to be done if queue priority is provided */
1935 if (pdata->queue_priority_mapping)
1936 return 0;
1937
1938 /*
1939 * Configure TC/queue priority as follows:
1940 * Q0 - priority 0
1941 * Q1 - priority 1
1942 * Q2 - priority 2
1943 * ...
1944 * The meaning of priority numbers: 0 highest priority, 7 lowest
1945 * priority. So Q0 is the highest priority queue and the last queue has
1946 * the lowest priority.
1947 */
1948 queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
1949 GFP_KERNEL);
1950 if (!queue_priority_map)
1951 return -ENOMEM;
1952
1953 for (i = 0; i < ecc->num_tc; i++) {
1954 queue_priority_map[i][0] = i;
1955 queue_priority_map[i][1] = i;
1956 }
1957 queue_priority_map[i][0] = -1;
1958 queue_priority_map[i][1] = -1;
1959
1960 pdata->queue_priority_mapping = queue_priority_map;
1961 /* Default queue has the lowest priority */
1962 pdata->default_queue = i - 1;
1963
1964 return 0;
1965 }
1966
1967 #if IS_ENABLED(CONFIG_OF)
1968 static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
1969 size_t sz)
1970 {
1971 const char pname[] = "ti,edma-xbar-event-map";
1972 struct resource res;
1973 void __iomem *xbar;
1974 s16 (*xbar_chans)[2];
1975 size_t nelm = sz / sizeof(s16);
1976 u32 shift, offset, mux;
1977 int ret, i;
1978
1979 xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
1980 if (!xbar_chans)
1981 return -ENOMEM;
1982
1983 ret = of_address_to_resource(dev->of_node, 1, &res);
1984 if (ret)
1985 return -ENOMEM;
1986
1987 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1988 if (!xbar)
1989 return -ENOMEM;
1990
1991 ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
1992 nelm);
1993 if (ret)
1994 return -EIO;
1995
1996 /* Invalidate last entry for the other user of this mess */
1997 nelm >>= 1;
1998 xbar_chans[nelm][0] = -1;
1999 xbar_chans[nelm][1] = -1;
2000
2001 for (i = 0; i < nelm; i++) {
2002 shift = (xbar_chans[i][1] & 0x03) << 3;
2003 offset = xbar_chans[i][1] & 0xfffffffc;
2004 mux = readl(xbar + offset);
2005 mux &= ~(0xff << shift);
2006 mux |= xbar_chans[i][0] << shift;
2007 writel(mux, (xbar + offset));
2008 }
2009
2010 pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
2011 return 0;
2012 }
2013
2014 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2015 bool legacy_mode)
2016 {
2017 struct edma_soc_info *info;
2018 struct property *prop;
2019 size_t sz;
2020 int ret;
2021
2022 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
2023 if (!info)
2024 return ERR_PTR(-ENOMEM);
2025
2026 if (legacy_mode) {
2027 prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map",
2028 &sz);
2029 if (prop) {
2030 ret = edma_xbar_event_map(dev, info, sz);
2031 if (ret)
2032 return ERR_PTR(ret);
2033 }
2034 return info;
2035 }
2036
2037 /* Get the list of channels allocated to be used for memcpy */
2038 prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz);
2039 if (prop) {
2040 const char pname[] = "ti,edma-memcpy-channels";
2041 size_t nelm = sz / sizeof(s32);
2042 s32 *memcpy_ch;
2043
2044 memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s32),
2045 GFP_KERNEL);
2046 if (!memcpy_ch)
2047 return ERR_PTR(-ENOMEM);
2048
2049 ret = of_property_read_u32_array(dev->of_node, pname,
2050 (u32 *)memcpy_ch, nelm);
2051 if (ret)
2052 return ERR_PTR(ret);
2053
2054 memcpy_ch[nelm] = -1;
2055 info->memcpy_channels = memcpy_ch;
2056 }
2057
2058 prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges",
2059 &sz);
2060 if (prop) {
2061 const char pname[] = "ti,edma-reserved-slot-ranges";
2062 u32 (*tmp)[2];
2063 s16 (*rsv_slots)[2];
2064 size_t nelm = sz / sizeof(*tmp);
2065 struct edma_rsv_info *rsv_info;
2066 int i;
2067
2068 if (!nelm)
2069 return info;
2070
2071 tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL);
2072 if (!tmp)
2073 return ERR_PTR(-ENOMEM);
2074
2075 rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL);
2076 if (!rsv_info) {
2077 kfree(tmp);
2078 return ERR_PTR(-ENOMEM);
2079 }
2080
2081 rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots),
2082 GFP_KERNEL);
2083 if (!rsv_slots) {
2084 kfree(tmp);
2085 return ERR_PTR(-ENOMEM);
2086 }
2087
2088 ret = of_property_read_u32_array(dev->of_node, pname,
2089 (u32 *)tmp, nelm * 2);
2090 if (ret) {
2091 kfree(tmp);
2092 return ERR_PTR(ret);
2093 }
2094
2095 for (i = 0; i < nelm; i++) {
2096 rsv_slots[i][0] = tmp[i][0];
2097 rsv_slots[i][1] = tmp[i][1];
2098 }
2099 rsv_slots[nelm][0] = -1;
2100 rsv_slots[nelm][1] = -1;
2101
2102 info->rsv = rsv_info;
2103 info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots;
2104
2105 kfree(tmp);
2106 }
2107
2108 return info;
2109 }
2110
2111 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2112 struct of_dma *ofdma)
2113 {
2114 struct edma_cc *ecc = ofdma->of_dma_data;
2115 struct dma_chan *chan = NULL;
2116 struct edma_chan *echan;
2117 int i;
2118
2119 if (!ecc || dma_spec->args_count < 1)
2120 return NULL;
2121
2122 for (i = 0; i < ecc->num_channels; i++) {
2123 echan = &ecc->slave_chans[i];
2124 if (echan->ch_num == dma_spec->args[0]) {
2125 chan = &echan->vchan.chan;
2126 break;
2127 }
2128 }
2129
2130 if (!chan)
2131 return NULL;
2132
2133 if (echan->ecc->legacy_mode && dma_spec->args_count == 1)
2134 goto out;
2135
2136 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 &&
2137 dma_spec->args[1] < echan->ecc->num_tc) {
2138 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]];
2139 goto out;
2140 }
2141
2142 return NULL;
2143 out:
2144 /* The channel is going to be used as HW synchronized */
2145 echan->hw_triggered = true;
2146 return dma_get_slave_channel(chan);
2147 }
2148 #else
2149 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2150 bool legacy_mode)
2151 {
2152 return ERR_PTR(-EINVAL);
2153 }
2154
2155 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2156 struct of_dma *ofdma)
2157 {
2158 return NULL;
2159 }
2160 #endif
2161
2162 static int edma_probe(struct platform_device *pdev)
2163 {
2164 struct edma_soc_info *info = pdev->dev.platform_data;
2165 s8 (*queue_priority_mapping)[2];
2166 int i, off, ln;
2167 const s16 (*rsv_slots)[2];
2168 const s16 (*xbar_chans)[2];
2169 int irq;
2170 char *irq_name;
2171 struct resource *mem;
2172 struct device_node *node = pdev->dev.of_node;
2173 struct device *dev = &pdev->dev;
2174 struct edma_cc *ecc;
2175 bool legacy_mode = true;
2176 int ret;
2177
2178 if (node) {
2179 const struct of_device_id *match;
2180
2181 match = of_match_node(edma_of_ids, node);
2182 if (match && (u32)match->data == EDMA_BINDING_TPCC)
2183 legacy_mode = false;
2184
2185 info = edma_setup_info_from_dt(dev, legacy_mode);
2186 if (IS_ERR(info)) {
2187 dev_err(dev, "failed to get DT data\n");
2188 return PTR_ERR(info);
2189 }
2190 }
2191
2192 if (!info)
2193 return -ENODEV;
2194
2195 pm_runtime_enable(dev);
2196 ret = pm_runtime_get_sync(dev);
2197 if (ret < 0) {
2198 dev_err(dev, "pm_runtime_get_sync() failed\n");
2199 return ret;
2200 }
2201
2202 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2203 if (ret)
2204 return ret;
2205
2206 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
2207 if (!ecc)
2208 return -ENOMEM;
2209
2210 ecc->dev = dev;
2211 ecc->id = pdev->id;
2212 ecc->legacy_mode = legacy_mode;
2213 /* When booting with DT the pdev->id is -1 */
2214 if (ecc->id < 0)
2215 ecc->id = 0;
2216
2217 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
2218 if (!mem) {
2219 dev_dbg(dev, "mem resource not found, using index 0\n");
2220 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2221 if (!mem) {
2222 dev_err(dev, "no mem resource?\n");
2223 return -ENODEV;
2224 }
2225 }
2226 ecc->base = devm_ioremap_resource(dev, mem);
2227 if (IS_ERR(ecc->base))
2228 return PTR_ERR(ecc->base);
2229
2230 platform_set_drvdata(pdev, ecc);
2231
2232 /* Get eDMA3 configuration from IP */
2233 ret = edma_setup_from_hw(dev, info, ecc);
2234 if (ret)
2235 return ret;
2236
2237 /* Allocate memory based on the information we got from the IP */
2238 ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
2239 sizeof(*ecc->slave_chans), GFP_KERNEL);
2240 if (!ecc->slave_chans)
2241 return -ENOMEM;
2242
2243 ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
2244 sizeof(unsigned long), GFP_KERNEL);
2245 if (!ecc->slot_inuse)
2246 return -ENOMEM;
2247
2248 ecc->default_queue = info->default_queue;
2249
2250 for (i = 0; i < ecc->num_slots; i++)
2251 edma_write_slot(ecc, i, &dummy_paramset);
2252
2253 if (info->rsv) {
2254 /* Set the reserved slots in inuse list */
2255 rsv_slots = info->rsv->rsv_slots;
2256 if (rsv_slots) {
2257 for (i = 0; rsv_slots[i][0] != -1; i++) {
2258 off = rsv_slots[i][0];
2259 ln = rsv_slots[i][1];
2260 set_bits(off, ln, ecc->slot_inuse);
2261 }
2262 }
2263 }
2264
2265 /* Clear the xbar mapped channels in unused list */
2266 xbar_chans = info->xbar_chans;
2267 if (xbar_chans) {
2268 for (i = 0; xbar_chans[i][1] != -1; i++) {
2269 off = xbar_chans[i][1];
2270 }
2271 }
2272
2273 irq = platform_get_irq_byname(pdev, "edma3_ccint");
2274 if (irq < 0 && node)
2275 irq = irq_of_parse_and_map(node, 0);
2276
2277 if (irq >= 0) {
2278 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
2279 dev_name(dev));
2280 ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
2281 ecc);
2282 if (ret) {
2283 dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
2284 return ret;
2285 }
2286 }
2287
2288 irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
2289 if (irq < 0 && node)
2290 irq = irq_of_parse_and_map(node, 2);
2291
2292 if (irq >= 0) {
2293 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
2294 dev_name(dev));
2295 ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
2296 ecc);
2297 if (ret) {
2298 dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
2299 return ret;
2300 }
2301 }
2302
2303 ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
2304 if (ecc->dummy_slot < 0) {
2305 dev_err(dev, "Can't allocate PaRAM dummy slot\n");
2306 return ecc->dummy_slot;
2307 }
2308
2309 queue_priority_mapping = info->queue_priority_mapping;
2310
2311 if (!ecc->legacy_mode) {
2312 int lowest_priority = 0;
2313 struct of_phandle_args tc_args;
2314
2315 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc,
2316 sizeof(*ecc->tc_list), GFP_KERNEL);
2317 if (!ecc->tc_list)
2318 return -ENOMEM;
2319
2320 for (i = 0;; i++) {
2321 ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs",
2322 1, i, &tc_args);
2323 if (ret || i == ecc->num_tc)
2324 break;
2325
2326 ecc->tc_list[i].node = tc_args.np;
2327 ecc->tc_list[i].id = i;
2328 queue_priority_mapping[i][1] = tc_args.args[0];
2329 if (queue_priority_mapping[i][1] > lowest_priority) {
2330 lowest_priority = queue_priority_mapping[i][1];
2331 info->default_queue = i;
2332 }
2333 }
2334 }
2335
2336 /* Event queue priority mapping */
2337 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2338 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2339 queue_priority_mapping[i][1]);
2340
2341 for (i = 0; i < ecc->num_region; i++) {
2342 edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
2343 edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
2344 edma_write_array(ecc, EDMA_QRAE, i, 0x0);
2345 }
2346 ecc->info = info;
2347
2348 /* Init the dma device and channels */
2349 edma_dma_init(ecc, legacy_mode);
2350
2351 for (i = 0; i < ecc->num_channels; i++) {
2352 /* Assign all channels to the default queue */
2353 edma_assign_channel_eventq(&ecc->slave_chans[i],
2354 info->default_queue);
2355 /* Set entry slot to the dummy slot */
2356 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot);
2357 }
2358
2359 ecc->dma_slave.filter.map = info->slave_map;
2360 ecc->dma_slave.filter.mapcnt = info->slavecnt;
2361 ecc->dma_slave.filter.fn = edma_filter_fn;
2362
2363 ret = dma_async_device_register(&ecc->dma_slave);
2364 if (ret) {
2365 dev_err(dev, "slave ddev registration failed (%d)\n", ret);
2366 goto err_reg1;
2367 }
2368
2369 if (ecc->dma_memcpy) {
2370 ret = dma_async_device_register(ecc->dma_memcpy);
2371 if (ret) {
2372 dev_err(dev, "memcpy ddev registration failed (%d)\n",
2373 ret);
2374 dma_async_device_unregister(&ecc->dma_slave);
2375 goto err_reg1;
2376 }
2377 }
2378
2379 if (node)
2380 of_dma_controller_register(node, of_edma_xlate, ecc);
2381
2382 dev_info(dev, "TI EDMA DMA engine driver\n");
2383
2384 return 0;
2385
2386 err_reg1:
2387 edma_free_slot(ecc, ecc->dummy_slot);
2388 return ret;
2389 }
2390
2391 static int edma_remove(struct platform_device *pdev)
2392 {
2393 struct device *dev = &pdev->dev;
2394 struct edma_cc *ecc = dev_get_drvdata(dev);
2395
2396 if (dev->of_node)
2397 of_dma_controller_free(dev->of_node);
2398 dma_async_device_unregister(&ecc->dma_slave);
2399 if (ecc->dma_memcpy)
2400 dma_async_device_unregister(ecc->dma_memcpy);
2401 edma_free_slot(ecc, ecc->dummy_slot);
2402
2403 return 0;
2404 }
2405
2406 #ifdef CONFIG_PM_SLEEP
2407 static int edma_pm_suspend(struct device *dev)
2408 {
2409 struct edma_cc *ecc = dev_get_drvdata(dev);
2410 struct edma_chan *echan = ecc->slave_chans;
2411 int i;
2412
2413 for (i = 0; i < ecc->num_channels; i++) {
2414 if (echan[i].alloced)
2415 edma_setup_interrupt(&echan[i], false);
2416 }
2417
2418 return 0;
2419 }
2420
2421 static int edma_pm_resume(struct device *dev)
2422 {
2423 struct edma_cc *ecc = dev_get_drvdata(dev);
2424 struct edma_chan *echan = ecc->slave_chans;
2425 int i;
2426 s8 (*queue_priority_mapping)[2];
2427
2428 queue_priority_mapping = ecc->info->queue_priority_mapping;
2429
2430 /* Event queue priority mapping */
2431 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2432 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2433 queue_priority_mapping[i][1]);
2434
2435 for (i = 0; i < ecc->num_channels; i++) {
2436 if (echan[i].alloced) {
2437 /* ensure access through shadow region 0 */
2438 edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
2439 BIT(i & 0x1f));
2440
2441 edma_setup_interrupt(&echan[i], true);
2442
2443 /* Set up channel -> slot mapping for the entry slot */
2444 edma_set_chmap(&echan[i], echan[i].slot[0]);
2445 }
2446 }
2447
2448 return 0;
2449 }
2450 #endif
2451
2452 static const struct dev_pm_ops edma_pm_ops = {
2453 SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume)
2454 };
2455
2456 static struct platform_driver edma_driver = {
2457 .probe = edma_probe,
2458 .remove = edma_remove,
2459 .driver = {
2460 .name = "edma",
2461 .pm = &edma_pm_ops,
2462 .of_match_table = edma_of_ids,
2463 },
2464 };
2465
2466 static int edma_tptc_probe(struct platform_device *pdev)
2467 {
2468 pm_runtime_enable(&pdev->dev);
2469 return pm_runtime_get_sync(&pdev->dev);
2470 }
2471
2472 static struct platform_driver edma_tptc_driver = {
2473 .probe = edma_tptc_probe,
2474 .driver = {
2475 .name = "edma3-tptc",
2476 .of_match_table = edma_tptc_of_ids,
2477 },
2478 };
2479
2480 bool edma_filter_fn(struct dma_chan *chan, void *param)
2481 {
2482 bool match = false;
2483
2484 if (chan->device->dev->driver == &edma_driver.driver) {
2485 struct edma_chan *echan = to_edma_chan(chan);
2486 unsigned ch_req = *(unsigned *)param;
2487 if (ch_req == echan->ch_num) {
2488 /* The channel is going to be used as HW synchronized */
2489 echan->hw_triggered = true;
2490 match = true;
2491 }
2492 }
2493 return match;
2494 }
2495 EXPORT_SYMBOL(edma_filter_fn);
2496
2497 static int edma_init(void)
2498 {
2499 int ret;
2500
2501 ret = platform_driver_register(&edma_tptc_driver);
2502 if (ret)
2503 return ret;
2504
2505 return platform_driver_register(&edma_driver);
2506 }
2507 subsys_initcall(edma_init);
2508
2509 static void __exit edma_exit(void)
2510 {
2511 platform_driver_unregister(&edma_driver);
2512 platform_driver_unregister(&edma_tptc_driver);
2513 }
2514 module_exit(edma_exit);
2515
2516 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
2517 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
2518 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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