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dmaengine: imx-dma: fix slow path issue in prep_dma_cyclic
[deliverable/linux.git] / drivers / dma / imx-dma.c
1 /*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
9 *
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
13 *
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
16 */
17 #include <linux/err.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/mm.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/slab.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/module.h>
30 #include <linux/of_device.h>
31 #include <linux/of_dma.h>
32
33 #include <asm/irq.h>
34 #include <linux/platform_data/dma-imx.h>
35
36 #include "dmaengine.h"
37 #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
38 #define IMX_DMA_CHANNELS 16
39
40 #define IMX_DMA_2D_SLOTS 2
41 #define IMX_DMA_2D_SLOT_A 0
42 #define IMX_DMA_2D_SLOT_B 1
43
44 #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
45 #define IMX_DMA_MEMSIZE_32 (0 << 4)
46 #define IMX_DMA_MEMSIZE_8 (1 << 4)
47 #define IMX_DMA_MEMSIZE_16 (2 << 4)
48 #define IMX_DMA_TYPE_LINEAR (0 << 10)
49 #define IMX_DMA_TYPE_2D (1 << 10)
50 #define IMX_DMA_TYPE_FIFO (2 << 10)
51
52 #define IMX_DMA_ERR_BURST (1 << 0)
53 #define IMX_DMA_ERR_REQUEST (1 << 1)
54 #define IMX_DMA_ERR_TRANSFER (1 << 2)
55 #define IMX_DMA_ERR_BUFFER (1 << 3)
56 #define IMX_DMA_ERR_TIMEOUT (1 << 4)
57
58 #define DMA_DCR 0x00 /* Control Register */
59 #define DMA_DISR 0x04 /* Interrupt status Register */
60 #define DMA_DIMR 0x08 /* Interrupt mask Register */
61 #define DMA_DBTOSR 0x0c /* Burst timeout status Register */
62 #define DMA_DRTOSR 0x10 /* Request timeout Register */
63 #define DMA_DSESR 0x14 /* Transfer Error Status Register */
64 #define DMA_DBOSR 0x18 /* Buffer overflow status Register */
65 #define DMA_DBTOCR 0x1c /* Burst timeout control Register */
66 #define DMA_WSRA 0x40 /* W-Size Register A */
67 #define DMA_XSRA 0x44 /* X-Size Register A */
68 #define DMA_YSRA 0x48 /* Y-Size Register A */
69 #define DMA_WSRB 0x4c /* W-Size Register B */
70 #define DMA_XSRB 0x50 /* X-Size Register B */
71 #define DMA_YSRB 0x54 /* Y-Size Register B */
72 #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
73 #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
74 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
75 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
76 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
77 #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
78 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
79 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
80 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
81
82 #define DCR_DRST (1<<1)
83 #define DCR_DEN (1<<0)
84 #define DBTOCR_EN (1<<15)
85 #define DBTOCR_CNT(x) ((x) & 0x7fff)
86 #define CNTR_CNT(x) ((x) & 0xffffff)
87 #define CCR_ACRPT (1<<14)
88 #define CCR_DMOD_LINEAR (0x0 << 12)
89 #define CCR_DMOD_2D (0x1 << 12)
90 #define CCR_DMOD_FIFO (0x2 << 12)
91 #define CCR_DMOD_EOBFIFO (0x3 << 12)
92 #define CCR_SMOD_LINEAR (0x0 << 10)
93 #define CCR_SMOD_2D (0x1 << 10)
94 #define CCR_SMOD_FIFO (0x2 << 10)
95 #define CCR_SMOD_EOBFIFO (0x3 << 10)
96 #define CCR_MDIR_DEC (1<<9)
97 #define CCR_MSEL_B (1<<8)
98 #define CCR_DSIZ_32 (0x0 << 6)
99 #define CCR_DSIZ_8 (0x1 << 6)
100 #define CCR_DSIZ_16 (0x2 << 6)
101 #define CCR_SSIZ_32 (0x0 << 4)
102 #define CCR_SSIZ_8 (0x1 << 4)
103 #define CCR_SSIZ_16 (0x2 << 4)
104 #define CCR_REN (1<<3)
105 #define CCR_RPT (1<<2)
106 #define CCR_FRC (1<<1)
107 #define CCR_CEN (1<<0)
108 #define RTOR_EN (1<<15)
109 #define RTOR_CLK (1<<14)
110 #define RTOR_PSC (1<<13)
111
112 enum imxdma_prep_type {
113 IMXDMA_DESC_MEMCPY,
114 IMXDMA_DESC_INTERLEAVED,
115 IMXDMA_DESC_SLAVE_SG,
116 IMXDMA_DESC_CYCLIC,
117 };
118
119 struct imx_dma_2d_config {
120 u16 xsr;
121 u16 ysr;
122 u16 wsr;
123 int count;
124 };
125
126 struct imxdma_desc {
127 struct list_head node;
128 struct dma_async_tx_descriptor desc;
129 enum dma_status status;
130 dma_addr_t src;
131 dma_addr_t dest;
132 size_t len;
133 enum dma_transfer_direction direction;
134 enum imxdma_prep_type type;
135 /* For memcpy and interleaved */
136 unsigned int config_port;
137 unsigned int config_mem;
138 /* For interleaved transfers */
139 unsigned int x;
140 unsigned int y;
141 unsigned int w;
142 /* For slave sg and cyclic */
143 struct scatterlist *sg;
144 unsigned int sgcount;
145 };
146
147 struct imxdma_channel {
148 int hw_chaining;
149 struct timer_list watchdog;
150 struct imxdma_engine *imxdma;
151 unsigned int channel;
152
153 struct tasklet_struct dma_tasklet;
154 struct list_head ld_free;
155 struct list_head ld_queue;
156 struct list_head ld_active;
157 int descs_allocated;
158 enum dma_slave_buswidth word_size;
159 dma_addr_t per_address;
160 u32 watermark_level;
161 struct dma_chan chan;
162 struct dma_async_tx_descriptor desc;
163 enum dma_status status;
164 int dma_request;
165 struct scatterlist *sg_list;
166 u32 ccr_from_device;
167 u32 ccr_to_device;
168 bool enabled_2d;
169 int slot_2d;
170 };
171
172 enum imx_dma_type {
173 IMX1_DMA,
174 IMX21_DMA,
175 IMX27_DMA,
176 };
177
178 struct imxdma_engine {
179 struct device *dev;
180 struct device_dma_parameters dma_parms;
181 struct dma_device dma_device;
182 void __iomem *base;
183 struct clk *dma_ahb;
184 struct clk *dma_ipg;
185 spinlock_t lock;
186 struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
187 struct imxdma_channel channel[IMX_DMA_CHANNELS];
188 enum imx_dma_type devtype;
189 };
190
191 struct imxdma_filter_data {
192 struct imxdma_engine *imxdma;
193 int request;
194 };
195
196 static struct platform_device_id imx_dma_devtype[] = {
197 {
198 .name = "imx1-dma",
199 .driver_data = IMX1_DMA,
200 }, {
201 .name = "imx21-dma",
202 .driver_data = IMX21_DMA,
203 }, {
204 .name = "imx27-dma",
205 .driver_data = IMX27_DMA,
206 }, {
207 /* sentinel */
208 }
209 };
210 MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
211
212 static const struct of_device_id imx_dma_of_dev_id[] = {
213 {
214 .compatible = "fsl,imx1-dma",
215 .data = &imx_dma_devtype[IMX1_DMA],
216 }, {
217 .compatible = "fsl,imx21-dma",
218 .data = &imx_dma_devtype[IMX21_DMA],
219 }, {
220 .compatible = "fsl,imx27-dma",
221 .data = &imx_dma_devtype[IMX27_DMA],
222 }, {
223 /* sentinel */
224 }
225 };
226 MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id);
227
228 static inline int is_imx1_dma(struct imxdma_engine *imxdma)
229 {
230 return imxdma->devtype == IMX1_DMA;
231 }
232
233 static inline int is_imx21_dma(struct imxdma_engine *imxdma)
234 {
235 return imxdma->devtype == IMX21_DMA;
236 }
237
238 static inline int is_imx27_dma(struct imxdma_engine *imxdma)
239 {
240 return imxdma->devtype == IMX27_DMA;
241 }
242
243 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
244 {
245 return container_of(chan, struct imxdma_channel, chan);
246 }
247
248 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
249 {
250 struct imxdma_desc *desc;
251
252 if (!list_empty(&imxdmac->ld_active)) {
253 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
254 node);
255 if (desc->type == IMXDMA_DESC_CYCLIC)
256 return true;
257 }
258 return false;
259 }
260
261
262
263 static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
264 unsigned offset)
265 {
266 __raw_writel(val, imxdma->base + offset);
267 }
268
269 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
270 {
271 return __raw_readl(imxdma->base + offset);
272 }
273
274 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
275 {
276 struct imxdma_engine *imxdma = imxdmac->imxdma;
277
278 if (is_imx27_dma(imxdma))
279 return imxdmac->hw_chaining;
280 else
281 return 0;
282 }
283
284 /*
285 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
286 */
287 static inline int imxdma_sg_next(struct imxdma_desc *d)
288 {
289 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
290 struct imxdma_engine *imxdma = imxdmac->imxdma;
291 struct scatterlist *sg = d->sg;
292 unsigned long now;
293
294 now = min(d->len, sg_dma_len(sg));
295 if (d->len != IMX_DMA_LENGTH_LOOP)
296 d->len -= now;
297
298 if (d->direction == DMA_DEV_TO_MEM)
299 imx_dmav1_writel(imxdma, sg->dma_address,
300 DMA_DAR(imxdmac->channel));
301 else
302 imx_dmav1_writel(imxdma, sg->dma_address,
303 DMA_SAR(imxdmac->channel));
304
305 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
306
307 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
308 "size 0x%08x\n", __func__, imxdmac->channel,
309 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
310 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
311 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
312
313 return now;
314 }
315
316 static void imxdma_enable_hw(struct imxdma_desc *d)
317 {
318 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
319 struct imxdma_engine *imxdma = imxdmac->imxdma;
320 int channel = imxdmac->channel;
321 unsigned long flags;
322
323 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
324
325 local_irq_save(flags);
326
327 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
328 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
329 ~(1 << channel), DMA_DIMR);
330 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
331 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
332
333 if (!is_imx1_dma(imxdma) &&
334 d->sg && imxdma_hw_chain(imxdmac)) {
335 d->sg = sg_next(d->sg);
336 if (d->sg) {
337 u32 tmp;
338 imxdma_sg_next(d);
339 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
340 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
341 DMA_CCR(channel));
342 }
343 }
344
345 local_irq_restore(flags);
346 }
347
348 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
349 {
350 struct imxdma_engine *imxdma = imxdmac->imxdma;
351 int channel = imxdmac->channel;
352 unsigned long flags;
353
354 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
355
356 if (imxdma_hw_chain(imxdmac))
357 del_timer(&imxdmac->watchdog);
358
359 local_irq_save(flags);
360 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
361 (1 << channel), DMA_DIMR);
362 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
363 ~CCR_CEN, DMA_CCR(channel));
364 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
365 local_irq_restore(flags);
366 }
367
368 static void imxdma_watchdog(unsigned long data)
369 {
370 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
371 struct imxdma_engine *imxdma = imxdmac->imxdma;
372 int channel = imxdmac->channel;
373
374 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
375
376 /* Tasklet watchdog error handler */
377 tasklet_schedule(&imxdmac->dma_tasklet);
378 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
379 imxdmac->channel);
380 }
381
382 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
383 {
384 struct imxdma_engine *imxdma = dev_id;
385 unsigned int err_mask;
386 int i, disr;
387 int errcode;
388
389 disr = imx_dmav1_readl(imxdma, DMA_DISR);
390
391 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
392 imx_dmav1_readl(imxdma, DMA_DRTOSR) |
393 imx_dmav1_readl(imxdma, DMA_DSESR) |
394 imx_dmav1_readl(imxdma, DMA_DBOSR);
395
396 if (!err_mask)
397 return IRQ_HANDLED;
398
399 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
400
401 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
402 if (!(err_mask & (1 << i)))
403 continue;
404 errcode = 0;
405
406 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
407 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
408 errcode |= IMX_DMA_ERR_BURST;
409 }
410 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
411 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
412 errcode |= IMX_DMA_ERR_REQUEST;
413 }
414 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
415 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
416 errcode |= IMX_DMA_ERR_TRANSFER;
417 }
418 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
419 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
420 errcode |= IMX_DMA_ERR_BUFFER;
421 }
422 /* Tasklet error handler */
423 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
424
425 printk(KERN_WARNING
426 "DMA timeout on channel %d -%s%s%s%s\n", i,
427 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
428 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
429 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
430 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
431 }
432 return IRQ_HANDLED;
433 }
434
435 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
436 {
437 struct imxdma_engine *imxdma = imxdmac->imxdma;
438 int chno = imxdmac->channel;
439 struct imxdma_desc *desc;
440
441 spin_lock(&imxdma->lock);
442 if (list_empty(&imxdmac->ld_active)) {
443 spin_unlock(&imxdma->lock);
444 goto out;
445 }
446
447 desc = list_first_entry(&imxdmac->ld_active,
448 struct imxdma_desc,
449 node);
450 spin_unlock(&imxdma->lock);
451
452 if (desc->sg) {
453 u32 tmp;
454 desc->sg = sg_next(desc->sg);
455
456 if (desc->sg) {
457 imxdma_sg_next(desc);
458
459 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
460
461 if (imxdma_hw_chain(imxdmac)) {
462 /* FIXME: The timeout should probably be
463 * configurable
464 */
465 mod_timer(&imxdmac->watchdog,
466 jiffies + msecs_to_jiffies(500));
467
468 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
469 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
470 } else {
471 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
472 DMA_CCR(chno));
473 tmp |= CCR_CEN;
474 }
475
476 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
477
478 if (imxdma_chan_is_doing_cyclic(imxdmac))
479 /* Tasklet progression */
480 tasklet_schedule(&imxdmac->dma_tasklet);
481
482 return;
483 }
484
485 if (imxdma_hw_chain(imxdmac)) {
486 del_timer(&imxdmac->watchdog);
487 return;
488 }
489 }
490
491 out:
492 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
493 /* Tasklet irq */
494 tasklet_schedule(&imxdmac->dma_tasklet);
495 }
496
497 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
498 {
499 struct imxdma_engine *imxdma = dev_id;
500 int i, disr;
501
502 if (!is_imx1_dma(imxdma))
503 imxdma_err_handler(irq, dev_id);
504
505 disr = imx_dmav1_readl(imxdma, DMA_DISR);
506
507 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
508
509 imx_dmav1_writel(imxdma, disr, DMA_DISR);
510 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
511 if (disr & (1 << i))
512 dma_irq_handle_channel(&imxdma->channel[i]);
513 }
514
515 return IRQ_HANDLED;
516 }
517
518 static int imxdma_xfer_desc(struct imxdma_desc *d)
519 {
520 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
521 struct imxdma_engine *imxdma = imxdmac->imxdma;
522 unsigned long flags;
523 int slot = -1;
524 int i;
525
526 /* Configure and enable */
527 switch (d->type) {
528 case IMXDMA_DESC_INTERLEAVED:
529 /* Try to get a free 2D slot */
530 spin_lock_irqsave(&imxdma->lock, flags);
531 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
532 if ((imxdma->slots_2d[i].count > 0) &&
533 ((imxdma->slots_2d[i].xsr != d->x) ||
534 (imxdma->slots_2d[i].ysr != d->y) ||
535 (imxdma->slots_2d[i].wsr != d->w)))
536 continue;
537 slot = i;
538 break;
539 }
540 if (slot < 0) {
541 spin_unlock_irqrestore(&imxdma->lock, flags);
542 return -EBUSY;
543 }
544
545 imxdma->slots_2d[slot].xsr = d->x;
546 imxdma->slots_2d[slot].ysr = d->y;
547 imxdma->slots_2d[slot].wsr = d->w;
548 imxdma->slots_2d[slot].count++;
549
550 imxdmac->slot_2d = slot;
551 imxdmac->enabled_2d = true;
552 spin_unlock_irqrestore(&imxdma->lock, flags);
553
554 if (slot == IMX_DMA_2D_SLOT_A) {
555 d->config_mem &= ~CCR_MSEL_B;
556 d->config_port &= ~CCR_MSEL_B;
557 imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
558 imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
559 imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
560 } else {
561 d->config_mem |= CCR_MSEL_B;
562 d->config_port |= CCR_MSEL_B;
563 imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
564 imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
565 imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
566 }
567 /*
568 * We fall-through here intentionally, since a 2D transfer is
569 * similar to MEMCPY just adding the 2D slot configuration.
570 */
571 case IMXDMA_DESC_MEMCPY:
572 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
573 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
574 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
575 DMA_CCR(imxdmac->channel));
576
577 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
578
579 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
580 "dma_length=%d\n", __func__, imxdmac->channel,
581 d->dest, d->src, d->len);
582
583 break;
584 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
585 case IMXDMA_DESC_CYCLIC:
586 case IMXDMA_DESC_SLAVE_SG:
587 if (d->direction == DMA_DEV_TO_MEM) {
588 imx_dmav1_writel(imxdma, imxdmac->per_address,
589 DMA_SAR(imxdmac->channel));
590 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
591 DMA_CCR(imxdmac->channel));
592
593 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
594 "total length=%d dev_addr=0x%08x (dev2mem)\n",
595 __func__, imxdmac->channel, d->sg, d->sgcount,
596 d->len, imxdmac->per_address);
597 } else if (d->direction == DMA_MEM_TO_DEV) {
598 imx_dmav1_writel(imxdma, imxdmac->per_address,
599 DMA_DAR(imxdmac->channel));
600 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
601 DMA_CCR(imxdmac->channel));
602
603 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
604 "total length=%d dev_addr=0x%08x (mem2dev)\n",
605 __func__, imxdmac->channel, d->sg, d->sgcount,
606 d->len, imxdmac->per_address);
607 } else {
608 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
609 __func__, imxdmac->channel);
610 return -EINVAL;
611 }
612
613 imxdma_sg_next(d);
614
615 break;
616 default:
617 return -EINVAL;
618 }
619 imxdma_enable_hw(d);
620 return 0;
621 }
622
623 static void imxdma_tasklet(unsigned long data)
624 {
625 struct imxdma_channel *imxdmac = (void *)data;
626 struct imxdma_engine *imxdma = imxdmac->imxdma;
627 struct imxdma_desc *desc;
628
629 spin_lock(&imxdma->lock);
630
631 if (list_empty(&imxdmac->ld_active)) {
632 /* Someone might have called terminate all */
633 goto out;
634 }
635 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
636
637 if (desc->desc.callback)
638 desc->desc.callback(desc->desc.callback_param);
639
640 /* If we are dealing with a cyclic descriptor, keep it on ld_active
641 * and dont mark the descriptor as complete.
642 * Only in non-cyclic cases it would be marked as complete
643 */
644 if (imxdma_chan_is_doing_cyclic(imxdmac))
645 goto out;
646 else
647 dma_cookie_complete(&desc->desc);
648
649 /* Free 2D slot if it was an interleaved transfer */
650 if (imxdmac->enabled_2d) {
651 imxdma->slots_2d[imxdmac->slot_2d].count--;
652 imxdmac->enabled_2d = false;
653 }
654
655 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
656
657 if (!list_empty(&imxdmac->ld_queue)) {
658 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
659 node);
660 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
661 if (imxdma_xfer_desc(desc) < 0)
662 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
663 __func__, imxdmac->channel);
664 }
665 out:
666 spin_unlock(&imxdma->lock);
667 }
668
669 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
670 unsigned long arg)
671 {
672 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
673 struct dma_slave_config *dmaengine_cfg = (void *)arg;
674 struct imxdma_engine *imxdma = imxdmac->imxdma;
675 unsigned long flags;
676 unsigned int mode = 0;
677
678 switch (cmd) {
679 case DMA_TERMINATE_ALL:
680 imxdma_disable_hw(imxdmac);
681
682 spin_lock_irqsave(&imxdma->lock, flags);
683 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
684 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
685 spin_unlock_irqrestore(&imxdma->lock, flags);
686 return 0;
687 case DMA_SLAVE_CONFIG:
688 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
689 imxdmac->per_address = dmaengine_cfg->src_addr;
690 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
691 imxdmac->word_size = dmaengine_cfg->src_addr_width;
692 } else {
693 imxdmac->per_address = dmaengine_cfg->dst_addr;
694 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
695 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
696 }
697
698 switch (imxdmac->word_size) {
699 case DMA_SLAVE_BUSWIDTH_1_BYTE:
700 mode = IMX_DMA_MEMSIZE_8;
701 break;
702 case DMA_SLAVE_BUSWIDTH_2_BYTES:
703 mode = IMX_DMA_MEMSIZE_16;
704 break;
705 default:
706 case DMA_SLAVE_BUSWIDTH_4_BYTES:
707 mode = IMX_DMA_MEMSIZE_32;
708 break;
709 }
710
711 imxdmac->hw_chaining = 0;
712
713 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
714 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
715 CCR_REN;
716 imxdmac->ccr_to_device =
717 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
718 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
719 imx_dmav1_writel(imxdma, imxdmac->dma_request,
720 DMA_RSSR(imxdmac->channel));
721
722 /* Set burst length */
723 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
724 imxdmac->word_size, DMA_BLR(imxdmac->channel));
725
726 return 0;
727 default:
728 return -ENOSYS;
729 }
730
731 return -EINVAL;
732 }
733
734 static enum dma_status imxdma_tx_status(struct dma_chan *chan,
735 dma_cookie_t cookie,
736 struct dma_tx_state *txstate)
737 {
738 return dma_cookie_status(chan, cookie, txstate);
739 }
740
741 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
742 {
743 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
744 struct imxdma_engine *imxdma = imxdmac->imxdma;
745 dma_cookie_t cookie;
746 unsigned long flags;
747
748 spin_lock_irqsave(&imxdma->lock, flags);
749 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
750 cookie = dma_cookie_assign(tx);
751 spin_unlock_irqrestore(&imxdma->lock, flags);
752
753 return cookie;
754 }
755
756 static int imxdma_alloc_chan_resources(struct dma_chan *chan)
757 {
758 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
759 struct imx_dma_data *data = chan->private;
760
761 if (data != NULL)
762 imxdmac->dma_request = data->dma_request;
763
764 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
765 struct imxdma_desc *desc;
766
767 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
768 if (!desc)
769 break;
770 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
771 dma_async_tx_descriptor_init(&desc->desc, chan);
772 desc->desc.tx_submit = imxdma_tx_submit;
773 /* txd.flags will be overwritten in prep funcs */
774 desc->desc.flags = DMA_CTRL_ACK;
775 desc->status = DMA_SUCCESS;
776
777 list_add_tail(&desc->node, &imxdmac->ld_free);
778 imxdmac->descs_allocated++;
779 }
780
781 if (!imxdmac->descs_allocated)
782 return -ENOMEM;
783
784 return imxdmac->descs_allocated;
785 }
786
787 static void imxdma_free_chan_resources(struct dma_chan *chan)
788 {
789 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
790 struct imxdma_engine *imxdma = imxdmac->imxdma;
791 struct imxdma_desc *desc, *_desc;
792 unsigned long flags;
793
794 spin_lock_irqsave(&imxdma->lock, flags);
795
796 imxdma_disable_hw(imxdmac);
797 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
798 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
799
800 spin_unlock_irqrestore(&imxdma->lock, flags);
801
802 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
803 kfree(desc);
804 imxdmac->descs_allocated--;
805 }
806 INIT_LIST_HEAD(&imxdmac->ld_free);
807
808 kfree(imxdmac->sg_list);
809 imxdmac->sg_list = NULL;
810 }
811
812 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
813 struct dma_chan *chan, struct scatterlist *sgl,
814 unsigned int sg_len, enum dma_transfer_direction direction,
815 unsigned long flags, void *context)
816 {
817 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
818 struct scatterlist *sg;
819 int i, dma_length = 0;
820 struct imxdma_desc *desc;
821
822 if (list_empty(&imxdmac->ld_free) ||
823 imxdma_chan_is_doing_cyclic(imxdmac))
824 return NULL;
825
826 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
827
828 for_each_sg(sgl, sg, sg_len, i) {
829 dma_length += sg_dma_len(sg);
830 }
831
832 switch (imxdmac->word_size) {
833 case DMA_SLAVE_BUSWIDTH_4_BYTES:
834 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
835 return NULL;
836 break;
837 case DMA_SLAVE_BUSWIDTH_2_BYTES:
838 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
839 return NULL;
840 break;
841 case DMA_SLAVE_BUSWIDTH_1_BYTE:
842 break;
843 default:
844 return NULL;
845 }
846
847 desc->type = IMXDMA_DESC_SLAVE_SG;
848 desc->sg = sgl;
849 desc->sgcount = sg_len;
850 desc->len = dma_length;
851 desc->direction = direction;
852 if (direction == DMA_DEV_TO_MEM) {
853 desc->src = imxdmac->per_address;
854 } else {
855 desc->dest = imxdmac->per_address;
856 }
857 desc->desc.callback = NULL;
858 desc->desc.callback_param = NULL;
859
860 return &desc->desc;
861 }
862
863 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
864 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
865 size_t period_len, enum dma_transfer_direction direction,
866 unsigned long flags, void *context)
867 {
868 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
869 struct imxdma_engine *imxdma = imxdmac->imxdma;
870 struct imxdma_desc *desc;
871 int i;
872 unsigned int periods = buf_len / period_len;
873
874 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
875 __func__, imxdmac->channel, buf_len, period_len);
876
877 if (list_empty(&imxdmac->ld_free) ||
878 imxdma_chan_is_doing_cyclic(imxdmac))
879 return NULL;
880
881 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
882
883 kfree(imxdmac->sg_list);
884
885 imxdmac->sg_list = kcalloc(periods + 1,
886 sizeof(struct scatterlist), GFP_ATOMIC);
887 if (!imxdmac->sg_list)
888 return NULL;
889
890 sg_init_table(imxdmac->sg_list, periods);
891
892 for (i = 0; i < periods; i++) {
893 imxdmac->sg_list[i].page_link = 0;
894 imxdmac->sg_list[i].offset = 0;
895 imxdmac->sg_list[i].dma_address = dma_addr;
896 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
897 dma_addr += period_len;
898 }
899
900 /* close the loop */
901 imxdmac->sg_list[periods].offset = 0;
902 sg_dma_len(&imxdmac->sg_list[periods]) = 0;
903 imxdmac->sg_list[periods].page_link =
904 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
905
906 desc->type = IMXDMA_DESC_CYCLIC;
907 desc->sg = imxdmac->sg_list;
908 desc->sgcount = periods;
909 desc->len = IMX_DMA_LENGTH_LOOP;
910 desc->direction = direction;
911 if (direction == DMA_DEV_TO_MEM) {
912 desc->src = imxdmac->per_address;
913 } else {
914 desc->dest = imxdmac->per_address;
915 }
916 desc->desc.callback = NULL;
917 desc->desc.callback_param = NULL;
918
919 return &desc->desc;
920 }
921
922 static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
923 struct dma_chan *chan, dma_addr_t dest,
924 dma_addr_t src, size_t len, unsigned long flags)
925 {
926 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
927 struct imxdma_engine *imxdma = imxdmac->imxdma;
928 struct imxdma_desc *desc;
929
930 dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
931 __func__, imxdmac->channel, src, dest, len);
932
933 if (list_empty(&imxdmac->ld_free) ||
934 imxdma_chan_is_doing_cyclic(imxdmac))
935 return NULL;
936
937 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
938
939 desc->type = IMXDMA_DESC_MEMCPY;
940 desc->src = src;
941 desc->dest = dest;
942 desc->len = len;
943 desc->direction = DMA_MEM_TO_MEM;
944 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
945 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
946 desc->desc.callback = NULL;
947 desc->desc.callback_param = NULL;
948
949 return &desc->desc;
950 }
951
952 static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
953 struct dma_chan *chan, struct dma_interleaved_template *xt,
954 unsigned long flags)
955 {
956 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
957 struct imxdma_engine *imxdma = imxdmac->imxdma;
958 struct imxdma_desc *desc;
959
960 dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
961 " src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
962 imxdmac->channel, xt->src_start, xt->dst_start,
963 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
964 xt->numf, xt->frame_size);
965
966 if (list_empty(&imxdmac->ld_free) ||
967 imxdma_chan_is_doing_cyclic(imxdmac))
968 return NULL;
969
970 if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
971 return NULL;
972
973 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
974
975 desc->type = IMXDMA_DESC_INTERLEAVED;
976 desc->src = xt->src_start;
977 desc->dest = xt->dst_start;
978 desc->x = xt->sgl[0].size;
979 desc->y = xt->numf;
980 desc->w = xt->sgl[0].icg + desc->x;
981 desc->len = desc->x * desc->y;
982 desc->direction = DMA_MEM_TO_MEM;
983 desc->config_port = IMX_DMA_MEMSIZE_32;
984 desc->config_mem = IMX_DMA_MEMSIZE_32;
985 if (xt->src_sgl)
986 desc->config_mem |= IMX_DMA_TYPE_2D;
987 if (xt->dst_sgl)
988 desc->config_port |= IMX_DMA_TYPE_2D;
989 desc->desc.callback = NULL;
990 desc->desc.callback_param = NULL;
991
992 return &desc->desc;
993 }
994
995 static void imxdma_issue_pending(struct dma_chan *chan)
996 {
997 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
998 struct imxdma_engine *imxdma = imxdmac->imxdma;
999 struct imxdma_desc *desc;
1000 unsigned long flags;
1001
1002 spin_lock_irqsave(&imxdma->lock, flags);
1003 if (list_empty(&imxdmac->ld_active) &&
1004 !list_empty(&imxdmac->ld_queue)) {
1005 desc = list_first_entry(&imxdmac->ld_queue,
1006 struct imxdma_desc, node);
1007
1008 if (imxdma_xfer_desc(desc) < 0) {
1009 dev_warn(imxdma->dev,
1010 "%s: channel: %d couldn't issue DMA xfer\n",
1011 __func__, imxdmac->channel);
1012 } else {
1013 list_move_tail(imxdmac->ld_queue.next,
1014 &imxdmac->ld_active);
1015 }
1016 }
1017 spin_unlock_irqrestore(&imxdma->lock, flags);
1018 }
1019
1020 static bool imxdma_filter_fn(struct dma_chan *chan, void *param)
1021 {
1022 struct imxdma_filter_data *fdata = param;
1023 struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan);
1024
1025 if (chan->device->dev != fdata->imxdma->dev)
1026 return false;
1027
1028 imxdma_chan->dma_request = fdata->request;
1029 chan->private = NULL;
1030
1031 return true;
1032 }
1033
1034 static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec,
1035 struct of_dma *ofdma)
1036 {
1037 int count = dma_spec->args_count;
1038 struct imxdma_engine *imxdma = ofdma->of_dma_data;
1039 struct imxdma_filter_data fdata = {
1040 .imxdma = imxdma,
1041 };
1042
1043 if (count != 1)
1044 return NULL;
1045
1046 fdata.request = dma_spec->args[0];
1047
1048 return dma_request_channel(imxdma->dma_device.cap_mask,
1049 imxdma_filter_fn, &fdata);
1050 }
1051
1052 static int __init imxdma_probe(struct platform_device *pdev)
1053 {
1054 struct imxdma_engine *imxdma;
1055 struct resource *res;
1056 const struct of_device_id *of_id;
1057 int ret, i;
1058 int irq, irq_err;
1059
1060 of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev);
1061 if (of_id)
1062 pdev->id_entry = of_id->data;
1063
1064 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
1065 if (!imxdma)
1066 return -ENOMEM;
1067
1068 imxdma->dev = &pdev->dev;
1069 imxdma->devtype = pdev->id_entry->driver_data;
1070
1071 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1072 imxdma->base = devm_ioremap_resource(&pdev->dev, res);
1073 if (IS_ERR(imxdma->base))
1074 return PTR_ERR(imxdma->base);
1075
1076 irq = platform_get_irq(pdev, 0);
1077 if (irq < 0)
1078 return irq;
1079
1080 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
1081 if (IS_ERR(imxdma->dma_ipg))
1082 return PTR_ERR(imxdma->dma_ipg);
1083
1084 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
1085 if (IS_ERR(imxdma->dma_ahb))
1086 return PTR_ERR(imxdma->dma_ahb);
1087
1088 clk_prepare_enable(imxdma->dma_ipg);
1089 clk_prepare_enable(imxdma->dma_ahb);
1090
1091 /* reset DMA module */
1092 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
1093
1094 if (is_imx1_dma(imxdma)) {
1095 ret = devm_request_irq(&pdev->dev, irq,
1096 dma_irq_handler, 0, "DMA", imxdma);
1097 if (ret) {
1098 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
1099 goto err;
1100 }
1101
1102 irq_err = platform_get_irq(pdev, 1);
1103 if (irq_err < 0) {
1104 ret = irq_err;
1105 goto err;
1106 }
1107
1108 ret = devm_request_irq(&pdev->dev, irq_err,
1109 imxdma_err_handler, 0, "DMA", imxdma);
1110 if (ret) {
1111 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
1112 goto err;
1113 }
1114 }
1115
1116 /* enable DMA module */
1117 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
1118
1119 /* clear all interrupts */
1120 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
1121
1122 /* disable interrupts */
1123 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
1124
1125 INIT_LIST_HEAD(&imxdma->dma_device.channels);
1126
1127 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1128 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
1129 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
1130 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1131
1132 /* Initialize 2D global parameters */
1133 for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1134 imxdma->slots_2d[i].count = 0;
1135
1136 spin_lock_init(&imxdma->lock);
1137
1138 /* Initialize channel parameters */
1139 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1140 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1141
1142 if (!is_imx1_dma(imxdma)) {
1143 ret = devm_request_irq(&pdev->dev, irq + i,
1144 dma_irq_handler, 0, "DMA", imxdma);
1145 if (ret) {
1146 dev_warn(imxdma->dev, "Can't register IRQ %d "
1147 "for DMA channel %d\n",
1148 irq + i, i);
1149 goto err;
1150 }
1151 init_timer(&imxdmac->watchdog);
1152 imxdmac->watchdog.function = &imxdma_watchdog;
1153 imxdmac->watchdog.data = (unsigned long)imxdmac;
1154 }
1155
1156 imxdmac->imxdma = imxdma;
1157
1158 INIT_LIST_HEAD(&imxdmac->ld_queue);
1159 INIT_LIST_HEAD(&imxdmac->ld_free);
1160 INIT_LIST_HEAD(&imxdmac->ld_active);
1161
1162 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1163 (unsigned long)imxdmac);
1164 imxdmac->chan.device = &imxdma->dma_device;
1165 dma_cookie_init(&imxdmac->chan);
1166 imxdmac->channel = i;
1167
1168 /* Add the channel to the DMAC list */
1169 list_add_tail(&imxdmac->chan.device_node,
1170 &imxdma->dma_device.channels);
1171 }
1172
1173 imxdma->dma_device.dev = &pdev->dev;
1174
1175 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1176 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1177 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1178 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1179 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1180 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1181 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
1182 imxdma->dma_device.device_control = imxdma_control;
1183 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1184
1185 platform_set_drvdata(pdev, imxdma);
1186
1187 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
1188 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1189 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1190
1191 ret = dma_async_device_register(&imxdma->dma_device);
1192 if (ret) {
1193 dev_err(&pdev->dev, "unable to register\n");
1194 goto err;
1195 }
1196
1197 if (pdev->dev.of_node) {
1198 ret = of_dma_controller_register(pdev->dev.of_node,
1199 imxdma_xlate, imxdma);
1200 if (ret) {
1201 dev_err(&pdev->dev, "unable to register of_dma_controller\n");
1202 goto err_of_dma_controller;
1203 }
1204 }
1205
1206 return 0;
1207
1208 err_of_dma_controller:
1209 dma_async_device_unregister(&imxdma->dma_device);
1210 err:
1211 clk_disable_unprepare(imxdma->dma_ipg);
1212 clk_disable_unprepare(imxdma->dma_ahb);
1213 return ret;
1214 }
1215
1216 static int imxdma_remove(struct platform_device *pdev)
1217 {
1218 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
1219
1220 dma_async_device_unregister(&imxdma->dma_device);
1221
1222 if (pdev->dev.of_node)
1223 of_dma_controller_free(pdev->dev.of_node);
1224
1225 clk_disable_unprepare(imxdma->dma_ipg);
1226 clk_disable_unprepare(imxdma->dma_ahb);
1227
1228 return 0;
1229 }
1230
1231 static struct platform_driver imxdma_driver = {
1232 .driver = {
1233 .name = "imx-dma",
1234 .of_match_table = imx_dma_of_dev_id,
1235 },
1236 .id_table = imx_dma_devtype,
1237 .remove = imxdma_remove,
1238 };
1239
1240 static int __init imxdma_module_init(void)
1241 {
1242 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1243 }
1244 subsys_initcall(imxdma_module_init);
1245
1246 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1247 MODULE_DESCRIPTION("i.MX dma driver");
1248 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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