2 * drivers/dma/imx-sdma.c
4 * This file contains a driver for the Freescale Smart DMA engine
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 * Based on code from Freescale:
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/bitops.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/wait.h>
28 #include <linux/sched.h>
29 #include <linux/semaphore.h>
30 #include <linux/spinlock.h>
31 #include <linux/device.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/firmware.h>
34 #include <linux/slab.h>
35 #include <linux/platform_device.h>
36 #include <linux/dmaengine.h>
38 #include <linux/of_device.h>
39 #include <linux/module.h>
42 #include <mach/sdma.h>
44 #include <mach/hardware.h>
47 #define SDMA_H_C0PTR 0x000
48 #define SDMA_H_INTR 0x004
49 #define SDMA_H_STATSTOP 0x008
50 #define SDMA_H_START 0x00c
51 #define SDMA_H_EVTOVR 0x010
52 #define SDMA_H_DSPOVR 0x014
53 #define SDMA_H_HOSTOVR 0x018
54 #define SDMA_H_EVTPEND 0x01c
55 #define SDMA_H_DSPENBL 0x020
56 #define SDMA_H_RESET 0x024
57 #define SDMA_H_EVTERR 0x028
58 #define SDMA_H_INTRMSK 0x02c
59 #define SDMA_H_PSW 0x030
60 #define SDMA_H_EVTERRDBG 0x034
61 #define SDMA_H_CONFIG 0x038
62 #define SDMA_ONCE_ENB 0x040
63 #define SDMA_ONCE_DATA 0x044
64 #define SDMA_ONCE_INSTR 0x048
65 #define SDMA_ONCE_STAT 0x04c
66 #define SDMA_ONCE_CMD 0x050
67 #define SDMA_EVT_MIRROR 0x054
68 #define SDMA_ILLINSTADDR 0x058
69 #define SDMA_CHN0ADDR 0x05c
70 #define SDMA_ONCE_RTB 0x060
71 #define SDMA_XTRIG_CONF1 0x070
72 #define SDMA_XTRIG_CONF2 0x074
73 #define SDMA_CHNENBL0_IMX35 0x200
74 #define SDMA_CHNENBL0_IMX31 0x080
75 #define SDMA_CHNPRI_0 0x100
78 * Buffer descriptor status values.
89 * Data Node descriptor status values.
91 #define DND_END_OF_FRAME 0x80
92 #define DND_END_OF_XFER 0x40
94 #define DND_UNUSED 0x01
97 * IPCV2 descriptor status values.
99 #define BD_IPCV2_END_OF_FRAME 0x40
101 #define IPCV2_MAX_NODES 50
103 * Error bit set in the CCB status field by the SDMA,
104 * in setbd routine, in case of a transfer error
106 #define DATA_ERROR 0x10000000
109 * Buffer descriptor commands.
114 #define C0_SETCTX 0x07
115 #define C0_GETCTX 0x03
116 #define C0_SETDM 0x01
117 #define C0_SETPM 0x04
118 #define C0_GETDM 0x02
119 #define C0_GETPM 0x08
121 * Change endianness indicator in the BD command field
123 #define CHANGE_ENDIANNESS 0x80
126 * Mode/Count of data node descriptors - IPCv2
128 struct sdma_mode_count
{
129 u32 count
: 16; /* size of the buffer pointed by this BD */
130 u32 status
: 8; /* E,R,I,C,W,D status bits stored here */
131 u32 command
: 8; /* command mostlky used for channel 0 */
137 struct sdma_buffer_descriptor
{
138 struct sdma_mode_count mode
;
139 u32 buffer_addr
; /* address of the buffer described */
140 u32 ext_buffer_addr
; /* extended buffer address */
141 } __attribute__ ((packed
));
144 * struct sdma_channel_control - Channel control Block
146 * @current_bd_ptr current buffer descriptor processed
147 * @base_bd_ptr first element of buffer descriptor array
148 * @unused padding. The SDMA engine expects an array of 128 byte
151 struct sdma_channel_control
{
155 } __attribute__ ((packed
));
158 * struct sdma_state_registers - SDMA context for a channel
160 * @pc: program counter
161 * @t: test bit: status of arithmetic & test instruction
162 * @rpc: return program counter
163 * @sf: source fault while loading data
164 * @spc: loop start program counter
165 * @df: destination fault while storing data
166 * @epc: loop end program counter
169 struct sdma_state_registers
{
181 } __attribute__ ((packed
));
184 * struct sdma_context_data - sdma context specific to a channel
186 * @channel_state: channel state bits
187 * @gReg: general registers
188 * @mda: burst dma destination address register
189 * @msa: burst dma source address register
190 * @ms: burst dma status register
191 * @md: burst dma data register
192 * @pda: peripheral dma destination address register
193 * @psa: peripheral dma source address register
194 * @ps: peripheral dma status register
195 * @pd: peripheral dma data register
196 * @ca: CRC polynomial register
197 * @cs: CRC accumulator register
198 * @dda: dedicated core destination address register
199 * @dsa: dedicated core source address register
200 * @ds: dedicated core status register
201 * @dd: dedicated core data register
203 struct sdma_context_data
{
204 struct sdma_state_registers channel_state
;
228 } __attribute__ ((packed
));
230 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
235 * struct sdma_channel - housekeeping for a SDMA channel
237 * @sdma pointer to the SDMA engine for this channel
238 * @channel the channel number, matches dmaengine chan_id + 1
239 * @direction transfer type. Needed for setting SDMA script
240 * @peripheral_type Peripheral type. Needed for setting SDMA script
241 * @event_id0 aka dma request line
242 * @event_id1 for channels that use 2 events
243 * @word_size peripheral access size
244 * @buf_tail ID of the buffer that was processed
245 * @done channel completion
246 * @num_bd max NUM_BD. number of descriptors currently handling
248 struct sdma_channel
{
249 struct sdma_engine
*sdma
;
250 unsigned int channel
;
251 enum dma_transfer_direction direction
;
252 enum sdma_peripheral_type peripheral_type
;
253 unsigned int event_id0
;
254 unsigned int event_id1
;
255 enum dma_slave_buswidth word_size
;
256 unsigned int buf_tail
;
257 struct completion done
;
259 struct sdma_buffer_descriptor
*bd
;
261 unsigned int pc_from_device
, pc_to_device
;
263 dma_addr_t per_address
;
264 unsigned long event_mask
[2];
265 unsigned long watermark_level
;
266 u32 shp_addr
, per_addr
;
267 struct dma_chan chan
;
269 struct dma_async_tx_descriptor desc
;
270 dma_cookie_t last_completed
;
271 enum dma_status status
;
272 unsigned int chn_count
;
273 unsigned int chn_real_count
;
276 #define IMX_DMA_SG_LOOP BIT(0)
278 #define MAX_DMA_CHANNELS 32
279 #define MXC_SDMA_DEFAULT_PRIORITY 1
280 #define MXC_SDMA_MIN_PRIORITY 1
281 #define MXC_SDMA_MAX_PRIORITY 7
283 #define SDMA_FIRMWARE_MAGIC 0x414d4453
286 * struct sdma_firmware_header - Layout of the firmware image
289 * @version_major increased whenever layout of struct sdma_script_start_addrs
291 * @version_minor firmware minor version (for binary compatible changes)
292 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
293 * @num_script_addrs Number of script addresses in this image
294 * @ram_code_start offset of SDMA ram image in this firmware image
295 * @ram_code_size size of SDMA ram image
296 * @script_addrs Stores the start address of the SDMA scripts
297 * (in SDMA memory space)
299 struct sdma_firmware_header
{
303 u32 script_addrs_start
;
304 u32 num_script_addrs
;
310 IMX31_SDMA
, /* runs on i.mx31 */
311 IMX35_SDMA
, /* runs on i.mx35 and later */
316 struct device_dma_parameters dma_parms
;
317 struct sdma_channel channel
[MAX_DMA_CHANNELS
];
318 struct sdma_channel_control
*channel_control
;
320 enum sdma_devtype devtype
;
321 unsigned int num_events
;
322 struct sdma_context_data
*context
;
323 dma_addr_t context_phys
;
324 struct dma_device dma_device
;
326 struct mutex channel_0_lock
;
327 struct sdma_script_start_addrs
*script_addrs
;
330 static struct platform_device_id sdma_devtypes
[] = {
332 .name
= "imx31-sdma",
333 .driver_data
= IMX31_SDMA
,
335 .name
= "imx35-sdma",
336 .driver_data
= IMX35_SDMA
,
341 MODULE_DEVICE_TABLE(platform
, sdma_devtypes
);
343 static const struct of_device_id sdma_dt_ids
[] = {
344 { .compatible
= "fsl,imx31-sdma", .data
= &sdma_devtypes
[IMX31_SDMA
], },
345 { .compatible
= "fsl,imx35-sdma", .data
= &sdma_devtypes
[IMX35_SDMA
], },
348 MODULE_DEVICE_TABLE(of
, sdma_dt_ids
);
350 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
351 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
352 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
353 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
355 static inline u32
chnenbl_ofs(struct sdma_engine
*sdma
, unsigned int event
)
357 u32 chnenbl0
= (sdma
->devtype
== IMX31_SDMA
? SDMA_CHNENBL0_IMX31
:
358 SDMA_CHNENBL0_IMX35
);
359 return chnenbl0
+ event
* 4;
362 static int sdma_config_ownership(struct sdma_channel
*sdmac
,
363 bool event_override
, bool mcu_override
, bool dsp_override
)
365 struct sdma_engine
*sdma
= sdmac
->sdma
;
366 int channel
= sdmac
->channel
;
367 unsigned long evt
, mcu
, dsp
;
369 if (event_override
&& mcu_override
&& dsp_override
)
372 evt
= readl_relaxed(sdma
->regs
+ SDMA_H_EVTOVR
);
373 mcu
= readl_relaxed(sdma
->regs
+ SDMA_H_HOSTOVR
);
374 dsp
= readl_relaxed(sdma
->regs
+ SDMA_H_DSPOVR
);
377 __clear_bit(channel
, &dsp
);
379 __set_bit(channel
, &dsp
);
382 __clear_bit(channel
, &evt
);
384 __set_bit(channel
, &evt
);
387 __clear_bit(channel
, &mcu
);
389 __set_bit(channel
, &mcu
);
391 writel_relaxed(evt
, sdma
->regs
+ SDMA_H_EVTOVR
);
392 writel_relaxed(mcu
, sdma
->regs
+ SDMA_H_HOSTOVR
);
393 writel_relaxed(dsp
, sdma
->regs
+ SDMA_H_DSPOVR
);
398 static void sdma_enable_channel(struct sdma_engine
*sdma
, int channel
)
400 writel(BIT(channel
), sdma
->regs
+ SDMA_H_START
);
404 * sdma_run_channel - run a channel and wait till it's done
406 static int sdma_run_channel(struct sdma_channel
*sdmac
)
408 struct sdma_engine
*sdma
= sdmac
->sdma
;
409 int channel
= sdmac
->channel
;
412 init_completion(&sdmac
->done
);
414 sdma_enable_channel(sdma
, channel
);
416 ret
= wait_for_completion_timeout(&sdmac
->done
, HZ
);
418 return ret
? 0 : -ETIMEDOUT
;
421 static int sdma_load_script(struct sdma_engine
*sdma
, void *buf
, int size
,
424 struct sdma_buffer_descriptor
*bd0
= sdma
->channel
[0].bd
;
429 mutex_lock(&sdma
->channel_0_lock
);
431 buf_virt
= dma_alloc_coherent(NULL
,
433 &buf_phys
, GFP_KERNEL
);
439 bd0
->mode
.command
= C0_SETPM
;
440 bd0
->mode
.status
= BD_DONE
| BD_INTR
| BD_WRAP
| BD_EXTD
;
441 bd0
->mode
.count
= size
/ 2;
442 bd0
->buffer_addr
= buf_phys
;
443 bd0
->ext_buffer_addr
= address
;
445 memcpy(buf_virt
, buf
, size
);
447 ret
= sdma_run_channel(&sdma
->channel
[0]);
449 dma_free_coherent(NULL
, size
, buf_virt
, buf_phys
);
452 mutex_unlock(&sdma
->channel_0_lock
);
457 static void sdma_event_enable(struct sdma_channel
*sdmac
, unsigned int event
)
459 struct sdma_engine
*sdma
= sdmac
->sdma
;
460 int channel
= sdmac
->channel
;
462 u32 chnenbl
= chnenbl_ofs(sdma
, event
);
464 val
= readl_relaxed(sdma
->regs
+ chnenbl
);
465 __set_bit(channel
, &val
);
466 writel_relaxed(val
, sdma
->regs
+ chnenbl
);
469 static void sdma_event_disable(struct sdma_channel
*sdmac
, unsigned int event
)
471 struct sdma_engine
*sdma
= sdmac
->sdma
;
472 int channel
= sdmac
->channel
;
473 u32 chnenbl
= chnenbl_ofs(sdma
, event
);
476 val
= readl_relaxed(sdma
->regs
+ chnenbl
);
477 __clear_bit(channel
, &val
);
478 writel_relaxed(val
, sdma
->regs
+ chnenbl
);
481 static void sdma_handle_channel_loop(struct sdma_channel
*sdmac
)
483 struct sdma_buffer_descriptor
*bd
;
486 * loop mode. Iterate over descriptors, re-setup them and
487 * call callback function.
490 bd
= &sdmac
->bd
[sdmac
->buf_tail
];
492 if (bd
->mode
.status
& BD_DONE
)
495 if (bd
->mode
.status
& BD_RROR
)
496 sdmac
->status
= DMA_ERROR
;
498 sdmac
->status
= DMA_IN_PROGRESS
;
500 bd
->mode
.status
|= BD_DONE
;
502 sdmac
->buf_tail
%= sdmac
->num_bd
;
504 if (sdmac
->desc
.callback
)
505 sdmac
->desc
.callback(sdmac
->desc
.callback_param
);
509 static void mxc_sdma_handle_channel_normal(struct sdma_channel
*sdmac
)
511 struct sdma_buffer_descriptor
*bd
;
514 sdmac
->chn_real_count
= 0;
516 * non loop mode. Iterate over all descriptors, collect
517 * errors and call callback function
519 for (i
= 0; i
< sdmac
->num_bd
; i
++) {
522 if (bd
->mode
.status
& (BD_DONE
| BD_RROR
))
524 sdmac
->chn_real_count
+= bd
->mode
.count
;
528 sdmac
->status
= DMA_ERROR
;
530 sdmac
->status
= DMA_SUCCESS
;
532 sdmac
->last_completed
= sdmac
->desc
.cookie
;
533 if (sdmac
->desc
.callback
)
534 sdmac
->desc
.callback(sdmac
->desc
.callback_param
);
537 static void mxc_sdma_handle_channel(struct sdma_channel
*sdmac
)
539 complete(&sdmac
->done
);
541 /* not interested in channel 0 interrupts */
542 if (sdmac
->channel
== 0)
545 if (sdmac
->flags
& IMX_DMA_SG_LOOP
)
546 sdma_handle_channel_loop(sdmac
);
548 mxc_sdma_handle_channel_normal(sdmac
);
551 static irqreturn_t
sdma_int_handler(int irq
, void *dev_id
)
553 struct sdma_engine
*sdma
= dev_id
;
556 stat
= readl_relaxed(sdma
->regs
+ SDMA_H_INTR
);
557 writel_relaxed(stat
, sdma
->regs
+ SDMA_H_INTR
);
560 int channel
= fls(stat
) - 1;
561 struct sdma_channel
*sdmac
= &sdma
->channel
[channel
];
563 mxc_sdma_handle_channel(sdmac
);
565 __clear_bit(channel
, &stat
);
572 * sets the pc of SDMA script according to the peripheral type
574 static void sdma_get_pc(struct sdma_channel
*sdmac
,
575 enum sdma_peripheral_type peripheral_type
)
577 struct sdma_engine
*sdma
= sdmac
->sdma
;
578 int per_2_emi
= 0, emi_2_per
= 0;
580 * These are needed once we start to support transfers between
581 * two peripherals or memory-to-memory transfers
583 int per_2_per
= 0, emi_2_emi
= 0;
585 sdmac
->pc_from_device
= 0;
586 sdmac
->pc_to_device
= 0;
588 switch (peripheral_type
) {
589 case IMX_DMATYPE_MEMORY
:
590 emi_2_emi
= sdma
->script_addrs
->ap_2_ap_addr
;
592 case IMX_DMATYPE_DSP
:
593 emi_2_per
= sdma
->script_addrs
->bp_2_ap_addr
;
594 per_2_emi
= sdma
->script_addrs
->ap_2_bp_addr
;
596 case IMX_DMATYPE_FIRI
:
597 per_2_emi
= sdma
->script_addrs
->firi_2_mcu_addr
;
598 emi_2_per
= sdma
->script_addrs
->mcu_2_firi_addr
;
600 case IMX_DMATYPE_UART
:
601 per_2_emi
= sdma
->script_addrs
->uart_2_mcu_addr
;
602 emi_2_per
= sdma
->script_addrs
->mcu_2_app_addr
;
604 case IMX_DMATYPE_UART_SP
:
605 per_2_emi
= sdma
->script_addrs
->uartsh_2_mcu_addr
;
606 emi_2_per
= sdma
->script_addrs
->mcu_2_shp_addr
;
608 case IMX_DMATYPE_ATA
:
609 per_2_emi
= sdma
->script_addrs
->ata_2_mcu_addr
;
610 emi_2_per
= sdma
->script_addrs
->mcu_2_ata_addr
;
612 case IMX_DMATYPE_CSPI
:
613 case IMX_DMATYPE_EXT
:
614 case IMX_DMATYPE_SSI
:
615 per_2_emi
= sdma
->script_addrs
->app_2_mcu_addr
;
616 emi_2_per
= sdma
->script_addrs
->mcu_2_app_addr
;
618 case IMX_DMATYPE_SSI_SP
:
619 case IMX_DMATYPE_MMC
:
620 case IMX_DMATYPE_SDHC
:
621 case IMX_DMATYPE_CSPI_SP
:
622 case IMX_DMATYPE_ESAI
:
623 case IMX_DMATYPE_MSHC_SP
:
624 per_2_emi
= sdma
->script_addrs
->shp_2_mcu_addr
;
625 emi_2_per
= sdma
->script_addrs
->mcu_2_shp_addr
;
627 case IMX_DMATYPE_ASRC
:
628 per_2_emi
= sdma
->script_addrs
->asrc_2_mcu_addr
;
629 emi_2_per
= sdma
->script_addrs
->asrc_2_mcu_addr
;
630 per_2_per
= sdma
->script_addrs
->per_2_per_addr
;
632 case IMX_DMATYPE_MSHC
:
633 per_2_emi
= sdma
->script_addrs
->mshc_2_mcu_addr
;
634 emi_2_per
= sdma
->script_addrs
->mcu_2_mshc_addr
;
636 case IMX_DMATYPE_CCM
:
637 per_2_emi
= sdma
->script_addrs
->dptc_dvfs_addr
;
639 case IMX_DMATYPE_SPDIF
:
640 per_2_emi
= sdma
->script_addrs
->spdif_2_mcu_addr
;
641 emi_2_per
= sdma
->script_addrs
->mcu_2_spdif_addr
;
643 case IMX_DMATYPE_IPU_MEMORY
:
644 emi_2_per
= sdma
->script_addrs
->ext_mem_2_ipu_addr
;
650 sdmac
->pc_from_device
= per_2_emi
;
651 sdmac
->pc_to_device
= emi_2_per
;
654 static int sdma_load_context(struct sdma_channel
*sdmac
)
656 struct sdma_engine
*sdma
= sdmac
->sdma
;
657 int channel
= sdmac
->channel
;
659 struct sdma_context_data
*context
= sdma
->context
;
660 struct sdma_buffer_descriptor
*bd0
= sdma
->channel
[0].bd
;
663 if (sdmac
->direction
== DMA_DEV_TO_MEM
) {
664 load_address
= sdmac
->pc_from_device
;
666 load_address
= sdmac
->pc_to_device
;
669 if (load_address
< 0)
672 dev_dbg(sdma
->dev
, "load_address = %d\n", load_address
);
673 dev_dbg(sdma
->dev
, "wml = 0x%08x\n", (u32
)sdmac
->watermark_level
);
674 dev_dbg(sdma
->dev
, "shp_addr = 0x%08x\n", sdmac
->shp_addr
);
675 dev_dbg(sdma
->dev
, "per_addr = 0x%08x\n", sdmac
->per_addr
);
676 dev_dbg(sdma
->dev
, "event_mask0 = 0x%08x\n", (u32
)sdmac
->event_mask
[0]);
677 dev_dbg(sdma
->dev
, "event_mask1 = 0x%08x\n", (u32
)sdmac
->event_mask
[1]);
679 mutex_lock(&sdma
->channel_0_lock
);
681 memset(context
, 0, sizeof(*context
));
682 context
->channel_state
.pc
= load_address
;
684 /* Send by context the event mask,base address for peripheral
685 * and watermark level
687 context
->gReg
[0] = sdmac
->event_mask
[1];
688 context
->gReg
[1] = sdmac
->event_mask
[0];
689 context
->gReg
[2] = sdmac
->per_addr
;
690 context
->gReg
[6] = sdmac
->shp_addr
;
691 context
->gReg
[7] = sdmac
->watermark_level
;
693 bd0
->mode
.command
= C0_SETDM
;
694 bd0
->mode
.status
= BD_DONE
| BD_INTR
| BD_WRAP
| BD_EXTD
;
695 bd0
->mode
.count
= sizeof(*context
) / 4;
696 bd0
->buffer_addr
= sdma
->context_phys
;
697 bd0
->ext_buffer_addr
= 2048 + (sizeof(*context
) / 4) * channel
;
699 ret
= sdma_run_channel(&sdma
->channel
[0]);
701 mutex_unlock(&sdma
->channel_0_lock
);
706 static void sdma_disable_channel(struct sdma_channel
*sdmac
)
708 struct sdma_engine
*sdma
= sdmac
->sdma
;
709 int channel
= sdmac
->channel
;
711 writel_relaxed(BIT(channel
), sdma
->regs
+ SDMA_H_STATSTOP
);
712 sdmac
->status
= DMA_ERROR
;
715 static int sdma_config_channel(struct sdma_channel
*sdmac
)
719 sdma_disable_channel(sdmac
);
721 sdmac
->event_mask
[0] = 0;
722 sdmac
->event_mask
[1] = 0;
726 if (sdmac
->event_id0
) {
727 if (sdmac
->event_id0
>= sdmac
->sdma
->num_events
)
729 sdma_event_enable(sdmac
, sdmac
->event_id0
);
732 switch (sdmac
->peripheral_type
) {
733 case IMX_DMATYPE_DSP
:
734 sdma_config_ownership(sdmac
, false, true, true);
736 case IMX_DMATYPE_MEMORY
:
737 sdma_config_ownership(sdmac
, false, true, false);
740 sdma_config_ownership(sdmac
, true, true, false);
744 sdma_get_pc(sdmac
, sdmac
->peripheral_type
);
746 if ((sdmac
->peripheral_type
!= IMX_DMATYPE_MEMORY
) &&
747 (sdmac
->peripheral_type
!= IMX_DMATYPE_DSP
)) {
748 /* Handle multiple event channels differently */
749 if (sdmac
->event_id1
) {
750 sdmac
->event_mask
[1] = BIT(sdmac
->event_id1
% 32);
751 if (sdmac
->event_id1
> 31)
752 __set_bit(31, &sdmac
->watermark_level
);
753 sdmac
->event_mask
[0] = BIT(sdmac
->event_id0
% 32);
754 if (sdmac
->event_id0
> 31)
755 __set_bit(30, &sdmac
->watermark_level
);
757 __set_bit(sdmac
->event_id0
, sdmac
->event_mask
);
759 /* Watermark Level */
760 sdmac
->watermark_level
|= sdmac
->watermark_level
;
762 sdmac
->shp_addr
= sdmac
->per_address
;
764 sdmac
->watermark_level
= 0; /* FIXME: M3_BASE_ADDRESS */
767 ret
= sdma_load_context(sdmac
);
772 static int sdma_set_channel_priority(struct sdma_channel
*sdmac
,
773 unsigned int priority
)
775 struct sdma_engine
*sdma
= sdmac
->sdma
;
776 int channel
= sdmac
->channel
;
778 if (priority
< MXC_SDMA_MIN_PRIORITY
779 || priority
> MXC_SDMA_MAX_PRIORITY
) {
783 writel_relaxed(priority
, sdma
->regs
+ SDMA_CHNPRI_0
+ 4 * channel
);
788 static int sdma_request_channel(struct sdma_channel
*sdmac
)
790 struct sdma_engine
*sdma
= sdmac
->sdma
;
791 int channel
= sdmac
->channel
;
794 sdmac
->bd
= dma_alloc_coherent(NULL
, PAGE_SIZE
, &sdmac
->bd_phys
, GFP_KERNEL
);
800 memset(sdmac
->bd
, 0, PAGE_SIZE
);
802 sdma
->channel_control
[channel
].base_bd_ptr
= sdmac
->bd_phys
;
803 sdma
->channel_control
[channel
].current_bd_ptr
= sdmac
->bd_phys
;
805 sdma_set_channel_priority(sdmac
, MXC_SDMA_DEFAULT_PRIORITY
);
807 init_completion(&sdmac
->done
);
817 static dma_cookie_t
sdma_assign_cookie(struct sdma_channel
*sdmac
)
819 dma_cookie_t cookie
= sdmac
->chan
.cookie
;
824 sdmac
->chan
.cookie
= cookie
;
825 sdmac
->desc
.cookie
= cookie
;
830 static struct sdma_channel
*to_sdma_chan(struct dma_chan
*chan
)
832 return container_of(chan
, struct sdma_channel
, chan
);
835 static dma_cookie_t
sdma_tx_submit(struct dma_async_tx_descriptor
*tx
)
838 struct sdma_channel
*sdmac
= to_sdma_chan(tx
->chan
);
841 spin_lock_irqsave(&sdmac
->lock
, flags
);
843 cookie
= sdma_assign_cookie(sdmac
);
845 spin_unlock_irqrestore(&sdmac
->lock
, flags
);
850 static int sdma_alloc_chan_resources(struct dma_chan
*chan
)
852 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
853 struct imx_dma_data
*data
= chan
->private;
859 switch (data
->priority
) {
863 case DMA_PRIO_MEDIUM
:
872 sdmac
->peripheral_type
= data
->peripheral_type
;
873 sdmac
->event_id0
= data
->dma_request
;
875 clk_enable(sdmac
->sdma
->clk
);
877 ret
= sdma_request_channel(sdmac
);
881 ret
= sdma_set_channel_priority(sdmac
, prio
);
885 dma_async_tx_descriptor_init(&sdmac
->desc
, chan
);
886 sdmac
->desc
.tx_submit
= sdma_tx_submit
;
887 /* txd.flags will be overwritten in prep funcs */
888 sdmac
->desc
.flags
= DMA_CTRL_ACK
;
893 static void sdma_free_chan_resources(struct dma_chan
*chan
)
895 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
896 struct sdma_engine
*sdma
= sdmac
->sdma
;
898 sdma_disable_channel(sdmac
);
900 if (sdmac
->event_id0
)
901 sdma_event_disable(sdmac
, sdmac
->event_id0
);
902 if (sdmac
->event_id1
)
903 sdma_event_disable(sdmac
, sdmac
->event_id1
);
905 sdmac
->event_id0
= 0;
906 sdmac
->event_id1
= 0;
908 sdma_set_channel_priority(sdmac
, 0);
910 dma_free_coherent(NULL
, PAGE_SIZE
, sdmac
->bd
, sdmac
->bd_phys
);
912 clk_disable(sdma
->clk
);
915 static struct dma_async_tx_descriptor
*sdma_prep_slave_sg(
916 struct dma_chan
*chan
, struct scatterlist
*sgl
,
917 unsigned int sg_len
, enum dma_transfer_direction direction
,
920 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
921 struct sdma_engine
*sdma
= sdmac
->sdma
;
923 int channel
= sdmac
->channel
;
924 struct scatterlist
*sg
;
926 if (sdmac
->status
== DMA_IN_PROGRESS
)
928 sdmac
->status
= DMA_IN_PROGRESS
;
932 dev_dbg(sdma
->dev
, "setting up %d entries for channel %d.\n",
935 sdmac
->direction
= direction
;
936 ret
= sdma_load_context(sdmac
);
940 if (sg_len
> NUM_BD
) {
941 dev_err(sdma
->dev
, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
942 channel
, sg_len
, NUM_BD
);
947 sdmac
->chn_count
= 0;
948 for_each_sg(sgl
, sg
, sg_len
, i
) {
949 struct sdma_buffer_descriptor
*bd
= &sdmac
->bd
[i
];
952 bd
->buffer_addr
= sg
->dma_address
;
956 if (count
> 0xffff) {
957 dev_err(sdma
->dev
, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
958 channel
, count
, 0xffff);
963 bd
->mode
.count
= count
;
964 sdmac
->chn_count
+= count
;
966 if (sdmac
->word_size
> DMA_SLAVE_BUSWIDTH_4_BYTES
) {
971 switch (sdmac
->word_size
) {
972 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
973 bd
->mode
.command
= 0;
974 if (count
& 3 || sg
->dma_address
& 3)
977 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
978 bd
->mode
.command
= 2;
979 if (count
& 1 || sg
->dma_address
& 1)
982 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
983 bd
->mode
.command
= 1;
989 param
= BD_DONE
| BD_EXTD
| BD_CONT
;
991 if (i
+ 1 == sg_len
) {
997 dev_dbg(sdma
->dev
, "entry %d: count: %d dma: 0x%08x %s%s\n",
998 i
, count
, sg
->dma_address
,
999 param
& BD_WRAP
? "wrap" : "",
1000 param
& BD_INTR
? " intr" : "");
1002 bd
->mode
.status
= param
;
1005 sdmac
->num_bd
= sg_len
;
1006 sdma
->channel_control
[channel
].current_bd_ptr
= sdmac
->bd_phys
;
1008 return &sdmac
->desc
;
1010 sdmac
->status
= DMA_ERROR
;
1014 static struct dma_async_tx_descriptor
*sdma_prep_dma_cyclic(
1015 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t buf_len
,
1016 size_t period_len
, enum dma_transfer_direction direction
)
1018 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
1019 struct sdma_engine
*sdma
= sdmac
->sdma
;
1020 int num_periods
= buf_len
/ period_len
;
1021 int channel
= sdmac
->channel
;
1022 int ret
, i
= 0, buf
= 0;
1024 dev_dbg(sdma
->dev
, "%s channel: %d\n", __func__
, channel
);
1026 if (sdmac
->status
== DMA_IN_PROGRESS
)
1029 sdmac
->status
= DMA_IN_PROGRESS
;
1031 sdmac
->flags
|= IMX_DMA_SG_LOOP
;
1032 sdmac
->direction
= direction
;
1033 ret
= sdma_load_context(sdmac
);
1037 if (num_periods
> NUM_BD
) {
1038 dev_err(sdma
->dev
, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1039 channel
, num_periods
, NUM_BD
);
1043 if (period_len
> 0xffff) {
1044 dev_err(sdma
->dev
, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1045 channel
, period_len
, 0xffff);
1049 while (buf
< buf_len
) {
1050 struct sdma_buffer_descriptor
*bd
= &sdmac
->bd
[i
];
1053 bd
->buffer_addr
= dma_addr
;
1055 bd
->mode
.count
= period_len
;
1057 if (sdmac
->word_size
> DMA_SLAVE_BUSWIDTH_4_BYTES
)
1059 if (sdmac
->word_size
== DMA_SLAVE_BUSWIDTH_4_BYTES
)
1060 bd
->mode
.command
= 0;
1062 bd
->mode
.command
= sdmac
->word_size
;
1064 param
= BD_DONE
| BD_EXTD
| BD_CONT
| BD_INTR
;
1065 if (i
+ 1 == num_periods
)
1068 dev_dbg(sdma
->dev
, "entry %d: count: %d dma: 0x%08x %s%s\n",
1069 i
, period_len
, dma_addr
,
1070 param
& BD_WRAP
? "wrap" : "",
1071 param
& BD_INTR
? " intr" : "");
1073 bd
->mode
.status
= param
;
1075 dma_addr
+= period_len
;
1081 sdmac
->num_bd
= num_periods
;
1082 sdma
->channel_control
[channel
].current_bd_ptr
= sdmac
->bd_phys
;
1084 return &sdmac
->desc
;
1086 sdmac
->status
= DMA_ERROR
;
1090 static int sdma_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1093 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
1094 struct dma_slave_config
*dmaengine_cfg
= (void *)arg
;
1097 case DMA_TERMINATE_ALL
:
1098 sdma_disable_channel(sdmac
);
1100 case DMA_SLAVE_CONFIG
:
1101 if (dmaengine_cfg
->direction
== DMA_DEV_TO_MEM
) {
1102 sdmac
->per_address
= dmaengine_cfg
->src_addr
;
1103 sdmac
->watermark_level
= dmaengine_cfg
->src_maxburst
*
1104 dmaengine_cfg
->src_addr_width
;
1105 sdmac
->word_size
= dmaengine_cfg
->src_addr_width
;
1107 sdmac
->per_address
= dmaengine_cfg
->dst_addr
;
1108 sdmac
->watermark_level
= dmaengine_cfg
->dst_maxburst
*
1109 dmaengine_cfg
->dst_addr_width
;
1110 sdmac
->word_size
= dmaengine_cfg
->dst_addr_width
;
1112 sdmac
->direction
= dmaengine_cfg
->direction
;
1113 return sdma_config_channel(sdmac
);
1121 static enum dma_status
sdma_tx_status(struct dma_chan
*chan
,
1122 dma_cookie_t cookie
,
1123 struct dma_tx_state
*txstate
)
1125 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
1126 dma_cookie_t last_used
;
1128 last_used
= chan
->cookie
;
1130 dma_set_tx_state(txstate
, sdmac
->last_completed
, last_used
,
1131 sdmac
->chn_count
- sdmac
->chn_real_count
);
1133 return sdmac
->status
;
1136 static void sdma_issue_pending(struct dma_chan
*chan
)
1138 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
1139 struct sdma_engine
*sdma
= sdmac
->sdma
;
1141 if (sdmac
->status
== DMA_IN_PROGRESS
)
1142 sdma_enable_channel(sdma
, sdmac
->channel
);
1145 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1147 static void sdma_add_scripts(struct sdma_engine
*sdma
,
1148 const struct sdma_script_start_addrs
*addr
)
1150 s32
*addr_arr
= (u32
*)addr
;
1151 s32
*saddr_arr
= (u32
*)sdma
->script_addrs
;
1154 for (i
= 0; i
< SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1
; i
++)
1155 if (addr_arr
[i
] > 0)
1156 saddr_arr
[i
] = addr_arr
[i
];
1159 static void sdma_load_firmware(const struct firmware
*fw
, void *context
)
1161 struct sdma_engine
*sdma
= context
;
1162 const struct sdma_firmware_header
*header
;
1163 const struct sdma_script_start_addrs
*addr
;
1164 unsigned short *ram_code
;
1167 dev_err(sdma
->dev
, "firmware not found\n");
1171 if (fw
->size
< sizeof(*header
))
1174 header
= (struct sdma_firmware_header
*)fw
->data
;
1176 if (header
->magic
!= SDMA_FIRMWARE_MAGIC
)
1178 if (header
->ram_code_start
+ header
->ram_code_size
> fw
->size
)
1181 addr
= (void *)header
+ header
->script_addrs_start
;
1182 ram_code
= (void *)header
+ header
->ram_code_start
;
1184 clk_enable(sdma
->clk
);
1185 /* download the RAM image for SDMA */
1186 sdma_load_script(sdma
, ram_code
,
1187 header
->ram_code_size
,
1188 addr
->ram_code_start_addr
);
1189 clk_disable(sdma
->clk
);
1191 sdma_add_scripts(sdma
, addr
);
1193 dev_info(sdma
->dev
, "loaded firmware %d.%d\n",
1194 header
->version_major
,
1195 header
->version_minor
);
1198 release_firmware(fw
);
1201 static int __init
sdma_get_firmware(struct sdma_engine
*sdma
,
1202 const char *fw_name
)
1206 ret
= request_firmware_nowait(THIS_MODULE
,
1207 FW_ACTION_HOTPLUG
, fw_name
, sdma
->dev
,
1208 GFP_KERNEL
, sdma
, sdma_load_firmware
);
1213 static int __init
sdma_init(struct sdma_engine
*sdma
)
1216 dma_addr_t ccb_phys
;
1218 switch (sdma
->devtype
) {
1220 sdma
->num_events
= 32;
1223 sdma
->num_events
= 48;
1226 dev_err(sdma
->dev
, "Unknown sdma type %d. aborting\n",
1231 clk_enable(sdma
->clk
);
1233 /* Be sure SDMA has not started yet */
1234 writel_relaxed(0, sdma
->regs
+ SDMA_H_C0PTR
);
1236 sdma
->channel_control
= dma_alloc_coherent(NULL
,
1237 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
) +
1238 sizeof(struct sdma_context_data
),
1239 &ccb_phys
, GFP_KERNEL
);
1241 if (!sdma
->channel_control
) {
1246 sdma
->context
= (void *)sdma
->channel_control
+
1247 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
);
1248 sdma
->context_phys
= ccb_phys
+
1249 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
);
1251 /* Zero-out the CCB structures array just allocated */
1252 memset(sdma
->channel_control
, 0,
1253 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
));
1255 /* disable all channels */
1256 for (i
= 0; i
< sdma
->num_events
; i
++)
1257 writel_relaxed(0, sdma
->regs
+ chnenbl_ofs(sdma
, i
));
1259 /* All channels have priority 0 */
1260 for (i
= 0; i
< MAX_DMA_CHANNELS
; i
++)
1261 writel_relaxed(0, sdma
->regs
+ SDMA_CHNPRI_0
+ i
* 4);
1263 ret
= sdma_request_channel(&sdma
->channel
[0]);
1267 sdma_config_ownership(&sdma
->channel
[0], false, true, false);
1269 /* Set Command Channel (Channel Zero) */
1270 writel_relaxed(0x4050, sdma
->regs
+ SDMA_CHN0ADDR
);
1272 /* Set bits of CONFIG register but with static context switching */
1273 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1274 writel_relaxed(0, sdma
->regs
+ SDMA_H_CONFIG
);
1276 writel_relaxed(ccb_phys
, sdma
->regs
+ SDMA_H_C0PTR
);
1278 /* Set bits of CONFIG register with given context switching mode */
1279 writel_relaxed(SDMA_H_CONFIG_CSM
, sdma
->regs
+ SDMA_H_CONFIG
);
1281 /* Initializes channel's priorities */
1282 sdma_set_channel_priority(&sdma
->channel
[0], 7);
1284 clk_disable(sdma
->clk
);
1289 clk_disable(sdma
->clk
);
1290 dev_err(sdma
->dev
, "initialisation failed with %d\n", ret
);
1294 static int __init
sdma_probe(struct platform_device
*pdev
)
1296 const struct of_device_id
*of_id
=
1297 of_match_device(sdma_dt_ids
, &pdev
->dev
);
1298 struct device_node
*np
= pdev
->dev
.of_node
;
1299 const char *fw_name
;
1302 struct resource
*iores
;
1303 struct sdma_platform_data
*pdata
= pdev
->dev
.platform_data
;
1305 struct sdma_engine
*sdma
;
1308 sdma
= kzalloc(sizeof(*sdma
), GFP_KERNEL
);
1312 mutex_init(&sdma
->channel_0_lock
);
1314 sdma
->dev
= &pdev
->dev
;
1316 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1317 irq
= platform_get_irq(pdev
, 0);
1318 if (!iores
|| irq
< 0) {
1323 if (!request_mem_region(iores
->start
, resource_size(iores
), pdev
->name
)) {
1325 goto err_request_region
;
1328 sdma
->clk
= clk_get(&pdev
->dev
, NULL
);
1329 if (IS_ERR(sdma
->clk
)) {
1330 ret
= PTR_ERR(sdma
->clk
);
1334 sdma
->regs
= ioremap(iores
->start
, resource_size(iores
));
1340 ret
= request_irq(irq
, sdma_int_handler
, 0, "sdma", sdma
);
1342 goto err_request_irq
;
1344 sdma
->script_addrs
= kzalloc(sizeof(*sdma
->script_addrs
), GFP_KERNEL
);
1345 if (!sdma
->script_addrs
) {
1350 /* initially no scripts available */
1351 saddr_arr
= (s32
*)sdma
->script_addrs
;
1352 for (i
= 0; i
< SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1
; i
++)
1353 saddr_arr
[i
] = -EINVAL
;
1356 pdev
->id_entry
= of_id
->data
;
1357 sdma
->devtype
= pdev
->id_entry
->driver_data
;
1359 dma_cap_set(DMA_SLAVE
, sdma
->dma_device
.cap_mask
);
1360 dma_cap_set(DMA_CYCLIC
, sdma
->dma_device
.cap_mask
);
1362 INIT_LIST_HEAD(&sdma
->dma_device
.channels
);
1363 /* Initialize channel parameters */
1364 for (i
= 0; i
< MAX_DMA_CHANNELS
; i
++) {
1365 struct sdma_channel
*sdmac
= &sdma
->channel
[i
];
1368 spin_lock_init(&sdmac
->lock
);
1370 sdmac
->chan
.device
= &sdma
->dma_device
;
1374 * Add the channel to the DMAC list. Do not add channel 0 though
1375 * because we need it internally in the SDMA driver. This also means
1376 * that channel 0 in dmaengine counting matches sdma channel 1.
1379 list_add_tail(&sdmac
->chan
.device_node
,
1380 &sdma
->dma_device
.channels
);
1383 ret
= sdma_init(sdma
);
1387 if (pdata
&& pdata
->script_addrs
)
1388 sdma_add_scripts(sdma
, pdata
->script_addrs
);
1391 sdma_get_firmware(sdma
, pdata
->fw_name
);
1394 * Because that device tree does not encode ROM script address,
1395 * the RAM script in firmware is mandatory for device tree
1396 * probe, otherwise it fails.
1398 ret
= of_property_read_string(np
, "fsl,sdma-ram-script-name",
1401 dev_err(&pdev
->dev
, "failed to get firmware name\n");
1405 ret
= sdma_get_firmware(sdma
, fw_name
);
1407 dev_err(&pdev
->dev
, "failed to get firmware\n");
1412 sdma
->dma_device
.dev
= &pdev
->dev
;
1414 sdma
->dma_device
.device_alloc_chan_resources
= sdma_alloc_chan_resources
;
1415 sdma
->dma_device
.device_free_chan_resources
= sdma_free_chan_resources
;
1416 sdma
->dma_device
.device_tx_status
= sdma_tx_status
;
1417 sdma
->dma_device
.device_prep_slave_sg
= sdma_prep_slave_sg
;
1418 sdma
->dma_device
.device_prep_dma_cyclic
= sdma_prep_dma_cyclic
;
1419 sdma
->dma_device
.device_control
= sdma_control
;
1420 sdma
->dma_device
.device_issue_pending
= sdma_issue_pending
;
1421 sdma
->dma_device
.dev
->dma_parms
= &sdma
->dma_parms
;
1422 dma_set_max_seg_size(sdma
->dma_device
.dev
, 65535);
1424 ret
= dma_async_device_register(&sdma
->dma_device
);
1426 dev_err(&pdev
->dev
, "unable to register\n");
1430 dev_info(sdma
->dev
, "initialized\n");
1435 kfree(sdma
->script_addrs
);
1437 free_irq(irq
, sdma
);
1439 iounmap(sdma
->regs
);
1443 release_mem_region(iores
->start
, resource_size(iores
));
1450 static int __exit
sdma_remove(struct platform_device
*pdev
)
1455 static struct platform_driver sdma_driver
= {
1458 .of_match_table
= sdma_dt_ids
,
1460 .id_table
= sdma_devtypes
,
1461 .remove
= __exit_p(sdma_remove
),
1464 static int __init
sdma_module_init(void)
1466 return platform_driver_probe(&sdma_driver
, sdma_probe
);
1468 module_init(sdma_module_init
);
1470 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1471 MODULE_DESCRIPTION("i.MX SDMA driver");
1472 MODULE_LICENSE("GPL");