2 * drivers/dma/imx-sdma.c
4 * This file contains a driver for the Freescale Smart DMA engine
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 * Based on code from Freescale:
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/bitops.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/semaphore.h>
30 #include <linux/spinlock.h>
31 #include <linux/device.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/firmware.h>
34 #include <linux/slab.h>
35 #include <linux/platform_device.h>
36 #include <linux/dmaengine.h>
38 #include <linux/of_device.h>
41 #include <mach/sdma.h>
43 #include <mach/hardware.h>
45 #include "dmaengine.h"
48 #define SDMA_H_C0PTR 0x000
49 #define SDMA_H_INTR 0x004
50 #define SDMA_H_STATSTOP 0x008
51 #define SDMA_H_START 0x00c
52 #define SDMA_H_EVTOVR 0x010
53 #define SDMA_H_DSPOVR 0x014
54 #define SDMA_H_HOSTOVR 0x018
55 #define SDMA_H_EVTPEND 0x01c
56 #define SDMA_H_DSPENBL 0x020
57 #define SDMA_H_RESET 0x024
58 #define SDMA_H_EVTERR 0x028
59 #define SDMA_H_INTRMSK 0x02c
60 #define SDMA_H_PSW 0x030
61 #define SDMA_H_EVTERRDBG 0x034
62 #define SDMA_H_CONFIG 0x038
63 #define SDMA_ONCE_ENB 0x040
64 #define SDMA_ONCE_DATA 0x044
65 #define SDMA_ONCE_INSTR 0x048
66 #define SDMA_ONCE_STAT 0x04c
67 #define SDMA_ONCE_CMD 0x050
68 #define SDMA_EVT_MIRROR 0x054
69 #define SDMA_ILLINSTADDR 0x058
70 #define SDMA_CHN0ADDR 0x05c
71 #define SDMA_ONCE_RTB 0x060
72 #define SDMA_XTRIG_CONF1 0x070
73 #define SDMA_XTRIG_CONF2 0x074
74 #define SDMA_CHNENBL0_IMX35 0x200
75 #define SDMA_CHNENBL0_IMX31 0x080
76 #define SDMA_CHNPRI_0 0x100
79 * Buffer descriptor status values.
90 * Data Node descriptor status values.
92 #define DND_END_OF_FRAME 0x80
93 #define DND_END_OF_XFER 0x40
95 #define DND_UNUSED 0x01
98 * IPCV2 descriptor status values.
100 #define BD_IPCV2_END_OF_FRAME 0x40
102 #define IPCV2_MAX_NODES 50
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
107 #define DATA_ERROR 0x10000000
110 * Buffer descriptor commands.
115 #define C0_SETCTX 0x07
116 #define C0_GETCTX 0x03
117 #define C0_SETDM 0x01
118 #define C0_SETPM 0x04
119 #define C0_GETDM 0x02
120 #define C0_GETPM 0x08
122 * Change endianness indicator in the BD command field
124 #define CHANGE_ENDIANNESS 0x80
127 * Mode/Count of data node descriptors - IPCv2
129 struct sdma_mode_count
{
130 u32 count
: 16; /* size of the buffer pointed by this BD */
131 u32 status
: 8; /* E,R,I,C,W,D status bits stored here */
132 u32 command
: 8; /* command mostlky used for channel 0 */
138 struct sdma_buffer_descriptor
{
139 struct sdma_mode_count mode
;
140 u32 buffer_addr
; /* address of the buffer described */
141 u32 ext_buffer_addr
; /* extended buffer address */
142 } __attribute__ ((packed
));
145 * struct sdma_channel_control - Channel control Block
147 * @current_bd_ptr current buffer descriptor processed
148 * @base_bd_ptr first element of buffer descriptor array
149 * @unused padding. The SDMA engine expects an array of 128 byte
152 struct sdma_channel_control
{
156 } __attribute__ ((packed
));
159 * struct sdma_state_registers - SDMA context for a channel
161 * @pc: program counter
162 * @t: test bit: status of arithmetic & test instruction
163 * @rpc: return program counter
164 * @sf: source fault while loading data
165 * @spc: loop start program counter
166 * @df: destination fault while storing data
167 * @epc: loop end program counter
170 struct sdma_state_registers
{
182 } __attribute__ ((packed
));
185 * struct sdma_context_data - sdma context specific to a channel
187 * @channel_state: channel state bits
188 * @gReg: general registers
189 * @mda: burst dma destination address register
190 * @msa: burst dma source address register
191 * @ms: burst dma status register
192 * @md: burst dma data register
193 * @pda: peripheral dma destination address register
194 * @psa: peripheral dma source address register
195 * @ps: peripheral dma status register
196 * @pd: peripheral dma data register
197 * @ca: CRC polynomial register
198 * @cs: CRC accumulator register
199 * @dda: dedicated core destination address register
200 * @dsa: dedicated core source address register
201 * @ds: dedicated core status register
202 * @dd: dedicated core data register
204 struct sdma_context_data
{
205 struct sdma_state_registers channel_state
;
229 } __attribute__ ((packed
));
231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
236 * struct sdma_channel - housekeeping for a SDMA channel
238 * @sdma pointer to the SDMA engine for this channel
239 * @channel the channel number, matches dmaengine chan_id + 1
240 * @direction transfer type. Needed for setting SDMA script
241 * @peripheral_type Peripheral type. Needed for setting SDMA script
242 * @event_id0 aka dma request line
243 * @event_id1 for channels that use 2 events
244 * @word_size peripheral access size
245 * @buf_tail ID of the buffer that was processed
246 * @done channel completion
247 * @num_bd max NUM_BD. number of descriptors currently handling
249 struct sdma_channel
{
250 struct sdma_engine
*sdma
;
251 unsigned int channel
;
252 enum dma_transfer_direction direction
;
253 enum sdma_peripheral_type peripheral_type
;
254 unsigned int event_id0
;
255 unsigned int event_id1
;
256 enum dma_slave_buswidth word_size
;
257 unsigned int buf_tail
;
258 struct completion done
;
260 struct sdma_buffer_descriptor
*bd
;
262 unsigned int pc_from_device
, pc_to_device
;
264 dma_addr_t per_address
;
265 unsigned long event_mask
[2];
266 unsigned long watermark_level
;
267 u32 shp_addr
, per_addr
;
268 struct dma_chan chan
;
270 struct dma_async_tx_descriptor desc
;
271 enum dma_status status
;
272 unsigned int chn_count
;
273 unsigned int chn_real_count
;
274 struct tasklet_struct tasklet
;
277 #define IMX_DMA_SG_LOOP BIT(0)
279 #define MAX_DMA_CHANNELS 32
280 #define MXC_SDMA_DEFAULT_PRIORITY 1
281 #define MXC_SDMA_MIN_PRIORITY 1
282 #define MXC_SDMA_MAX_PRIORITY 7
284 #define SDMA_FIRMWARE_MAGIC 0x414d4453
287 * struct sdma_firmware_header - Layout of the firmware image
290 * @version_major increased whenever layout of struct sdma_script_start_addrs
292 * @version_minor firmware minor version (for binary compatible changes)
293 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
294 * @num_script_addrs Number of script addresses in this image
295 * @ram_code_start offset of SDMA ram image in this firmware image
296 * @ram_code_size size of SDMA ram image
297 * @script_addrs Stores the start address of the SDMA scripts
298 * (in SDMA memory space)
300 struct sdma_firmware_header
{
304 u32 script_addrs_start
;
305 u32 num_script_addrs
;
311 IMX31_SDMA
, /* runs on i.mx31 */
312 IMX35_SDMA
, /* runs on i.mx35 and later */
317 struct device_dma_parameters dma_parms
;
318 struct sdma_channel channel
[MAX_DMA_CHANNELS
];
319 struct sdma_channel_control
*channel_control
;
321 enum sdma_devtype devtype
;
322 unsigned int num_events
;
323 struct sdma_context_data
*context
;
324 dma_addr_t context_phys
;
325 struct dma_device dma_device
;
328 spinlock_t channel_0_lock
;
329 struct sdma_script_start_addrs
*script_addrs
;
332 static struct platform_device_id sdma_devtypes
[] = {
334 .name
= "imx31-sdma",
335 .driver_data
= IMX31_SDMA
,
337 .name
= "imx35-sdma",
338 .driver_data
= IMX35_SDMA
,
343 MODULE_DEVICE_TABLE(platform
, sdma_devtypes
);
345 static const struct of_device_id sdma_dt_ids
[] = {
346 { .compatible
= "fsl,imx31-sdma", .data
= &sdma_devtypes
[IMX31_SDMA
], },
347 { .compatible
= "fsl,imx35-sdma", .data
= &sdma_devtypes
[IMX35_SDMA
], },
350 MODULE_DEVICE_TABLE(of
, sdma_dt_ids
);
352 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
353 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
354 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
355 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
357 static inline u32
chnenbl_ofs(struct sdma_engine
*sdma
, unsigned int event
)
359 u32 chnenbl0
= (sdma
->devtype
== IMX31_SDMA
? SDMA_CHNENBL0_IMX31
:
360 SDMA_CHNENBL0_IMX35
);
361 return chnenbl0
+ event
* 4;
364 static int sdma_config_ownership(struct sdma_channel
*sdmac
,
365 bool event_override
, bool mcu_override
, bool dsp_override
)
367 struct sdma_engine
*sdma
= sdmac
->sdma
;
368 int channel
= sdmac
->channel
;
369 unsigned long evt
, mcu
, dsp
;
371 if (event_override
&& mcu_override
&& dsp_override
)
374 evt
= readl_relaxed(sdma
->regs
+ SDMA_H_EVTOVR
);
375 mcu
= readl_relaxed(sdma
->regs
+ SDMA_H_HOSTOVR
);
376 dsp
= readl_relaxed(sdma
->regs
+ SDMA_H_DSPOVR
);
379 __clear_bit(channel
, &dsp
);
381 __set_bit(channel
, &dsp
);
384 __clear_bit(channel
, &evt
);
386 __set_bit(channel
, &evt
);
389 __clear_bit(channel
, &mcu
);
391 __set_bit(channel
, &mcu
);
393 writel_relaxed(evt
, sdma
->regs
+ SDMA_H_EVTOVR
);
394 writel_relaxed(mcu
, sdma
->regs
+ SDMA_H_HOSTOVR
);
395 writel_relaxed(dsp
, sdma
->regs
+ SDMA_H_DSPOVR
);
400 static void sdma_enable_channel(struct sdma_engine
*sdma
, int channel
)
402 writel(BIT(channel
), sdma
->regs
+ SDMA_H_START
);
406 * sdma_run_channel0 - run a channel and wait till it's done
408 static int sdma_run_channel0(struct sdma_engine
*sdma
)
411 unsigned long timeout
= 500;
413 sdma_enable_channel(sdma
, 0);
415 while (!(ret
= readl_relaxed(sdma
->regs
+ SDMA_H_INTR
) & 1)) {
422 /* Clear the interrupt status */
423 writel_relaxed(ret
, sdma
->regs
+ SDMA_H_INTR
);
425 dev_err(sdma
->dev
, "Timeout waiting for CH0 ready\n");
428 return ret
? 0 : -ETIMEDOUT
;
431 static int sdma_load_script(struct sdma_engine
*sdma
, void *buf
, int size
,
434 struct sdma_buffer_descriptor
*bd0
= sdma
->channel
[0].bd
;
440 buf_virt
= dma_alloc_coherent(NULL
,
442 &buf_phys
, GFP_KERNEL
);
447 spin_lock_irqsave(&sdma
->channel_0_lock
, flags
);
449 bd0
->mode
.command
= C0_SETPM
;
450 bd0
->mode
.status
= BD_DONE
| BD_INTR
| BD_WRAP
| BD_EXTD
;
451 bd0
->mode
.count
= size
/ 2;
452 bd0
->buffer_addr
= buf_phys
;
453 bd0
->ext_buffer_addr
= address
;
455 memcpy(buf_virt
, buf
, size
);
457 ret
= sdma_run_channel0(sdma
);
459 spin_unlock_irqrestore(&sdma
->channel_0_lock
, flags
);
461 dma_free_coherent(NULL
, size
, buf_virt
, buf_phys
);
466 static void sdma_event_enable(struct sdma_channel
*sdmac
, unsigned int event
)
468 struct sdma_engine
*sdma
= sdmac
->sdma
;
469 int channel
= sdmac
->channel
;
471 u32 chnenbl
= chnenbl_ofs(sdma
, event
);
473 val
= readl_relaxed(sdma
->regs
+ chnenbl
);
474 __set_bit(channel
, &val
);
475 writel_relaxed(val
, sdma
->regs
+ chnenbl
);
478 static void sdma_event_disable(struct sdma_channel
*sdmac
, unsigned int event
)
480 struct sdma_engine
*sdma
= sdmac
->sdma
;
481 int channel
= sdmac
->channel
;
482 u32 chnenbl
= chnenbl_ofs(sdma
, event
);
485 val
= readl_relaxed(sdma
->regs
+ chnenbl
);
486 __clear_bit(channel
, &val
);
487 writel_relaxed(val
, sdma
->regs
+ chnenbl
);
490 static void sdma_handle_channel_loop(struct sdma_channel
*sdmac
)
492 struct sdma_buffer_descriptor
*bd
;
495 * loop mode. Iterate over descriptors, re-setup them and
496 * call callback function.
499 bd
= &sdmac
->bd
[sdmac
->buf_tail
];
501 if (bd
->mode
.status
& BD_DONE
)
504 if (bd
->mode
.status
& BD_RROR
)
505 sdmac
->status
= DMA_ERROR
;
507 sdmac
->status
= DMA_IN_PROGRESS
;
509 bd
->mode
.status
|= BD_DONE
;
511 sdmac
->buf_tail
%= sdmac
->num_bd
;
513 if (sdmac
->desc
.callback
)
514 sdmac
->desc
.callback(sdmac
->desc
.callback_param
);
518 static void mxc_sdma_handle_channel_normal(struct sdma_channel
*sdmac
)
520 struct sdma_buffer_descriptor
*bd
;
523 sdmac
->chn_real_count
= 0;
525 * non loop mode. Iterate over all descriptors, collect
526 * errors and call callback function
528 for (i
= 0; i
< sdmac
->num_bd
; i
++) {
531 if (bd
->mode
.status
& (BD_DONE
| BD_RROR
))
533 sdmac
->chn_real_count
+= bd
->mode
.count
;
537 sdmac
->status
= DMA_ERROR
;
539 sdmac
->status
= DMA_SUCCESS
;
541 dma_cookie_complete(&sdmac
->desc
);
542 if (sdmac
->desc
.callback
)
543 sdmac
->desc
.callback(sdmac
->desc
.callback_param
);
546 static void sdma_tasklet(unsigned long data
)
548 struct sdma_channel
*sdmac
= (struct sdma_channel
*) data
;
550 complete(&sdmac
->done
);
552 if (sdmac
->flags
& IMX_DMA_SG_LOOP
)
553 sdma_handle_channel_loop(sdmac
);
555 mxc_sdma_handle_channel_normal(sdmac
);
558 static irqreturn_t
sdma_int_handler(int irq
, void *dev_id
)
560 struct sdma_engine
*sdma
= dev_id
;
563 stat
= readl_relaxed(sdma
->regs
+ SDMA_H_INTR
);
564 /* not interested in channel 0 interrupts */
566 writel_relaxed(stat
, sdma
->regs
+ SDMA_H_INTR
);
569 int channel
= fls(stat
) - 1;
570 struct sdma_channel
*sdmac
= &sdma
->channel
[channel
];
572 tasklet_schedule(&sdmac
->tasklet
);
574 __clear_bit(channel
, &stat
);
581 * sets the pc of SDMA script according to the peripheral type
583 static void sdma_get_pc(struct sdma_channel
*sdmac
,
584 enum sdma_peripheral_type peripheral_type
)
586 struct sdma_engine
*sdma
= sdmac
->sdma
;
587 int per_2_emi
= 0, emi_2_per
= 0;
589 * These are needed once we start to support transfers between
590 * two peripherals or memory-to-memory transfers
592 int per_2_per
= 0, emi_2_emi
= 0;
594 sdmac
->pc_from_device
= 0;
595 sdmac
->pc_to_device
= 0;
597 switch (peripheral_type
) {
598 case IMX_DMATYPE_MEMORY
:
599 emi_2_emi
= sdma
->script_addrs
->ap_2_ap_addr
;
601 case IMX_DMATYPE_DSP
:
602 emi_2_per
= sdma
->script_addrs
->bp_2_ap_addr
;
603 per_2_emi
= sdma
->script_addrs
->ap_2_bp_addr
;
605 case IMX_DMATYPE_FIRI
:
606 per_2_emi
= sdma
->script_addrs
->firi_2_mcu_addr
;
607 emi_2_per
= sdma
->script_addrs
->mcu_2_firi_addr
;
609 case IMX_DMATYPE_UART
:
610 per_2_emi
= sdma
->script_addrs
->uart_2_mcu_addr
;
611 emi_2_per
= sdma
->script_addrs
->mcu_2_app_addr
;
613 case IMX_DMATYPE_UART_SP
:
614 per_2_emi
= sdma
->script_addrs
->uartsh_2_mcu_addr
;
615 emi_2_per
= sdma
->script_addrs
->mcu_2_shp_addr
;
617 case IMX_DMATYPE_ATA
:
618 per_2_emi
= sdma
->script_addrs
->ata_2_mcu_addr
;
619 emi_2_per
= sdma
->script_addrs
->mcu_2_ata_addr
;
621 case IMX_DMATYPE_CSPI
:
622 case IMX_DMATYPE_EXT
:
623 case IMX_DMATYPE_SSI
:
624 per_2_emi
= sdma
->script_addrs
->app_2_mcu_addr
;
625 emi_2_per
= sdma
->script_addrs
->mcu_2_app_addr
;
627 case IMX_DMATYPE_SSI_SP
:
628 case IMX_DMATYPE_MMC
:
629 case IMX_DMATYPE_SDHC
:
630 case IMX_DMATYPE_CSPI_SP
:
631 case IMX_DMATYPE_ESAI
:
632 case IMX_DMATYPE_MSHC_SP
:
633 per_2_emi
= sdma
->script_addrs
->shp_2_mcu_addr
;
634 emi_2_per
= sdma
->script_addrs
->mcu_2_shp_addr
;
636 case IMX_DMATYPE_ASRC
:
637 per_2_emi
= sdma
->script_addrs
->asrc_2_mcu_addr
;
638 emi_2_per
= sdma
->script_addrs
->asrc_2_mcu_addr
;
639 per_2_per
= sdma
->script_addrs
->per_2_per_addr
;
641 case IMX_DMATYPE_MSHC
:
642 per_2_emi
= sdma
->script_addrs
->mshc_2_mcu_addr
;
643 emi_2_per
= sdma
->script_addrs
->mcu_2_mshc_addr
;
645 case IMX_DMATYPE_CCM
:
646 per_2_emi
= sdma
->script_addrs
->dptc_dvfs_addr
;
648 case IMX_DMATYPE_SPDIF
:
649 per_2_emi
= sdma
->script_addrs
->spdif_2_mcu_addr
;
650 emi_2_per
= sdma
->script_addrs
->mcu_2_spdif_addr
;
652 case IMX_DMATYPE_IPU_MEMORY
:
653 emi_2_per
= sdma
->script_addrs
->ext_mem_2_ipu_addr
;
659 sdmac
->pc_from_device
= per_2_emi
;
660 sdmac
->pc_to_device
= emi_2_per
;
663 static int sdma_load_context(struct sdma_channel
*sdmac
)
665 struct sdma_engine
*sdma
= sdmac
->sdma
;
666 int channel
= sdmac
->channel
;
668 struct sdma_context_data
*context
= sdma
->context
;
669 struct sdma_buffer_descriptor
*bd0
= sdma
->channel
[0].bd
;
673 if (sdmac
->direction
== DMA_DEV_TO_MEM
) {
674 load_address
= sdmac
->pc_from_device
;
676 load_address
= sdmac
->pc_to_device
;
679 if (load_address
< 0)
682 dev_dbg(sdma
->dev
, "load_address = %d\n", load_address
);
683 dev_dbg(sdma
->dev
, "wml = 0x%08x\n", (u32
)sdmac
->watermark_level
);
684 dev_dbg(sdma
->dev
, "shp_addr = 0x%08x\n", sdmac
->shp_addr
);
685 dev_dbg(sdma
->dev
, "per_addr = 0x%08x\n", sdmac
->per_addr
);
686 dev_dbg(sdma
->dev
, "event_mask0 = 0x%08x\n", (u32
)sdmac
->event_mask
[0]);
687 dev_dbg(sdma
->dev
, "event_mask1 = 0x%08x\n", (u32
)sdmac
->event_mask
[1]);
689 spin_lock_irqsave(&sdma
->channel_0_lock
, flags
);
691 memset(context
, 0, sizeof(*context
));
692 context
->channel_state
.pc
= load_address
;
694 /* Send by context the event mask,base address for peripheral
695 * and watermark level
697 context
->gReg
[0] = sdmac
->event_mask
[1];
698 context
->gReg
[1] = sdmac
->event_mask
[0];
699 context
->gReg
[2] = sdmac
->per_addr
;
700 context
->gReg
[6] = sdmac
->shp_addr
;
701 context
->gReg
[7] = sdmac
->watermark_level
;
703 bd0
->mode
.command
= C0_SETDM
;
704 bd0
->mode
.status
= BD_DONE
| BD_INTR
| BD_WRAP
| BD_EXTD
;
705 bd0
->mode
.count
= sizeof(*context
) / 4;
706 bd0
->buffer_addr
= sdma
->context_phys
;
707 bd0
->ext_buffer_addr
= 2048 + (sizeof(*context
) / 4) * channel
;
708 ret
= sdma_run_channel0(sdma
);
710 spin_unlock_irqrestore(&sdma
->channel_0_lock
, flags
);
715 static void sdma_disable_channel(struct sdma_channel
*sdmac
)
717 struct sdma_engine
*sdma
= sdmac
->sdma
;
718 int channel
= sdmac
->channel
;
720 writel_relaxed(BIT(channel
), sdma
->regs
+ SDMA_H_STATSTOP
);
721 sdmac
->status
= DMA_ERROR
;
724 static int sdma_config_channel(struct sdma_channel
*sdmac
)
728 sdma_disable_channel(sdmac
);
730 sdmac
->event_mask
[0] = 0;
731 sdmac
->event_mask
[1] = 0;
735 if (sdmac
->event_id0
) {
736 if (sdmac
->event_id0
>= sdmac
->sdma
->num_events
)
738 sdma_event_enable(sdmac
, sdmac
->event_id0
);
741 switch (sdmac
->peripheral_type
) {
742 case IMX_DMATYPE_DSP
:
743 sdma_config_ownership(sdmac
, false, true, true);
745 case IMX_DMATYPE_MEMORY
:
746 sdma_config_ownership(sdmac
, false, true, false);
749 sdma_config_ownership(sdmac
, true, true, false);
753 sdma_get_pc(sdmac
, sdmac
->peripheral_type
);
755 if ((sdmac
->peripheral_type
!= IMX_DMATYPE_MEMORY
) &&
756 (sdmac
->peripheral_type
!= IMX_DMATYPE_DSP
)) {
757 /* Handle multiple event channels differently */
758 if (sdmac
->event_id1
) {
759 sdmac
->event_mask
[1] = BIT(sdmac
->event_id1
% 32);
760 if (sdmac
->event_id1
> 31)
761 __set_bit(31, &sdmac
->watermark_level
);
762 sdmac
->event_mask
[0] = BIT(sdmac
->event_id0
% 32);
763 if (sdmac
->event_id0
> 31)
764 __set_bit(30, &sdmac
->watermark_level
);
766 __set_bit(sdmac
->event_id0
, sdmac
->event_mask
);
768 /* Watermark Level */
769 sdmac
->watermark_level
|= sdmac
->watermark_level
;
771 sdmac
->shp_addr
= sdmac
->per_address
;
773 sdmac
->watermark_level
= 0; /* FIXME: M3_BASE_ADDRESS */
776 ret
= sdma_load_context(sdmac
);
781 static int sdma_set_channel_priority(struct sdma_channel
*sdmac
,
782 unsigned int priority
)
784 struct sdma_engine
*sdma
= sdmac
->sdma
;
785 int channel
= sdmac
->channel
;
787 if (priority
< MXC_SDMA_MIN_PRIORITY
788 || priority
> MXC_SDMA_MAX_PRIORITY
) {
792 writel_relaxed(priority
, sdma
->regs
+ SDMA_CHNPRI_0
+ 4 * channel
);
797 static int sdma_request_channel(struct sdma_channel
*sdmac
)
799 struct sdma_engine
*sdma
= sdmac
->sdma
;
800 int channel
= sdmac
->channel
;
803 sdmac
->bd
= dma_alloc_coherent(NULL
, PAGE_SIZE
, &sdmac
->bd_phys
, GFP_KERNEL
);
809 memset(sdmac
->bd
, 0, PAGE_SIZE
);
811 sdma
->channel_control
[channel
].base_bd_ptr
= sdmac
->bd_phys
;
812 sdma
->channel_control
[channel
].current_bd_ptr
= sdmac
->bd_phys
;
814 sdma_set_channel_priority(sdmac
, MXC_SDMA_DEFAULT_PRIORITY
);
816 init_completion(&sdmac
->done
);
826 static struct sdma_channel
*to_sdma_chan(struct dma_chan
*chan
)
828 return container_of(chan
, struct sdma_channel
, chan
);
831 static dma_cookie_t
sdma_tx_submit(struct dma_async_tx_descriptor
*tx
)
834 struct sdma_channel
*sdmac
= to_sdma_chan(tx
->chan
);
837 spin_lock_irqsave(&sdmac
->lock
, flags
);
839 cookie
= dma_cookie_assign(tx
);
841 spin_unlock_irqrestore(&sdmac
->lock
, flags
);
846 static int sdma_alloc_chan_resources(struct dma_chan
*chan
)
848 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
849 struct imx_dma_data
*data
= chan
->private;
855 switch (data
->priority
) {
859 case DMA_PRIO_MEDIUM
:
868 sdmac
->peripheral_type
= data
->peripheral_type
;
869 sdmac
->event_id0
= data
->dma_request
;
871 clk_enable(sdmac
->sdma
->clk_ipg
);
872 clk_enable(sdmac
->sdma
->clk_ahb
);
874 ret
= sdma_request_channel(sdmac
);
878 ret
= sdma_set_channel_priority(sdmac
, prio
);
882 dma_async_tx_descriptor_init(&sdmac
->desc
, chan
);
883 sdmac
->desc
.tx_submit
= sdma_tx_submit
;
884 /* txd.flags will be overwritten in prep funcs */
885 sdmac
->desc
.flags
= DMA_CTRL_ACK
;
890 static void sdma_free_chan_resources(struct dma_chan
*chan
)
892 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
893 struct sdma_engine
*sdma
= sdmac
->sdma
;
895 sdma_disable_channel(sdmac
);
897 if (sdmac
->event_id0
)
898 sdma_event_disable(sdmac
, sdmac
->event_id0
);
899 if (sdmac
->event_id1
)
900 sdma_event_disable(sdmac
, sdmac
->event_id1
);
902 sdmac
->event_id0
= 0;
903 sdmac
->event_id1
= 0;
905 sdma_set_channel_priority(sdmac
, 0);
907 dma_free_coherent(NULL
, PAGE_SIZE
, sdmac
->bd
, sdmac
->bd_phys
);
909 clk_disable(sdma
->clk_ipg
);
910 clk_disable(sdma
->clk_ahb
);
913 static struct dma_async_tx_descriptor
*sdma_prep_slave_sg(
914 struct dma_chan
*chan
, struct scatterlist
*sgl
,
915 unsigned int sg_len
, enum dma_transfer_direction direction
,
916 unsigned long flags
, void *context
)
918 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
919 struct sdma_engine
*sdma
= sdmac
->sdma
;
921 int channel
= sdmac
->channel
;
922 struct scatterlist
*sg
;
924 if (sdmac
->status
== DMA_IN_PROGRESS
)
926 sdmac
->status
= DMA_IN_PROGRESS
;
930 dev_dbg(sdma
->dev
, "setting up %d entries for channel %d.\n",
933 sdmac
->direction
= direction
;
934 ret
= sdma_load_context(sdmac
);
938 if (sg_len
> NUM_BD
) {
939 dev_err(sdma
->dev
, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
940 channel
, sg_len
, NUM_BD
);
945 sdmac
->chn_count
= 0;
946 for_each_sg(sgl
, sg
, sg_len
, i
) {
947 struct sdma_buffer_descriptor
*bd
= &sdmac
->bd
[i
];
950 bd
->buffer_addr
= sg
->dma_address
;
952 count
= sg_dma_len(sg
);
954 if (count
> 0xffff) {
955 dev_err(sdma
->dev
, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
956 channel
, count
, 0xffff);
961 bd
->mode
.count
= count
;
962 sdmac
->chn_count
+= count
;
964 if (sdmac
->word_size
> DMA_SLAVE_BUSWIDTH_4_BYTES
) {
969 switch (sdmac
->word_size
) {
970 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
971 bd
->mode
.command
= 0;
972 if (count
& 3 || sg
->dma_address
& 3)
975 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
976 bd
->mode
.command
= 2;
977 if (count
& 1 || sg
->dma_address
& 1)
980 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
981 bd
->mode
.command
= 1;
987 param
= BD_DONE
| BD_EXTD
| BD_CONT
;
989 if (i
+ 1 == sg_len
) {
995 dev_dbg(sdma
->dev
, "entry %d: count: %d dma: 0x%08x %s%s\n",
996 i
, count
, sg
->dma_address
,
997 param
& BD_WRAP
? "wrap" : "",
998 param
& BD_INTR
? " intr" : "");
1000 bd
->mode
.status
= param
;
1003 sdmac
->num_bd
= sg_len
;
1004 sdma
->channel_control
[channel
].current_bd_ptr
= sdmac
->bd_phys
;
1006 return &sdmac
->desc
;
1008 sdmac
->status
= DMA_ERROR
;
1012 static struct dma_async_tx_descriptor
*sdma_prep_dma_cyclic(
1013 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t buf_len
,
1014 size_t period_len
, enum dma_transfer_direction direction
,
1017 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
1018 struct sdma_engine
*sdma
= sdmac
->sdma
;
1019 int num_periods
= buf_len
/ period_len
;
1020 int channel
= sdmac
->channel
;
1021 int ret
, i
= 0, buf
= 0;
1023 dev_dbg(sdma
->dev
, "%s channel: %d\n", __func__
, channel
);
1025 if (sdmac
->status
== DMA_IN_PROGRESS
)
1028 sdmac
->status
= DMA_IN_PROGRESS
;
1030 sdmac
->flags
|= IMX_DMA_SG_LOOP
;
1031 sdmac
->direction
= direction
;
1032 ret
= sdma_load_context(sdmac
);
1036 if (num_periods
> NUM_BD
) {
1037 dev_err(sdma
->dev
, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1038 channel
, num_periods
, NUM_BD
);
1042 if (period_len
> 0xffff) {
1043 dev_err(sdma
->dev
, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1044 channel
, period_len
, 0xffff);
1048 while (buf
< buf_len
) {
1049 struct sdma_buffer_descriptor
*bd
= &sdmac
->bd
[i
];
1052 bd
->buffer_addr
= dma_addr
;
1054 bd
->mode
.count
= period_len
;
1056 if (sdmac
->word_size
> DMA_SLAVE_BUSWIDTH_4_BYTES
)
1058 if (sdmac
->word_size
== DMA_SLAVE_BUSWIDTH_4_BYTES
)
1059 bd
->mode
.command
= 0;
1061 bd
->mode
.command
= sdmac
->word_size
;
1063 param
= BD_DONE
| BD_EXTD
| BD_CONT
| BD_INTR
;
1064 if (i
+ 1 == num_periods
)
1067 dev_dbg(sdma
->dev
, "entry %d: count: %d dma: 0x%08x %s%s\n",
1068 i
, period_len
, dma_addr
,
1069 param
& BD_WRAP
? "wrap" : "",
1070 param
& BD_INTR
? " intr" : "");
1072 bd
->mode
.status
= param
;
1074 dma_addr
+= period_len
;
1080 sdmac
->num_bd
= num_periods
;
1081 sdma
->channel_control
[channel
].current_bd_ptr
= sdmac
->bd_phys
;
1083 return &sdmac
->desc
;
1085 sdmac
->status
= DMA_ERROR
;
1089 static int sdma_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1092 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
1093 struct dma_slave_config
*dmaengine_cfg
= (void *)arg
;
1096 case DMA_TERMINATE_ALL
:
1097 sdma_disable_channel(sdmac
);
1099 case DMA_SLAVE_CONFIG
:
1100 if (dmaengine_cfg
->direction
== DMA_DEV_TO_MEM
) {
1101 sdmac
->per_address
= dmaengine_cfg
->src_addr
;
1102 sdmac
->watermark_level
= dmaengine_cfg
->src_maxburst
*
1103 dmaengine_cfg
->src_addr_width
;
1104 sdmac
->word_size
= dmaengine_cfg
->src_addr_width
;
1106 sdmac
->per_address
= dmaengine_cfg
->dst_addr
;
1107 sdmac
->watermark_level
= dmaengine_cfg
->dst_maxburst
*
1108 dmaengine_cfg
->dst_addr_width
;
1109 sdmac
->word_size
= dmaengine_cfg
->dst_addr_width
;
1111 sdmac
->direction
= dmaengine_cfg
->direction
;
1112 return sdma_config_channel(sdmac
);
1120 static enum dma_status
sdma_tx_status(struct dma_chan
*chan
,
1121 dma_cookie_t cookie
,
1122 struct dma_tx_state
*txstate
)
1124 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
1125 dma_cookie_t last_used
;
1127 last_used
= chan
->cookie
;
1129 dma_set_tx_state(txstate
, chan
->completed_cookie
, last_used
,
1130 sdmac
->chn_count
- sdmac
->chn_real_count
);
1132 return sdmac
->status
;
1135 static void sdma_issue_pending(struct dma_chan
*chan
)
1137 struct sdma_channel
*sdmac
= to_sdma_chan(chan
);
1138 struct sdma_engine
*sdma
= sdmac
->sdma
;
1140 if (sdmac
->status
== DMA_IN_PROGRESS
)
1141 sdma_enable_channel(sdma
, sdmac
->channel
);
1144 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1146 static void sdma_add_scripts(struct sdma_engine
*sdma
,
1147 const struct sdma_script_start_addrs
*addr
)
1149 s32
*addr_arr
= (u32
*)addr
;
1150 s32
*saddr_arr
= (u32
*)sdma
->script_addrs
;
1153 for (i
= 0; i
< SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1
; i
++)
1154 if (addr_arr
[i
] > 0)
1155 saddr_arr
[i
] = addr_arr
[i
];
1158 static void sdma_load_firmware(const struct firmware
*fw
, void *context
)
1160 struct sdma_engine
*sdma
= context
;
1161 const struct sdma_firmware_header
*header
;
1162 const struct sdma_script_start_addrs
*addr
;
1163 unsigned short *ram_code
;
1166 dev_err(sdma
->dev
, "firmware not found\n");
1170 if (fw
->size
< sizeof(*header
))
1173 header
= (struct sdma_firmware_header
*)fw
->data
;
1175 if (header
->magic
!= SDMA_FIRMWARE_MAGIC
)
1177 if (header
->ram_code_start
+ header
->ram_code_size
> fw
->size
)
1180 addr
= (void *)header
+ header
->script_addrs_start
;
1181 ram_code
= (void *)header
+ header
->ram_code_start
;
1183 clk_enable(sdma
->clk_ipg
);
1184 clk_enable(sdma
->clk_ahb
);
1185 /* download the RAM image for SDMA */
1186 sdma_load_script(sdma
, ram_code
,
1187 header
->ram_code_size
,
1188 addr
->ram_code_start_addr
);
1189 clk_disable(sdma
->clk_ipg
);
1190 clk_disable(sdma
->clk_ahb
);
1192 sdma_add_scripts(sdma
, addr
);
1194 dev_info(sdma
->dev
, "loaded firmware %d.%d\n",
1195 header
->version_major
,
1196 header
->version_minor
);
1199 release_firmware(fw
);
1202 static int __init
sdma_get_firmware(struct sdma_engine
*sdma
,
1203 const char *fw_name
)
1207 ret
= request_firmware_nowait(THIS_MODULE
,
1208 FW_ACTION_HOTPLUG
, fw_name
, sdma
->dev
,
1209 GFP_KERNEL
, sdma
, sdma_load_firmware
);
1214 static int __init
sdma_init(struct sdma_engine
*sdma
)
1217 dma_addr_t ccb_phys
;
1219 switch (sdma
->devtype
) {
1221 sdma
->num_events
= 32;
1224 sdma
->num_events
= 48;
1227 dev_err(sdma
->dev
, "Unknown sdma type %d. aborting\n",
1232 clk_enable(sdma
->clk_ipg
);
1233 clk_enable(sdma
->clk_ahb
);
1235 /* Be sure SDMA has not started yet */
1236 writel_relaxed(0, sdma
->regs
+ SDMA_H_C0PTR
);
1238 sdma
->channel_control
= dma_alloc_coherent(NULL
,
1239 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
) +
1240 sizeof(struct sdma_context_data
),
1241 &ccb_phys
, GFP_KERNEL
);
1243 if (!sdma
->channel_control
) {
1248 sdma
->context
= (void *)sdma
->channel_control
+
1249 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
);
1250 sdma
->context_phys
= ccb_phys
+
1251 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
);
1253 /* Zero-out the CCB structures array just allocated */
1254 memset(sdma
->channel_control
, 0,
1255 MAX_DMA_CHANNELS
* sizeof (struct sdma_channel_control
));
1257 /* disable all channels */
1258 for (i
= 0; i
< sdma
->num_events
; i
++)
1259 writel_relaxed(0, sdma
->regs
+ chnenbl_ofs(sdma
, i
));
1261 /* All channels have priority 0 */
1262 for (i
= 0; i
< MAX_DMA_CHANNELS
; i
++)
1263 writel_relaxed(0, sdma
->regs
+ SDMA_CHNPRI_0
+ i
* 4);
1265 ret
= sdma_request_channel(&sdma
->channel
[0]);
1269 sdma_config_ownership(&sdma
->channel
[0], false, true, false);
1271 /* Set Command Channel (Channel Zero) */
1272 writel_relaxed(0x4050, sdma
->regs
+ SDMA_CHN0ADDR
);
1274 /* Set bits of CONFIG register but with static context switching */
1275 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1276 writel_relaxed(0, sdma
->regs
+ SDMA_H_CONFIG
);
1278 writel_relaxed(ccb_phys
, sdma
->regs
+ SDMA_H_C0PTR
);
1280 /* Set bits of CONFIG register with given context switching mode */
1281 writel_relaxed(SDMA_H_CONFIG_CSM
, sdma
->regs
+ SDMA_H_CONFIG
);
1283 /* Initializes channel's priorities */
1284 sdma_set_channel_priority(&sdma
->channel
[0], 7);
1286 clk_disable(sdma
->clk_ipg
);
1287 clk_disable(sdma
->clk_ahb
);
1292 clk_disable(sdma
->clk_ipg
);
1293 clk_disable(sdma
->clk_ahb
);
1294 dev_err(sdma
->dev
, "initialisation failed with %d\n", ret
);
1298 static int __init
sdma_probe(struct platform_device
*pdev
)
1300 const struct of_device_id
*of_id
=
1301 of_match_device(sdma_dt_ids
, &pdev
->dev
);
1302 struct device_node
*np
= pdev
->dev
.of_node
;
1303 const char *fw_name
;
1306 struct resource
*iores
;
1307 struct sdma_platform_data
*pdata
= pdev
->dev
.platform_data
;
1309 struct sdma_engine
*sdma
;
1312 sdma
= kzalloc(sizeof(*sdma
), GFP_KERNEL
);
1316 spin_lock_init(&sdma
->channel_0_lock
);
1318 sdma
->dev
= &pdev
->dev
;
1320 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1321 irq
= platform_get_irq(pdev
, 0);
1322 if (!iores
|| irq
< 0) {
1327 if (!request_mem_region(iores
->start
, resource_size(iores
), pdev
->name
)) {
1329 goto err_request_region
;
1332 sdma
->clk_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
1333 if (IS_ERR(sdma
->clk_ipg
)) {
1334 ret
= PTR_ERR(sdma
->clk_ipg
);
1338 sdma
->clk_ahb
= devm_clk_get(&pdev
->dev
, "ahb");
1339 if (IS_ERR(sdma
->clk_ahb
)) {
1340 ret
= PTR_ERR(sdma
->clk_ahb
);
1344 clk_prepare(sdma
->clk_ipg
);
1345 clk_prepare(sdma
->clk_ahb
);
1347 sdma
->regs
= ioremap(iores
->start
, resource_size(iores
));
1353 ret
= request_irq(irq
, sdma_int_handler
, 0, "sdma", sdma
);
1355 goto err_request_irq
;
1357 sdma
->script_addrs
= kzalloc(sizeof(*sdma
->script_addrs
), GFP_KERNEL
);
1358 if (!sdma
->script_addrs
) {
1363 /* initially no scripts available */
1364 saddr_arr
= (s32
*)sdma
->script_addrs
;
1365 for (i
= 0; i
< SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1
; i
++)
1366 saddr_arr
[i
] = -EINVAL
;
1369 pdev
->id_entry
= of_id
->data
;
1370 sdma
->devtype
= pdev
->id_entry
->driver_data
;
1372 dma_cap_set(DMA_SLAVE
, sdma
->dma_device
.cap_mask
);
1373 dma_cap_set(DMA_CYCLIC
, sdma
->dma_device
.cap_mask
);
1375 INIT_LIST_HEAD(&sdma
->dma_device
.channels
);
1376 /* Initialize channel parameters */
1377 for (i
= 0; i
< MAX_DMA_CHANNELS
; i
++) {
1378 struct sdma_channel
*sdmac
= &sdma
->channel
[i
];
1381 spin_lock_init(&sdmac
->lock
);
1383 sdmac
->chan
.device
= &sdma
->dma_device
;
1384 dma_cookie_init(&sdmac
->chan
);
1387 tasklet_init(&sdmac
->tasklet
, sdma_tasklet
,
1388 (unsigned long) sdmac
);
1390 * Add the channel to the DMAC list. Do not add channel 0 though
1391 * because we need it internally in the SDMA driver. This also means
1392 * that channel 0 in dmaengine counting matches sdma channel 1.
1395 list_add_tail(&sdmac
->chan
.device_node
,
1396 &sdma
->dma_device
.channels
);
1399 ret
= sdma_init(sdma
);
1403 if (pdata
&& pdata
->script_addrs
)
1404 sdma_add_scripts(sdma
, pdata
->script_addrs
);
1407 ret
= sdma_get_firmware(sdma
, pdata
->fw_name
);
1409 dev_warn(&pdev
->dev
, "failed to get firmware from platform data\n");
1412 * Because that device tree does not encode ROM script address,
1413 * the RAM script in firmware is mandatory for device tree
1414 * probe, otherwise it fails.
1416 ret
= of_property_read_string(np
, "fsl,sdma-ram-script-name",
1419 dev_warn(&pdev
->dev
, "failed to get firmware name\n");
1421 ret
= sdma_get_firmware(sdma
, fw_name
);
1423 dev_warn(&pdev
->dev
, "failed to get firmware from device tree\n");
1427 sdma
->dma_device
.dev
= &pdev
->dev
;
1429 sdma
->dma_device
.device_alloc_chan_resources
= sdma_alloc_chan_resources
;
1430 sdma
->dma_device
.device_free_chan_resources
= sdma_free_chan_resources
;
1431 sdma
->dma_device
.device_tx_status
= sdma_tx_status
;
1432 sdma
->dma_device
.device_prep_slave_sg
= sdma_prep_slave_sg
;
1433 sdma
->dma_device
.device_prep_dma_cyclic
= sdma_prep_dma_cyclic
;
1434 sdma
->dma_device
.device_control
= sdma_control
;
1435 sdma
->dma_device
.device_issue_pending
= sdma_issue_pending
;
1436 sdma
->dma_device
.dev
->dma_parms
= &sdma
->dma_parms
;
1437 dma_set_max_seg_size(sdma
->dma_device
.dev
, 65535);
1439 ret
= dma_async_device_register(&sdma
->dma_device
);
1441 dev_err(&pdev
->dev
, "unable to register\n");
1445 dev_info(sdma
->dev
, "initialized\n");
1450 kfree(sdma
->script_addrs
);
1452 free_irq(irq
, sdma
);
1454 iounmap(sdma
->regs
);
1457 release_mem_region(iores
->start
, resource_size(iores
));
1464 static int __exit
sdma_remove(struct platform_device
*pdev
)
1469 static struct platform_driver sdma_driver
= {
1472 .of_match_table
= sdma_dt_ids
,
1474 .id_table
= sdma_devtypes
,
1475 .remove
= __exit_p(sdma_remove
),
1478 static int __init
sdma_module_init(void)
1480 return platform_driver_probe(&sdma_driver
, sdma_probe
);
1482 module_init(sdma_module_init
);
1484 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1485 MODULE_DESCRIPTION("i.MX SDMA driver");
1486 MODULE_LICENSE("GPL");