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dmaengine: imx-sdma: Add i.MX7 support
[deliverable/linux.git] / drivers / dma / imx-sdma.c
1 /*
2 * drivers/dma/imx-sdma.c
3 *
4 * This file contains a driver for the Freescale Smart DMA engine
5 *
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 *
8 * Based on code from Freescale:
9 *
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19
20 #include <linux/init.h>
21 #include <linux/iopoll.h>
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/bitops.h>
25 #include <linux/mm.h>
26 #include <linux/interrupt.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/sched.h>
30 #include <linux/semaphore.h>
31 #include <linux/spinlock.h>
32 #include <linux/device.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/firmware.h>
35 #include <linux/slab.h>
36 #include <linux/platform_device.h>
37 #include <linux/dmaengine.h>
38 #include <linux/of.h>
39 #include <linux/of_address.h>
40 #include <linux/of_device.h>
41 #include <linux/of_dma.h>
42
43 #include <asm/irq.h>
44 #include <linux/platform_data/dma-imx-sdma.h>
45 #include <linux/platform_data/dma-imx.h>
46 #include <linux/regmap.h>
47 #include <linux/mfd/syscon.h>
48 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
49
50 #include "dmaengine.h"
51
52 /* SDMA registers */
53 #define SDMA_H_C0PTR 0x000
54 #define SDMA_H_INTR 0x004
55 #define SDMA_H_STATSTOP 0x008
56 #define SDMA_H_START 0x00c
57 #define SDMA_H_EVTOVR 0x010
58 #define SDMA_H_DSPOVR 0x014
59 #define SDMA_H_HOSTOVR 0x018
60 #define SDMA_H_EVTPEND 0x01c
61 #define SDMA_H_DSPENBL 0x020
62 #define SDMA_H_RESET 0x024
63 #define SDMA_H_EVTERR 0x028
64 #define SDMA_H_INTRMSK 0x02c
65 #define SDMA_H_PSW 0x030
66 #define SDMA_H_EVTERRDBG 0x034
67 #define SDMA_H_CONFIG 0x038
68 #define SDMA_ONCE_ENB 0x040
69 #define SDMA_ONCE_DATA 0x044
70 #define SDMA_ONCE_INSTR 0x048
71 #define SDMA_ONCE_STAT 0x04c
72 #define SDMA_ONCE_CMD 0x050
73 #define SDMA_EVT_MIRROR 0x054
74 #define SDMA_ILLINSTADDR 0x058
75 #define SDMA_CHN0ADDR 0x05c
76 #define SDMA_ONCE_RTB 0x060
77 #define SDMA_XTRIG_CONF1 0x070
78 #define SDMA_XTRIG_CONF2 0x074
79 #define SDMA_CHNENBL0_IMX35 0x200
80 #define SDMA_CHNENBL0_IMX31 0x080
81 #define SDMA_CHNPRI_0 0x100
82
83 /*
84 * Buffer descriptor status values.
85 */
86 #define BD_DONE 0x01
87 #define BD_WRAP 0x02
88 #define BD_CONT 0x04
89 #define BD_INTR 0x08
90 #define BD_RROR 0x10
91 #define BD_LAST 0x20
92 #define BD_EXTD 0x80
93
94 /*
95 * Data Node descriptor status values.
96 */
97 #define DND_END_OF_FRAME 0x80
98 #define DND_END_OF_XFER 0x40
99 #define DND_DONE 0x20
100 #define DND_UNUSED 0x01
101
102 /*
103 * IPCV2 descriptor status values.
104 */
105 #define BD_IPCV2_END_OF_FRAME 0x40
106
107 #define IPCV2_MAX_NODES 50
108 /*
109 * Error bit set in the CCB status field by the SDMA,
110 * in setbd routine, in case of a transfer error
111 */
112 #define DATA_ERROR 0x10000000
113
114 /*
115 * Buffer descriptor commands.
116 */
117 #define C0_ADDR 0x01
118 #define C0_LOAD 0x02
119 #define C0_DUMP 0x03
120 #define C0_SETCTX 0x07
121 #define C0_GETCTX 0x03
122 #define C0_SETDM 0x01
123 #define C0_SETPM 0x04
124 #define C0_GETDM 0x02
125 #define C0_GETPM 0x08
126 /*
127 * Change endianness indicator in the BD command field
128 */
129 #define CHANGE_ENDIANNESS 0x80
130
131 /*
132 * p_2_p watermark_level description
133 * Bits Name Description
134 * 0-7 Lower WML Lower watermark level
135 * 8 PS 1: Pad Swallowing
136 * 0: No Pad Swallowing
137 * 9 PA 1: Pad Adding
138 * 0: No Pad Adding
139 * 10 SPDIF If this bit is set both source
140 * and destination are on SPBA
141 * 11 Source Bit(SP) 1: Source on SPBA
142 * 0: Source on AIPS
143 * 12 Destination Bit(DP) 1: Destination on SPBA
144 * 0: Destination on AIPS
145 * 13-15 --------- MUST BE 0
146 * 16-23 Higher WML HWML
147 * 24-27 N Total number of samples after
148 * which Pad adding/Swallowing
149 * must be done. It must be odd.
150 * 28 Lower WML Event(LWE) SDMA events reg to check for
151 * LWML event mask
152 * 0: LWE in EVENTS register
153 * 1: LWE in EVENTS2 register
154 * 29 Higher WML Event(HWE) SDMA events reg to check for
155 * HWML event mask
156 * 0: HWE in EVENTS register
157 * 1: HWE in EVENTS2 register
158 * 30 --------- MUST BE 0
159 * 31 CONT 1: Amount of samples to be
160 * transferred is unknown and
161 * script will keep on
162 * transferring samples as long as
163 * both events are detected and
164 * script must be manually stopped
165 * by the application
166 * 0: The amount of samples to be
167 * transferred is equal to the
168 * count field of mode word
169 */
170 #define SDMA_WATERMARK_LEVEL_LWML 0xFF
171 #define SDMA_WATERMARK_LEVEL_PS BIT(8)
172 #define SDMA_WATERMARK_LEVEL_PA BIT(9)
173 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
174 #define SDMA_WATERMARK_LEVEL_SP BIT(11)
175 #define SDMA_WATERMARK_LEVEL_DP BIT(12)
176 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
177 #define SDMA_WATERMARK_LEVEL_LWE BIT(28)
178 #define SDMA_WATERMARK_LEVEL_HWE BIT(29)
179 #define SDMA_WATERMARK_LEVEL_CONT BIT(31)
180
181 /*
182 * Mode/Count of data node descriptors - IPCv2
183 */
184 struct sdma_mode_count {
185 u32 count : 16; /* size of the buffer pointed by this BD */
186 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
187 u32 command : 8; /* command mostly used for channel 0 */
188 };
189
190 /*
191 * Buffer descriptor
192 */
193 struct sdma_buffer_descriptor {
194 struct sdma_mode_count mode;
195 u32 buffer_addr; /* address of the buffer described */
196 u32 ext_buffer_addr; /* extended buffer address */
197 } __attribute__ ((packed));
198
199 /**
200 * struct sdma_channel_control - Channel control Block
201 *
202 * @current_bd_ptr current buffer descriptor processed
203 * @base_bd_ptr first element of buffer descriptor array
204 * @unused padding. The SDMA engine expects an array of 128 byte
205 * control blocks
206 */
207 struct sdma_channel_control {
208 u32 current_bd_ptr;
209 u32 base_bd_ptr;
210 u32 unused[2];
211 } __attribute__ ((packed));
212
213 /**
214 * struct sdma_state_registers - SDMA context for a channel
215 *
216 * @pc: program counter
217 * @t: test bit: status of arithmetic & test instruction
218 * @rpc: return program counter
219 * @sf: source fault while loading data
220 * @spc: loop start program counter
221 * @df: destination fault while storing data
222 * @epc: loop end program counter
223 * @lm: loop mode
224 */
225 struct sdma_state_registers {
226 u32 pc :14;
227 u32 unused1: 1;
228 u32 t : 1;
229 u32 rpc :14;
230 u32 unused0: 1;
231 u32 sf : 1;
232 u32 spc :14;
233 u32 unused2: 1;
234 u32 df : 1;
235 u32 epc :14;
236 u32 lm : 2;
237 } __attribute__ ((packed));
238
239 /**
240 * struct sdma_context_data - sdma context specific to a channel
241 *
242 * @channel_state: channel state bits
243 * @gReg: general registers
244 * @mda: burst dma destination address register
245 * @msa: burst dma source address register
246 * @ms: burst dma status register
247 * @md: burst dma data register
248 * @pda: peripheral dma destination address register
249 * @psa: peripheral dma source address register
250 * @ps: peripheral dma status register
251 * @pd: peripheral dma data register
252 * @ca: CRC polynomial register
253 * @cs: CRC accumulator register
254 * @dda: dedicated core destination address register
255 * @dsa: dedicated core source address register
256 * @ds: dedicated core status register
257 * @dd: dedicated core data register
258 */
259 struct sdma_context_data {
260 struct sdma_state_registers channel_state;
261 u32 gReg[8];
262 u32 mda;
263 u32 msa;
264 u32 ms;
265 u32 md;
266 u32 pda;
267 u32 psa;
268 u32 ps;
269 u32 pd;
270 u32 ca;
271 u32 cs;
272 u32 dda;
273 u32 dsa;
274 u32 ds;
275 u32 dd;
276 u32 scratch0;
277 u32 scratch1;
278 u32 scratch2;
279 u32 scratch3;
280 u32 scratch4;
281 u32 scratch5;
282 u32 scratch6;
283 u32 scratch7;
284 } __attribute__ ((packed));
285
286 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
287
288 struct sdma_engine;
289
290 /**
291 * struct sdma_channel - housekeeping for a SDMA channel
292 *
293 * @sdma pointer to the SDMA engine for this channel
294 * @channel the channel number, matches dmaengine chan_id + 1
295 * @direction transfer type. Needed for setting SDMA script
296 * @peripheral_type Peripheral type. Needed for setting SDMA script
297 * @event_id0 aka dma request line
298 * @event_id1 for channels that use 2 events
299 * @word_size peripheral access size
300 * @buf_tail ID of the buffer that was processed
301 * @num_bd max NUM_BD. number of descriptors currently handling
302 */
303 struct sdma_channel {
304 struct sdma_engine *sdma;
305 unsigned int channel;
306 enum dma_transfer_direction direction;
307 enum sdma_peripheral_type peripheral_type;
308 unsigned int event_id0;
309 unsigned int event_id1;
310 enum dma_slave_buswidth word_size;
311 unsigned int buf_tail;
312 unsigned int num_bd;
313 unsigned int period_len;
314 struct sdma_buffer_descriptor *bd;
315 dma_addr_t bd_phys;
316 unsigned int pc_from_device, pc_to_device;
317 unsigned int device_to_device;
318 unsigned long flags;
319 dma_addr_t per_address, per_address2;
320 unsigned long event_mask[2];
321 unsigned long watermark_level;
322 u32 shp_addr, per_addr;
323 struct dma_chan chan;
324 spinlock_t lock;
325 struct dma_async_tx_descriptor desc;
326 enum dma_status status;
327 unsigned int chn_count;
328 unsigned int chn_real_count;
329 struct tasklet_struct tasklet;
330 struct imx_dma_data data;
331 };
332
333 #define IMX_DMA_SG_LOOP BIT(0)
334
335 #define MAX_DMA_CHANNELS 32
336 #define MXC_SDMA_DEFAULT_PRIORITY 1
337 #define MXC_SDMA_MIN_PRIORITY 1
338 #define MXC_SDMA_MAX_PRIORITY 7
339
340 #define SDMA_FIRMWARE_MAGIC 0x414d4453
341
342 /**
343 * struct sdma_firmware_header - Layout of the firmware image
344 *
345 * @magic "SDMA"
346 * @version_major increased whenever layout of struct sdma_script_start_addrs
347 * changes.
348 * @version_minor firmware minor version (for binary compatible changes)
349 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
350 * @num_script_addrs Number of script addresses in this image
351 * @ram_code_start offset of SDMA ram image in this firmware image
352 * @ram_code_size size of SDMA ram image
353 * @script_addrs Stores the start address of the SDMA scripts
354 * (in SDMA memory space)
355 */
356 struct sdma_firmware_header {
357 u32 magic;
358 u32 version_major;
359 u32 version_minor;
360 u32 script_addrs_start;
361 u32 num_script_addrs;
362 u32 ram_code_start;
363 u32 ram_code_size;
364 };
365
366 struct sdma_driver_data {
367 int chnenbl0;
368 int num_events;
369 struct sdma_script_start_addrs *script_addrs;
370 };
371
372 struct sdma_engine {
373 struct device *dev;
374 struct device_dma_parameters dma_parms;
375 struct sdma_channel channel[MAX_DMA_CHANNELS];
376 struct sdma_channel_control *channel_control;
377 void __iomem *regs;
378 struct sdma_context_data *context;
379 dma_addr_t context_phys;
380 struct dma_device dma_device;
381 struct clk *clk_ipg;
382 struct clk *clk_ahb;
383 spinlock_t channel_0_lock;
384 u32 script_number;
385 struct sdma_script_start_addrs *script_addrs;
386 const struct sdma_driver_data *drvdata;
387 u32 spba_start_addr;
388 u32 spba_end_addr;
389 unsigned int irq;
390 };
391
392 static struct sdma_driver_data sdma_imx31 = {
393 .chnenbl0 = SDMA_CHNENBL0_IMX31,
394 .num_events = 32,
395 };
396
397 static struct sdma_script_start_addrs sdma_script_imx25 = {
398 .ap_2_ap_addr = 729,
399 .uart_2_mcu_addr = 904,
400 .per_2_app_addr = 1255,
401 .mcu_2_app_addr = 834,
402 .uartsh_2_mcu_addr = 1120,
403 .per_2_shp_addr = 1329,
404 .mcu_2_shp_addr = 1048,
405 .ata_2_mcu_addr = 1560,
406 .mcu_2_ata_addr = 1479,
407 .app_2_per_addr = 1189,
408 .app_2_mcu_addr = 770,
409 .shp_2_per_addr = 1407,
410 .shp_2_mcu_addr = 979,
411 };
412
413 static struct sdma_driver_data sdma_imx25 = {
414 .chnenbl0 = SDMA_CHNENBL0_IMX35,
415 .num_events = 48,
416 .script_addrs = &sdma_script_imx25,
417 };
418
419 static struct sdma_driver_data sdma_imx35 = {
420 .chnenbl0 = SDMA_CHNENBL0_IMX35,
421 .num_events = 48,
422 };
423
424 static struct sdma_script_start_addrs sdma_script_imx51 = {
425 .ap_2_ap_addr = 642,
426 .uart_2_mcu_addr = 817,
427 .mcu_2_app_addr = 747,
428 .mcu_2_shp_addr = 961,
429 .ata_2_mcu_addr = 1473,
430 .mcu_2_ata_addr = 1392,
431 .app_2_per_addr = 1033,
432 .app_2_mcu_addr = 683,
433 .shp_2_per_addr = 1251,
434 .shp_2_mcu_addr = 892,
435 };
436
437 static struct sdma_driver_data sdma_imx51 = {
438 .chnenbl0 = SDMA_CHNENBL0_IMX35,
439 .num_events = 48,
440 .script_addrs = &sdma_script_imx51,
441 };
442
443 static struct sdma_script_start_addrs sdma_script_imx53 = {
444 .ap_2_ap_addr = 642,
445 .app_2_mcu_addr = 683,
446 .mcu_2_app_addr = 747,
447 .uart_2_mcu_addr = 817,
448 .shp_2_mcu_addr = 891,
449 .mcu_2_shp_addr = 960,
450 .uartsh_2_mcu_addr = 1032,
451 .spdif_2_mcu_addr = 1100,
452 .mcu_2_spdif_addr = 1134,
453 .firi_2_mcu_addr = 1193,
454 .mcu_2_firi_addr = 1290,
455 };
456
457 static struct sdma_driver_data sdma_imx53 = {
458 .chnenbl0 = SDMA_CHNENBL0_IMX35,
459 .num_events = 48,
460 .script_addrs = &sdma_script_imx53,
461 };
462
463 static struct sdma_script_start_addrs sdma_script_imx6q = {
464 .ap_2_ap_addr = 642,
465 .uart_2_mcu_addr = 817,
466 .mcu_2_app_addr = 747,
467 .per_2_per_addr = 6331,
468 .uartsh_2_mcu_addr = 1032,
469 .mcu_2_shp_addr = 960,
470 .app_2_mcu_addr = 683,
471 .shp_2_mcu_addr = 891,
472 .spdif_2_mcu_addr = 1100,
473 .mcu_2_spdif_addr = 1134,
474 };
475
476 static struct sdma_driver_data sdma_imx6q = {
477 .chnenbl0 = SDMA_CHNENBL0_IMX35,
478 .num_events = 48,
479 .script_addrs = &sdma_script_imx6q,
480 };
481
482 static struct sdma_script_start_addrs sdma_script_imx7d = {
483 .ap_2_ap_addr = 644,
484 .uart_2_mcu_addr = 819,
485 .mcu_2_app_addr = 749,
486 .uartsh_2_mcu_addr = 1034,
487 .mcu_2_shp_addr = 962,
488 .app_2_mcu_addr = 685,
489 .shp_2_mcu_addr = 893,
490 .spdif_2_mcu_addr = 1102,
491 .mcu_2_spdif_addr = 1136,
492 };
493
494 static struct sdma_driver_data sdma_imx7d = {
495 .chnenbl0 = SDMA_CHNENBL0_IMX35,
496 .num_events = 48,
497 .script_addrs = &sdma_script_imx7d,
498 };
499
500 static const struct platform_device_id sdma_devtypes[] = {
501 {
502 .name = "imx25-sdma",
503 .driver_data = (unsigned long)&sdma_imx25,
504 }, {
505 .name = "imx31-sdma",
506 .driver_data = (unsigned long)&sdma_imx31,
507 }, {
508 .name = "imx35-sdma",
509 .driver_data = (unsigned long)&sdma_imx35,
510 }, {
511 .name = "imx51-sdma",
512 .driver_data = (unsigned long)&sdma_imx51,
513 }, {
514 .name = "imx53-sdma",
515 .driver_data = (unsigned long)&sdma_imx53,
516 }, {
517 .name = "imx6q-sdma",
518 .driver_data = (unsigned long)&sdma_imx6q,
519 }, {
520 .name = "imx7d-sdma",
521 .driver_data = (unsigned long)&sdma_imx7d,
522 }, {
523 /* sentinel */
524 }
525 };
526 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
527
528 static const struct of_device_id sdma_dt_ids[] = {
529 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
530 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
531 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
532 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
533 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
534 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
535 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
536 { /* sentinel */ }
537 };
538 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
539
540 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
541 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
542 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
543 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
544
545 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
546 {
547 u32 chnenbl0 = sdma->drvdata->chnenbl0;
548 return chnenbl0 + event * 4;
549 }
550
551 static int sdma_config_ownership(struct sdma_channel *sdmac,
552 bool event_override, bool mcu_override, bool dsp_override)
553 {
554 struct sdma_engine *sdma = sdmac->sdma;
555 int channel = sdmac->channel;
556 unsigned long evt, mcu, dsp;
557
558 if (event_override && mcu_override && dsp_override)
559 return -EINVAL;
560
561 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
562 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
563 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
564
565 if (dsp_override)
566 __clear_bit(channel, &dsp);
567 else
568 __set_bit(channel, &dsp);
569
570 if (event_override)
571 __clear_bit(channel, &evt);
572 else
573 __set_bit(channel, &evt);
574
575 if (mcu_override)
576 __clear_bit(channel, &mcu);
577 else
578 __set_bit(channel, &mcu);
579
580 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
581 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
582 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
583
584 return 0;
585 }
586
587 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
588 {
589 writel(BIT(channel), sdma->regs + SDMA_H_START);
590 }
591
592 /*
593 * sdma_run_channel0 - run a channel and wait till it's done
594 */
595 static int sdma_run_channel0(struct sdma_engine *sdma)
596 {
597 int ret;
598 u32 reg;
599
600 sdma_enable_channel(sdma, 0);
601
602 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
603 reg, !(reg & 1), 1, 500);
604 if (ret)
605 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
606
607 /* Set bits of CONFIG register with dynamic context switching */
608 if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
609 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
610
611 return ret;
612 }
613
614 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
615 u32 address)
616 {
617 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
618 void *buf_virt;
619 dma_addr_t buf_phys;
620 int ret;
621 unsigned long flags;
622
623 buf_virt = dma_alloc_coherent(NULL,
624 size,
625 &buf_phys, GFP_KERNEL);
626 if (!buf_virt) {
627 return -ENOMEM;
628 }
629
630 spin_lock_irqsave(&sdma->channel_0_lock, flags);
631
632 bd0->mode.command = C0_SETPM;
633 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
634 bd0->mode.count = size / 2;
635 bd0->buffer_addr = buf_phys;
636 bd0->ext_buffer_addr = address;
637
638 memcpy(buf_virt, buf, size);
639
640 ret = sdma_run_channel0(sdma);
641
642 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
643
644 dma_free_coherent(NULL, size, buf_virt, buf_phys);
645
646 return ret;
647 }
648
649 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
650 {
651 struct sdma_engine *sdma = sdmac->sdma;
652 int channel = sdmac->channel;
653 unsigned long val;
654 u32 chnenbl = chnenbl_ofs(sdma, event);
655
656 val = readl_relaxed(sdma->regs + chnenbl);
657 __set_bit(channel, &val);
658 writel_relaxed(val, sdma->regs + chnenbl);
659 }
660
661 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
662 {
663 struct sdma_engine *sdma = sdmac->sdma;
664 int channel = sdmac->channel;
665 u32 chnenbl = chnenbl_ofs(sdma, event);
666 unsigned long val;
667
668 val = readl_relaxed(sdma->regs + chnenbl);
669 __clear_bit(channel, &val);
670 writel_relaxed(val, sdma->regs + chnenbl);
671 }
672
673 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
674 {
675 if (sdmac->desc.callback)
676 sdmac->desc.callback(sdmac->desc.callback_param);
677 }
678
679 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
680 {
681 struct sdma_buffer_descriptor *bd;
682
683 /*
684 * loop mode. Iterate over descriptors, re-setup them and
685 * call callback function.
686 */
687 while (1) {
688 bd = &sdmac->bd[sdmac->buf_tail];
689
690 if (bd->mode.status & BD_DONE)
691 break;
692
693 if (bd->mode.status & BD_RROR)
694 sdmac->status = DMA_ERROR;
695
696 bd->mode.status |= BD_DONE;
697 sdmac->buf_tail++;
698 sdmac->buf_tail %= sdmac->num_bd;
699 }
700 }
701
702 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
703 {
704 struct sdma_buffer_descriptor *bd;
705 int i, error = 0;
706
707 sdmac->chn_real_count = 0;
708 /*
709 * non loop mode. Iterate over all descriptors, collect
710 * errors and call callback function
711 */
712 for (i = 0; i < sdmac->num_bd; i++) {
713 bd = &sdmac->bd[i];
714
715 if (bd->mode.status & (BD_DONE | BD_RROR))
716 error = -EIO;
717 sdmac->chn_real_count += bd->mode.count;
718 }
719
720 if (error)
721 sdmac->status = DMA_ERROR;
722 else
723 sdmac->status = DMA_COMPLETE;
724
725 dma_cookie_complete(&sdmac->desc);
726 if (sdmac->desc.callback)
727 sdmac->desc.callback(sdmac->desc.callback_param);
728 }
729
730 static void sdma_tasklet(unsigned long data)
731 {
732 struct sdma_channel *sdmac = (struct sdma_channel *) data;
733
734 if (sdmac->flags & IMX_DMA_SG_LOOP)
735 sdma_handle_channel_loop(sdmac);
736 else
737 mxc_sdma_handle_channel_normal(sdmac);
738 }
739
740 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
741 {
742 struct sdma_engine *sdma = dev_id;
743 unsigned long stat;
744
745 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
746 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
747 /* channel 0 is special and not handled here, see run_channel0() */
748 stat &= ~1;
749
750 while (stat) {
751 int channel = fls(stat) - 1;
752 struct sdma_channel *sdmac = &sdma->channel[channel];
753
754 if (sdmac->flags & IMX_DMA_SG_LOOP)
755 sdma_update_channel_loop(sdmac);
756
757 tasklet_schedule(&sdmac->tasklet);
758
759 __clear_bit(channel, &stat);
760 }
761
762 return IRQ_HANDLED;
763 }
764
765 /*
766 * sets the pc of SDMA script according to the peripheral type
767 */
768 static void sdma_get_pc(struct sdma_channel *sdmac,
769 enum sdma_peripheral_type peripheral_type)
770 {
771 struct sdma_engine *sdma = sdmac->sdma;
772 int per_2_emi = 0, emi_2_per = 0;
773 /*
774 * These are needed once we start to support transfers between
775 * two peripherals or memory-to-memory transfers
776 */
777 int per_2_per = 0;
778
779 sdmac->pc_from_device = 0;
780 sdmac->pc_to_device = 0;
781 sdmac->device_to_device = 0;
782
783 switch (peripheral_type) {
784 case IMX_DMATYPE_MEMORY:
785 break;
786 case IMX_DMATYPE_DSP:
787 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
788 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
789 break;
790 case IMX_DMATYPE_FIRI:
791 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
792 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
793 break;
794 case IMX_DMATYPE_UART:
795 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
796 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
797 break;
798 case IMX_DMATYPE_UART_SP:
799 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
800 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
801 break;
802 case IMX_DMATYPE_ATA:
803 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
804 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
805 break;
806 case IMX_DMATYPE_CSPI:
807 case IMX_DMATYPE_EXT:
808 case IMX_DMATYPE_SSI:
809 case IMX_DMATYPE_SAI:
810 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
811 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
812 break;
813 case IMX_DMATYPE_SSI_DUAL:
814 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
815 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
816 break;
817 case IMX_DMATYPE_SSI_SP:
818 case IMX_DMATYPE_MMC:
819 case IMX_DMATYPE_SDHC:
820 case IMX_DMATYPE_CSPI_SP:
821 case IMX_DMATYPE_ESAI:
822 case IMX_DMATYPE_MSHC_SP:
823 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
824 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
825 break;
826 case IMX_DMATYPE_ASRC:
827 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
828 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
829 per_2_per = sdma->script_addrs->per_2_per_addr;
830 break;
831 case IMX_DMATYPE_ASRC_SP:
832 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
833 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
834 per_2_per = sdma->script_addrs->per_2_per_addr;
835 break;
836 case IMX_DMATYPE_MSHC:
837 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
838 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
839 break;
840 case IMX_DMATYPE_CCM:
841 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
842 break;
843 case IMX_DMATYPE_SPDIF:
844 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
845 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
846 break;
847 case IMX_DMATYPE_IPU_MEMORY:
848 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
849 break;
850 default:
851 break;
852 }
853
854 sdmac->pc_from_device = per_2_emi;
855 sdmac->pc_to_device = emi_2_per;
856 sdmac->device_to_device = per_2_per;
857 }
858
859 static int sdma_load_context(struct sdma_channel *sdmac)
860 {
861 struct sdma_engine *sdma = sdmac->sdma;
862 int channel = sdmac->channel;
863 int load_address;
864 struct sdma_context_data *context = sdma->context;
865 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
866 int ret;
867 unsigned long flags;
868
869 if (sdmac->direction == DMA_DEV_TO_MEM)
870 load_address = sdmac->pc_from_device;
871 else if (sdmac->direction == DMA_DEV_TO_DEV)
872 load_address = sdmac->device_to_device;
873 else
874 load_address = sdmac->pc_to_device;
875
876 if (load_address < 0)
877 return load_address;
878
879 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
880 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
881 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
882 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
883 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
884 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
885
886 spin_lock_irqsave(&sdma->channel_0_lock, flags);
887
888 memset(context, 0, sizeof(*context));
889 context->channel_state.pc = load_address;
890
891 /* Send by context the event mask,base address for peripheral
892 * and watermark level
893 */
894 context->gReg[0] = sdmac->event_mask[1];
895 context->gReg[1] = sdmac->event_mask[0];
896 context->gReg[2] = sdmac->per_addr;
897 context->gReg[6] = sdmac->shp_addr;
898 context->gReg[7] = sdmac->watermark_level;
899
900 bd0->mode.command = C0_SETDM;
901 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
902 bd0->mode.count = sizeof(*context) / 4;
903 bd0->buffer_addr = sdma->context_phys;
904 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
905 ret = sdma_run_channel0(sdma);
906
907 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
908
909 return ret;
910 }
911
912 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
913 {
914 return container_of(chan, struct sdma_channel, chan);
915 }
916
917 static int sdma_disable_channel(struct dma_chan *chan)
918 {
919 struct sdma_channel *sdmac = to_sdma_chan(chan);
920 struct sdma_engine *sdma = sdmac->sdma;
921 int channel = sdmac->channel;
922
923 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
924 sdmac->status = DMA_ERROR;
925
926 return 0;
927 }
928
929 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
930 {
931 struct sdma_engine *sdma = sdmac->sdma;
932
933 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
934 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
935
936 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
937 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
938
939 if (sdmac->event_id0 > 31)
940 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
941
942 if (sdmac->event_id1 > 31)
943 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
944
945 /*
946 * If LWML(src_maxburst) > HWML(dst_maxburst), we need
947 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
948 * r0(event_mask[1]) and r1(event_mask[0]).
949 */
950 if (lwml > hwml) {
951 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
952 SDMA_WATERMARK_LEVEL_HWML);
953 sdmac->watermark_level |= hwml;
954 sdmac->watermark_level |= lwml << 16;
955 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
956 }
957
958 if (sdmac->per_address2 >= sdma->spba_start_addr &&
959 sdmac->per_address2 <= sdma->spba_end_addr)
960 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
961
962 if (sdmac->per_address >= sdma->spba_start_addr &&
963 sdmac->per_address <= sdma->spba_end_addr)
964 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
965
966 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
967 }
968
969 static int sdma_config_channel(struct dma_chan *chan)
970 {
971 struct sdma_channel *sdmac = to_sdma_chan(chan);
972 int ret;
973
974 sdma_disable_channel(chan);
975
976 sdmac->event_mask[0] = 0;
977 sdmac->event_mask[1] = 0;
978 sdmac->shp_addr = 0;
979 sdmac->per_addr = 0;
980
981 if (sdmac->event_id0) {
982 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
983 return -EINVAL;
984 sdma_event_enable(sdmac, sdmac->event_id0);
985 }
986
987 if (sdmac->event_id1) {
988 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
989 return -EINVAL;
990 sdma_event_enable(sdmac, sdmac->event_id1);
991 }
992
993 switch (sdmac->peripheral_type) {
994 case IMX_DMATYPE_DSP:
995 sdma_config_ownership(sdmac, false, true, true);
996 break;
997 case IMX_DMATYPE_MEMORY:
998 sdma_config_ownership(sdmac, false, true, false);
999 break;
1000 default:
1001 sdma_config_ownership(sdmac, true, true, false);
1002 break;
1003 }
1004
1005 sdma_get_pc(sdmac, sdmac->peripheral_type);
1006
1007 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1008 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1009 /* Handle multiple event channels differently */
1010 if (sdmac->event_id1) {
1011 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1012 sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1013 sdma_set_watermarklevel_for_p2p(sdmac);
1014 } else
1015 __set_bit(sdmac->event_id0, sdmac->event_mask);
1016
1017 /* Address */
1018 sdmac->shp_addr = sdmac->per_address;
1019 sdmac->per_addr = sdmac->per_address2;
1020 } else {
1021 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1022 }
1023
1024 ret = sdma_load_context(sdmac);
1025
1026 return ret;
1027 }
1028
1029 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1030 unsigned int priority)
1031 {
1032 struct sdma_engine *sdma = sdmac->sdma;
1033 int channel = sdmac->channel;
1034
1035 if (priority < MXC_SDMA_MIN_PRIORITY
1036 || priority > MXC_SDMA_MAX_PRIORITY) {
1037 return -EINVAL;
1038 }
1039
1040 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1041
1042 return 0;
1043 }
1044
1045 static int sdma_request_channel(struct sdma_channel *sdmac)
1046 {
1047 struct sdma_engine *sdma = sdmac->sdma;
1048 int channel = sdmac->channel;
1049 int ret = -EBUSY;
1050
1051 sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
1052 GFP_KERNEL);
1053 if (!sdmac->bd) {
1054 ret = -ENOMEM;
1055 goto out;
1056 }
1057
1058 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
1059 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1060
1061 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
1062 return 0;
1063 out:
1064
1065 return ret;
1066 }
1067
1068 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
1069 {
1070 unsigned long flags;
1071 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
1072 dma_cookie_t cookie;
1073
1074 spin_lock_irqsave(&sdmac->lock, flags);
1075
1076 cookie = dma_cookie_assign(tx);
1077
1078 spin_unlock_irqrestore(&sdmac->lock, flags);
1079
1080 return cookie;
1081 }
1082
1083 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1084 {
1085 struct sdma_channel *sdmac = to_sdma_chan(chan);
1086 struct imx_dma_data *data = chan->private;
1087 int prio, ret;
1088
1089 if (!data)
1090 return -EINVAL;
1091
1092 switch (data->priority) {
1093 case DMA_PRIO_HIGH:
1094 prio = 3;
1095 break;
1096 case DMA_PRIO_MEDIUM:
1097 prio = 2;
1098 break;
1099 case DMA_PRIO_LOW:
1100 default:
1101 prio = 1;
1102 break;
1103 }
1104
1105 sdmac->peripheral_type = data->peripheral_type;
1106 sdmac->event_id0 = data->dma_request;
1107 sdmac->event_id1 = data->dma_request2;
1108
1109 ret = clk_enable(sdmac->sdma->clk_ipg);
1110 if (ret)
1111 return ret;
1112 ret = clk_enable(sdmac->sdma->clk_ahb);
1113 if (ret)
1114 goto disable_clk_ipg;
1115
1116 ret = sdma_request_channel(sdmac);
1117 if (ret)
1118 goto disable_clk_ahb;
1119
1120 ret = sdma_set_channel_priority(sdmac, prio);
1121 if (ret)
1122 goto disable_clk_ahb;
1123
1124 dma_async_tx_descriptor_init(&sdmac->desc, chan);
1125 sdmac->desc.tx_submit = sdma_tx_submit;
1126 /* txd.flags will be overwritten in prep funcs */
1127 sdmac->desc.flags = DMA_CTRL_ACK;
1128
1129 return 0;
1130
1131 disable_clk_ahb:
1132 clk_disable(sdmac->sdma->clk_ahb);
1133 disable_clk_ipg:
1134 clk_disable(sdmac->sdma->clk_ipg);
1135 return ret;
1136 }
1137
1138 static void sdma_free_chan_resources(struct dma_chan *chan)
1139 {
1140 struct sdma_channel *sdmac = to_sdma_chan(chan);
1141 struct sdma_engine *sdma = sdmac->sdma;
1142
1143 sdma_disable_channel(chan);
1144
1145 if (sdmac->event_id0)
1146 sdma_event_disable(sdmac, sdmac->event_id0);
1147 if (sdmac->event_id1)
1148 sdma_event_disable(sdmac, sdmac->event_id1);
1149
1150 sdmac->event_id0 = 0;
1151 sdmac->event_id1 = 0;
1152
1153 sdma_set_channel_priority(sdmac, 0);
1154
1155 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1156
1157 clk_disable(sdma->clk_ipg);
1158 clk_disable(sdma->clk_ahb);
1159 }
1160
1161 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1162 struct dma_chan *chan, struct scatterlist *sgl,
1163 unsigned int sg_len, enum dma_transfer_direction direction,
1164 unsigned long flags, void *context)
1165 {
1166 struct sdma_channel *sdmac = to_sdma_chan(chan);
1167 struct sdma_engine *sdma = sdmac->sdma;
1168 int ret, i, count;
1169 int channel = sdmac->channel;
1170 struct scatterlist *sg;
1171
1172 if (sdmac->status == DMA_IN_PROGRESS)
1173 return NULL;
1174 sdmac->status = DMA_IN_PROGRESS;
1175
1176 sdmac->flags = 0;
1177
1178 sdmac->buf_tail = 0;
1179
1180 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1181 sg_len, channel);
1182
1183 sdmac->direction = direction;
1184 ret = sdma_load_context(sdmac);
1185 if (ret)
1186 goto err_out;
1187
1188 if (sg_len > NUM_BD) {
1189 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1190 channel, sg_len, NUM_BD);
1191 ret = -EINVAL;
1192 goto err_out;
1193 }
1194
1195 sdmac->chn_count = 0;
1196 for_each_sg(sgl, sg, sg_len, i) {
1197 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1198 int param;
1199
1200 bd->buffer_addr = sg->dma_address;
1201
1202 count = sg_dma_len(sg);
1203
1204 if (count > 0xffff) {
1205 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1206 channel, count, 0xffff);
1207 ret = -EINVAL;
1208 goto err_out;
1209 }
1210
1211 bd->mode.count = count;
1212 sdmac->chn_count += count;
1213
1214 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1215 ret = -EINVAL;
1216 goto err_out;
1217 }
1218
1219 switch (sdmac->word_size) {
1220 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1221 bd->mode.command = 0;
1222 if (count & 3 || sg->dma_address & 3)
1223 return NULL;
1224 break;
1225 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1226 bd->mode.command = 2;
1227 if (count & 1 || sg->dma_address & 1)
1228 return NULL;
1229 break;
1230 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1231 bd->mode.command = 1;
1232 break;
1233 default:
1234 return NULL;
1235 }
1236
1237 param = BD_DONE | BD_EXTD | BD_CONT;
1238
1239 if (i + 1 == sg_len) {
1240 param |= BD_INTR;
1241 param |= BD_LAST;
1242 param &= ~BD_CONT;
1243 }
1244
1245 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1246 i, count, (u64)sg->dma_address,
1247 param & BD_WRAP ? "wrap" : "",
1248 param & BD_INTR ? " intr" : "");
1249
1250 bd->mode.status = param;
1251 }
1252
1253 sdmac->num_bd = sg_len;
1254 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1255
1256 return &sdmac->desc;
1257 err_out:
1258 sdmac->status = DMA_ERROR;
1259 return NULL;
1260 }
1261
1262 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1263 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1264 size_t period_len, enum dma_transfer_direction direction,
1265 unsigned long flags)
1266 {
1267 struct sdma_channel *sdmac = to_sdma_chan(chan);
1268 struct sdma_engine *sdma = sdmac->sdma;
1269 int num_periods = buf_len / period_len;
1270 int channel = sdmac->channel;
1271 int ret, i = 0, buf = 0;
1272
1273 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1274
1275 if (sdmac->status == DMA_IN_PROGRESS)
1276 return NULL;
1277
1278 sdmac->status = DMA_IN_PROGRESS;
1279
1280 sdmac->buf_tail = 0;
1281 sdmac->period_len = period_len;
1282
1283 sdmac->flags |= IMX_DMA_SG_LOOP;
1284 sdmac->direction = direction;
1285 ret = sdma_load_context(sdmac);
1286 if (ret)
1287 goto err_out;
1288
1289 if (num_periods > NUM_BD) {
1290 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1291 channel, num_periods, NUM_BD);
1292 goto err_out;
1293 }
1294
1295 if (period_len > 0xffff) {
1296 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1297 channel, period_len, 0xffff);
1298 goto err_out;
1299 }
1300
1301 while (buf < buf_len) {
1302 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1303 int param;
1304
1305 bd->buffer_addr = dma_addr;
1306
1307 bd->mode.count = period_len;
1308
1309 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1310 goto err_out;
1311 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1312 bd->mode.command = 0;
1313 else
1314 bd->mode.command = sdmac->word_size;
1315
1316 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1317 if (i + 1 == num_periods)
1318 param |= BD_WRAP;
1319
1320 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1321 i, period_len, (u64)dma_addr,
1322 param & BD_WRAP ? "wrap" : "",
1323 param & BD_INTR ? " intr" : "");
1324
1325 bd->mode.status = param;
1326
1327 dma_addr += period_len;
1328 buf += period_len;
1329
1330 i++;
1331 }
1332
1333 sdmac->num_bd = num_periods;
1334 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1335
1336 return &sdmac->desc;
1337 err_out:
1338 sdmac->status = DMA_ERROR;
1339 return NULL;
1340 }
1341
1342 static int sdma_config(struct dma_chan *chan,
1343 struct dma_slave_config *dmaengine_cfg)
1344 {
1345 struct sdma_channel *sdmac = to_sdma_chan(chan);
1346
1347 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1348 sdmac->per_address = dmaengine_cfg->src_addr;
1349 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1350 dmaengine_cfg->src_addr_width;
1351 sdmac->word_size = dmaengine_cfg->src_addr_width;
1352 } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1353 sdmac->per_address2 = dmaengine_cfg->src_addr;
1354 sdmac->per_address = dmaengine_cfg->dst_addr;
1355 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1356 SDMA_WATERMARK_LEVEL_LWML;
1357 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1358 SDMA_WATERMARK_LEVEL_HWML;
1359 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1360 } else {
1361 sdmac->per_address = dmaengine_cfg->dst_addr;
1362 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1363 dmaengine_cfg->dst_addr_width;
1364 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1365 }
1366 sdmac->direction = dmaengine_cfg->direction;
1367 return sdma_config_channel(chan);
1368 }
1369
1370 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1371 dma_cookie_t cookie,
1372 struct dma_tx_state *txstate)
1373 {
1374 struct sdma_channel *sdmac = to_sdma_chan(chan);
1375 u32 residue;
1376
1377 if (sdmac->flags & IMX_DMA_SG_LOOP)
1378 residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
1379 else
1380 residue = sdmac->chn_count - sdmac->chn_real_count;
1381
1382 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1383 residue);
1384
1385 return sdmac->status;
1386 }
1387
1388 static void sdma_issue_pending(struct dma_chan *chan)
1389 {
1390 struct sdma_channel *sdmac = to_sdma_chan(chan);
1391 struct sdma_engine *sdma = sdmac->sdma;
1392
1393 if (sdmac->status == DMA_IN_PROGRESS)
1394 sdma_enable_channel(sdma, sdmac->channel);
1395 }
1396
1397 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1398 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1399 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1400 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1401
1402 static void sdma_add_scripts(struct sdma_engine *sdma,
1403 const struct sdma_script_start_addrs *addr)
1404 {
1405 s32 *addr_arr = (u32 *)addr;
1406 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1407 int i;
1408
1409 /* use the default firmware in ROM if missing external firmware */
1410 if (!sdma->script_number)
1411 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1412
1413 for (i = 0; i < sdma->script_number; i++)
1414 if (addr_arr[i] > 0)
1415 saddr_arr[i] = addr_arr[i];
1416 }
1417
1418 static void sdma_load_firmware(const struct firmware *fw, void *context)
1419 {
1420 struct sdma_engine *sdma = context;
1421 const struct sdma_firmware_header *header;
1422 const struct sdma_script_start_addrs *addr;
1423 unsigned short *ram_code;
1424
1425 if (!fw) {
1426 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1427 /* In this case we just use the ROM firmware. */
1428 return;
1429 }
1430
1431 if (fw->size < sizeof(*header))
1432 goto err_firmware;
1433
1434 header = (struct sdma_firmware_header *)fw->data;
1435
1436 if (header->magic != SDMA_FIRMWARE_MAGIC)
1437 goto err_firmware;
1438 if (header->ram_code_start + header->ram_code_size > fw->size)
1439 goto err_firmware;
1440 switch (header->version_major) {
1441 case 1:
1442 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1443 break;
1444 case 2:
1445 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1446 break;
1447 case 3:
1448 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1449 break;
1450 case 4:
1451 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1452 break;
1453 default:
1454 dev_err(sdma->dev, "unknown firmware version\n");
1455 goto err_firmware;
1456 }
1457
1458 addr = (void *)header + header->script_addrs_start;
1459 ram_code = (void *)header + header->ram_code_start;
1460
1461 clk_enable(sdma->clk_ipg);
1462 clk_enable(sdma->clk_ahb);
1463 /* download the RAM image for SDMA */
1464 sdma_load_script(sdma, ram_code,
1465 header->ram_code_size,
1466 addr->ram_code_start_addr);
1467 clk_disable(sdma->clk_ipg);
1468 clk_disable(sdma->clk_ahb);
1469
1470 sdma_add_scripts(sdma, addr);
1471
1472 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1473 header->version_major,
1474 header->version_minor);
1475
1476 err_firmware:
1477 release_firmware(fw);
1478 }
1479
1480 #define EVENT_REMAP_CELLS 3
1481
1482 static int sdma_event_remap(struct sdma_engine *sdma)
1483 {
1484 struct device_node *np = sdma->dev->of_node;
1485 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1486 struct property *event_remap;
1487 struct regmap *gpr;
1488 char propname[] = "fsl,sdma-event-remap";
1489 u32 reg, val, shift, num_map, i;
1490 int ret = 0;
1491
1492 if (IS_ERR(np) || IS_ERR(gpr_np))
1493 goto out;
1494
1495 event_remap = of_find_property(np, propname, NULL);
1496 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1497 if (!num_map) {
1498 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1499 goto out;
1500 } else if (num_map % EVENT_REMAP_CELLS) {
1501 dev_err(sdma->dev, "the property %s must modulo %d\n",
1502 propname, EVENT_REMAP_CELLS);
1503 ret = -EINVAL;
1504 goto out;
1505 }
1506
1507 gpr = syscon_node_to_regmap(gpr_np);
1508 if (IS_ERR(gpr)) {
1509 dev_err(sdma->dev, "failed to get gpr regmap\n");
1510 ret = PTR_ERR(gpr);
1511 goto out;
1512 }
1513
1514 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1515 ret = of_property_read_u32_index(np, propname, i, &reg);
1516 if (ret) {
1517 dev_err(sdma->dev, "failed to read property %s index %d\n",
1518 propname, i);
1519 goto out;
1520 }
1521
1522 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1523 if (ret) {
1524 dev_err(sdma->dev, "failed to read property %s index %d\n",
1525 propname, i + 1);
1526 goto out;
1527 }
1528
1529 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1530 if (ret) {
1531 dev_err(sdma->dev, "failed to read property %s index %d\n",
1532 propname, i + 2);
1533 goto out;
1534 }
1535
1536 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1537 }
1538
1539 out:
1540 if (!IS_ERR(gpr_np))
1541 of_node_put(gpr_np);
1542
1543 return ret;
1544 }
1545
1546 static int sdma_get_firmware(struct sdma_engine *sdma,
1547 const char *fw_name)
1548 {
1549 int ret;
1550
1551 ret = request_firmware_nowait(THIS_MODULE,
1552 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1553 GFP_KERNEL, sdma, sdma_load_firmware);
1554
1555 return ret;
1556 }
1557
1558 static int sdma_init(struct sdma_engine *sdma)
1559 {
1560 int i, ret;
1561 dma_addr_t ccb_phys;
1562
1563 ret = clk_enable(sdma->clk_ipg);
1564 if (ret)
1565 return ret;
1566 ret = clk_enable(sdma->clk_ahb);
1567 if (ret)
1568 goto disable_clk_ipg;
1569
1570 /* Be sure SDMA has not started yet */
1571 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1572
1573 sdma->channel_control = dma_alloc_coherent(NULL,
1574 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1575 sizeof(struct sdma_context_data),
1576 &ccb_phys, GFP_KERNEL);
1577
1578 if (!sdma->channel_control) {
1579 ret = -ENOMEM;
1580 goto err_dma_alloc;
1581 }
1582
1583 sdma->context = (void *)sdma->channel_control +
1584 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1585 sdma->context_phys = ccb_phys +
1586 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1587
1588 /* Zero-out the CCB structures array just allocated */
1589 memset(sdma->channel_control, 0,
1590 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1591
1592 /* disable all channels */
1593 for (i = 0; i < sdma->drvdata->num_events; i++)
1594 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1595
1596 /* All channels have priority 0 */
1597 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1598 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1599
1600 ret = sdma_request_channel(&sdma->channel[0]);
1601 if (ret)
1602 goto err_dma_alloc;
1603
1604 sdma_config_ownership(&sdma->channel[0], false, true, false);
1605
1606 /* Set Command Channel (Channel Zero) */
1607 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1608
1609 /* Set bits of CONFIG register but with static context switching */
1610 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1611 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1612
1613 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1614
1615 /* Initializes channel's priorities */
1616 sdma_set_channel_priority(&sdma->channel[0], 7);
1617
1618 clk_disable(sdma->clk_ipg);
1619 clk_disable(sdma->clk_ahb);
1620
1621 return 0;
1622
1623 err_dma_alloc:
1624 clk_disable(sdma->clk_ahb);
1625 disable_clk_ipg:
1626 clk_disable(sdma->clk_ipg);
1627 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1628 return ret;
1629 }
1630
1631 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1632 {
1633 struct sdma_channel *sdmac = to_sdma_chan(chan);
1634 struct imx_dma_data *data = fn_param;
1635
1636 if (!imx_dma_is_general_purpose(chan))
1637 return false;
1638
1639 sdmac->data = *data;
1640 chan->private = &sdmac->data;
1641
1642 return true;
1643 }
1644
1645 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1646 struct of_dma *ofdma)
1647 {
1648 struct sdma_engine *sdma = ofdma->of_dma_data;
1649 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1650 struct imx_dma_data data;
1651
1652 if (dma_spec->args_count != 3)
1653 return NULL;
1654
1655 data.dma_request = dma_spec->args[0];
1656 data.peripheral_type = dma_spec->args[1];
1657 data.priority = dma_spec->args[2];
1658 /*
1659 * init dma_request2 to zero, which is not used by the dts.
1660 * For P2P, dma_request2 is init from dma_request_channel(),
1661 * chan->private will point to the imx_dma_data, and in
1662 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1663 * be set to sdmac->event_id1.
1664 */
1665 data.dma_request2 = 0;
1666
1667 return dma_request_channel(mask, sdma_filter_fn, &data);
1668 }
1669
1670 static int sdma_probe(struct platform_device *pdev)
1671 {
1672 const struct of_device_id *of_id =
1673 of_match_device(sdma_dt_ids, &pdev->dev);
1674 struct device_node *np = pdev->dev.of_node;
1675 struct device_node *spba_bus;
1676 const char *fw_name;
1677 int ret;
1678 int irq;
1679 struct resource *iores;
1680 struct resource spba_res;
1681 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1682 int i;
1683 struct sdma_engine *sdma;
1684 s32 *saddr_arr;
1685 const struct sdma_driver_data *drvdata = NULL;
1686
1687 if (of_id)
1688 drvdata = of_id->data;
1689 else if (pdev->id_entry)
1690 drvdata = (void *)pdev->id_entry->driver_data;
1691
1692 if (!drvdata) {
1693 dev_err(&pdev->dev, "unable to find driver data\n");
1694 return -EINVAL;
1695 }
1696
1697 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1698 if (ret)
1699 return ret;
1700
1701 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1702 if (!sdma)
1703 return -ENOMEM;
1704
1705 spin_lock_init(&sdma->channel_0_lock);
1706
1707 sdma->dev = &pdev->dev;
1708 sdma->drvdata = drvdata;
1709
1710 irq = platform_get_irq(pdev, 0);
1711 if (irq < 0)
1712 return irq;
1713
1714 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1715 sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1716 if (IS_ERR(sdma->regs))
1717 return PTR_ERR(sdma->regs);
1718
1719 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1720 if (IS_ERR(sdma->clk_ipg))
1721 return PTR_ERR(sdma->clk_ipg);
1722
1723 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1724 if (IS_ERR(sdma->clk_ahb))
1725 return PTR_ERR(sdma->clk_ahb);
1726
1727 clk_prepare(sdma->clk_ipg);
1728 clk_prepare(sdma->clk_ahb);
1729
1730 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1731 sdma);
1732 if (ret)
1733 return ret;
1734
1735 sdma->irq = irq;
1736
1737 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1738 if (!sdma->script_addrs)
1739 return -ENOMEM;
1740
1741 /* initially no scripts available */
1742 saddr_arr = (s32 *)sdma->script_addrs;
1743 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1744 saddr_arr[i] = -EINVAL;
1745
1746 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1747 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1748
1749 INIT_LIST_HEAD(&sdma->dma_device.channels);
1750 /* Initialize channel parameters */
1751 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1752 struct sdma_channel *sdmac = &sdma->channel[i];
1753
1754 sdmac->sdma = sdma;
1755 spin_lock_init(&sdmac->lock);
1756
1757 sdmac->chan.device = &sdma->dma_device;
1758 dma_cookie_init(&sdmac->chan);
1759 sdmac->channel = i;
1760
1761 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1762 (unsigned long) sdmac);
1763 /*
1764 * Add the channel to the DMAC list. Do not add channel 0 though
1765 * because we need it internally in the SDMA driver. This also means
1766 * that channel 0 in dmaengine counting matches sdma channel 1.
1767 */
1768 if (i)
1769 list_add_tail(&sdmac->chan.device_node,
1770 &sdma->dma_device.channels);
1771 }
1772
1773 ret = sdma_init(sdma);
1774 if (ret)
1775 goto err_init;
1776
1777 ret = sdma_event_remap(sdma);
1778 if (ret)
1779 goto err_init;
1780
1781 if (sdma->drvdata->script_addrs)
1782 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1783 if (pdata && pdata->script_addrs)
1784 sdma_add_scripts(sdma, pdata->script_addrs);
1785
1786 if (pdata) {
1787 ret = sdma_get_firmware(sdma, pdata->fw_name);
1788 if (ret)
1789 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1790 } else {
1791 /*
1792 * Because that device tree does not encode ROM script address,
1793 * the RAM script in firmware is mandatory for device tree
1794 * probe, otherwise it fails.
1795 */
1796 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1797 &fw_name);
1798 if (ret)
1799 dev_warn(&pdev->dev, "failed to get firmware name\n");
1800 else {
1801 ret = sdma_get_firmware(sdma, fw_name);
1802 if (ret)
1803 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1804 }
1805 }
1806
1807 sdma->dma_device.dev = &pdev->dev;
1808
1809 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1810 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1811 sdma->dma_device.device_tx_status = sdma_tx_status;
1812 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1813 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1814 sdma->dma_device.device_config = sdma_config;
1815 sdma->dma_device.device_terminate_all = sdma_disable_channel;
1816 sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1817 sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1818 sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1819 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1820 sdma->dma_device.device_issue_pending = sdma_issue_pending;
1821 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1822 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1823
1824 platform_set_drvdata(pdev, sdma);
1825
1826 ret = dma_async_device_register(&sdma->dma_device);
1827 if (ret) {
1828 dev_err(&pdev->dev, "unable to register\n");
1829 goto err_init;
1830 }
1831
1832 if (np) {
1833 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1834 if (ret) {
1835 dev_err(&pdev->dev, "failed to register controller\n");
1836 goto err_register;
1837 }
1838
1839 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
1840 ret = of_address_to_resource(spba_bus, 0, &spba_res);
1841 if (!ret) {
1842 sdma->spba_start_addr = spba_res.start;
1843 sdma->spba_end_addr = spba_res.end;
1844 }
1845 of_node_put(spba_bus);
1846 }
1847
1848 return 0;
1849
1850 err_register:
1851 dma_async_device_unregister(&sdma->dma_device);
1852 err_init:
1853 kfree(sdma->script_addrs);
1854 return ret;
1855 }
1856
1857 static int sdma_remove(struct platform_device *pdev)
1858 {
1859 struct sdma_engine *sdma = platform_get_drvdata(pdev);
1860 int i;
1861
1862 devm_free_irq(&pdev->dev, sdma->irq, sdma);
1863 dma_async_device_unregister(&sdma->dma_device);
1864 kfree(sdma->script_addrs);
1865 /* Kill the tasklet */
1866 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1867 struct sdma_channel *sdmac = &sdma->channel[i];
1868
1869 tasklet_kill(&sdmac->tasklet);
1870 }
1871
1872 platform_set_drvdata(pdev, NULL);
1873 return 0;
1874 }
1875
1876 static struct platform_driver sdma_driver = {
1877 .driver = {
1878 .name = "imx-sdma",
1879 .of_match_table = sdma_dt_ids,
1880 },
1881 .id_table = sdma_devtypes,
1882 .remove = sdma_remove,
1883 .probe = sdma_probe,
1884 };
1885
1886 module_platform_driver(sdma_driver);
1887
1888 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1889 MODULE_DESCRIPTION("i.MX SDMA driver");
1890 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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