2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2009 Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
20 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/slab.h>
27 #include <linux/pci.h>
28 #include <linux/interrupt.h>
29 #include <linux/dmaengine.h>
30 #include <linux/delay.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/workqueue.h>
33 #include <linux/prefetch.h>
34 #include <linux/i7300_idle.h>
36 #include "registers.h"
39 #include "../dmaengine.h"
41 int ioat_pending_level
= 4;
42 module_param(ioat_pending_level
, int, 0644);
43 MODULE_PARM_DESC(ioat_pending_level
,
44 "high-water mark for pushing ioat descriptors (default: 4)");
46 /* internal functions */
47 static void ioat1_cleanup(struct ioat_dma_chan
*ioat
);
48 static void ioat1_dma_start_null_desc(struct ioat_dma_chan
*ioat
);
51 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
53 * @data: interrupt data
55 static irqreturn_t
ioat_dma_do_interrupt(int irq
, void *data
)
57 struct ioatdma_device
*instance
= data
;
58 struct ioat_chan_common
*chan
;
59 unsigned long attnstatus
;
63 intrctrl
= readb(instance
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
65 if (!(intrctrl
& IOAT_INTRCTRL_MASTER_INT_EN
))
68 if (!(intrctrl
& IOAT_INTRCTRL_INT_STATUS
)) {
69 writeb(intrctrl
, instance
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
73 attnstatus
= readl(instance
->reg_base
+ IOAT_ATTNSTATUS_OFFSET
);
74 for_each_set_bit(bit
, &attnstatus
, BITS_PER_LONG
) {
75 chan
= ioat_chan_by_index(instance
, bit
);
76 if (test_bit(IOAT_RUN
, &chan
->state
))
77 tasklet_schedule(&chan
->cleanup_task
);
80 writeb(intrctrl
, instance
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
85 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
87 * @data: interrupt data
89 static irqreturn_t
ioat_dma_do_interrupt_msix(int irq
, void *data
)
91 struct ioat_chan_common
*chan
= data
;
93 if (test_bit(IOAT_RUN
, &chan
->state
))
94 tasklet_schedule(&chan
->cleanup_task
);
99 /* common channel initialization */
100 void ioat_init_channel(struct ioatdma_device
*device
, struct ioat_chan_common
*chan
, int idx
)
102 struct dma_device
*dma
= &device
->common
;
103 struct dma_chan
*c
= &chan
->common
;
104 unsigned long data
= (unsigned long) c
;
106 chan
->device
= device
;
107 chan
->reg_base
= device
->reg_base
+ (0x80 * (idx
+ 1));
108 spin_lock_init(&chan
->cleanup_lock
);
109 chan
->common
.device
= dma
;
110 dma_cookie_init(&chan
->common
);
111 list_add_tail(&chan
->common
.device_node
, &dma
->channels
);
112 device
->idx
[idx
] = chan
;
113 init_timer(&chan
->timer
);
114 chan
->timer
.function
= device
->timer_fn
;
115 chan
->timer
.data
= data
;
116 tasklet_init(&chan
->cleanup_task
, device
->cleanup_fn
, data
);
120 * ioat1_dma_enumerate_channels - find and initialize the device's channels
121 * @device: the device to be enumerated
123 static int ioat1_enumerate_channels(struct ioatdma_device
*device
)
128 struct ioat_dma_chan
*ioat
;
129 struct device
*dev
= &device
->pdev
->dev
;
130 struct dma_device
*dma
= &device
->common
;
132 INIT_LIST_HEAD(&dma
->channels
);
133 dma
->chancnt
= readb(device
->reg_base
+ IOAT_CHANCNT_OFFSET
);
134 dma
->chancnt
&= 0x1f; /* bits [4:0] valid */
135 if (dma
->chancnt
> ARRAY_SIZE(device
->idx
)) {
136 dev_warn(dev
, "(%d) exceeds max supported channels (%zu)\n",
137 dma
->chancnt
, ARRAY_SIZE(device
->idx
));
138 dma
->chancnt
= ARRAY_SIZE(device
->idx
);
140 xfercap_scale
= readb(device
->reg_base
+ IOAT_XFERCAP_OFFSET
);
141 xfercap_scale
&= 0x1f; /* bits [4:0] valid */
142 xfercap
= (xfercap_scale
== 0 ? -1 : (1UL << xfercap_scale
));
143 dev_dbg(dev
, "%s: xfercap = %d\n", __func__
, xfercap
);
145 #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
146 if (i7300_idle_platform_probe(NULL
, NULL
, 1) == 0)
149 for (i
= 0; i
< dma
->chancnt
; i
++) {
150 ioat
= devm_kzalloc(dev
, sizeof(*ioat
), GFP_KERNEL
);
154 ioat_init_channel(device
, &ioat
->base
, i
);
155 ioat
->xfercap
= xfercap
;
156 spin_lock_init(&ioat
->desc_lock
);
157 INIT_LIST_HEAD(&ioat
->free_desc
);
158 INIT_LIST_HEAD(&ioat
->used_desc
);
165 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
167 * @chan: DMA channel handle
170 __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan
*ioat
)
172 void __iomem
*reg_base
= ioat
->base
.reg_base
;
174 dev_dbg(to_dev(&ioat
->base
), "%s: pending: %d\n",
175 __func__
, ioat
->pending
);
177 writeb(IOAT_CHANCMD_APPEND
, reg_base
+ IOAT1_CHANCMD_OFFSET
);
180 static void ioat1_dma_memcpy_issue_pending(struct dma_chan
*chan
)
182 struct ioat_dma_chan
*ioat
= to_ioat_chan(chan
);
184 if (ioat
->pending
> 0) {
185 spin_lock_bh(&ioat
->desc_lock
);
186 __ioat1_dma_memcpy_issue_pending(ioat
);
187 spin_unlock_bh(&ioat
->desc_lock
);
192 * ioat1_reset_channel - restart a channel
193 * @ioat: IOAT DMA channel handle
195 static void ioat1_reset_channel(struct ioat_dma_chan
*ioat
)
197 struct ioat_chan_common
*chan
= &ioat
->base
;
198 void __iomem
*reg_base
= chan
->reg_base
;
199 u32 chansts
, chanerr
;
201 dev_warn(to_dev(chan
), "reset\n");
202 chanerr
= readl(reg_base
+ IOAT_CHANERR_OFFSET
);
203 chansts
= *chan
->completion
& IOAT_CHANSTS_STATUS
;
205 dev_err(to_dev(chan
),
206 "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
207 chan_num(chan
), chansts
, chanerr
);
208 writel(chanerr
, reg_base
+ IOAT_CHANERR_OFFSET
);
212 * whack it upside the head with a reset
213 * and wait for things to settle out.
214 * force the pending count to a really big negative
215 * to make sure no one forces an issue_pending
216 * while we're waiting.
219 ioat
->pending
= INT_MIN
;
220 writeb(IOAT_CHANCMD_RESET
,
221 reg_base
+ IOAT_CHANCMD_OFFSET(chan
->device
->version
));
222 set_bit(IOAT_RESET_PENDING
, &chan
->state
);
223 mod_timer(&chan
->timer
, jiffies
+ RESET_DELAY
);
226 static dma_cookie_t
ioat1_tx_submit(struct dma_async_tx_descriptor
*tx
)
228 struct dma_chan
*c
= tx
->chan
;
229 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
230 struct ioat_desc_sw
*desc
= tx_to_ioat_desc(tx
);
231 struct ioat_chan_common
*chan
= &ioat
->base
;
232 struct ioat_desc_sw
*first
;
233 struct ioat_desc_sw
*chain_tail
;
236 spin_lock_bh(&ioat
->desc_lock
);
237 /* cookie incr and addition to used_list must be atomic */
238 cookie
= dma_cookie_assign(tx
);
239 dev_dbg(to_dev(&ioat
->base
), "%s: cookie: %d\n", __func__
, cookie
);
241 /* write address into NextDescriptor field of last desc in chain */
242 first
= to_ioat_desc(desc
->tx_list
.next
);
243 chain_tail
= to_ioat_desc(ioat
->used_desc
.prev
);
244 /* make descriptor updates globally visible before chaining */
246 chain_tail
->hw
->next
= first
->txd
.phys
;
247 list_splice_tail_init(&desc
->tx_list
, &ioat
->used_desc
);
248 dump_desc_dbg(ioat
, chain_tail
);
249 dump_desc_dbg(ioat
, first
);
251 if (!test_and_set_bit(IOAT_COMPLETION_PENDING
, &chan
->state
))
252 mod_timer(&chan
->timer
, jiffies
+ COMPLETION_TIMEOUT
);
254 ioat
->active
+= desc
->hw
->tx_cnt
;
255 ioat
->pending
+= desc
->hw
->tx_cnt
;
256 if (ioat
->pending
>= ioat_pending_level
)
257 __ioat1_dma_memcpy_issue_pending(ioat
);
258 spin_unlock_bh(&ioat
->desc_lock
);
264 * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
265 * @ioat: the channel supplying the memory pool for the descriptors
266 * @flags: allocation flags
268 static struct ioat_desc_sw
*
269 ioat_dma_alloc_descriptor(struct ioat_dma_chan
*ioat
, gfp_t flags
)
271 struct ioat_dma_descriptor
*desc
;
272 struct ioat_desc_sw
*desc_sw
;
273 struct ioatdma_device
*ioatdma_device
;
276 ioatdma_device
= ioat
->base
.device
;
277 desc
= pci_pool_alloc(ioatdma_device
->dma_pool
, flags
, &phys
);
281 desc_sw
= kzalloc(sizeof(*desc_sw
), flags
);
282 if (unlikely(!desc_sw
)) {
283 pci_pool_free(ioatdma_device
->dma_pool
, desc
, phys
);
287 memset(desc
, 0, sizeof(*desc
));
289 INIT_LIST_HEAD(&desc_sw
->tx_list
);
290 dma_async_tx_descriptor_init(&desc_sw
->txd
, &ioat
->base
.common
);
291 desc_sw
->txd
.tx_submit
= ioat1_tx_submit
;
293 desc_sw
->txd
.phys
= phys
;
294 set_desc_id(desc_sw
, -1);
299 static int ioat_initial_desc_count
= 256;
300 module_param(ioat_initial_desc_count
, int, 0644);
301 MODULE_PARM_DESC(ioat_initial_desc_count
,
302 "ioat1: initial descriptors per channel (default: 256)");
304 * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
305 * @chan: the channel to be filled out
307 static int ioat1_dma_alloc_chan_resources(struct dma_chan
*c
)
309 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
310 struct ioat_chan_common
*chan
= &ioat
->base
;
311 struct ioat_desc_sw
*desc
;
316 /* have we already been set up? */
317 if (!list_empty(&ioat
->free_desc
))
318 return ioat
->desccount
;
320 /* Setup register to interrupt and write completion status on error */
321 writew(IOAT_CHANCTRL_RUN
, chan
->reg_base
+ IOAT_CHANCTRL_OFFSET
);
323 chanerr
= readl(chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
325 dev_err(to_dev(chan
), "CHANERR = %x, clearing\n", chanerr
);
326 writel(chanerr
, chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
329 /* Allocate descriptors */
330 for (i
= 0; i
< ioat_initial_desc_count
; i
++) {
331 desc
= ioat_dma_alloc_descriptor(ioat
, GFP_KERNEL
);
333 dev_err(to_dev(chan
), "Only %d initial descriptors\n", i
);
336 set_desc_id(desc
, i
);
337 list_add_tail(&desc
->node
, &tmp_list
);
339 spin_lock_bh(&ioat
->desc_lock
);
341 list_splice(&tmp_list
, &ioat
->free_desc
);
342 spin_unlock_bh(&ioat
->desc_lock
);
344 /* allocate a completion writeback area */
345 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
346 chan
->completion
= pci_pool_alloc(chan
->device
->completion_pool
,
347 GFP_KERNEL
, &chan
->completion_dma
);
348 memset(chan
->completion
, 0, sizeof(*chan
->completion
));
349 writel(((u64
) chan
->completion_dma
) & 0x00000000FFFFFFFF,
350 chan
->reg_base
+ IOAT_CHANCMP_OFFSET_LOW
);
351 writel(((u64
) chan
->completion_dma
) >> 32,
352 chan
->reg_base
+ IOAT_CHANCMP_OFFSET_HIGH
);
354 set_bit(IOAT_RUN
, &chan
->state
);
355 ioat1_dma_start_null_desc(ioat
); /* give chain to dma device */
356 dev_dbg(to_dev(chan
), "%s: allocated %d descriptors\n",
357 __func__
, ioat
->desccount
);
358 return ioat
->desccount
;
361 void ioat_stop(struct ioat_chan_common
*chan
)
363 struct ioatdma_device
*device
= chan
->device
;
364 struct pci_dev
*pdev
= device
->pdev
;
365 int chan_id
= chan_num(chan
);
366 struct msix_entry
*msix
;
368 /* 1/ stop irq from firing tasklets
369 * 2/ stop the tasklet from re-arming irqs
371 clear_bit(IOAT_RUN
, &chan
->state
);
373 /* flush inflight interrupts */
374 switch (device
->irq_mode
) {
376 msix
= &device
->msix_entries
[chan_id
];
377 synchronize_irq(msix
->vector
);
381 synchronize_irq(pdev
->irq
);
387 /* flush inflight timers */
388 del_timer_sync(&chan
->timer
);
390 /* flush inflight tasklet runs */
391 tasklet_kill(&chan
->cleanup_task
);
393 /* final cleanup now that everything is quiesced and can't re-arm */
394 device
->cleanup_fn((unsigned long) &chan
->common
);
398 * ioat1_dma_free_chan_resources - release all the descriptors
399 * @chan: the channel to be cleaned
401 static void ioat1_dma_free_chan_resources(struct dma_chan
*c
)
403 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
404 struct ioat_chan_common
*chan
= &ioat
->base
;
405 struct ioatdma_device
*ioatdma_device
= chan
->device
;
406 struct ioat_desc_sw
*desc
, *_desc
;
407 int in_use_descs
= 0;
409 /* Before freeing channel resources first check
410 * if they have been previously allocated for this channel.
412 if (ioat
->desccount
== 0)
417 /* Delay 100ms after reset to allow internal DMA logic to quiesce
418 * before removing DMA descriptor resources.
420 writeb(IOAT_CHANCMD_RESET
,
421 chan
->reg_base
+ IOAT_CHANCMD_OFFSET(chan
->device
->version
));
424 spin_lock_bh(&ioat
->desc_lock
);
425 list_for_each_entry_safe(desc
, _desc
, &ioat
->used_desc
, node
) {
426 dev_dbg(to_dev(chan
), "%s: freeing %d from used list\n",
427 __func__
, desc_id(desc
));
428 dump_desc_dbg(ioat
, desc
);
430 list_del(&desc
->node
);
431 pci_pool_free(ioatdma_device
->dma_pool
, desc
->hw
,
435 list_for_each_entry_safe(desc
, _desc
,
436 &ioat
->free_desc
, node
) {
437 list_del(&desc
->node
);
438 pci_pool_free(ioatdma_device
->dma_pool
, desc
->hw
,
442 spin_unlock_bh(&ioat
->desc_lock
);
444 pci_pool_free(ioatdma_device
->completion_pool
,
446 chan
->completion_dma
);
448 /* one is ok since we left it on there on purpose */
449 if (in_use_descs
> 1)
450 dev_err(to_dev(chan
), "Freeing %d in use descriptors!\n",
453 chan
->last_completion
= 0;
454 chan
->completion_dma
= 0;
460 * ioat1_dma_get_next_descriptor - return the next available descriptor
461 * @ioat: IOAT DMA channel handle
463 * Gets the next descriptor from the chain, and must be called with the
464 * channel's desc_lock held. Allocates more descriptors if the channel
467 static struct ioat_desc_sw
*
468 ioat1_dma_get_next_descriptor(struct ioat_dma_chan
*ioat
)
470 struct ioat_desc_sw
*new;
472 if (!list_empty(&ioat
->free_desc
)) {
473 new = to_ioat_desc(ioat
->free_desc
.next
);
474 list_del(&new->node
);
476 /* try to get another desc */
477 new = ioat_dma_alloc_descriptor(ioat
, GFP_ATOMIC
);
479 dev_err(to_dev(&ioat
->base
), "alloc failed\n");
483 dev_dbg(to_dev(&ioat
->base
), "%s: allocated: %d\n",
484 __func__
, desc_id(new));
489 static struct dma_async_tx_descriptor
*
490 ioat1_dma_prep_memcpy(struct dma_chan
*c
, dma_addr_t dma_dest
,
491 dma_addr_t dma_src
, size_t len
, unsigned long flags
)
493 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
494 struct ioat_desc_sw
*desc
;
497 dma_addr_t src
= dma_src
;
498 dma_addr_t dest
= dma_dest
;
499 size_t total_len
= len
;
500 struct ioat_dma_descriptor
*hw
= NULL
;
503 spin_lock_bh(&ioat
->desc_lock
);
504 desc
= ioat1_dma_get_next_descriptor(ioat
);
510 copy
= min_t(size_t, len
, ioat
->xfercap
);
518 list_add_tail(&desc
->node
, &chain
);
524 struct ioat_desc_sw
*next
;
526 async_tx_ack(&desc
->txd
);
527 next
= ioat1_dma_get_next_descriptor(ioat
);
528 hw
->next
= next
? next
->txd
.phys
: 0;
529 dump_desc_dbg(ioat
, desc
);
536 struct ioat_chan_common
*chan
= &ioat
->base
;
538 dev_err(to_dev(chan
),
539 "chan%d - get_next_desc failed\n", chan_num(chan
));
540 list_splice(&chain
, &ioat
->free_desc
);
541 spin_unlock_bh(&ioat
->desc_lock
);
544 spin_unlock_bh(&ioat
->desc_lock
);
546 desc
->txd
.flags
= flags
;
547 desc
->len
= total_len
;
548 list_splice(&chain
, &desc
->tx_list
);
549 hw
->ctl_f
.int_en
= !!(flags
& DMA_PREP_INTERRUPT
);
550 hw
->ctl_f
.compl_write
= 1;
552 dump_desc_dbg(ioat
, desc
);
557 static void ioat1_cleanup_event(unsigned long data
)
559 struct ioat_dma_chan
*ioat
= to_ioat_chan((void *) data
);
560 struct ioat_chan_common
*chan
= &ioat
->base
;
563 if (!test_bit(IOAT_RUN
, &chan
->state
))
565 writew(IOAT_CHANCTRL_RUN
, ioat
->base
.reg_base
+ IOAT_CHANCTRL_OFFSET
);
568 dma_addr_t
ioat_get_current_completion(struct ioat_chan_common
*chan
)
570 dma_addr_t phys_complete
;
573 completion
= *chan
->completion
;
574 phys_complete
= ioat_chansts_to_addr(completion
);
576 dev_dbg(to_dev(chan
), "%s: phys_complete: %#llx\n", __func__
,
577 (unsigned long long) phys_complete
);
579 if (is_ioat_halted(completion
)) {
580 u32 chanerr
= readl(chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
581 dev_err(to_dev(chan
), "Channel halted, chanerr = %x\n",
584 /* TODO do something to salvage the situation */
587 return phys_complete
;
590 bool ioat_cleanup_preamble(struct ioat_chan_common
*chan
,
591 dma_addr_t
*phys_complete
)
593 *phys_complete
= ioat_get_current_completion(chan
);
594 if (*phys_complete
== chan
->last_completion
)
596 clear_bit(IOAT_COMPLETION_ACK
, &chan
->state
);
597 mod_timer(&chan
->timer
, jiffies
+ COMPLETION_TIMEOUT
);
602 static void __cleanup(struct ioat_dma_chan
*ioat
, dma_addr_t phys_complete
)
604 struct ioat_chan_common
*chan
= &ioat
->base
;
605 struct list_head
*_desc
, *n
;
606 struct dma_async_tx_descriptor
*tx
;
608 dev_dbg(to_dev(chan
), "%s: phys_complete: %llx\n",
609 __func__
, (unsigned long long) phys_complete
);
610 list_for_each_safe(_desc
, n
, &ioat
->used_desc
) {
611 struct ioat_desc_sw
*desc
;
614 desc
= list_entry(_desc
, typeof(*desc
), node
);
617 * Incoming DMA requests may use multiple descriptors,
618 * due to exceeding xfercap, perhaps. If so, only the
619 * last one will have a cookie, and require unmapping.
621 dump_desc_dbg(ioat
, desc
);
623 dma_cookie_complete(tx
);
624 dma_descriptor_unmap(tx
);
625 ioat
->active
-= desc
->hw
->tx_cnt
;
627 tx
->callback(tx
->callback_param
);
632 if (tx
->phys
!= phys_complete
) {
634 * a completed entry, but not the last, so clean
635 * up if the client is done with the descriptor
637 if (async_tx_test_ack(tx
))
638 list_move_tail(&desc
->node
, &ioat
->free_desc
);
641 * last used desc. Do not remove, so we can
645 /* if nothing else is pending, cancel the
648 if (n
== &ioat
->used_desc
) {
649 dev_dbg(to_dev(chan
),
650 "%s cancel completion timeout\n",
652 clear_bit(IOAT_COMPLETION_PENDING
, &chan
->state
);
655 /* TODO check status bits? */
660 chan
->last_completion
= phys_complete
;
664 * ioat1_cleanup - cleanup up finished descriptors
665 * @chan: ioat channel to be cleaned up
667 * To prevent lock contention we defer cleanup when the locks are
668 * contended with a terminal timeout that forces cleanup and catches
669 * completion notification errors.
671 static void ioat1_cleanup(struct ioat_dma_chan
*ioat
)
673 struct ioat_chan_common
*chan
= &ioat
->base
;
674 dma_addr_t phys_complete
;
676 prefetch(chan
->completion
);
678 if (!spin_trylock_bh(&chan
->cleanup_lock
))
681 if (!ioat_cleanup_preamble(chan
, &phys_complete
)) {
682 spin_unlock_bh(&chan
->cleanup_lock
);
686 if (!spin_trylock_bh(&ioat
->desc_lock
)) {
687 spin_unlock_bh(&chan
->cleanup_lock
);
691 __cleanup(ioat
, phys_complete
);
693 spin_unlock_bh(&ioat
->desc_lock
);
694 spin_unlock_bh(&chan
->cleanup_lock
);
697 static void ioat1_timer_event(unsigned long data
)
699 struct ioat_dma_chan
*ioat
= to_ioat_chan((void *) data
);
700 struct ioat_chan_common
*chan
= &ioat
->base
;
702 dev_dbg(to_dev(chan
), "%s: state: %lx\n", __func__
, chan
->state
);
704 spin_lock_bh(&chan
->cleanup_lock
);
705 if (test_and_clear_bit(IOAT_RESET_PENDING
, &chan
->state
)) {
706 struct ioat_desc_sw
*desc
;
708 spin_lock_bh(&ioat
->desc_lock
);
710 /* restart active descriptors */
711 desc
= to_ioat_desc(ioat
->used_desc
.prev
);
712 ioat_set_chainaddr(ioat
, desc
->txd
.phys
);
716 set_bit(IOAT_COMPLETION_PENDING
, &chan
->state
);
717 mod_timer(&chan
->timer
, jiffies
+ COMPLETION_TIMEOUT
);
718 spin_unlock_bh(&ioat
->desc_lock
);
719 } else if (test_bit(IOAT_COMPLETION_PENDING
, &chan
->state
)) {
720 dma_addr_t phys_complete
;
722 spin_lock_bh(&ioat
->desc_lock
);
723 /* if we haven't made progress and we have already
724 * acknowledged a pending completion once, then be more
725 * forceful with a restart
727 if (ioat_cleanup_preamble(chan
, &phys_complete
))
728 __cleanup(ioat
, phys_complete
);
729 else if (test_bit(IOAT_COMPLETION_ACK
, &chan
->state
))
730 ioat1_reset_channel(ioat
);
732 u64 status
= ioat_chansts(chan
);
734 /* manually update the last completion address */
735 if (ioat_chansts_to_addr(status
) != 0)
736 *chan
->completion
= status
;
738 set_bit(IOAT_COMPLETION_ACK
, &chan
->state
);
739 mod_timer(&chan
->timer
, jiffies
+ COMPLETION_TIMEOUT
);
741 spin_unlock_bh(&ioat
->desc_lock
);
743 spin_unlock_bh(&chan
->cleanup_lock
);
747 ioat_dma_tx_status(struct dma_chan
*c
, dma_cookie_t cookie
,
748 struct dma_tx_state
*txstate
)
750 struct ioat_chan_common
*chan
= to_chan_common(c
);
751 struct ioatdma_device
*device
= chan
->device
;
754 ret
= dma_cookie_status(c
, cookie
, txstate
);
755 if (ret
== DMA_COMPLETE
)
758 device
->cleanup_fn((unsigned long) c
);
760 return dma_cookie_status(c
, cookie
, txstate
);
763 static void ioat1_dma_start_null_desc(struct ioat_dma_chan
*ioat
)
765 struct ioat_chan_common
*chan
= &ioat
->base
;
766 struct ioat_desc_sw
*desc
;
767 struct ioat_dma_descriptor
*hw
;
769 spin_lock_bh(&ioat
->desc_lock
);
771 desc
= ioat1_dma_get_next_descriptor(ioat
);
774 dev_err(to_dev(chan
),
775 "Unable to start null desc - get next desc failed\n");
776 spin_unlock_bh(&ioat
->desc_lock
);
783 hw
->ctl_f
.int_en
= 1;
784 hw
->ctl_f
.compl_write
= 1;
785 /* set size to non-zero value (channel returns error when size is 0) */
786 hw
->size
= NULL_DESC_BUFFER_SIZE
;
789 async_tx_ack(&desc
->txd
);
791 list_add_tail(&desc
->node
, &ioat
->used_desc
);
792 dump_desc_dbg(ioat
, desc
);
794 ioat_set_chainaddr(ioat
, desc
->txd
.phys
);
796 spin_unlock_bh(&ioat
->desc_lock
);
800 * Perform a IOAT transaction to verify the HW works.
802 #define IOAT_TEST_SIZE 2000
804 static void ioat_dma_test_callback(void *dma_async_param
)
806 struct completion
*cmp
= dma_async_param
;
812 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
813 * @device: device to be tested
815 int ioat_dma_self_test(struct ioatdma_device
*device
)
820 struct dma_device
*dma
= &device
->common
;
821 struct device
*dev
= &device
->pdev
->dev
;
822 struct dma_chan
*dma_chan
;
823 struct dma_async_tx_descriptor
*tx
;
824 dma_addr_t dma_dest
, dma_src
;
827 struct completion cmp
;
831 src
= kzalloc(sizeof(u8
) * IOAT_TEST_SIZE
, GFP_KERNEL
);
834 dest
= kzalloc(sizeof(u8
) * IOAT_TEST_SIZE
, GFP_KERNEL
);
840 /* Fill in src buffer */
841 for (i
= 0; i
< IOAT_TEST_SIZE
; i
++)
844 /* Start copy, using first DMA channel */
845 dma_chan
= container_of(dma
->channels
.next
, struct dma_chan
,
847 if (dma
->device_alloc_chan_resources(dma_chan
) < 1) {
848 dev_err(dev
, "selftest cannot allocate chan resource\n");
853 dma_src
= dma_map_single(dev
, src
, IOAT_TEST_SIZE
, DMA_TO_DEVICE
);
854 if (dma_mapping_error(dev
, dma_src
)) {
855 dev_err(dev
, "mapping src buffer failed\n");
858 dma_dest
= dma_map_single(dev
, dest
, IOAT_TEST_SIZE
, DMA_FROM_DEVICE
);
859 if (dma_mapping_error(dev
, dma_dest
)) {
860 dev_err(dev
, "mapping dest buffer failed\n");
863 flags
= DMA_PREP_INTERRUPT
;
864 tx
= device
->common
.device_prep_dma_memcpy(dma_chan
, dma_dest
, dma_src
,
865 IOAT_TEST_SIZE
, flags
);
867 dev_err(dev
, "Self-test prep failed, disabling\n");
873 init_completion(&cmp
);
874 tx
->callback
= ioat_dma_test_callback
;
875 tx
->callback_param
= &cmp
;
876 cookie
= tx
->tx_submit(tx
);
878 dev_err(dev
, "Self-test setup failed, disabling\n");
882 dma
->device_issue_pending(dma_chan
);
884 tmo
= wait_for_completion_timeout(&cmp
, msecs_to_jiffies(3000));
887 dma
->device_tx_status(dma_chan
, cookie
, NULL
)
889 dev_err(dev
, "Self-test copy timed out, disabling\n");
893 if (memcmp(src
, dest
, IOAT_TEST_SIZE
)) {
894 dev_err(dev
, "Self-test copy failed compare, disabling\n");
900 dma_unmap_single(dev
, dma_dest
, IOAT_TEST_SIZE
, DMA_FROM_DEVICE
);
902 dma_unmap_single(dev
, dma_src
, IOAT_TEST_SIZE
, DMA_TO_DEVICE
);
904 dma
->device_free_chan_resources(dma_chan
);
911 static char ioat_interrupt_style
[32] = "msix";
912 module_param_string(ioat_interrupt_style
, ioat_interrupt_style
,
913 sizeof(ioat_interrupt_style
), 0644);
914 MODULE_PARM_DESC(ioat_interrupt_style
,
915 "set ioat interrupt style: msix (default), msi, intx");
918 * ioat_dma_setup_interrupts - setup interrupt handler
919 * @device: ioat device
921 int ioat_dma_setup_interrupts(struct ioatdma_device
*device
)
923 struct ioat_chan_common
*chan
;
924 struct pci_dev
*pdev
= device
->pdev
;
925 struct device
*dev
= &pdev
->dev
;
926 struct msix_entry
*msix
;
931 if (!strcmp(ioat_interrupt_style
, "msix"))
933 if (!strcmp(ioat_interrupt_style
, "msi"))
935 if (!strcmp(ioat_interrupt_style
, "intx"))
937 dev_err(dev
, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style
);
941 /* The number of MSI-X vectors should equal the number of channels */
942 msixcnt
= device
->common
.chancnt
;
943 for (i
= 0; i
< msixcnt
; i
++)
944 device
->msix_entries
[i
].entry
= i
;
946 err
= pci_enable_msix_exact(pdev
, device
->msix_entries
, msixcnt
);
950 for (i
= 0; i
< msixcnt
; i
++) {
951 msix
= &device
->msix_entries
[i
];
952 chan
= ioat_chan_by_index(device
, i
);
953 err
= devm_request_irq(dev
, msix
->vector
,
954 ioat_dma_do_interrupt_msix
, 0,
957 for (j
= 0; j
< i
; j
++) {
958 msix
= &device
->msix_entries
[j
];
959 chan
= ioat_chan_by_index(device
, j
);
960 devm_free_irq(dev
, msix
->vector
, chan
);
965 intrctrl
|= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL
;
966 device
->irq_mode
= IOAT_MSIX
;
970 err
= pci_enable_msi(pdev
);
974 err
= devm_request_irq(dev
, pdev
->irq
, ioat_dma_do_interrupt
, 0,
977 pci_disable_msi(pdev
);
980 device
->irq_mode
= IOAT_MSI
;
984 err
= devm_request_irq(dev
, pdev
->irq
, ioat_dma_do_interrupt
,
985 IRQF_SHARED
, "ioat-intx", device
);
989 device
->irq_mode
= IOAT_INTX
;
991 if (device
->intr_quirk
)
992 device
->intr_quirk(device
);
993 intrctrl
|= IOAT_INTRCTRL_MASTER_INT_EN
;
994 writeb(intrctrl
, device
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
998 /* Disable all interrupt generation */
999 writeb(0, device
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
1000 device
->irq_mode
= IOAT_NOIRQ
;
1001 dev_err(dev
, "no usable interrupts\n");
1004 EXPORT_SYMBOL(ioat_dma_setup_interrupts
);
1006 static void ioat_disable_interrupts(struct ioatdma_device
*device
)
1008 /* Disable all interrupt generation */
1009 writeb(0, device
->reg_base
+ IOAT_INTRCTRL_OFFSET
);
1012 int ioat_probe(struct ioatdma_device
*device
)
1015 struct dma_device
*dma
= &device
->common
;
1016 struct pci_dev
*pdev
= device
->pdev
;
1017 struct device
*dev
= &pdev
->dev
;
1019 /* DMA coherent memory pool for DMA descriptor allocations */
1020 device
->dma_pool
= pci_pool_create("dma_desc_pool", pdev
,
1021 sizeof(struct ioat_dma_descriptor
),
1023 if (!device
->dma_pool
) {
1028 device
->completion_pool
= pci_pool_create("completion_pool", pdev
,
1029 sizeof(u64
), SMP_CACHE_BYTES
,
1032 if (!device
->completion_pool
) {
1034 goto err_completion_pool
;
1037 device
->enumerate_channels(device
);
1039 dma_cap_set(DMA_MEMCPY
, dma
->cap_mask
);
1040 dma
->dev
= &pdev
->dev
;
1042 if (!dma
->chancnt
) {
1043 dev_err(dev
, "channel enumeration error\n");
1044 goto err_setup_interrupts
;
1047 err
= ioat_dma_setup_interrupts(device
);
1049 goto err_setup_interrupts
;
1051 err
= device
->self_test(device
);
1058 ioat_disable_interrupts(device
);
1059 err_setup_interrupts
:
1060 pci_pool_destroy(device
->completion_pool
);
1061 err_completion_pool
:
1062 pci_pool_destroy(device
->dma_pool
);
1067 int ioat_register(struct ioatdma_device
*device
)
1069 int err
= dma_async_device_register(&device
->common
);
1072 ioat_disable_interrupts(device
);
1073 pci_pool_destroy(device
->completion_pool
);
1074 pci_pool_destroy(device
->dma_pool
);
1080 /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1081 static void ioat1_intr_quirk(struct ioatdma_device
*device
)
1083 struct pci_dev
*pdev
= device
->pdev
;
1086 pci_read_config_dword(pdev
, IOAT_PCI_DMACTRL_OFFSET
, &dmactrl
);
1087 if (pdev
->msi_enabled
)
1088 dmactrl
|= IOAT_PCI_DMACTRL_MSI_EN
;
1090 dmactrl
&= ~IOAT_PCI_DMACTRL_MSI_EN
;
1091 pci_write_config_dword(pdev
, IOAT_PCI_DMACTRL_OFFSET
, dmactrl
);
1094 static ssize_t
ring_size_show(struct dma_chan
*c
, char *page
)
1096 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
1098 return sprintf(page
, "%d\n", ioat
->desccount
);
1100 static struct ioat_sysfs_entry ring_size_attr
= __ATTR_RO(ring_size
);
1102 static ssize_t
ring_active_show(struct dma_chan
*c
, char *page
)
1104 struct ioat_dma_chan
*ioat
= to_ioat_chan(c
);
1106 return sprintf(page
, "%d\n", ioat
->active
);
1108 static struct ioat_sysfs_entry ring_active_attr
= __ATTR_RO(ring_active
);
1110 static ssize_t
cap_show(struct dma_chan
*c
, char *page
)
1112 struct dma_device
*dma
= c
->device
;
1114 return sprintf(page
, "copy%s%s%s%s%s\n",
1115 dma_has_cap(DMA_PQ
, dma
->cap_mask
) ? " pq" : "",
1116 dma_has_cap(DMA_PQ_VAL
, dma
->cap_mask
) ? " pq_val" : "",
1117 dma_has_cap(DMA_XOR
, dma
->cap_mask
) ? " xor" : "",
1118 dma_has_cap(DMA_XOR_VAL
, dma
->cap_mask
) ? " xor_val" : "",
1119 dma_has_cap(DMA_INTERRUPT
, dma
->cap_mask
) ? " intr" : "");
1122 struct ioat_sysfs_entry ioat_cap_attr
= __ATTR_RO(cap
);
1124 static ssize_t
version_show(struct dma_chan
*c
, char *page
)
1126 struct dma_device
*dma
= c
->device
;
1127 struct ioatdma_device
*device
= to_ioatdma_device(dma
);
1129 return sprintf(page
, "%d.%d\n",
1130 device
->version
>> 4, device
->version
& 0xf);
1132 struct ioat_sysfs_entry ioat_version_attr
= __ATTR_RO(version
);
1134 static struct attribute
*ioat1_attrs
[] = {
1135 &ring_size_attr
.attr
,
1136 &ring_active_attr
.attr
,
1137 &ioat_cap_attr
.attr
,
1138 &ioat_version_attr
.attr
,
1143 ioat_attr_show(struct kobject
*kobj
, struct attribute
*attr
, char *page
)
1145 struct ioat_sysfs_entry
*entry
;
1146 struct ioat_chan_common
*chan
;
1148 entry
= container_of(attr
, struct ioat_sysfs_entry
, attr
);
1149 chan
= container_of(kobj
, struct ioat_chan_common
, kobj
);
1153 return entry
->show(&chan
->common
, page
);
1156 const struct sysfs_ops ioat_sysfs_ops
= {
1157 .show
= ioat_attr_show
,
1160 static struct kobj_type ioat1_ktype
= {
1161 .sysfs_ops
= &ioat_sysfs_ops
,
1162 .default_attrs
= ioat1_attrs
,
1165 void ioat_kobject_add(struct ioatdma_device
*device
, struct kobj_type
*type
)
1167 struct dma_device
*dma
= &device
->common
;
1170 list_for_each_entry(c
, &dma
->channels
, device_node
) {
1171 struct ioat_chan_common
*chan
= to_chan_common(c
);
1172 struct kobject
*parent
= &c
->dev
->device
.kobj
;
1175 err
= kobject_init_and_add(&chan
->kobj
, type
, parent
, "quickdata");
1177 dev_warn(to_dev(chan
),
1178 "sysfs init error (%d), continuing...\n", err
);
1179 kobject_put(&chan
->kobj
);
1180 set_bit(IOAT_KOBJ_INIT_FAIL
, &chan
->state
);
1185 void ioat_kobject_del(struct ioatdma_device
*device
)
1187 struct dma_device
*dma
= &device
->common
;
1190 list_for_each_entry(c
, &dma
->channels
, device_node
) {
1191 struct ioat_chan_common
*chan
= to_chan_common(c
);
1193 if (!test_bit(IOAT_KOBJ_INIT_FAIL
, &chan
->state
)) {
1194 kobject_del(&chan
->kobj
);
1195 kobject_put(&chan
->kobj
);
1200 int ioat1_dma_probe(struct ioatdma_device
*device
, int dca
)
1202 struct pci_dev
*pdev
= device
->pdev
;
1203 struct dma_device
*dma
;
1206 device
->intr_quirk
= ioat1_intr_quirk
;
1207 device
->enumerate_channels
= ioat1_enumerate_channels
;
1208 device
->self_test
= ioat_dma_self_test
;
1209 device
->timer_fn
= ioat1_timer_event
;
1210 device
->cleanup_fn
= ioat1_cleanup_event
;
1211 dma
= &device
->common
;
1212 dma
->device_prep_dma_memcpy
= ioat1_dma_prep_memcpy
;
1213 dma
->device_issue_pending
= ioat1_dma_memcpy_issue_pending
;
1214 dma
->device_alloc_chan_resources
= ioat1_dma_alloc_chan_resources
;
1215 dma
->device_free_chan_resources
= ioat1_dma_free_chan_resources
;
1216 dma
->device_tx_status
= ioat_dma_tx_status
;
1218 err
= ioat_probe(device
);
1221 err
= ioat_register(device
);
1224 ioat_kobject_add(device
, &ioat1_ktype
);
1227 device
->dca
= ioat_dca_init(pdev
, device
->reg_base
);
1232 void ioat_dma_remove(struct ioatdma_device
*device
)
1234 struct dma_device
*dma
= &device
->common
;
1236 ioat_disable_interrupts(device
);
1238 ioat_kobject_del(device
);
1240 dma_async_device_unregister(dma
);
1242 pci_pool_destroy(device
->dma_pool
);
1243 pci_pool_destroy(device
->completion_pool
);
1245 INIT_LIST_HEAD(&dma
->channels
);