2 * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
3 * Copyright (C) Semihalf 2009
4 * Copyright (C) Ilya Yanok, Emcraft Systems 2010
6 * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
7 * (defines, structures and comments) was taken from MPC5121 DMA driver
8 * written by Hongjun Chen <hong-jun.chen@freescale.com>.
10 * Approved as OSADL project by a majority of OSADL members and funded
11 * by OSADL membership fees in 2009; for details see www.osadl.org.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the Free
15 * Software Foundation; either version 2 of the License, or (at your option)
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
23 * You should have received a copy of the GNU General Public License along with
24 * this program; if not, write to the Free Software Foundation, Inc., 59
25 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * The full GNU General Public License is included in this distribution in the
28 * file called COPYING.
32 * This is initial version of MPC5121 DMA driver. Only memory to memory
33 * transfers are supported (tested using dmatest module).
36 #include <linux/module.h>
37 #include <linux/dmaengine.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/interrupt.h>
41 #include <linux/slab.h>
42 #include <linux/of_device.h>
43 #include <linux/of_platform.h>
45 #include <linux/random.h>
47 #include "dmaengine.h"
49 /* Number of DMA Transfer descriptors allocated per channel */
50 #define MPC_DMA_DESCRIPTORS 64
52 /* Macro definitions */
53 #define MPC_DMA_CHANNELS 64
54 #define MPC_DMA_TCD_OFFSET 0x1000
56 /* Arbitration mode of group and channel */
57 #define MPC_DMA_DMACR_EDCG (1 << 31)
58 #define MPC_DMA_DMACR_ERGA (1 << 3)
59 #define MPC_DMA_DMACR_ERCA (1 << 2)
62 #define MPC_DMA_DMAES_VLD (1 << 31)
63 #define MPC_DMA_DMAES_GPE (1 << 15)
64 #define MPC_DMA_DMAES_CPE (1 << 14)
65 #define MPC_DMA_DMAES_ERRCHN(err) \
67 #define MPC_DMA_DMAES_SAE (1 << 7)
68 #define MPC_DMA_DMAES_SOE (1 << 6)
69 #define MPC_DMA_DMAES_DAE (1 << 5)
70 #define MPC_DMA_DMAES_DOE (1 << 4)
71 #define MPC_DMA_DMAES_NCE (1 << 3)
72 #define MPC_DMA_DMAES_SGE (1 << 2)
73 #define MPC_DMA_DMAES_SBE (1 << 1)
74 #define MPC_DMA_DMAES_DBE (1 << 0)
76 #define MPC_DMA_DMAGPOR_SNOOP_ENABLE (1 << 6)
78 #define MPC_DMA_TSIZE_1 0x00
79 #define MPC_DMA_TSIZE_2 0x01
80 #define MPC_DMA_TSIZE_4 0x02
81 #define MPC_DMA_TSIZE_16 0x04
82 #define MPC_DMA_TSIZE_32 0x05
84 /* MPC5121 DMA engine registers */
85 struct __attribute__ ((__packed__
)) mpc_dma_regs
{
87 u32 dmacr
; /* DMA control register */
88 u32 dmaes
; /* DMA error status */
90 u32 dmaerqh
; /* DMA enable request high(channels 63~32) */
91 u32 dmaerql
; /* DMA enable request low(channels 31~0) */
92 u32 dmaeeih
; /* DMA enable error interrupt high(ch63~32) */
93 u32 dmaeeil
; /* DMA enable error interrupt low(ch31~0) */
95 u8 dmaserq
; /* DMA set enable request */
96 u8 dmacerq
; /* DMA clear enable request */
97 u8 dmaseei
; /* DMA set enable error interrupt */
98 u8 dmaceei
; /* DMA clear enable error interrupt */
100 u8 dmacint
; /* DMA clear interrupt request */
101 u8 dmacerr
; /* DMA clear error */
102 u8 dmassrt
; /* DMA set start bit */
103 u8 dmacdne
; /* DMA clear DONE status bit */
105 u32 dmainth
; /* DMA interrupt request high(ch63~32) */
106 u32 dmaintl
; /* DMA interrupt request low(ch31~0) */
107 u32 dmaerrh
; /* DMA error high(ch63~32) */
108 u32 dmaerrl
; /* DMA error low(ch31~0) */
110 u32 dmahrsh
; /* DMA hw request status high(ch63~32) */
111 u32 dmahrsl
; /* DMA hardware request status low(ch31~0) */
113 u32 dmaihsa
; /* DMA interrupt high select AXE(ch63~32) */
114 u32 dmagpor
; /* (General purpose register on MPC8308) */
116 u32 dmailsa
; /* DMA interrupt low select AXE(ch31~0) */
118 u32 reserve0
[48]; /* Reserved */
120 u8 dchpri
[MPC_DMA_CHANNELS
];
121 /* DMA channels(0~63) priority */
124 struct __attribute__ ((__packed__
)) mpc_dma_tcd
{
126 u32 saddr
; /* Source address */
128 u32 smod
:5; /* Source address modulo */
129 u32 ssize
:3; /* Source data transfer size */
130 u32 dmod
:5; /* Destination address modulo */
131 u32 dsize
:3; /* Destination data transfer size */
132 u32 soff
:16; /* Signed source address offset */
135 u32 nbytes
; /* Inner "minor" byte count */
136 u32 slast
; /* Last source address adjustment */
137 u32 daddr
; /* Destination address */
140 u32 citer_elink
:1; /* Enable channel-to-channel linking on
141 * minor loop complete
143 u32 citer_linkch
:6; /* Link channel for minor loop complete */
144 u32 citer
:9; /* Current "major" iteration count */
145 u32 doff
:16; /* Signed destination address offset */
148 u32 dlast_sga
; /* Last Destination address adjustment/scatter
153 u32 biter_elink
:1; /* Enable channel-to-channel linking on major
157 u32 biter
:9; /* Beginning "major" iteration count */
158 u32 bwc
:2; /* Bandwidth control */
159 u32 major_linkch
:6; /* Link channel number */
160 u32 done
:1; /* Channel done */
161 u32 active
:1; /* Channel active */
162 u32 major_elink
:1; /* Enable channel-to-channel linking on major
165 u32 e_sg
:1; /* Enable scatter/gather processing */
166 u32 d_req
:1; /* Disable request */
167 u32 int_half
:1; /* Enable an interrupt when major counter is
170 u32 int_maj
:1; /* Enable an interrupt when major iteration
173 u32 start
:1; /* Channel start */
176 struct mpc_dma_desc
{
177 struct dma_async_tx_descriptor desc
;
178 struct mpc_dma_tcd
*tcd
;
179 dma_addr_t tcd_paddr
;
181 struct list_head node
;
184 struct mpc_dma_chan
{
185 struct dma_chan chan
;
186 struct list_head free
;
187 struct list_head prepared
;
188 struct list_head queued
;
189 struct list_head active
;
190 struct list_head completed
;
191 struct mpc_dma_tcd
*tcd
;
192 dma_addr_t tcd_paddr
;
194 /* Lock for this structure */
199 struct dma_device dma
;
200 struct tasklet_struct tasklet
;
201 struct mpc_dma_chan channels
[MPC_DMA_CHANNELS
];
202 struct mpc_dma_regs __iomem
*regs
;
203 struct mpc_dma_tcd __iomem
*tcd
;
209 /* Lock for error_status field in this structure */
210 spinlock_t error_status_lock
;
213 #define DRV_NAME "mpc512x_dma"
215 /* Convert struct dma_chan to struct mpc_dma_chan */
216 static inline struct mpc_dma_chan
*dma_chan_to_mpc_dma_chan(struct dma_chan
*c
)
218 return container_of(c
, struct mpc_dma_chan
, chan
);
221 /* Convert struct dma_chan to struct mpc_dma */
222 static inline struct mpc_dma
*dma_chan_to_mpc_dma(struct dma_chan
*c
)
224 struct mpc_dma_chan
*mchan
= dma_chan_to_mpc_dma_chan(c
);
225 return container_of(mchan
, struct mpc_dma
, channels
[c
->chan_id
]);
229 * Execute all queued DMA descriptors.
231 * Following requirements must be met while calling mpc_dma_execute():
232 * a) mchan->lock is acquired,
233 * b) mchan->active list is empty,
234 * c) mchan->queued list contains at least one entry.
236 static void mpc_dma_execute(struct mpc_dma_chan
*mchan
)
238 struct mpc_dma
*mdma
= dma_chan_to_mpc_dma(&mchan
->chan
);
239 struct mpc_dma_desc
*first
= NULL
;
240 struct mpc_dma_desc
*prev
= NULL
;
241 struct mpc_dma_desc
*mdesc
;
242 int cid
= mchan
->chan
.chan_id
;
244 /* Move all queued descriptors to active list */
245 list_splice_tail_init(&mchan
->queued
, &mchan
->active
);
247 /* Chain descriptors into one transaction */
248 list_for_each_entry(mdesc
, &mchan
->active
, node
) {
257 prev
->tcd
->dlast_sga
= mdesc
->tcd_paddr
;
259 mdesc
->tcd
->start
= 1;
264 prev
->tcd
->int_maj
= 1;
266 /* Send first descriptor in chain into hardware */
267 memcpy_toio(&mdma
->tcd
[cid
], first
->tcd
, sizeof(struct mpc_dma_tcd
));
270 mdma
->tcd
[cid
].e_sg
= 1;
271 out_8(&mdma
->regs
->dmassrt
, cid
);
274 /* Handle interrupt on one half of DMA controller (32 channels) */
275 static void mpc_dma_irq_process(struct mpc_dma
*mdma
, u32 is
, u32 es
, int off
)
277 struct mpc_dma_chan
*mchan
;
278 struct mpc_dma_desc
*mdesc
;
279 u32 status
= is
| es
;
282 while ((ch
= fls(status
) - 1) >= 0) {
283 status
&= ~(1 << ch
);
284 mchan
= &mdma
->channels
[ch
+ off
];
286 spin_lock(&mchan
->lock
);
288 out_8(&mdma
->regs
->dmacint
, ch
+ off
);
289 out_8(&mdma
->regs
->dmacerr
, ch
+ off
);
291 /* Check error status */
293 list_for_each_entry(mdesc
, &mchan
->active
, node
)
296 /* Execute queued descriptors */
297 list_splice_tail_init(&mchan
->active
, &mchan
->completed
);
298 if (!list_empty(&mchan
->queued
))
299 mpc_dma_execute(mchan
);
301 spin_unlock(&mchan
->lock
);
305 /* Interrupt handler */
306 static irqreturn_t
mpc_dma_irq(int irq
, void *data
)
308 struct mpc_dma
*mdma
= data
;
311 /* Save error status register */
312 es
= in_be32(&mdma
->regs
->dmaes
);
313 spin_lock(&mdma
->error_status_lock
);
314 if ((es
& MPC_DMA_DMAES_VLD
) && mdma
->error_status
== 0)
315 mdma
->error_status
= es
;
316 spin_unlock(&mdma
->error_status_lock
);
318 /* Handle interrupt on each channel */
319 if (mdma
->dma
.chancnt
> 32) {
320 mpc_dma_irq_process(mdma
, in_be32(&mdma
->regs
->dmainth
),
321 in_be32(&mdma
->regs
->dmaerrh
), 32);
323 mpc_dma_irq_process(mdma
, in_be32(&mdma
->regs
->dmaintl
),
324 in_be32(&mdma
->regs
->dmaerrl
), 0);
326 /* Schedule tasklet */
327 tasklet_schedule(&mdma
->tasklet
);
332 /* process completed descriptors */
333 static void mpc_dma_process_completed(struct mpc_dma
*mdma
)
335 dma_cookie_t last_cookie
= 0;
336 struct mpc_dma_chan
*mchan
;
337 struct mpc_dma_desc
*mdesc
;
338 struct dma_async_tx_descriptor
*desc
;
343 for (i
= 0; i
< mdma
->dma
.chancnt
; i
++) {
344 mchan
= &mdma
->channels
[i
];
346 /* Get all completed descriptors */
347 spin_lock_irqsave(&mchan
->lock
, flags
);
348 if (!list_empty(&mchan
->completed
))
349 list_splice_tail_init(&mchan
->completed
, &list
);
350 spin_unlock_irqrestore(&mchan
->lock
, flags
);
352 if (list_empty(&list
))
355 /* Execute callbacks and run dependencies */
356 list_for_each_entry(mdesc
, &list
, node
) {
360 desc
->callback(desc
->callback_param
);
362 last_cookie
= desc
->cookie
;
363 dma_run_dependencies(desc
);
366 /* Free descriptors */
367 spin_lock_irqsave(&mchan
->lock
, flags
);
368 list_splice_tail_init(&list
, &mchan
->free
);
369 mchan
->chan
.completed_cookie
= last_cookie
;
370 spin_unlock_irqrestore(&mchan
->lock
, flags
);
375 static void mpc_dma_tasklet(unsigned long data
)
377 struct mpc_dma
*mdma
= (void *)data
;
381 spin_lock_irqsave(&mdma
->error_status_lock
, flags
);
382 es
= mdma
->error_status
;
383 mdma
->error_status
= 0;
384 spin_unlock_irqrestore(&mdma
->error_status_lock
, flags
);
386 /* Print nice error report */
388 dev_err(mdma
->dma
.dev
,
389 "Hardware reported following error(s) on channel %u:\n",
390 MPC_DMA_DMAES_ERRCHN(es
));
392 if (es
& MPC_DMA_DMAES_GPE
)
393 dev_err(mdma
->dma
.dev
, "- Group Priority Error\n");
394 if (es
& MPC_DMA_DMAES_CPE
)
395 dev_err(mdma
->dma
.dev
, "- Channel Priority Error\n");
396 if (es
& MPC_DMA_DMAES_SAE
)
397 dev_err(mdma
->dma
.dev
, "- Source Address Error\n");
398 if (es
& MPC_DMA_DMAES_SOE
)
399 dev_err(mdma
->dma
.dev
, "- Source Offset"
400 " Configuration Error\n");
401 if (es
& MPC_DMA_DMAES_DAE
)
402 dev_err(mdma
->dma
.dev
, "- Destination Address"
404 if (es
& MPC_DMA_DMAES_DOE
)
405 dev_err(mdma
->dma
.dev
, "- Destination Offset"
406 " Configuration Error\n");
407 if (es
& MPC_DMA_DMAES_NCE
)
408 dev_err(mdma
->dma
.dev
, "- NBytes/Citter"
409 " Configuration Error\n");
410 if (es
& MPC_DMA_DMAES_SGE
)
411 dev_err(mdma
->dma
.dev
, "- Scatter/Gather"
412 " Configuration Error\n");
413 if (es
& MPC_DMA_DMAES_SBE
)
414 dev_err(mdma
->dma
.dev
, "- Source Bus Error\n");
415 if (es
& MPC_DMA_DMAES_DBE
)
416 dev_err(mdma
->dma
.dev
, "- Destination Bus Error\n");
419 mpc_dma_process_completed(mdma
);
422 /* Submit descriptor to hardware */
423 static dma_cookie_t
mpc_dma_tx_submit(struct dma_async_tx_descriptor
*txd
)
425 struct mpc_dma_chan
*mchan
= dma_chan_to_mpc_dma_chan(txd
->chan
);
426 struct mpc_dma_desc
*mdesc
;
430 mdesc
= container_of(txd
, struct mpc_dma_desc
, desc
);
432 spin_lock_irqsave(&mchan
->lock
, flags
);
434 /* Move descriptor to queue */
435 list_move_tail(&mdesc
->node
, &mchan
->queued
);
437 /* If channel is idle, execute all queued descriptors */
438 if (list_empty(&mchan
->active
))
439 mpc_dma_execute(mchan
);
442 cookie
= mchan
->chan
.cookie
+ 1;
446 mchan
->chan
.cookie
= cookie
;
447 mdesc
->desc
.cookie
= cookie
;
449 spin_unlock_irqrestore(&mchan
->lock
, flags
);
454 /* Alloc channel resources */
455 static int mpc_dma_alloc_chan_resources(struct dma_chan
*chan
)
457 struct mpc_dma
*mdma
= dma_chan_to_mpc_dma(chan
);
458 struct mpc_dma_chan
*mchan
= dma_chan_to_mpc_dma_chan(chan
);
459 struct mpc_dma_desc
*mdesc
;
460 struct mpc_dma_tcd
*tcd
;
461 dma_addr_t tcd_paddr
;
466 /* Alloc DMA memory for Transfer Control Descriptors */
467 tcd
= dma_alloc_coherent(mdma
->dma
.dev
,
468 MPC_DMA_DESCRIPTORS
* sizeof(struct mpc_dma_tcd
),
469 &tcd_paddr
, GFP_KERNEL
);
473 /* Alloc descriptors for this channel */
474 for (i
= 0; i
< MPC_DMA_DESCRIPTORS
; i
++) {
475 mdesc
= kzalloc(sizeof(struct mpc_dma_desc
), GFP_KERNEL
);
477 dev_notice(mdma
->dma
.dev
, "Memory allocation error. "
478 "Allocated only %u descriptors\n", i
);
482 dma_async_tx_descriptor_init(&mdesc
->desc
, chan
);
483 mdesc
->desc
.flags
= DMA_CTRL_ACK
;
484 mdesc
->desc
.tx_submit
= mpc_dma_tx_submit
;
486 mdesc
->tcd
= &tcd
[i
];
487 mdesc
->tcd_paddr
= tcd_paddr
+ (i
* sizeof(struct mpc_dma_tcd
));
489 list_add_tail(&mdesc
->node
, &descs
);
492 /* Return error only if no descriptors were allocated */
494 dma_free_coherent(mdma
->dma
.dev
,
495 MPC_DMA_DESCRIPTORS
* sizeof(struct mpc_dma_tcd
),
500 spin_lock_irqsave(&mchan
->lock
, flags
);
502 mchan
->tcd_paddr
= tcd_paddr
;
503 list_splice_tail_init(&descs
, &mchan
->free
);
504 spin_unlock_irqrestore(&mchan
->lock
, flags
);
506 /* Enable Error Interrupt */
507 out_8(&mdma
->regs
->dmaseei
, chan
->chan_id
);
512 /* Free channel resources */
513 static void mpc_dma_free_chan_resources(struct dma_chan
*chan
)
515 struct mpc_dma
*mdma
= dma_chan_to_mpc_dma(chan
);
516 struct mpc_dma_chan
*mchan
= dma_chan_to_mpc_dma_chan(chan
);
517 struct mpc_dma_desc
*mdesc
, *tmp
;
518 struct mpc_dma_tcd
*tcd
;
519 dma_addr_t tcd_paddr
;
523 spin_lock_irqsave(&mchan
->lock
, flags
);
525 /* Channel must be idle */
526 BUG_ON(!list_empty(&mchan
->prepared
));
527 BUG_ON(!list_empty(&mchan
->queued
));
528 BUG_ON(!list_empty(&mchan
->active
));
529 BUG_ON(!list_empty(&mchan
->completed
));
532 list_splice_tail_init(&mchan
->free
, &descs
);
534 tcd_paddr
= mchan
->tcd_paddr
;
536 spin_unlock_irqrestore(&mchan
->lock
, flags
);
538 /* Free DMA memory used by descriptors */
539 dma_free_coherent(mdma
->dma
.dev
,
540 MPC_DMA_DESCRIPTORS
* sizeof(struct mpc_dma_tcd
),
543 /* Free descriptors */
544 list_for_each_entry_safe(mdesc
, tmp
, &descs
, node
)
547 /* Disable Error Interrupt */
548 out_8(&mdma
->regs
->dmaceei
, chan
->chan_id
);
551 /* Send all pending descriptor to hardware */
552 static void mpc_dma_issue_pending(struct dma_chan
*chan
)
555 * We are posting descriptors to the hardware as soon as
556 * they are ready, so this function does nothing.
560 /* Check request completion status */
561 static enum dma_status
562 mpc_dma_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
563 struct dma_tx_state
*txstate
)
565 struct mpc_dma_chan
*mchan
= dma_chan_to_mpc_dma_chan(chan
);
567 dma_cookie_t last_used
;
568 dma_cookie_t last_complete
;
570 spin_lock_irqsave(&mchan
->lock
, flags
);
571 last_used
= mchan
->chan
.cookie
;
572 last_complete
= mchan
->chan
.completed_cookie
;
573 spin_unlock_irqrestore(&mchan
->lock
, flags
);
575 dma_set_tx_state(txstate
, last_complete
, last_used
, 0);
576 return dma_async_is_complete(cookie
, last_complete
, last_used
);
579 /* Prepare descriptor for memory to memory copy */
580 static struct dma_async_tx_descriptor
*
581 mpc_dma_prep_memcpy(struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t src
,
582 size_t len
, unsigned long flags
)
584 struct mpc_dma
*mdma
= dma_chan_to_mpc_dma(chan
);
585 struct mpc_dma_chan
*mchan
= dma_chan_to_mpc_dma_chan(chan
);
586 struct mpc_dma_desc
*mdesc
= NULL
;
587 struct mpc_dma_tcd
*tcd
;
588 unsigned long iflags
;
590 /* Get free descriptor */
591 spin_lock_irqsave(&mchan
->lock
, iflags
);
592 if (!list_empty(&mchan
->free
)) {
593 mdesc
= list_first_entry(&mchan
->free
, struct mpc_dma_desc
,
595 list_del(&mdesc
->node
);
597 spin_unlock_irqrestore(&mchan
->lock
, iflags
);
600 /* try to free completed descriptors */
601 mpc_dma_process_completed(mdma
);
608 /* Prepare Transfer Control Descriptor for this transaction */
609 memset(tcd
, 0, sizeof(struct mpc_dma_tcd
));
611 if (IS_ALIGNED(src
| dst
| len
, 32)) {
612 tcd
->ssize
= MPC_DMA_TSIZE_32
;
613 tcd
->dsize
= MPC_DMA_TSIZE_32
;
616 } else if (!mdma
->is_mpc8308
&& IS_ALIGNED(src
| dst
| len
, 16)) {
617 /* MPC8308 doesn't support 16 byte transfers */
618 tcd
->ssize
= MPC_DMA_TSIZE_16
;
619 tcd
->dsize
= MPC_DMA_TSIZE_16
;
622 } else if (IS_ALIGNED(src
| dst
| len
, 4)) {
623 tcd
->ssize
= MPC_DMA_TSIZE_4
;
624 tcd
->dsize
= MPC_DMA_TSIZE_4
;
627 } else if (IS_ALIGNED(src
| dst
| len
, 2)) {
628 tcd
->ssize
= MPC_DMA_TSIZE_2
;
629 tcd
->dsize
= MPC_DMA_TSIZE_2
;
633 tcd
->ssize
= MPC_DMA_TSIZE_1
;
634 tcd
->dsize
= MPC_DMA_TSIZE_1
;
645 /* Place descriptor in prepared list */
646 spin_lock_irqsave(&mchan
->lock
, iflags
);
647 list_add_tail(&mdesc
->node
, &mchan
->prepared
);
648 spin_unlock_irqrestore(&mchan
->lock
, iflags
);
653 static int __devinit
mpc_dma_probe(struct platform_device
*op
)
655 struct device_node
*dn
= op
->dev
.of_node
;
656 struct device
*dev
= &op
->dev
;
657 struct dma_device
*dma
;
658 struct mpc_dma
*mdma
;
659 struct mpc_dma_chan
*mchan
;
661 ulong regs_start
, regs_size
;
664 mdma
= devm_kzalloc(dev
, sizeof(struct mpc_dma
), GFP_KERNEL
);
666 dev_err(dev
, "Memory exhausted!\n");
670 mdma
->irq
= irq_of_parse_and_map(dn
, 0);
671 if (mdma
->irq
== NO_IRQ
) {
672 dev_err(dev
, "Error mapping IRQ!\n");
676 if (of_device_is_compatible(dn
, "fsl,mpc8308-dma")) {
677 mdma
->is_mpc8308
= 1;
678 mdma
->irq2
= irq_of_parse_and_map(dn
, 1);
679 if (mdma
->irq2
== NO_IRQ
) {
680 dev_err(dev
, "Error mapping IRQ!\n");
685 retval
= of_address_to_resource(dn
, 0, &res
);
687 dev_err(dev
, "Error parsing memory region!\n");
691 regs_start
= res
.start
;
692 regs_size
= resource_size(&res
);
694 if (!devm_request_mem_region(dev
, regs_start
, regs_size
, DRV_NAME
)) {
695 dev_err(dev
, "Error requesting memory region!\n");
699 mdma
->regs
= devm_ioremap(dev
, regs_start
, regs_size
);
701 dev_err(dev
, "Error mapping memory region!\n");
705 mdma
->tcd
= (struct mpc_dma_tcd
*)((u8
*)(mdma
->regs
)
706 + MPC_DMA_TCD_OFFSET
);
708 retval
= devm_request_irq(dev
, mdma
->irq
, &mpc_dma_irq
, 0, DRV_NAME
,
711 dev_err(dev
, "Error requesting IRQ!\n");
715 if (mdma
->is_mpc8308
) {
716 retval
= devm_request_irq(dev
, mdma
->irq2
, &mpc_dma_irq
, 0,
719 dev_err(dev
, "Error requesting IRQ2!\n");
724 spin_lock_init(&mdma
->error_status_lock
);
728 if (!mdma
->is_mpc8308
)
729 dma
->chancnt
= MPC_DMA_CHANNELS
;
731 dma
->chancnt
= 16; /* MPC8308 DMA has only 16 channels */
732 dma
->device_alloc_chan_resources
= mpc_dma_alloc_chan_resources
;
733 dma
->device_free_chan_resources
= mpc_dma_free_chan_resources
;
734 dma
->device_issue_pending
= mpc_dma_issue_pending
;
735 dma
->device_tx_status
= mpc_dma_tx_status
;
736 dma
->device_prep_dma_memcpy
= mpc_dma_prep_memcpy
;
738 INIT_LIST_HEAD(&dma
->channels
);
739 dma_cap_set(DMA_MEMCPY
, dma
->cap_mask
);
741 for (i
= 0; i
< dma
->chancnt
; i
++) {
742 mchan
= &mdma
->channels
[i
];
744 mchan
->chan
.device
= dma
;
745 mchan
->chan
.cookie
= 1;
746 mchan
->chan
.completed_cookie
= mchan
->chan
.cookie
;
748 INIT_LIST_HEAD(&mchan
->free
);
749 INIT_LIST_HEAD(&mchan
->prepared
);
750 INIT_LIST_HEAD(&mchan
->queued
);
751 INIT_LIST_HEAD(&mchan
->active
);
752 INIT_LIST_HEAD(&mchan
->completed
);
754 spin_lock_init(&mchan
->lock
);
755 list_add_tail(&mchan
->chan
.device_node
, &dma
->channels
);
758 tasklet_init(&mdma
->tasklet
, mpc_dma_tasklet
, (unsigned long)mdma
);
761 * Configure DMA Engine:
763 * - Round-robin group arbitration,
764 * - Round-robin channel arbitration.
766 if (!mdma
->is_mpc8308
) {
767 out_be32(&mdma
->regs
->dmacr
, MPC_DMA_DMACR_EDCG
|
768 MPC_DMA_DMACR_ERGA
| MPC_DMA_DMACR_ERCA
);
770 /* Disable hardware DMA requests */
771 out_be32(&mdma
->regs
->dmaerqh
, 0);
772 out_be32(&mdma
->regs
->dmaerql
, 0);
774 /* Disable error interrupts */
775 out_be32(&mdma
->regs
->dmaeeih
, 0);
776 out_be32(&mdma
->regs
->dmaeeil
, 0);
778 /* Clear interrupts status */
779 out_be32(&mdma
->regs
->dmainth
, 0xFFFFFFFF);
780 out_be32(&mdma
->regs
->dmaintl
, 0xFFFFFFFF);
781 out_be32(&mdma
->regs
->dmaerrh
, 0xFFFFFFFF);
782 out_be32(&mdma
->regs
->dmaerrl
, 0xFFFFFFFF);
784 /* Route interrupts to IPIC */
785 out_be32(&mdma
->regs
->dmaihsa
, 0);
786 out_be32(&mdma
->regs
->dmailsa
, 0);
788 /* MPC8308 has 16 channels and lacks some registers */
789 out_be32(&mdma
->regs
->dmacr
, MPC_DMA_DMACR_ERCA
);
791 /* enable snooping */
792 out_be32(&mdma
->regs
->dmagpor
, MPC_DMA_DMAGPOR_SNOOP_ENABLE
);
793 /* Disable error interrupts */
794 out_be32(&mdma
->regs
->dmaeeil
, 0);
796 /* Clear interrupts status */
797 out_be32(&mdma
->regs
->dmaintl
, 0xFFFF);
798 out_be32(&mdma
->regs
->dmaerrl
, 0xFFFF);
801 /* Register DMA engine */
802 dev_set_drvdata(dev
, mdma
);
803 retval
= dma_async_device_register(dma
);
805 devm_free_irq(dev
, mdma
->irq
, mdma
);
806 irq_dispose_mapping(mdma
->irq
);
812 static int __devexit
mpc_dma_remove(struct platform_device
*op
)
814 struct device
*dev
= &op
->dev
;
815 struct mpc_dma
*mdma
= dev_get_drvdata(dev
);
817 dma_async_device_unregister(&mdma
->dma
);
818 devm_free_irq(dev
, mdma
->irq
, mdma
);
819 irq_dispose_mapping(mdma
->irq
);
824 static struct of_device_id mpc_dma_match
[] = {
825 { .compatible
= "fsl,mpc5121-dma", },
829 static struct platform_driver mpc_dma_driver
= {
830 .probe
= mpc_dma_probe
,
831 .remove
= __devexit_p(mpc_dma_remove
),
834 .owner
= THIS_MODULE
,
835 .of_match_table
= mpc_dma_match
,
839 module_platform_driver(mpc_dma_driver
);
841 MODULE_LICENSE("GPL");
842 MODULE_AUTHOR("Piotr Ziecik <kosmo@semihalf.com>");