2 * offload engine driver for the Marvell XOR engine
3 * Copyright (C) 2007, 2008, Marvell International Ltd.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/platform_device.h>
27 #include <linux/memory.h>
28 #include <linux/clk.h>
30 #include <linux/of_irq.h>
31 #include <linux/irqdomain.h>
32 #include <linux/platform_data/dma-mv_xor.h>
34 #include "dmaengine.h"
37 static void mv_xor_issue_pending(struct dma_chan
*chan
);
39 #define to_mv_xor_chan(chan) \
40 container_of(chan, struct mv_xor_chan, dmachan)
42 #define to_mv_xor_slot(tx) \
43 container_of(tx, struct mv_xor_desc_slot, async_tx)
45 #define mv_chan_to_devp(chan) \
48 static void mv_desc_init(struct mv_xor_desc_slot
*desc
, unsigned long flags
)
50 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
52 hw_desc
->status
= (1 << 31);
53 hw_desc
->phy_next_desc
= 0;
54 hw_desc
->desc_command
= (1 << 31);
57 static void mv_desc_set_byte_count(struct mv_xor_desc_slot
*desc
,
60 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
61 hw_desc
->byte_count
= byte_count
;
64 static void mv_desc_set_next_desc(struct mv_xor_desc_slot
*desc
,
67 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
68 BUG_ON(hw_desc
->phy_next_desc
);
69 hw_desc
->phy_next_desc
= next_desc_addr
;
72 static void mv_desc_clear_next_desc(struct mv_xor_desc_slot
*desc
)
74 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
75 hw_desc
->phy_next_desc
= 0;
78 static void mv_desc_set_dest_addr(struct mv_xor_desc_slot
*desc
,
81 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
82 hw_desc
->phy_dest_addr
= addr
;
85 static int mv_chan_memset_slot_count(size_t len
)
90 #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
92 static void mv_desc_set_src_addr(struct mv_xor_desc_slot
*desc
,
93 int index
, dma_addr_t addr
)
95 struct mv_xor_desc
*hw_desc
= desc
->hw_desc
;
96 hw_desc
->phy_src_addr
[mv_phy_src_idx(index
)] = addr
;
97 if (desc
->type
== DMA_XOR
)
98 hw_desc
->desc_command
|= (1 << index
);
101 static u32
mv_chan_get_current_desc(struct mv_xor_chan
*chan
)
103 return readl_relaxed(XOR_CURR_DESC(chan
));
106 static void mv_chan_set_next_descriptor(struct mv_xor_chan
*chan
,
109 writel_relaxed(next_desc_addr
, XOR_NEXT_DESC(chan
));
112 static void mv_chan_unmask_interrupts(struct mv_xor_chan
*chan
)
114 u32 val
= readl_relaxed(XOR_INTR_MASK(chan
));
115 val
|= XOR_INTR_MASK_VALUE
<< (chan
->idx
* 16);
116 writel_relaxed(val
, XOR_INTR_MASK(chan
));
119 static u32
mv_chan_get_intr_cause(struct mv_xor_chan
*chan
)
121 u32 intr_cause
= readl_relaxed(XOR_INTR_CAUSE(chan
));
122 intr_cause
= (intr_cause
>> (chan
->idx
* 16)) & 0xFFFF;
126 static int mv_is_err_intr(u32 intr_cause
)
128 if (intr_cause
& ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
134 static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan
*chan
)
136 u32 val
= ~(1 << (chan
->idx
* 16));
137 dev_dbg(mv_chan_to_devp(chan
), "%s, val 0x%08x\n", __func__
, val
);
138 writel_relaxed(val
, XOR_INTR_CAUSE(chan
));
141 static void mv_xor_device_clear_err_status(struct mv_xor_chan
*chan
)
143 u32 val
= 0xFFFF0000 >> (chan
->idx
* 16);
144 writel_relaxed(val
, XOR_INTR_CAUSE(chan
));
147 static int mv_can_chain(struct mv_xor_desc_slot
*desc
)
149 struct mv_xor_desc_slot
*chain_old_tail
= list_entry(
150 desc
->chain_node
.prev
, struct mv_xor_desc_slot
, chain_node
);
152 if (chain_old_tail
->type
!= desc
->type
)
158 static void mv_set_mode(struct mv_xor_chan
*chan
,
159 enum dma_transaction_type type
)
162 u32 config
= readl_relaxed(XOR_CONFIG(chan
));
166 op_mode
= XOR_OPERATION_MODE_XOR
;
169 op_mode
= XOR_OPERATION_MODE_MEMCPY
;
172 dev_err(mv_chan_to_devp(chan
),
173 "error: unsupported operation %d\n",
182 #if defined(__BIG_ENDIAN)
183 config
|= XOR_DESCRIPTOR_SWAP
;
185 config
&= ~XOR_DESCRIPTOR_SWAP
;
188 writel_relaxed(config
, XOR_CONFIG(chan
));
189 chan
->current_type
= type
;
192 static void mv_chan_activate(struct mv_xor_chan
*chan
)
196 dev_dbg(mv_chan_to_devp(chan
), " activate chan.\n");
197 activation
= readl_relaxed(XOR_ACTIVATION(chan
));
199 writel_relaxed(activation
, XOR_ACTIVATION(chan
));
202 static char mv_chan_is_busy(struct mv_xor_chan
*chan
)
204 u32 state
= readl_relaxed(XOR_ACTIVATION(chan
));
206 state
= (state
>> 4) & 0x3;
208 return (state
== 1) ? 1 : 0;
211 static int mv_chan_xor_slot_count(size_t len
, int src_cnt
)
217 * mv_xor_free_slots - flags descriptor slots for reuse
218 * @slot: Slot to free
219 * Caller must hold &mv_chan->lock while calling this function
221 static void mv_xor_free_slots(struct mv_xor_chan
*mv_chan
,
222 struct mv_xor_desc_slot
*slot
)
224 dev_dbg(mv_chan_to_devp(mv_chan
), "%s %d slot %p\n",
225 __func__
, __LINE__
, slot
);
227 slot
->slots_per_op
= 0;
232 * mv_xor_start_new_chain - program the engine to operate on new chain headed by
234 * Caller must hold &mv_chan->lock while calling this function
236 static void mv_xor_start_new_chain(struct mv_xor_chan
*mv_chan
,
237 struct mv_xor_desc_slot
*sw_desc
)
239 dev_dbg(mv_chan_to_devp(mv_chan
), "%s %d: sw_desc %p\n",
240 __func__
, __LINE__
, sw_desc
);
241 if (sw_desc
->type
!= mv_chan
->current_type
)
242 mv_set_mode(mv_chan
, sw_desc
->type
);
244 /* set the hardware chain */
245 mv_chan_set_next_descriptor(mv_chan
, sw_desc
->async_tx
.phys
);
247 mv_chan
->pending
+= sw_desc
->slot_cnt
;
248 mv_xor_issue_pending(&mv_chan
->dmachan
);
252 mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot
*desc
,
253 struct mv_xor_chan
*mv_chan
, dma_cookie_t cookie
)
255 BUG_ON(desc
->async_tx
.cookie
< 0);
257 if (desc
->async_tx
.cookie
> 0) {
258 cookie
= desc
->async_tx
.cookie
;
260 /* call the callback (must not sleep or submit new
261 * operations to this channel)
263 if (desc
->async_tx
.callback
)
264 desc
->async_tx
.callback(
265 desc
->async_tx
.callback_param
);
267 dma_descriptor_unmap(&desc
->async_tx
);
268 if (desc
->group_head
)
269 desc
->group_head
= NULL
;
272 /* run dependent operations */
273 dma_run_dependencies(&desc
->async_tx
);
279 mv_xor_clean_completed_slots(struct mv_xor_chan
*mv_chan
)
281 struct mv_xor_desc_slot
*iter
, *_iter
;
283 dev_dbg(mv_chan_to_devp(mv_chan
), "%s %d\n", __func__
, __LINE__
);
284 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->completed_slots
,
287 if (async_tx_test_ack(&iter
->async_tx
)) {
288 list_del(&iter
->completed_node
);
289 mv_xor_free_slots(mv_chan
, iter
);
296 mv_xor_clean_slot(struct mv_xor_desc_slot
*desc
,
297 struct mv_xor_chan
*mv_chan
)
299 dev_dbg(mv_chan_to_devp(mv_chan
), "%s %d: desc %p flags %d\n",
300 __func__
, __LINE__
, desc
, desc
->async_tx
.flags
);
301 list_del(&desc
->chain_node
);
302 /* the client is allowed to attach dependent operations
305 if (!async_tx_test_ack(&desc
->async_tx
)) {
306 /* move this slot to the completed_slots */
307 list_add_tail(&desc
->completed_node
, &mv_chan
->completed_slots
);
311 mv_xor_free_slots(mv_chan
, desc
);
315 static void __mv_xor_slot_cleanup(struct mv_xor_chan
*mv_chan
)
317 struct mv_xor_desc_slot
*iter
, *_iter
;
318 dma_cookie_t cookie
= 0;
319 int busy
= mv_chan_is_busy(mv_chan
);
320 u32 current_desc
= mv_chan_get_current_desc(mv_chan
);
321 int seen_current
= 0;
323 dev_dbg(mv_chan_to_devp(mv_chan
), "%s %d\n", __func__
, __LINE__
);
324 dev_dbg(mv_chan_to_devp(mv_chan
), "current_desc %x\n", current_desc
);
325 mv_xor_clean_completed_slots(mv_chan
);
327 /* free completed slots from the chain starting with
328 * the oldest descriptor
331 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->chain
,
334 prefetch(&_iter
->async_tx
);
336 /* do not advance past the current descriptor loaded into the
337 * hardware channel, subsequent descriptors are either in
338 * process or have not been submitted
343 /* stop the search if we reach the current descriptor and the
346 if (iter
->async_tx
.phys
== current_desc
) {
352 cookie
= mv_xor_run_tx_complete_actions(iter
, mv_chan
, cookie
);
354 if (mv_xor_clean_slot(iter
, mv_chan
))
358 if ((busy
== 0) && !list_empty(&mv_chan
->chain
)) {
359 struct mv_xor_desc_slot
*chain_head
;
360 chain_head
= list_entry(mv_chan
->chain
.next
,
361 struct mv_xor_desc_slot
,
364 mv_xor_start_new_chain(mv_chan
, chain_head
);
368 mv_chan
->dmachan
.completed_cookie
= cookie
;
372 mv_xor_slot_cleanup(struct mv_xor_chan
*mv_chan
)
374 spin_lock_bh(&mv_chan
->lock
);
375 __mv_xor_slot_cleanup(mv_chan
);
376 spin_unlock_bh(&mv_chan
->lock
);
379 static void mv_xor_tasklet(unsigned long data
)
381 struct mv_xor_chan
*chan
= (struct mv_xor_chan
*) data
;
382 mv_xor_slot_cleanup(chan
);
385 static struct mv_xor_desc_slot
*
386 mv_xor_alloc_slots(struct mv_xor_chan
*mv_chan
, int num_slots
,
389 struct mv_xor_desc_slot
*iter
, *_iter
, *alloc_start
= NULL
;
391 int slots_found
, retry
= 0;
393 /* start search from the last allocated descrtiptor
394 * if a contiguous allocation can not be found start searching
395 * from the beginning of the list
400 iter
= mv_chan
->last_used
;
402 iter
= list_entry(&mv_chan
->all_slots
,
403 struct mv_xor_desc_slot
,
406 list_for_each_entry_safe_continue(
407 iter
, _iter
, &mv_chan
->all_slots
, slot_node
) {
409 prefetch(&_iter
->async_tx
);
410 if (iter
->slots_per_op
) {
411 /* give up after finding the first busy slot
412 * on the second pass through the list
421 /* start the allocation if the slot is correctly aligned */
425 if (slots_found
== num_slots
) {
426 struct mv_xor_desc_slot
*alloc_tail
= NULL
;
427 struct mv_xor_desc_slot
*last_used
= NULL
;
432 /* pre-ack all but the last descriptor */
433 async_tx_ack(&iter
->async_tx
);
435 list_add_tail(&iter
->chain_node
, &chain
);
437 iter
->async_tx
.cookie
= 0;
438 iter
->slot_cnt
= num_slots
;
439 iter
->xor_check_result
= NULL
;
440 for (i
= 0; i
< slots_per_op
; i
++) {
441 iter
->slots_per_op
= slots_per_op
- i
;
443 iter
= list_entry(iter
->slot_node
.next
,
444 struct mv_xor_desc_slot
,
447 num_slots
-= slots_per_op
;
449 alloc_tail
->group_head
= alloc_start
;
450 alloc_tail
->async_tx
.cookie
= -EBUSY
;
451 list_splice(&chain
, &alloc_tail
->tx_list
);
452 mv_chan
->last_used
= last_used
;
453 mv_desc_clear_next_desc(alloc_start
);
454 mv_desc_clear_next_desc(alloc_tail
);
461 /* try to free some slots if the allocation fails */
462 tasklet_schedule(&mv_chan
->irq_tasklet
);
467 /************************ DMA engine API functions ****************************/
469 mv_xor_tx_submit(struct dma_async_tx_descriptor
*tx
)
471 struct mv_xor_desc_slot
*sw_desc
= to_mv_xor_slot(tx
);
472 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(tx
->chan
);
473 struct mv_xor_desc_slot
*grp_start
, *old_chain_tail
;
475 int new_hw_chain
= 1;
477 dev_dbg(mv_chan_to_devp(mv_chan
),
478 "%s sw_desc %p: async_tx %p\n",
479 __func__
, sw_desc
, &sw_desc
->async_tx
);
481 grp_start
= sw_desc
->group_head
;
483 spin_lock_bh(&mv_chan
->lock
);
484 cookie
= dma_cookie_assign(tx
);
486 if (list_empty(&mv_chan
->chain
))
487 list_splice_init(&sw_desc
->tx_list
, &mv_chan
->chain
);
491 old_chain_tail
= list_entry(mv_chan
->chain
.prev
,
492 struct mv_xor_desc_slot
,
494 list_splice_init(&grp_start
->tx_list
,
495 &old_chain_tail
->chain_node
);
497 if (!mv_can_chain(grp_start
))
500 dev_dbg(mv_chan_to_devp(mv_chan
), "Append to last desc %pa\n",
501 &old_chain_tail
->async_tx
.phys
);
503 /* fix up the hardware chain */
504 mv_desc_set_next_desc(old_chain_tail
, grp_start
->async_tx
.phys
);
506 /* if the channel is not busy */
507 if (!mv_chan_is_busy(mv_chan
)) {
508 u32 current_desc
= mv_chan_get_current_desc(mv_chan
);
510 * and the curren desc is the end of the chain before
511 * the append, then we need to start the channel
513 if (current_desc
== old_chain_tail
->async_tx
.phys
)
519 mv_xor_start_new_chain(mv_chan
, grp_start
);
522 spin_unlock_bh(&mv_chan
->lock
);
527 /* returns the number of allocated descriptors */
528 static int mv_xor_alloc_chan_resources(struct dma_chan
*chan
)
533 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
534 struct mv_xor_desc_slot
*slot
= NULL
;
535 int num_descs_in_pool
= MV_XOR_POOL_SIZE
/MV_XOR_SLOT_SIZE
;
537 /* Allocate descriptor slots */
538 idx
= mv_chan
->slots_allocated
;
539 while (idx
< num_descs_in_pool
) {
540 slot
= kzalloc(sizeof(*slot
), GFP_KERNEL
);
542 printk(KERN_INFO
"MV XOR Channel only initialized"
543 " %d descriptor slots", idx
);
546 virt_desc
= mv_chan
->dma_desc_pool_virt
;
547 slot
->hw_desc
= virt_desc
+ idx
* MV_XOR_SLOT_SIZE
;
549 dma_async_tx_descriptor_init(&slot
->async_tx
, chan
);
550 slot
->async_tx
.tx_submit
= mv_xor_tx_submit
;
551 INIT_LIST_HEAD(&slot
->chain_node
);
552 INIT_LIST_HEAD(&slot
->slot_node
);
553 INIT_LIST_HEAD(&slot
->tx_list
);
554 dma_desc
= mv_chan
->dma_desc_pool
;
555 slot
->async_tx
.phys
= dma_desc
+ idx
* MV_XOR_SLOT_SIZE
;
558 spin_lock_bh(&mv_chan
->lock
);
559 mv_chan
->slots_allocated
= idx
;
560 list_add_tail(&slot
->slot_node
, &mv_chan
->all_slots
);
561 spin_unlock_bh(&mv_chan
->lock
);
564 if (mv_chan
->slots_allocated
&& !mv_chan
->last_used
)
565 mv_chan
->last_used
= list_entry(mv_chan
->all_slots
.next
,
566 struct mv_xor_desc_slot
,
569 dev_dbg(mv_chan_to_devp(mv_chan
),
570 "allocated %d descriptor slots last_used: %p\n",
571 mv_chan
->slots_allocated
, mv_chan
->last_used
);
573 return mv_chan
->slots_allocated
? : -ENOMEM
;
576 static struct dma_async_tx_descriptor
*
577 mv_xor_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
578 size_t len
, unsigned long flags
)
580 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
581 struct mv_xor_desc_slot
*sw_desc
, *grp_start
;
584 dev_dbg(mv_chan_to_devp(mv_chan
),
585 "%s dest: %pad src %pad len: %u flags: %ld\n",
586 __func__
, &dest
, &src
, len
, flags
);
587 if (unlikely(len
< MV_XOR_MIN_BYTE_COUNT
))
590 BUG_ON(len
> MV_XOR_MAX_BYTE_COUNT
);
592 spin_lock_bh(&mv_chan
->lock
);
593 slot_cnt
= mv_chan_memcpy_slot_count(len
);
594 sw_desc
= mv_xor_alloc_slots(mv_chan
, slot_cnt
, 1);
596 sw_desc
->type
= DMA_MEMCPY
;
597 sw_desc
->async_tx
.flags
= flags
;
598 grp_start
= sw_desc
->group_head
;
599 mv_desc_init(grp_start
, flags
);
600 mv_desc_set_byte_count(grp_start
, len
);
601 mv_desc_set_dest_addr(sw_desc
->group_head
, dest
);
602 mv_desc_set_src_addr(grp_start
, 0, src
);
603 sw_desc
->unmap_src_cnt
= 1;
604 sw_desc
->unmap_len
= len
;
606 spin_unlock_bh(&mv_chan
->lock
);
608 dev_dbg(mv_chan_to_devp(mv_chan
),
609 "%s sw_desc %p async_tx %p\n",
610 __func__
, sw_desc
, sw_desc
? &sw_desc
->async_tx
: NULL
);
612 return sw_desc
? &sw_desc
->async_tx
: NULL
;
615 static struct dma_async_tx_descriptor
*
616 mv_xor_prep_dma_xor(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t
*src
,
617 unsigned int src_cnt
, size_t len
, unsigned long flags
)
619 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
620 struct mv_xor_desc_slot
*sw_desc
, *grp_start
;
623 if (unlikely(len
< MV_XOR_MIN_BYTE_COUNT
))
626 BUG_ON(len
> MV_XOR_MAX_BYTE_COUNT
);
628 dev_dbg(mv_chan_to_devp(mv_chan
),
629 "%s src_cnt: %d len: %u dest %pad flags: %ld\n",
630 __func__
, src_cnt
, len
, &dest
, flags
);
632 spin_lock_bh(&mv_chan
->lock
);
633 slot_cnt
= mv_chan_xor_slot_count(len
, src_cnt
);
634 sw_desc
= mv_xor_alloc_slots(mv_chan
, slot_cnt
, 1);
636 sw_desc
->type
= DMA_XOR
;
637 sw_desc
->async_tx
.flags
= flags
;
638 grp_start
= sw_desc
->group_head
;
639 mv_desc_init(grp_start
, flags
);
640 /* the byte count field is the same as in memcpy desc*/
641 mv_desc_set_byte_count(grp_start
, len
);
642 mv_desc_set_dest_addr(sw_desc
->group_head
, dest
);
643 sw_desc
->unmap_src_cnt
= src_cnt
;
644 sw_desc
->unmap_len
= len
;
646 mv_desc_set_src_addr(grp_start
, src_cnt
, src
[src_cnt
]);
648 spin_unlock_bh(&mv_chan
->lock
);
649 dev_dbg(mv_chan_to_devp(mv_chan
),
650 "%s sw_desc %p async_tx %p \n",
651 __func__
, sw_desc
, &sw_desc
->async_tx
);
652 return sw_desc
? &sw_desc
->async_tx
: NULL
;
655 static void mv_xor_free_chan_resources(struct dma_chan
*chan
)
657 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
658 struct mv_xor_desc_slot
*iter
, *_iter
;
659 int in_use_descs
= 0;
661 mv_xor_slot_cleanup(mv_chan
);
663 spin_lock_bh(&mv_chan
->lock
);
664 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->chain
,
667 list_del(&iter
->chain_node
);
669 list_for_each_entry_safe(iter
, _iter
, &mv_chan
->completed_slots
,
672 list_del(&iter
->completed_node
);
674 list_for_each_entry_safe_reverse(
675 iter
, _iter
, &mv_chan
->all_slots
, slot_node
) {
676 list_del(&iter
->slot_node
);
678 mv_chan
->slots_allocated
--;
680 mv_chan
->last_used
= NULL
;
682 dev_dbg(mv_chan_to_devp(mv_chan
), "%s slots_allocated %d\n",
683 __func__
, mv_chan
->slots_allocated
);
684 spin_unlock_bh(&mv_chan
->lock
);
687 dev_err(mv_chan_to_devp(mv_chan
),
688 "freeing %d in use descriptors!\n", in_use_descs
);
692 * mv_xor_status - poll the status of an XOR transaction
693 * @chan: XOR channel handle
694 * @cookie: XOR transaction identifier
695 * @txstate: XOR transactions state holder (or NULL)
697 static enum dma_status
mv_xor_status(struct dma_chan
*chan
,
699 struct dma_tx_state
*txstate
)
701 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
704 ret
= dma_cookie_status(chan
, cookie
, txstate
);
705 if (ret
== DMA_COMPLETE
) {
706 mv_xor_clean_completed_slots(mv_chan
);
709 mv_xor_slot_cleanup(mv_chan
);
711 return dma_cookie_status(chan
, cookie
, txstate
);
714 static void mv_dump_xor_regs(struct mv_xor_chan
*chan
)
718 val
= readl_relaxed(XOR_CONFIG(chan
));
719 dev_err(mv_chan_to_devp(chan
), "config 0x%08x\n", val
);
721 val
= readl_relaxed(XOR_ACTIVATION(chan
));
722 dev_err(mv_chan_to_devp(chan
), "activation 0x%08x\n", val
);
724 val
= readl_relaxed(XOR_INTR_CAUSE(chan
));
725 dev_err(mv_chan_to_devp(chan
), "intr cause 0x%08x\n", val
);
727 val
= readl_relaxed(XOR_INTR_MASK(chan
));
728 dev_err(mv_chan_to_devp(chan
), "intr mask 0x%08x\n", val
);
730 val
= readl_relaxed(XOR_ERROR_CAUSE(chan
));
731 dev_err(mv_chan_to_devp(chan
), "error cause 0x%08x\n", val
);
733 val
= readl_relaxed(XOR_ERROR_ADDR(chan
));
734 dev_err(mv_chan_to_devp(chan
), "error addr 0x%08x\n", val
);
737 static void mv_xor_err_interrupt_handler(struct mv_xor_chan
*chan
,
740 if (intr_cause
& (1 << 4)) {
741 dev_dbg(mv_chan_to_devp(chan
),
742 "ignore this error\n");
746 dev_err(mv_chan_to_devp(chan
),
747 "error on chan %d. intr cause 0x%08x\n",
748 chan
->idx
, intr_cause
);
750 mv_dump_xor_regs(chan
);
754 static irqreturn_t
mv_xor_interrupt_handler(int irq
, void *data
)
756 struct mv_xor_chan
*chan
= data
;
757 u32 intr_cause
= mv_chan_get_intr_cause(chan
);
759 dev_dbg(mv_chan_to_devp(chan
), "intr cause %x\n", intr_cause
);
761 if (mv_is_err_intr(intr_cause
))
762 mv_xor_err_interrupt_handler(chan
, intr_cause
);
764 tasklet_schedule(&chan
->irq_tasklet
);
766 mv_xor_device_clear_eoc_cause(chan
);
771 static void mv_xor_issue_pending(struct dma_chan
*chan
)
773 struct mv_xor_chan
*mv_chan
= to_mv_xor_chan(chan
);
775 if (mv_chan
->pending
>= MV_XOR_THRESHOLD
) {
776 mv_chan
->pending
= 0;
777 mv_chan_activate(mv_chan
);
782 * Perform a transaction to verify the HW works.
785 static int mv_xor_memcpy_self_test(struct mv_xor_chan
*mv_chan
)
789 dma_addr_t src_dma
, dest_dma
;
790 struct dma_chan
*dma_chan
;
792 struct dma_async_tx_descriptor
*tx
;
793 struct dmaengine_unmap_data
*unmap
;
796 src
= kmalloc(sizeof(u8
) * PAGE_SIZE
, GFP_KERNEL
);
800 dest
= kzalloc(sizeof(u8
) * PAGE_SIZE
, GFP_KERNEL
);
806 /* Fill in src buffer */
807 for (i
= 0; i
< PAGE_SIZE
; i
++)
808 ((u8
*) src
)[i
] = (u8
)i
;
810 dma_chan
= &mv_chan
->dmachan
;
811 if (mv_xor_alloc_chan_resources(dma_chan
) < 1) {
816 unmap
= dmaengine_get_unmap_data(dma_chan
->device
->dev
, 2, GFP_KERNEL
);
822 src_dma
= dma_map_page(dma_chan
->device
->dev
, virt_to_page(src
), 0,
823 PAGE_SIZE
, DMA_TO_DEVICE
);
824 unmap
->addr
[0] = src_dma
;
826 ret
= dma_mapping_error(dma_chan
->device
->dev
, src_dma
);
833 dest_dma
= dma_map_page(dma_chan
->device
->dev
, virt_to_page(dest
), 0,
834 PAGE_SIZE
, DMA_FROM_DEVICE
);
835 unmap
->addr
[1] = dest_dma
;
837 ret
= dma_mapping_error(dma_chan
->device
->dev
, dest_dma
);
843 unmap
->len
= PAGE_SIZE
;
845 tx
= mv_xor_prep_dma_memcpy(dma_chan
, dest_dma
, src_dma
,
848 dev_err(dma_chan
->device
->dev
,
849 "Self-test cannot prepare operation, disabling\n");
854 cookie
= mv_xor_tx_submit(tx
);
855 if (dma_submit_error(cookie
)) {
856 dev_err(dma_chan
->device
->dev
,
857 "Self-test submit error, disabling\n");
862 mv_xor_issue_pending(dma_chan
);
866 if (mv_xor_status(dma_chan
, cookie
, NULL
) !=
868 dev_err(dma_chan
->device
->dev
,
869 "Self-test copy timed out, disabling\n");
874 dma_sync_single_for_cpu(dma_chan
->device
->dev
, dest_dma
,
875 PAGE_SIZE
, DMA_FROM_DEVICE
);
876 if (memcmp(src
, dest
, PAGE_SIZE
)) {
877 dev_err(dma_chan
->device
->dev
,
878 "Self-test copy failed compare, disabling\n");
884 dmaengine_unmap_put(unmap
);
885 mv_xor_free_chan_resources(dma_chan
);
892 #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
894 mv_xor_xor_self_test(struct mv_xor_chan
*mv_chan
)
898 struct page
*xor_srcs
[MV_XOR_NUM_SRC_TEST
];
899 dma_addr_t dma_srcs
[MV_XOR_NUM_SRC_TEST
];
901 struct dma_async_tx_descriptor
*tx
;
902 struct dmaengine_unmap_data
*unmap
;
903 struct dma_chan
*dma_chan
;
908 int src_count
= MV_XOR_NUM_SRC_TEST
;
910 for (src_idx
= 0; src_idx
< src_count
; src_idx
++) {
911 xor_srcs
[src_idx
] = alloc_page(GFP_KERNEL
);
912 if (!xor_srcs
[src_idx
]) {
914 __free_page(xor_srcs
[src_idx
]);
919 dest
= alloc_page(GFP_KERNEL
);
922 __free_page(xor_srcs
[src_idx
]);
926 /* Fill in src buffers */
927 for (src_idx
= 0; src_idx
< src_count
; src_idx
++) {
928 u8
*ptr
= page_address(xor_srcs
[src_idx
]);
929 for (i
= 0; i
< PAGE_SIZE
; i
++)
930 ptr
[i
] = (1 << src_idx
);
933 for (src_idx
= 0; src_idx
< src_count
; src_idx
++)
934 cmp_byte
^= (u8
) (1 << src_idx
);
936 cmp_word
= (cmp_byte
<< 24) | (cmp_byte
<< 16) |
937 (cmp_byte
<< 8) | cmp_byte
;
939 memset(page_address(dest
), 0, PAGE_SIZE
);
941 dma_chan
= &mv_chan
->dmachan
;
942 if (mv_xor_alloc_chan_resources(dma_chan
) < 1) {
947 unmap
= dmaengine_get_unmap_data(dma_chan
->device
->dev
, src_count
+ 1,
955 for (i
= 0; i
< src_count
; i
++) {
956 unmap
->addr
[i
] = dma_map_page(dma_chan
->device
->dev
, xor_srcs
[i
],
957 0, PAGE_SIZE
, DMA_TO_DEVICE
);
958 dma_srcs
[i
] = unmap
->addr
[i
];
959 ret
= dma_mapping_error(dma_chan
->device
->dev
, unmap
->addr
[i
]);
967 unmap
->addr
[src_count
] = dma_map_page(dma_chan
->device
->dev
, dest
, 0, PAGE_SIZE
,
969 dest_dma
= unmap
->addr
[src_count
];
970 ret
= dma_mapping_error(dma_chan
->device
->dev
, unmap
->addr
[src_count
]);
976 unmap
->len
= PAGE_SIZE
;
978 tx
= mv_xor_prep_dma_xor(dma_chan
, dest_dma
, dma_srcs
,
979 src_count
, PAGE_SIZE
, 0);
981 dev_err(dma_chan
->device
->dev
,
982 "Self-test cannot prepare operation, disabling\n");
987 cookie
= mv_xor_tx_submit(tx
);
988 if (dma_submit_error(cookie
)) {
989 dev_err(dma_chan
->device
->dev
,
990 "Self-test submit error, disabling\n");
995 mv_xor_issue_pending(dma_chan
);
999 if (mv_xor_status(dma_chan
, cookie
, NULL
) !=
1001 dev_err(dma_chan
->device
->dev
,
1002 "Self-test xor timed out, disabling\n");
1004 goto free_resources
;
1007 dma_sync_single_for_cpu(dma_chan
->device
->dev
, dest_dma
,
1008 PAGE_SIZE
, DMA_FROM_DEVICE
);
1009 for (i
= 0; i
< (PAGE_SIZE
/ sizeof(u32
)); i
++) {
1010 u32
*ptr
= page_address(dest
);
1011 if (ptr
[i
] != cmp_word
) {
1012 dev_err(dma_chan
->device
->dev
,
1013 "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
1014 i
, ptr
[i
], cmp_word
);
1016 goto free_resources
;
1021 dmaengine_unmap_put(unmap
);
1022 mv_xor_free_chan_resources(dma_chan
);
1024 src_idx
= src_count
;
1026 __free_page(xor_srcs
[src_idx
]);
1031 /* This driver does not implement any of the optional DMA operations. */
1033 mv_xor_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1039 static int mv_xor_channel_remove(struct mv_xor_chan
*mv_chan
)
1041 struct dma_chan
*chan
, *_chan
;
1042 struct device
*dev
= mv_chan
->dmadev
.dev
;
1044 dma_async_device_unregister(&mv_chan
->dmadev
);
1046 dma_free_coherent(dev
, MV_XOR_POOL_SIZE
,
1047 mv_chan
->dma_desc_pool_virt
, mv_chan
->dma_desc_pool
);
1049 list_for_each_entry_safe(chan
, _chan
, &mv_chan
->dmadev
.channels
,
1051 list_del(&chan
->device_node
);
1054 free_irq(mv_chan
->irq
, mv_chan
);
1059 static struct mv_xor_chan
*
1060 mv_xor_channel_add(struct mv_xor_device
*xordev
,
1061 struct platform_device
*pdev
,
1062 int idx
, dma_cap_mask_t cap_mask
, int irq
)
1065 struct mv_xor_chan
*mv_chan
;
1066 struct dma_device
*dma_dev
;
1068 mv_chan
= devm_kzalloc(&pdev
->dev
, sizeof(*mv_chan
), GFP_KERNEL
);
1070 return ERR_PTR(-ENOMEM
);
1075 dma_dev
= &mv_chan
->dmadev
;
1077 /* allocate coherent memory for hardware descriptors
1078 * note: writecombine gives slightly better performance, but
1079 * requires that we explicitly flush the writes
1081 mv_chan
->dma_desc_pool_virt
=
1082 dma_alloc_writecombine(&pdev
->dev
, MV_XOR_POOL_SIZE
,
1083 &mv_chan
->dma_desc_pool
, GFP_KERNEL
);
1084 if (!mv_chan
->dma_desc_pool_virt
)
1085 return ERR_PTR(-ENOMEM
);
1087 /* discover transaction capabilites from the platform data */
1088 dma_dev
->cap_mask
= cap_mask
;
1090 INIT_LIST_HEAD(&dma_dev
->channels
);
1092 /* set base routines */
1093 dma_dev
->device_alloc_chan_resources
= mv_xor_alloc_chan_resources
;
1094 dma_dev
->device_free_chan_resources
= mv_xor_free_chan_resources
;
1095 dma_dev
->device_tx_status
= mv_xor_status
;
1096 dma_dev
->device_issue_pending
= mv_xor_issue_pending
;
1097 dma_dev
->device_control
= mv_xor_control
;
1098 dma_dev
->dev
= &pdev
->dev
;
1100 /* set prep routines based on capability */
1101 if (dma_has_cap(DMA_MEMCPY
, dma_dev
->cap_mask
))
1102 dma_dev
->device_prep_dma_memcpy
= mv_xor_prep_dma_memcpy
;
1103 if (dma_has_cap(DMA_XOR
, dma_dev
->cap_mask
)) {
1104 dma_dev
->max_xor
= 8;
1105 dma_dev
->device_prep_dma_xor
= mv_xor_prep_dma_xor
;
1108 mv_chan
->mmr_base
= xordev
->xor_base
;
1109 mv_chan
->mmr_high_base
= xordev
->xor_high_base
;
1110 tasklet_init(&mv_chan
->irq_tasklet
, mv_xor_tasklet
, (unsigned long)
1113 /* clear errors before enabling interrupts */
1114 mv_xor_device_clear_err_status(mv_chan
);
1116 ret
= request_irq(mv_chan
->irq
, mv_xor_interrupt_handler
,
1117 0, dev_name(&pdev
->dev
), mv_chan
);
1121 mv_chan_unmask_interrupts(mv_chan
);
1123 mv_set_mode(mv_chan
, DMA_MEMCPY
);
1125 spin_lock_init(&mv_chan
->lock
);
1126 INIT_LIST_HEAD(&mv_chan
->chain
);
1127 INIT_LIST_HEAD(&mv_chan
->completed_slots
);
1128 INIT_LIST_HEAD(&mv_chan
->all_slots
);
1129 mv_chan
->dmachan
.device
= dma_dev
;
1130 dma_cookie_init(&mv_chan
->dmachan
);
1132 list_add_tail(&mv_chan
->dmachan
.device_node
, &dma_dev
->channels
);
1134 if (dma_has_cap(DMA_MEMCPY
, dma_dev
->cap_mask
)) {
1135 ret
= mv_xor_memcpy_self_test(mv_chan
);
1136 dev_dbg(&pdev
->dev
, "memcpy self test returned %d\n", ret
);
1141 if (dma_has_cap(DMA_XOR
, dma_dev
->cap_mask
)) {
1142 ret
= mv_xor_xor_self_test(mv_chan
);
1143 dev_dbg(&pdev
->dev
, "xor self test returned %d\n", ret
);
1148 dev_info(&pdev
->dev
, "Marvell XOR: ( %s%s%s)\n",
1149 dma_has_cap(DMA_XOR
, dma_dev
->cap_mask
) ? "xor " : "",
1150 dma_has_cap(DMA_MEMCPY
, dma_dev
->cap_mask
) ? "cpy " : "",
1151 dma_has_cap(DMA_INTERRUPT
, dma_dev
->cap_mask
) ? "intr " : "");
1153 dma_async_device_register(dma_dev
);
1157 free_irq(mv_chan
->irq
, mv_chan
);
1159 dma_free_coherent(&pdev
->dev
, MV_XOR_POOL_SIZE
,
1160 mv_chan
->dma_desc_pool_virt
, mv_chan
->dma_desc_pool
);
1161 return ERR_PTR(ret
);
1165 mv_xor_conf_mbus_windows(struct mv_xor_device
*xordev
,
1166 const struct mbus_dram_target_info
*dram
)
1168 void __iomem
*base
= xordev
->xor_high_base
;
1172 for (i
= 0; i
< 8; i
++) {
1173 writel(0, base
+ WINDOW_BASE(i
));
1174 writel(0, base
+ WINDOW_SIZE(i
));
1176 writel(0, base
+ WINDOW_REMAP_HIGH(i
));
1179 for (i
= 0; i
< dram
->num_cs
; i
++) {
1180 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
1182 writel((cs
->base
& 0xffff0000) |
1183 (cs
->mbus_attr
<< 8) |
1184 dram
->mbus_dram_target_id
, base
+ WINDOW_BASE(i
));
1185 writel((cs
->size
- 1) & 0xffff0000, base
+ WINDOW_SIZE(i
));
1187 win_enable
|= (1 << i
);
1188 win_enable
|= 3 << (16 + (2 * i
));
1191 writel(win_enable
, base
+ WINDOW_BAR_ENABLE(0));
1192 writel(win_enable
, base
+ WINDOW_BAR_ENABLE(1));
1193 writel(0, base
+ WINDOW_OVERRIDE_CTRL(0));
1194 writel(0, base
+ WINDOW_OVERRIDE_CTRL(1));
1197 static int mv_xor_probe(struct platform_device
*pdev
)
1199 const struct mbus_dram_target_info
*dram
;
1200 struct mv_xor_device
*xordev
;
1201 struct mv_xor_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
1202 struct resource
*res
;
1205 dev_notice(&pdev
->dev
, "Marvell shared XOR driver\n");
1207 xordev
= devm_kzalloc(&pdev
->dev
, sizeof(*xordev
), GFP_KERNEL
);
1211 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1215 xordev
->xor_base
= devm_ioremap(&pdev
->dev
, res
->start
,
1216 resource_size(res
));
1217 if (!xordev
->xor_base
)
1220 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1224 xordev
->xor_high_base
= devm_ioremap(&pdev
->dev
, res
->start
,
1225 resource_size(res
));
1226 if (!xordev
->xor_high_base
)
1229 platform_set_drvdata(pdev
, xordev
);
1232 * (Re-)program MBUS remapping windows if we are asked to.
1234 dram
= mv_mbus_dram_info();
1236 mv_xor_conf_mbus_windows(xordev
, dram
);
1238 /* Not all platforms can gate the clock, so it is not
1239 * an error if the clock does not exists.
1241 xordev
->clk
= clk_get(&pdev
->dev
, NULL
);
1242 if (!IS_ERR(xordev
->clk
))
1243 clk_prepare_enable(xordev
->clk
);
1245 if (pdev
->dev
.of_node
) {
1246 struct device_node
*np
;
1249 for_each_child_of_node(pdev
->dev
.of_node
, np
) {
1250 struct mv_xor_chan
*chan
;
1251 dma_cap_mask_t cap_mask
;
1254 dma_cap_zero(cap_mask
);
1255 if (of_property_read_bool(np
, "dmacap,memcpy"))
1256 dma_cap_set(DMA_MEMCPY
, cap_mask
);
1257 if (of_property_read_bool(np
, "dmacap,xor"))
1258 dma_cap_set(DMA_XOR
, cap_mask
);
1259 if (of_property_read_bool(np
, "dmacap,interrupt"))
1260 dma_cap_set(DMA_INTERRUPT
, cap_mask
);
1262 irq
= irq_of_parse_and_map(np
, 0);
1265 goto err_channel_add
;
1268 chan
= mv_xor_channel_add(xordev
, pdev
, i
,
1271 ret
= PTR_ERR(chan
);
1272 irq_dispose_mapping(irq
);
1273 goto err_channel_add
;
1276 xordev
->channels
[i
] = chan
;
1279 } else if (pdata
&& pdata
->channels
) {
1280 for (i
= 0; i
< MV_XOR_MAX_CHANNELS
; i
++) {
1281 struct mv_xor_channel_data
*cd
;
1282 struct mv_xor_chan
*chan
;
1285 cd
= &pdata
->channels
[i
];
1288 goto err_channel_add
;
1291 irq
= platform_get_irq(pdev
, i
);
1294 goto err_channel_add
;
1297 chan
= mv_xor_channel_add(xordev
, pdev
, i
,
1300 ret
= PTR_ERR(chan
);
1301 goto err_channel_add
;
1304 xordev
->channels
[i
] = chan
;
1311 for (i
= 0; i
< MV_XOR_MAX_CHANNELS
; i
++)
1312 if (xordev
->channels
[i
]) {
1313 mv_xor_channel_remove(xordev
->channels
[i
]);
1314 if (pdev
->dev
.of_node
)
1315 irq_dispose_mapping(xordev
->channels
[i
]->irq
);
1318 if (!IS_ERR(xordev
->clk
)) {
1319 clk_disable_unprepare(xordev
->clk
);
1320 clk_put(xordev
->clk
);
1326 static int mv_xor_remove(struct platform_device
*pdev
)
1328 struct mv_xor_device
*xordev
= platform_get_drvdata(pdev
);
1331 for (i
= 0; i
< MV_XOR_MAX_CHANNELS
; i
++) {
1332 if (xordev
->channels
[i
])
1333 mv_xor_channel_remove(xordev
->channels
[i
]);
1336 if (!IS_ERR(xordev
->clk
)) {
1337 clk_disable_unprepare(xordev
->clk
);
1338 clk_put(xordev
->clk
);
1345 static struct of_device_id mv_xor_dt_ids
[] = {
1346 { .compatible
= "marvell,orion-xor", },
1349 MODULE_DEVICE_TABLE(of
, mv_xor_dt_ids
);
1352 static struct platform_driver mv_xor_driver
= {
1353 .probe
= mv_xor_probe
,
1354 .remove
= mv_xor_remove
,
1356 .owner
= THIS_MODULE
,
1357 .name
= MV_XOR_NAME
,
1358 .of_match_table
= of_match_ptr(mv_xor_dt_ids
),
1363 static int __init
mv_xor_init(void)
1365 return platform_driver_register(&mv_xor_driver
);
1367 module_init(mv_xor_init
);
1369 /* it's currently unsafe to unload this module */
1371 static void __exit
mv_xor_exit(void)
1373 platform_driver_unregister(&mv_xor_driver
);
1377 module_exit(mv_xor_exit
);
1380 MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1381 MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1382 MODULE_LICENSE("GPL");