2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Refer to drivers/dma/imx-sdma.c
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/clk.h>
16 #include <linux/wait.h>
17 #include <linux/sched.h>
18 #include <linux/semaphore.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/platform_device.h>
23 #include <linux/dmaengine.h>
24 #include <linux/delay.h>
25 #include <linux/module.h>
26 #include <linux/fsl/mxs-dma.h>
27 #include <linux/stmp_device.h>
29 #include <linux/of_device.h>
34 #include "dmaengine.h"
37 * NOTE: The term "PIO" throughout the mxs-dma implementation means
38 * PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
39 * dma can program the controller registers of peripheral devices.
42 #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH)
43 #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA)
45 #define HW_APBHX_CTRL0 0x000
46 #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
47 #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
48 #define BP_APBH_CTRL0_RESET_CHANNEL 16
49 #define HW_APBHX_CTRL1 0x010
50 #define HW_APBHX_CTRL2 0x020
51 #define HW_APBHX_CHANNEL_CTRL 0x030
52 #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
54 * The offset of NXTCMDAR register is different per both dma type and version,
55 * while stride for each channel is all the same 0x70.
57 #define HW_APBHX_CHn_NXTCMDAR(d, n) \
58 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
59 #define HW_APBHX_CHn_SEMA(d, n) \
60 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
63 * ccw bits definitions
68 * NAND_LOCK: 4 (1) - not implemented
69 * NAND_WAIT4READY: 5 (1) - not implemented
72 * HALT_ON_TERMINATE: 8 (1)
73 * TERMINATE_FLUSH: 9 (1)
74 * RESERVED: 10..11 (2)
77 #define BP_CCW_COMMAND 0
78 #define BM_CCW_COMMAND (3 << 0)
79 #define CCW_CHAIN (1 << 2)
80 #define CCW_IRQ (1 << 3)
81 #define CCW_DEC_SEM (1 << 6)
82 #define CCW_WAIT4END (1 << 7)
83 #define CCW_HALT_ON_TERM (1 << 8)
84 #define CCW_TERM_FLUSH (1 << 9)
85 #define BP_CCW_PIO_NUM 12
86 #define BM_CCW_PIO_NUM (0xf << 12)
88 #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
90 #define MXS_DMA_CMD_NO_XFER 0
91 #define MXS_DMA_CMD_WRITE 1
92 #define MXS_DMA_CMD_READ 2
93 #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
99 #define MAX_XFER_BYTES 0xff00
101 #define MXS_PIO_WORDS 16
102 u32 pio_words
[MXS_PIO_WORDS
];
105 #define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))
107 struct mxs_dma_chan
{
108 struct mxs_dma_engine
*mxs_dma
;
109 struct dma_chan chan
;
110 struct dma_async_tx_descriptor desc
;
111 struct tasklet_struct tasklet
;
113 struct mxs_dma_ccw
*ccw
;
116 enum dma_status status
;
118 #define MXS_DMA_SG_LOOP (1 << 0)
121 #define MXS_DMA_CHANNELS 16
122 #define MXS_DMA_CHANNELS_MASK 0xffff
124 enum mxs_dma_devtype
{
134 struct mxs_dma_engine
{
135 enum mxs_dma_id dev_id
;
136 enum mxs_dma_devtype type
;
139 struct dma_device dma_device
;
140 struct device_dma_parameters dma_parms
;
141 struct mxs_dma_chan mxs_chans
[MXS_DMA_CHANNELS
];
144 struct mxs_dma_type
{
146 enum mxs_dma_devtype type
;
149 static struct mxs_dma_type mxs_dma_types
[] = {
152 .type
= MXS_DMA_APBH
,
155 .type
= MXS_DMA_APBX
,
158 .type
= MXS_DMA_APBH
,
161 .type
= MXS_DMA_APBX
,
165 static struct platform_device_id mxs_dma_ids
[] = {
167 .name
= "imx23-dma-apbh",
168 .driver_data
= (kernel_ulong_t
) &mxs_dma_types
[0],
170 .name
= "imx23-dma-apbx",
171 .driver_data
= (kernel_ulong_t
) &mxs_dma_types
[1],
173 .name
= "imx28-dma-apbh",
174 .driver_data
= (kernel_ulong_t
) &mxs_dma_types
[2],
176 .name
= "imx28-dma-apbx",
177 .driver_data
= (kernel_ulong_t
) &mxs_dma_types
[3],
183 static const struct of_device_id mxs_dma_dt_ids
[] = {
184 { .compatible
= "fsl,imx23-dma-apbh", .data
= &mxs_dma_ids
[0], },
185 { .compatible
= "fsl,imx23-dma-apbx", .data
= &mxs_dma_ids
[1], },
186 { .compatible
= "fsl,imx28-dma-apbh", .data
= &mxs_dma_ids
[2], },
187 { .compatible
= "fsl,imx28-dma-apbx", .data
= &mxs_dma_ids
[3], },
190 MODULE_DEVICE_TABLE(of
, mxs_dma_dt_ids
);
192 static struct mxs_dma_chan
*to_mxs_dma_chan(struct dma_chan
*chan
)
194 return container_of(chan
, struct mxs_dma_chan
, chan
);
197 int mxs_dma_is_apbh(struct dma_chan
*chan
)
199 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
200 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
202 return dma_is_apbh(mxs_dma
);
205 int mxs_dma_is_apbx(struct dma_chan
*chan
)
207 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
208 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
210 return !dma_is_apbh(mxs_dma
);
213 static void mxs_dma_reset_chan(struct mxs_dma_chan
*mxs_chan
)
215 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
216 int chan_id
= mxs_chan
->chan
.chan_id
;
218 if (dma_is_apbh(mxs_dma
) && apbh_is_old(mxs_dma
))
219 writel(1 << (chan_id
+ BP_APBH_CTRL0_RESET_CHANNEL
),
220 mxs_dma
->base
+ HW_APBHX_CTRL0
+ STMP_OFFSET_REG_SET
);
222 writel(1 << (chan_id
+ BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL
),
223 mxs_dma
->base
+ HW_APBHX_CHANNEL_CTRL
+ STMP_OFFSET_REG_SET
);
226 static void mxs_dma_enable_chan(struct mxs_dma_chan
*mxs_chan
)
228 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
229 int chan_id
= mxs_chan
->chan
.chan_id
;
231 /* set cmd_addr up */
232 writel(mxs_chan
->ccw_phys
,
233 mxs_dma
->base
+ HW_APBHX_CHn_NXTCMDAR(mxs_dma
, chan_id
));
235 /* write 1 to SEMA to kick off the channel */
236 writel(1, mxs_dma
->base
+ HW_APBHX_CHn_SEMA(mxs_dma
, chan_id
));
239 static void mxs_dma_disable_chan(struct mxs_dma_chan
*mxs_chan
)
241 mxs_chan
->status
= DMA_SUCCESS
;
244 static void mxs_dma_pause_chan(struct mxs_dma_chan
*mxs_chan
)
246 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
247 int chan_id
= mxs_chan
->chan
.chan_id
;
249 /* freeze the channel */
250 if (dma_is_apbh(mxs_dma
) && apbh_is_old(mxs_dma
))
252 mxs_dma
->base
+ HW_APBHX_CTRL0
+ STMP_OFFSET_REG_SET
);
255 mxs_dma
->base
+ HW_APBHX_CHANNEL_CTRL
+ STMP_OFFSET_REG_SET
);
257 mxs_chan
->status
= DMA_PAUSED
;
260 static void mxs_dma_resume_chan(struct mxs_dma_chan
*mxs_chan
)
262 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
263 int chan_id
= mxs_chan
->chan
.chan_id
;
265 /* unfreeze the channel */
266 if (dma_is_apbh(mxs_dma
) && apbh_is_old(mxs_dma
))
268 mxs_dma
->base
+ HW_APBHX_CTRL0
+ STMP_OFFSET_REG_CLR
);
271 mxs_dma
->base
+ HW_APBHX_CHANNEL_CTRL
+ STMP_OFFSET_REG_CLR
);
273 mxs_chan
->status
= DMA_IN_PROGRESS
;
276 static dma_cookie_t
mxs_dma_tx_submit(struct dma_async_tx_descriptor
*tx
)
278 return dma_cookie_assign(tx
);
281 static void mxs_dma_tasklet(unsigned long data
)
283 struct mxs_dma_chan
*mxs_chan
= (struct mxs_dma_chan
*) data
;
285 if (mxs_chan
->desc
.callback
)
286 mxs_chan
->desc
.callback(mxs_chan
->desc
.callback_param
);
289 static irqreturn_t
mxs_dma_int_handler(int irq
, void *dev_id
)
291 struct mxs_dma_engine
*mxs_dma
= dev_id
;
294 /* completion status */
295 stat1
= readl(mxs_dma
->base
+ HW_APBHX_CTRL1
);
296 stat1
&= MXS_DMA_CHANNELS_MASK
;
297 writel(stat1
, mxs_dma
->base
+ HW_APBHX_CTRL1
+ STMP_OFFSET_REG_CLR
);
300 stat2
= readl(mxs_dma
->base
+ HW_APBHX_CTRL2
);
301 writel(stat2
, mxs_dma
->base
+ HW_APBHX_CTRL2
+ STMP_OFFSET_REG_CLR
);
304 * When both completion and error of termination bits set at the
305 * same time, we do not take it as an error. IOW, it only becomes
306 * an error we need to handle here in case of either it's (1) a bus
307 * error or (2) a termination error with no completion.
309 stat2
= ((stat2
>> MXS_DMA_CHANNELS
) & stat2
) | /* (1) */
310 (~(stat2
>> MXS_DMA_CHANNELS
) & stat2
& ~stat1
); /* (2) */
312 /* combine error and completion status for checking */
313 stat1
= (stat2
<< MXS_DMA_CHANNELS
) | stat1
;
315 int channel
= fls(stat1
) - 1;
316 struct mxs_dma_chan
*mxs_chan
=
317 &mxs_dma
->mxs_chans
[channel
% MXS_DMA_CHANNELS
];
319 if (channel
>= MXS_DMA_CHANNELS
) {
320 dev_dbg(mxs_dma
->dma_device
.dev
,
321 "%s: error in channel %d\n", __func__
,
322 channel
- MXS_DMA_CHANNELS
);
323 mxs_chan
->status
= DMA_ERROR
;
324 mxs_dma_reset_chan(mxs_chan
);
326 if (mxs_chan
->flags
& MXS_DMA_SG_LOOP
)
327 mxs_chan
->status
= DMA_IN_PROGRESS
;
329 mxs_chan
->status
= DMA_SUCCESS
;
332 stat1
&= ~(1 << channel
);
334 if (mxs_chan
->status
== DMA_SUCCESS
)
335 dma_cookie_complete(&mxs_chan
->desc
);
337 /* schedule tasklet on this channel */
338 tasklet_schedule(&mxs_chan
->tasklet
);
344 static int mxs_dma_alloc_chan_resources(struct dma_chan
*chan
)
346 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
347 struct mxs_dma_data
*data
= chan
->private;
348 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
354 mxs_chan
->chan_irq
= data
->chan_irq
;
356 mxs_chan
->ccw
= dma_alloc_coherent(mxs_dma
->dma_device
.dev
, PAGE_SIZE
,
357 &mxs_chan
->ccw_phys
, GFP_KERNEL
);
358 if (!mxs_chan
->ccw
) {
363 memset(mxs_chan
->ccw
, 0, PAGE_SIZE
);
365 if (mxs_chan
->chan_irq
!= NO_IRQ
) {
366 ret
= request_irq(mxs_chan
->chan_irq
, mxs_dma_int_handler
,
367 0, "mxs-dma", mxs_dma
);
372 ret
= clk_prepare_enable(mxs_dma
->clk
);
376 mxs_dma_reset_chan(mxs_chan
);
378 dma_async_tx_descriptor_init(&mxs_chan
->desc
, chan
);
379 mxs_chan
->desc
.tx_submit
= mxs_dma_tx_submit
;
381 /* the descriptor is ready */
382 async_tx_ack(&mxs_chan
->desc
);
387 free_irq(mxs_chan
->chan_irq
, mxs_dma
);
389 dma_free_coherent(mxs_dma
->dma_device
.dev
, PAGE_SIZE
,
390 mxs_chan
->ccw
, mxs_chan
->ccw_phys
);
395 static void mxs_dma_free_chan_resources(struct dma_chan
*chan
)
397 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
398 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
400 mxs_dma_disable_chan(mxs_chan
);
402 free_irq(mxs_chan
->chan_irq
, mxs_dma
);
404 dma_free_coherent(mxs_dma
->dma_device
.dev
, PAGE_SIZE
,
405 mxs_chan
->ccw
, mxs_chan
->ccw_phys
);
407 clk_disable_unprepare(mxs_dma
->clk
);
411 * How to use the flags for ->device_prep_slave_sg() :
412 * [1] If there is only one DMA command in the DMA chain, the code should be:
414 * ->device_prep_slave_sg(DMA_CTRL_ACK);
416 * [2] If there are two DMA commands in the DMA chain, the code should be
418 * ->device_prep_slave_sg(0);
420 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
422 * [3] If there are more than two DMA commands in the DMA chain, the code
425 * ->device_prep_slave_sg(0); // First
427 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
429 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
432 static struct dma_async_tx_descriptor
*mxs_dma_prep_slave_sg(
433 struct dma_chan
*chan
, struct scatterlist
*sgl
,
434 unsigned int sg_len
, enum dma_transfer_direction direction
,
435 unsigned long flags
, void *context
)
437 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
438 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
439 struct mxs_dma_ccw
*ccw
;
440 struct scatterlist
*sg
;
443 bool append
= flags
& DMA_PREP_INTERRUPT
;
444 int idx
= append
? mxs_chan
->desc_count
: 0;
446 if (mxs_chan
->status
== DMA_IN_PROGRESS
&& !append
)
449 if (sg_len
+ (append
? idx
: 0) > NUM_CCW
) {
450 dev_err(mxs_dma
->dma_device
.dev
,
451 "maximum number of sg exceeded: %d > %d\n",
456 mxs_chan
->status
= DMA_IN_PROGRESS
;
460 * If the sg is prepared with append flag set, the sg
461 * will be appended to the last prepared sg.
465 ccw
= &mxs_chan
->ccw
[idx
- 1];
466 ccw
->next
= mxs_chan
->ccw_phys
+ sizeof(*ccw
) * idx
;
467 ccw
->bits
|= CCW_CHAIN
;
468 ccw
->bits
&= ~CCW_IRQ
;
469 ccw
->bits
&= ~CCW_DEC_SEM
;
474 if (direction
== DMA_TRANS_NONE
) {
475 ccw
= &mxs_chan
->ccw
[idx
++];
478 for (j
= 0; j
< sg_len
;)
479 ccw
->pio_words
[j
++] = *pio
++;
482 ccw
->bits
|= CCW_IRQ
;
483 ccw
->bits
|= CCW_DEC_SEM
;
484 if (flags
& DMA_CTRL_ACK
)
485 ccw
->bits
|= CCW_WAIT4END
;
486 ccw
->bits
|= CCW_HALT_ON_TERM
;
487 ccw
->bits
|= CCW_TERM_FLUSH
;
488 ccw
->bits
|= BF_CCW(sg_len
, PIO_NUM
);
489 ccw
->bits
|= BF_CCW(MXS_DMA_CMD_NO_XFER
, COMMAND
);
491 for_each_sg(sgl
, sg
, sg_len
, i
) {
492 if (sg_dma_len(sg
) > MAX_XFER_BYTES
) {
493 dev_err(mxs_dma
->dma_device
.dev
, "maximum bytes for sg entry exceeded: %d > %d\n",
494 sg_dma_len(sg
), MAX_XFER_BYTES
);
498 ccw
= &mxs_chan
->ccw
[idx
++];
500 ccw
->next
= mxs_chan
->ccw_phys
+ sizeof(*ccw
) * idx
;
501 ccw
->bufaddr
= sg
->dma_address
;
502 ccw
->xfer_bytes
= sg_dma_len(sg
);
505 ccw
->bits
|= CCW_CHAIN
;
506 ccw
->bits
|= CCW_HALT_ON_TERM
;
507 ccw
->bits
|= CCW_TERM_FLUSH
;
508 ccw
->bits
|= BF_CCW(direction
== DMA_DEV_TO_MEM
?
509 MXS_DMA_CMD_WRITE
: MXS_DMA_CMD_READ
,
512 if (i
+ 1 == sg_len
) {
513 ccw
->bits
&= ~CCW_CHAIN
;
514 ccw
->bits
|= CCW_IRQ
;
515 ccw
->bits
|= CCW_DEC_SEM
;
516 if (flags
& DMA_CTRL_ACK
)
517 ccw
->bits
|= CCW_WAIT4END
;
521 mxs_chan
->desc_count
= idx
;
523 return &mxs_chan
->desc
;
526 mxs_chan
->status
= DMA_ERROR
;
530 static struct dma_async_tx_descriptor
*mxs_dma_prep_dma_cyclic(
531 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t buf_len
,
532 size_t period_len
, enum dma_transfer_direction direction
,
535 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
536 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
537 int num_periods
= buf_len
/ period_len
;
540 if (mxs_chan
->status
== DMA_IN_PROGRESS
)
543 mxs_chan
->status
= DMA_IN_PROGRESS
;
544 mxs_chan
->flags
|= MXS_DMA_SG_LOOP
;
546 if (num_periods
> NUM_CCW
) {
547 dev_err(mxs_dma
->dma_device
.dev
,
548 "maximum number of sg exceeded: %d > %d\n",
549 num_periods
, NUM_CCW
);
553 if (period_len
> MAX_XFER_BYTES
) {
554 dev_err(mxs_dma
->dma_device
.dev
,
555 "maximum period size exceeded: %d > %d\n",
556 period_len
, MAX_XFER_BYTES
);
560 while (buf
< buf_len
) {
561 struct mxs_dma_ccw
*ccw
= &mxs_chan
->ccw
[i
];
563 if (i
+ 1 == num_periods
)
564 ccw
->next
= mxs_chan
->ccw_phys
;
566 ccw
->next
= mxs_chan
->ccw_phys
+ sizeof(*ccw
) * (i
+ 1);
568 ccw
->bufaddr
= dma_addr
;
569 ccw
->xfer_bytes
= period_len
;
572 ccw
->bits
|= CCW_CHAIN
;
573 ccw
->bits
|= CCW_IRQ
;
574 ccw
->bits
|= CCW_HALT_ON_TERM
;
575 ccw
->bits
|= CCW_TERM_FLUSH
;
576 ccw
->bits
|= BF_CCW(direction
== DMA_DEV_TO_MEM
?
577 MXS_DMA_CMD_WRITE
: MXS_DMA_CMD_READ
, COMMAND
);
579 dma_addr
+= period_len
;
584 mxs_chan
->desc_count
= i
;
586 return &mxs_chan
->desc
;
589 mxs_chan
->status
= DMA_ERROR
;
593 static int mxs_dma_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
596 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
600 case DMA_TERMINATE_ALL
:
601 mxs_dma_reset_chan(mxs_chan
);
602 mxs_dma_disable_chan(mxs_chan
);
605 mxs_dma_pause_chan(mxs_chan
);
608 mxs_dma_resume_chan(mxs_chan
);
617 static enum dma_status
mxs_dma_tx_status(struct dma_chan
*chan
,
618 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
620 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
621 dma_cookie_t last_used
;
623 last_used
= chan
->cookie
;
624 dma_set_tx_state(txstate
, chan
->completed_cookie
, last_used
, 0);
626 return mxs_chan
->status
;
629 static void mxs_dma_issue_pending(struct dma_chan
*chan
)
631 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
633 mxs_dma_enable_chan(mxs_chan
);
636 static int __init
mxs_dma_init(struct mxs_dma_engine
*mxs_dma
)
640 ret
= clk_prepare_enable(mxs_dma
->clk
);
644 ret
= stmp_reset_block(mxs_dma
->base
);
648 /* enable apbh burst */
649 if (dma_is_apbh(mxs_dma
)) {
650 writel(BM_APBH_CTRL0_APB_BURST_EN
,
651 mxs_dma
->base
+ HW_APBHX_CTRL0
+ STMP_OFFSET_REG_SET
);
652 writel(BM_APBH_CTRL0_APB_BURST8_EN
,
653 mxs_dma
->base
+ HW_APBHX_CTRL0
+ STMP_OFFSET_REG_SET
);
656 /* enable irq for all the channels */
657 writel(MXS_DMA_CHANNELS_MASK
<< MXS_DMA_CHANNELS
,
658 mxs_dma
->base
+ HW_APBHX_CTRL1
+ STMP_OFFSET_REG_SET
);
661 clk_disable_unprepare(mxs_dma
->clk
);
665 static int __init
mxs_dma_probe(struct platform_device
*pdev
)
667 const struct platform_device_id
*id_entry
;
668 const struct of_device_id
*of_id
;
669 const struct mxs_dma_type
*dma_type
;
670 struct mxs_dma_engine
*mxs_dma
;
671 struct resource
*iores
;
674 mxs_dma
= kzalloc(sizeof(*mxs_dma
), GFP_KERNEL
);
678 of_id
= of_match_device(mxs_dma_dt_ids
, &pdev
->dev
);
680 id_entry
= of_id
->data
;
682 id_entry
= platform_get_device_id(pdev
);
684 dma_type
= (struct mxs_dma_type
*)id_entry
->driver_data
;
685 mxs_dma
->type
= dma_type
->type
;
686 mxs_dma
->dev_id
= dma_type
->id
;
688 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
690 if (!request_mem_region(iores
->start
, resource_size(iores
),
693 goto err_request_region
;
696 mxs_dma
->base
= ioremap(iores
->start
, resource_size(iores
));
697 if (!mxs_dma
->base
) {
702 mxs_dma
->clk
= clk_get(&pdev
->dev
, NULL
);
703 if (IS_ERR(mxs_dma
->clk
)) {
704 ret
= PTR_ERR(mxs_dma
->clk
);
708 dma_cap_set(DMA_SLAVE
, mxs_dma
->dma_device
.cap_mask
);
709 dma_cap_set(DMA_CYCLIC
, mxs_dma
->dma_device
.cap_mask
);
711 INIT_LIST_HEAD(&mxs_dma
->dma_device
.channels
);
713 /* Initialize channel parameters */
714 for (i
= 0; i
< MXS_DMA_CHANNELS
; i
++) {
715 struct mxs_dma_chan
*mxs_chan
= &mxs_dma
->mxs_chans
[i
];
717 mxs_chan
->mxs_dma
= mxs_dma
;
718 mxs_chan
->chan
.device
= &mxs_dma
->dma_device
;
719 dma_cookie_init(&mxs_chan
->chan
);
721 tasklet_init(&mxs_chan
->tasklet
, mxs_dma_tasklet
,
722 (unsigned long) mxs_chan
);
725 /* Add the channel to mxs_chan list */
726 list_add_tail(&mxs_chan
->chan
.device_node
,
727 &mxs_dma
->dma_device
.channels
);
730 ret
= mxs_dma_init(mxs_dma
);
734 mxs_dma
->dma_device
.dev
= &pdev
->dev
;
736 /* mxs_dma gets 65535 bytes maximum sg size */
737 mxs_dma
->dma_device
.dev
->dma_parms
= &mxs_dma
->dma_parms
;
738 dma_set_max_seg_size(mxs_dma
->dma_device
.dev
, MAX_XFER_BYTES
);
740 mxs_dma
->dma_device
.device_alloc_chan_resources
= mxs_dma_alloc_chan_resources
;
741 mxs_dma
->dma_device
.device_free_chan_resources
= mxs_dma_free_chan_resources
;
742 mxs_dma
->dma_device
.device_tx_status
= mxs_dma_tx_status
;
743 mxs_dma
->dma_device
.device_prep_slave_sg
= mxs_dma_prep_slave_sg
;
744 mxs_dma
->dma_device
.device_prep_dma_cyclic
= mxs_dma_prep_dma_cyclic
;
745 mxs_dma
->dma_device
.device_control
= mxs_dma_control
;
746 mxs_dma
->dma_device
.device_issue_pending
= mxs_dma_issue_pending
;
748 ret
= dma_async_device_register(&mxs_dma
->dma_device
);
750 dev_err(mxs_dma
->dma_device
.dev
, "unable to register\n");
754 dev_info(mxs_dma
->dma_device
.dev
, "initialized\n");
759 clk_put(mxs_dma
->clk
);
761 iounmap(mxs_dma
->base
);
763 release_mem_region(iores
->start
, resource_size(iores
));
769 static struct platform_driver mxs_dma_driver
= {
772 .of_match_table
= mxs_dma_dt_ids
,
774 .id_table
= mxs_dma_ids
,
777 static int __init
mxs_dma_module_init(void)
779 return platform_driver_probe(&mxs_dma_driver
, mxs_dma_probe
);
781 subsys_initcall(mxs_dma_module_init
);