2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
28 #include <linux/of_dma.h>
29 #include <linux/err.h>
31 #include "dmaengine.h"
32 #define PL330_MAX_CHAN 8
33 #define PL330_MAX_IRQS 32
34 #define PL330_MAX_PERI 32
36 enum pl330_cachectrl
{
37 CCTRL0
, /* Noncacheable and nonbufferable */
38 CCTRL1
, /* Bufferable only */
39 CCTRL2
, /* Cacheable, but do not allocate */
40 CCTRL3
, /* Cacheable and bufferable, but do not allocate */
41 INVALID1
, /* AWCACHE = 0x1000 */
43 CCTRL6
, /* Cacheable write-through, allocate on writes only */
44 CCTRL7
, /* Cacheable write-back, allocate on writes only */
55 /* Register and Bit field Definitions */
57 #define DS_ST_STOP 0x0
58 #define DS_ST_EXEC 0x1
59 #define DS_ST_CMISS 0x2
60 #define DS_ST_UPDTPC 0x3
62 #define DS_ST_ATBRR 0x5
63 #define DS_ST_QBUSY 0x6
65 #define DS_ST_KILL 0x8
66 #define DS_ST_CMPLT 0x9
67 #define DS_ST_FLTCMP 0xe
68 #define DS_ST_FAULT 0xf
73 #define INTSTATUS 0x28
80 #define FTC(n) (_FTC + (n)*0x4)
83 #define CS(n) (_CS + (n)*0x8)
84 #define CS_CNS (1 << 21)
87 #define CPC(n) (_CPC + (n)*0x8)
90 #define SA(n) (_SA + (n)*0x20)
93 #define DA(n) (_DA + (n)*0x20)
96 #define CC(n) (_CC + (n)*0x20)
98 #define CC_SRCINC (1 << 0)
99 #define CC_DSTINC (1 << 14)
100 #define CC_SRCPRI (1 << 8)
101 #define CC_DSTPRI (1 << 22)
102 #define CC_SRCNS (1 << 9)
103 #define CC_DSTNS (1 << 23)
104 #define CC_SRCIA (1 << 10)
105 #define CC_DSTIA (1 << 24)
106 #define CC_SRCBRSTLEN_SHFT 4
107 #define CC_DSTBRSTLEN_SHFT 18
108 #define CC_SRCBRSTSIZE_SHFT 1
109 #define CC_DSTBRSTSIZE_SHFT 15
110 #define CC_SRCCCTRL_SHFT 11
111 #define CC_SRCCCTRL_MASK 0x7
112 #define CC_DSTCCTRL_SHFT 25
113 #define CC_DRCCCTRL_MASK 0x7
114 #define CC_SWAP_SHFT 28
117 #define LC0(n) (_LC0 + (n)*0x20)
120 #define LC1(n) (_LC1 + (n)*0x20)
122 #define DBGSTATUS 0xd00
123 #define DBG_BUSY (1 << 0)
126 #define DBGINST0 0xd08
127 #define DBGINST1 0xd0c
136 #define PERIPH_ID 0xfe0
137 #define PERIPH_REV_SHIFT 20
138 #define PERIPH_REV_MASK 0xf
139 #define PERIPH_REV_R0P0 0
140 #define PERIPH_REV_R1P0 1
141 #define PERIPH_REV_R1P1 2
143 #define CR0_PERIPH_REQ_SET (1 << 0)
144 #define CR0_BOOT_EN_SET (1 << 1)
145 #define CR0_BOOT_MAN_NS (1 << 2)
146 #define CR0_NUM_CHANS_SHIFT 4
147 #define CR0_NUM_CHANS_MASK 0x7
148 #define CR0_NUM_PERIPH_SHIFT 12
149 #define CR0_NUM_PERIPH_MASK 0x1f
150 #define CR0_NUM_EVENTS_SHIFT 17
151 #define CR0_NUM_EVENTS_MASK 0x1f
153 #define CR1_ICACHE_LEN_SHIFT 0
154 #define CR1_ICACHE_LEN_MASK 0x7
155 #define CR1_NUM_ICACHELINES_SHIFT 4
156 #define CR1_NUM_ICACHELINES_MASK 0xf
158 #define CRD_DATA_WIDTH_SHIFT 0
159 #define CRD_DATA_WIDTH_MASK 0x7
160 #define CRD_WR_CAP_SHIFT 4
161 #define CRD_WR_CAP_MASK 0x7
162 #define CRD_WR_Q_DEP_SHIFT 8
163 #define CRD_WR_Q_DEP_MASK 0xf
164 #define CRD_RD_CAP_SHIFT 12
165 #define CRD_RD_CAP_MASK 0x7
166 #define CRD_RD_Q_DEP_SHIFT 16
167 #define CRD_RD_Q_DEP_MASK 0xf
168 #define CRD_DATA_BUFF_SHIFT 20
169 #define CRD_DATA_BUFF_MASK 0x3ff
172 #define DESIGNER 0x41
174 #define INTEG_CFG 0x0
175 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
177 #define PL330_STATE_STOPPED (1 << 0)
178 #define PL330_STATE_EXECUTING (1 << 1)
179 #define PL330_STATE_WFE (1 << 2)
180 #define PL330_STATE_FAULTING (1 << 3)
181 #define PL330_STATE_COMPLETING (1 << 4)
182 #define PL330_STATE_WFP (1 << 5)
183 #define PL330_STATE_KILLING (1 << 6)
184 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
185 #define PL330_STATE_CACHEMISS (1 << 8)
186 #define PL330_STATE_UPDTPC (1 << 9)
187 #define PL330_STATE_ATBARRIER (1 << 10)
188 #define PL330_STATE_QUEUEBUSY (1 << 11)
189 #define PL330_STATE_INVALID (1 << 15)
191 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
192 | PL330_STATE_WFE | PL330_STATE_FAULTING)
194 #define CMD_DMAADDH 0x54
195 #define CMD_DMAEND 0x00
196 #define CMD_DMAFLUSHP 0x35
197 #define CMD_DMAGO 0xa0
198 #define CMD_DMALD 0x04
199 #define CMD_DMALDP 0x25
200 #define CMD_DMALP 0x20
201 #define CMD_DMALPEND 0x28
202 #define CMD_DMAKILL 0x01
203 #define CMD_DMAMOV 0xbc
204 #define CMD_DMANOP 0x18
205 #define CMD_DMARMB 0x12
206 #define CMD_DMASEV 0x34
207 #define CMD_DMAST 0x08
208 #define CMD_DMASTP 0x29
209 #define CMD_DMASTZ 0x0c
210 #define CMD_DMAWFE 0x36
211 #define CMD_DMAWFP 0x30
212 #define CMD_DMAWMB 0x13
216 #define SZ_DMAFLUSHP 2
220 #define SZ_DMALPEND 2
234 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
235 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
237 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
238 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
241 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
242 * at 1byte/burst for P<->M and M<->M respectively.
243 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
244 * should be enough for P<->M and M<->M respectively.
246 #define MCODE_BUFF_PER_REQ 256
248 /* If the _pl330_req is available to the client */
249 #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
251 /* Use this _only_ to wait on transient states */
252 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254 #ifdef PL330_DEBUG_MCGEN
255 static unsigned cmd_line
;
256 #define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
261 #define PL330_DBGMC_START(addr) (cmd_line = addr)
263 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264 #define PL330_DBGMC_START(addr) do {} while (0)
267 /* The number of default descriptors */
269 #define NR_DEFAULT_DESC 16
271 /* Populated by the PL330 core driver for DMA API driver's info */
272 struct pl330_config
{
274 #define DMAC_MODE_NS (1 << 0)
276 unsigned int data_bus_width
:10; /* In number of bits */
277 unsigned int data_buf_dep
:10;
278 unsigned int num_chan
:4;
279 unsigned int num_peri
:6;
281 unsigned int num_events
:6;
285 /* Handle to the DMAC provided to the PL330 core */
289 /* Size of MicroCode buffers for each channel. */
291 /* ioremap'ed address of PL330 registers. */
293 /* PL330 core data, Client must not touch it. */
295 /* Populated by the PL330 core driver during pl330_add */
296 struct pl330_config pcfg
;
300 * Request Configuration.
301 * The PL330 core does not modify this and uses the last
302 * working configuration if the request doesn't provide any.
304 * The Client may want to provide this info only for the
305 * first request and a request with new settings.
307 struct pl330_reqcfg
{
308 /* Address Incrementing */
313 * For now, the SRC & DST protection levels
314 * and burst size/length are assumed same.
320 unsigned brst_size
:3; /* in power of 2 */
322 enum pl330_cachectrl dcctl
;
323 enum pl330_cachectrl scctl
;
324 enum pl330_byteswap swap
;
325 struct pl330_config
*pcfg
;
329 * One cycle of DMAC operation.
330 * There may be more than one xfer in a request.
339 /* The xfer callbacks are made with one of these arguments. */
341 /* The all xfers in the request were success. */
343 /* If req aborted due to global error. */
345 /* If req failed due to problem with Channel. */
349 /* A request defining Scatter-Gather List ending with NULL xfer. */
351 enum dma_transfer_direction rqtype
;
352 /* Index of peripheral for the xfer. */
354 /* Unique token for this xfer, set by the client. */
356 /* Callback to be called after xfer. */
357 void (*xfer_cb
)(void *token
, enum pl330_op_err err
);
358 /* If NULL, req will be done at last set parameters. */
359 struct pl330_reqcfg
*cfg
;
360 /* Pointer to first xfer in the request. */
361 struct pl330_xfer
*x
;
362 /* Hook to attach to DMAC's list of reqs with due callback */
363 struct list_head rqd
;
367 /* Start the channel */
369 /* Abort the active xfer */
371 /* Stop xfer and flush queue */
378 struct pl330_xfer
*x
;
401 /* Number of bytes taken to setup MC for the req */
406 /* ToBeDone for tasklet */
414 struct pl330_thread
{
417 /* If the channel is not yet acquired by any client */
420 struct pl330_dmac
*dmac
;
421 /* Only two at a time */
422 struct _pl330_req req
[2];
423 /* Index of the last enqueued request */
425 /* Index of the last submitted request or -1 if the DMA is stopped */
429 enum pl330_dmac_state
{
438 /* Holds list of reqs with due callbacks */
439 struct list_head req_done
;
440 /* Pointer to platform specific stuff */
441 struct pl330_info
*pinfo
;
442 /* Maximum possible events/irqs */
444 /* BUS address of MicroCode buffer */
445 dma_addr_t mcode_bus
;
446 /* CPU address of MicroCode buffer */
448 /* List of all Channel threads */
449 struct pl330_thread
*channels
;
450 /* Pointer to the MANAGER thread */
451 struct pl330_thread
*manager
;
452 /* To handle bad news in interrupt */
453 struct tasklet_struct tasks
;
454 struct _pl330_tbd dmac_tbd
;
455 /* State of DMAC operation */
456 enum pl330_dmac_state state
;
460 /* In the DMAC pool */
463 * Allocated to some channel during prep_xxx
464 * Also may be sitting on the work_list.
468 * Sitting on the work_list and already submitted
469 * to the PL330 core. Not more than two descriptors
470 * of a channel can be BUSY at any time.
474 * Sitting on the channel work_list but xfer done
480 struct dma_pl330_chan
{
481 /* Schedule desc completion */
482 struct tasklet_struct task
;
484 /* DMA-Engine Channel */
485 struct dma_chan chan
;
487 /* List of submitted descriptors */
488 struct list_head submitted_list
;
489 /* List of issued descriptors */
490 struct list_head work_list
;
491 /* List of completed descriptors */
492 struct list_head completed_list
;
494 /* Pointer to the DMAC that manages this channel,
495 * NULL if the channel is available to be acquired.
496 * As the parent, this DMAC also provides descriptors
499 struct dma_pl330_dmac
*dmac
;
501 /* To protect channel manipulation */
504 /* Token of a hardware channel thread of PL330 DMAC
505 * NULL if the channel is available to be acquired.
509 /* For D-to-M and M-to-D channels */
510 int burst_sz
; /* the peripheral fifo width */
511 int burst_len
; /* the number of burst */
512 dma_addr_t fifo_addr
;
514 /* for cyclic capability */
518 struct dma_pl330_dmac
{
519 struct pl330_info pif
;
521 /* DMA-Engine Device */
522 struct dma_device ddma
;
524 /* Holds info about sg limitations */
525 struct device_dma_parameters dma_parms
;
527 /* Pool of descriptors available for the DMAC's channels */
528 struct list_head desc_pool
;
529 /* To protect desc_pool manipulation */
530 spinlock_t pool_lock
;
532 /* Peripheral channels connected to this DMAC */
533 unsigned int num_peripherals
;
534 struct dma_pl330_chan
*peripherals
; /* keep at end */
537 struct dma_pl330_desc
{
538 /* To attach to a queue as child */
539 struct list_head node
;
541 /* Descriptor for the DMA Engine API */
542 struct dma_async_tx_descriptor txd
;
544 /* Xfer for PL330 core */
545 struct pl330_xfer px
;
547 struct pl330_reqcfg rqcfg
;
548 struct pl330_req req
;
550 enum desc_status status
;
552 /* The channel which currently holds this desc */
553 struct dma_pl330_chan
*pchan
;
556 static inline void _callback(struct pl330_req
*r
, enum pl330_op_err err
)
559 r
->xfer_cb(r
->token
, err
);
562 static inline bool _queue_empty(struct pl330_thread
*thrd
)
564 return (IS_FREE(&thrd
->req
[0]) && IS_FREE(&thrd
->req
[1]))
568 static inline bool _queue_full(struct pl330_thread
*thrd
)
570 return (IS_FREE(&thrd
->req
[0]) || IS_FREE(&thrd
->req
[1]))
574 static inline bool is_manager(struct pl330_thread
*thrd
)
576 struct pl330_dmac
*pl330
= thrd
->dmac
;
578 /* MANAGER is indexed at the end */
579 if (thrd
->id
== pl330
->pinfo
->pcfg
.num_chan
)
585 /* If manager of the thread is in Non-Secure mode */
586 static inline bool _manager_ns(struct pl330_thread
*thrd
)
588 struct pl330_dmac
*pl330
= thrd
->dmac
;
590 return (pl330
->pinfo
->pcfg
.mode
& DMAC_MODE_NS
) ? true : false;
593 static inline u32
get_revision(u32 periph_id
)
595 return (periph_id
>> PERIPH_REV_SHIFT
) & PERIPH_REV_MASK
;
598 static inline u32
_emit_ADDH(unsigned dry_run
, u8 buf
[],
599 enum pl330_dst da
, u16 val
)
604 buf
[0] = CMD_DMAADDH
;
606 *((u16
*)&buf
[1]) = val
;
608 PL330_DBGCMD_DUMP(SZ_DMAADDH
, "\tDMAADDH %s %u\n",
609 da
== 1 ? "DA" : "SA", val
);
614 static inline u32
_emit_END(unsigned dry_run
, u8 buf
[])
621 PL330_DBGCMD_DUMP(SZ_DMAEND
, "\tDMAEND\n");
626 static inline u32
_emit_FLUSHP(unsigned dry_run
, u8 buf
[], u8 peri
)
631 buf
[0] = CMD_DMAFLUSHP
;
637 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP
, "\tDMAFLUSHP %u\n", peri
>> 3);
642 static inline u32
_emit_LD(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
650 buf
[0] |= (0 << 1) | (1 << 0);
651 else if (cond
== BURST
)
652 buf
[0] |= (1 << 1) | (1 << 0);
654 PL330_DBGCMD_DUMP(SZ_DMALD
, "\tDMALD%c\n",
655 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
660 static inline u32
_emit_LDP(unsigned dry_run
, u8 buf
[],
661 enum pl330_cond cond
, u8 peri
)
675 PL330_DBGCMD_DUMP(SZ_DMALDP
, "\tDMALDP%c %u\n",
676 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
681 static inline u32
_emit_LP(unsigned dry_run
, u8 buf
[],
682 unsigned loop
, u8 cnt
)
692 cnt
--; /* DMAC increments by 1 internally */
695 PL330_DBGCMD_DUMP(SZ_DMALP
, "\tDMALP_%c %u\n", loop
? '1' : '0', cnt
);
701 enum pl330_cond cond
;
707 static inline u32
_emit_LPEND(unsigned dry_run
, u8 buf
[],
708 const struct _arg_LPEND
*arg
)
710 enum pl330_cond cond
= arg
->cond
;
711 bool forever
= arg
->forever
;
712 unsigned loop
= arg
->loop
;
713 u8 bjump
= arg
->bjump
;
718 buf
[0] = CMD_DMALPEND
;
727 buf
[0] |= (0 << 1) | (1 << 0);
728 else if (cond
== BURST
)
729 buf
[0] |= (1 << 1) | (1 << 0);
733 PL330_DBGCMD_DUMP(SZ_DMALPEND
, "\tDMALP%s%c_%c bjmpto_%x\n",
734 forever
? "FE" : "END",
735 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'),
742 static inline u32
_emit_KILL(unsigned dry_run
, u8 buf
[])
747 buf
[0] = CMD_DMAKILL
;
752 static inline u32
_emit_MOV(unsigned dry_run
, u8 buf
[],
753 enum dmamov_dst dst
, u32 val
)
760 *((u32
*)&buf
[2]) = val
;
762 PL330_DBGCMD_DUMP(SZ_DMAMOV
, "\tDMAMOV %s 0x%x\n",
763 dst
== SAR
? "SAR" : (dst
== DAR
? "DAR" : "CCR"), val
);
768 static inline u32
_emit_NOP(unsigned dry_run
, u8 buf
[])
775 PL330_DBGCMD_DUMP(SZ_DMANOP
, "\tDMANOP\n");
780 static inline u32
_emit_RMB(unsigned dry_run
, u8 buf
[])
787 PL330_DBGCMD_DUMP(SZ_DMARMB
, "\tDMARMB\n");
792 static inline u32
_emit_SEV(unsigned dry_run
, u8 buf
[], u8 ev
)
803 PL330_DBGCMD_DUMP(SZ_DMASEV
, "\tDMASEV %u\n", ev
>> 3);
808 static inline u32
_emit_ST(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
816 buf
[0] |= (0 << 1) | (1 << 0);
817 else if (cond
== BURST
)
818 buf
[0] |= (1 << 1) | (1 << 0);
820 PL330_DBGCMD_DUMP(SZ_DMAST
, "\tDMAST%c\n",
821 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
826 static inline u32
_emit_STP(unsigned dry_run
, u8 buf
[],
827 enum pl330_cond cond
, u8 peri
)
841 PL330_DBGCMD_DUMP(SZ_DMASTP
, "\tDMASTP%c %u\n",
842 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
847 static inline u32
_emit_STZ(unsigned dry_run
, u8 buf
[])
854 PL330_DBGCMD_DUMP(SZ_DMASTZ
, "\tDMASTZ\n");
859 static inline u32
_emit_WFE(unsigned dry_run
, u8 buf
[], u8 ev
,
874 PL330_DBGCMD_DUMP(SZ_DMAWFE
, "\tDMAWFE %u%s\n",
875 ev
>> 3, invalidate
? ", I" : "");
880 static inline u32
_emit_WFP(unsigned dry_run
, u8 buf
[],
881 enum pl330_cond cond
, u8 peri
)
889 buf
[0] |= (0 << 1) | (0 << 0);
890 else if (cond
== BURST
)
891 buf
[0] |= (1 << 1) | (0 << 0);
893 buf
[0] |= (0 << 1) | (1 << 0);
899 PL330_DBGCMD_DUMP(SZ_DMAWFP
, "\tDMAWFP%c %u\n",
900 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'P'), peri
>> 3);
905 static inline u32
_emit_WMB(unsigned dry_run
, u8 buf
[])
912 PL330_DBGCMD_DUMP(SZ_DMAWMB
, "\tDMAWMB\n");
923 static inline u32
_emit_GO(unsigned dry_run
, u8 buf
[],
924 const struct _arg_GO
*arg
)
927 u32 addr
= arg
->addr
;
928 unsigned ns
= arg
->ns
;
938 *((u32
*)&buf
[2]) = addr
;
943 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
945 /* Returns Time-Out */
946 static bool _until_dmac_idle(struct pl330_thread
*thrd
)
948 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
949 unsigned long loops
= msecs_to_loops(5);
952 /* Until Manager is Idle */
953 if (!(readl(regs
+ DBGSTATUS
) & DBG_BUSY
))
965 static inline void _execute_DBGINSN(struct pl330_thread
*thrd
,
966 u8 insn
[], bool as_manager
)
968 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
971 val
= (insn
[0] << 16) | (insn
[1] << 24);
974 val
|= (thrd
->id
<< 8); /* Channel Number */
976 writel(val
, regs
+ DBGINST0
);
978 val
= *((u32
*)&insn
[2]);
979 writel(val
, regs
+ DBGINST1
);
981 /* If timed out due to halted state-machine */
982 if (_until_dmac_idle(thrd
)) {
983 dev_err(thrd
->dmac
->pinfo
->dev
, "DMAC halted!\n");
988 writel(0, regs
+ DBGCMD
);
992 * Mark a _pl330_req as free.
993 * We do it by writing DMAEND as the first instruction
994 * because no valid request is going to have DMAEND as
995 * its first instruction to execute.
997 static void mark_free(struct pl330_thread
*thrd
, int idx
)
999 struct _pl330_req
*req
= &thrd
->req
[idx
];
1001 _emit_END(0, req
->mc_cpu
);
1004 thrd
->req_running
= -1;
1007 static inline u32
_state(struct pl330_thread
*thrd
)
1009 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1012 if (is_manager(thrd
))
1013 val
= readl(regs
+ DS
) & 0xf;
1015 val
= readl(regs
+ CS(thrd
->id
)) & 0xf;
1019 return PL330_STATE_STOPPED
;
1021 return PL330_STATE_EXECUTING
;
1023 return PL330_STATE_CACHEMISS
;
1025 return PL330_STATE_UPDTPC
;
1027 return PL330_STATE_WFE
;
1029 return PL330_STATE_FAULTING
;
1031 if (is_manager(thrd
))
1032 return PL330_STATE_INVALID
;
1034 return PL330_STATE_ATBARRIER
;
1036 if (is_manager(thrd
))
1037 return PL330_STATE_INVALID
;
1039 return PL330_STATE_QUEUEBUSY
;
1041 if (is_manager(thrd
))
1042 return PL330_STATE_INVALID
;
1044 return PL330_STATE_WFP
;
1046 if (is_manager(thrd
))
1047 return PL330_STATE_INVALID
;
1049 return PL330_STATE_KILLING
;
1051 if (is_manager(thrd
))
1052 return PL330_STATE_INVALID
;
1054 return PL330_STATE_COMPLETING
;
1056 if (is_manager(thrd
))
1057 return PL330_STATE_INVALID
;
1059 return PL330_STATE_FAULT_COMPLETING
;
1061 return PL330_STATE_INVALID
;
1065 static void _stop(struct pl330_thread
*thrd
)
1067 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1068 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1070 if (_state(thrd
) == PL330_STATE_FAULT_COMPLETING
)
1071 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1073 /* Return if nothing needs to be done */
1074 if (_state(thrd
) == PL330_STATE_COMPLETING
1075 || _state(thrd
) == PL330_STATE_KILLING
1076 || _state(thrd
) == PL330_STATE_STOPPED
)
1079 _emit_KILL(0, insn
);
1081 /* Stop generating interrupts for SEV */
1082 writel(readl(regs
+ INTEN
) & ~(1 << thrd
->ev
), regs
+ INTEN
);
1084 _execute_DBGINSN(thrd
, insn
, is_manager(thrd
));
1087 /* Start doing req 'idx' of thread 'thrd' */
1088 static bool _trigger(struct pl330_thread
*thrd
)
1090 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1091 struct _pl330_req
*req
;
1092 struct pl330_req
*r
;
1095 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1098 /* Return if already ACTIVE */
1099 if (_state(thrd
) != PL330_STATE_STOPPED
)
1102 idx
= 1 - thrd
->lstenq
;
1103 if (!IS_FREE(&thrd
->req
[idx
]))
1104 req
= &thrd
->req
[idx
];
1107 if (!IS_FREE(&thrd
->req
[idx
]))
1108 req
= &thrd
->req
[idx
];
1113 /* Return if no request */
1114 if (!req
|| !req
->r
)
1120 ns
= r
->cfg
->nonsecure
? 1 : 0;
1121 else if (readl(regs
+ CS(thrd
->id
)) & CS_CNS
)
1126 /* See 'Abort Sources' point-4 at Page 2-25 */
1127 if (_manager_ns(thrd
) && !ns
)
1128 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d Recipe for ABORT!\n",
1129 __func__
, __LINE__
);
1132 go
.addr
= req
->mc_bus
;
1134 _emit_GO(0, insn
, &go
);
1136 /* Set to generate interrupts for SEV */
1137 writel(readl(regs
+ INTEN
) | (1 << thrd
->ev
), regs
+ INTEN
);
1139 /* Only manager can execute GO */
1140 _execute_DBGINSN(thrd
, insn
, true);
1142 thrd
->req_running
= idx
;
1147 static bool _start(struct pl330_thread
*thrd
)
1149 switch (_state(thrd
)) {
1150 case PL330_STATE_FAULT_COMPLETING
:
1151 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1153 if (_state(thrd
) == PL330_STATE_KILLING
)
1154 UNTIL(thrd
, PL330_STATE_STOPPED
)
1156 case PL330_STATE_FAULTING
:
1159 case PL330_STATE_KILLING
:
1160 case PL330_STATE_COMPLETING
:
1161 UNTIL(thrd
, PL330_STATE_STOPPED
)
1163 case PL330_STATE_STOPPED
:
1164 return _trigger(thrd
);
1166 case PL330_STATE_WFP
:
1167 case PL330_STATE_QUEUEBUSY
:
1168 case PL330_STATE_ATBARRIER
:
1169 case PL330_STATE_UPDTPC
:
1170 case PL330_STATE_CACHEMISS
:
1171 case PL330_STATE_EXECUTING
:
1174 case PL330_STATE_WFE
: /* For RESUME, nothing yet */
1180 static inline int _ldst_memtomem(unsigned dry_run
, u8 buf
[],
1181 const struct _xfer_spec
*pxs
, int cyc
)
1184 struct pl330_config
*pcfg
= pxs
->r
->cfg
->pcfg
;
1186 /* check lock-up free version */
1187 if (get_revision(pcfg
->periph_id
) >= PERIPH_REV_R1P0
) {
1189 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1190 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1194 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1195 off
+= _emit_RMB(dry_run
, &buf
[off
]);
1196 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1197 off
+= _emit_WMB(dry_run
, &buf
[off
]);
1204 static inline int _ldst_devtomem(unsigned dry_run
, u8 buf
[],
1205 const struct _xfer_spec
*pxs
, int cyc
)
1210 off
+= _emit_WFP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1211 off
+= _emit_LDP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1212 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1213 off
+= _emit_FLUSHP(dry_run
, &buf
[off
], pxs
->r
->peri
);
1219 static inline int _ldst_memtodev(unsigned dry_run
, u8 buf
[],
1220 const struct _xfer_spec
*pxs
, int cyc
)
1225 off
+= _emit_WFP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1226 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1227 off
+= _emit_STP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1228 off
+= _emit_FLUSHP(dry_run
, &buf
[off
], pxs
->r
->peri
);
1234 static int _bursts(unsigned dry_run
, u8 buf
[],
1235 const struct _xfer_spec
*pxs
, int cyc
)
1239 switch (pxs
->r
->rqtype
) {
1240 case DMA_MEM_TO_DEV
:
1241 off
+= _ldst_memtodev(dry_run
, &buf
[off
], pxs
, cyc
);
1243 case DMA_DEV_TO_MEM
:
1244 off
+= _ldst_devtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1246 case DMA_MEM_TO_MEM
:
1247 off
+= _ldst_memtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1250 off
+= 0x40000000; /* Scare off the Client */
1257 /* Returns bytes consumed and updates bursts */
1258 static inline int _loop(unsigned dry_run
, u8 buf
[],
1259 unsigned long *bursts
, const struct _xfer_spec
*pxs
)
1261 int cyc
, cycmax
, szlp
, szlpend
, szbrst
, off
;
1262 unsigned lcnt0
, lcnt1
, ljmp0
, ljmp1
;
1263 struct _arg_LPEND lpend
;
1265 /* Max iterations possible in DMALP is 256 */
1266 if (*bursts
>= 256*256) {
1269 cyc
= *bursts
/ lcnt1
/ lcnt0
;
1270 } else if (*bursts
> 256) {
1272 lcnt0
= *bursts
/ lcnt1
;
1280 szlp
= _emit_LP(1, buf
, 0, 0);
1281 szbrst
= _bursts(1, buf
, pxs
, 1);
1283 lpend
.cond
= ALWAYS
;
1284 lpend
.forever
= false;
1287 szlpend
= _emit_LPEND(1, buf
, &lpend
);
1295 * Max bursts that we can unroll due to limit on the
1296 * size of backward jump that can be encoded in DMALPEND
1297 * which is 8-bits and hence 255
1299 cycmax
= (255 - (szlp
+ szlpend
)) / szbrst
;
1301 cyc
= (cycmax
< cyc
) ? cycmax
: cyc
;
1306 off
+= _emit_LP(dry_run
, &buf
[off
], 0, lcnt0
);
1310 off
+= _emit_LP(dry_run
, &buf
[off
], 1, lcnt1
);
1313 off
+= _bursts(dry_run
, &buf
[off
], pxs
, cyc
);
1315 lpend
.cond
= ALWAYS
;
1316 lpend
.forever
= false;
1318 lpend
.bjump
= off
- ljmp1
;
1319 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1322 lpend
.cond
= ALWAYS
;
1323 lpend
.forever
= false;
1325 lpend
.bjump
= off
- ljmp0
;
1326 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1329 *bursts
= lcnt1
* cyc
;
1336 static inline int _setup_loops(unsigned dry_run
, u8 buf
[],
1337 const struct _xfer_spec
*pxs
)
1339 struct pl330_xfer
*x
= pxs
->x
;
1341 unsigned long c
, bursts
= BYTE_TO_BURST(x
->bytes
, ccr
);
1346 off
+= _loop(dry_run
, &buf
[off
], &c
, pxs
);
1353 static inline int _setup_xfer(unsigned dry_run
, u8 buf
[],
1354 const struct _xfer_spec
*pxs
)
1356 struct pl330_xfer
*x
= pxs
->x
;
1359 /* DMAMOV SAR, x->src_addr */
1360 off
+= _emit_MOV(dry_run
, &buf
[off
], SAR
, x
->src_addr
);
1361 /* DMAMOV DAR, x->dst_addr */
1362 off
+= _emit_MOV(dry_run
, &buf
[off
], DAR
, x
->dst_addr
);
1365 off
+= _setup_loops(dry_run
, &buf
[off
], pxs
);
1371 * A req is a sequence of one or more xfer units.
1372 * Returns the number of bytes taken to setup the MC for the req.
1374 static int _setup_req(unsigned dry_run
, struct pl330_thread
*thrd
,
1375 unsigned index
, struct _xfer_spec
*pxs
)
1377 struct _pl330_req
*req
= &thrd
->req
[index
];
1378 struct pl330_xfer
*x
;
1379 u8
*buf
= req
->mc_cpu
;
1382 PL330_DBGMC_START(req
->mc_bus
);
1384 /* DMAMOV CCR, ccr */
1385 off
+= _emit_MOV(dry_run
, &buf
[off
], CCR
, pxs
->ccr
);
1388 /* Error if xfer length is not aligned at burst size */
1389 if (x
->bytes
% (BRST_SIZE(pxs
->ccr
) * BRST_LEN(pxs
->ccr
)))
1393 off
+= _setup_xfer(dry_run
, &buf
[off
], pxs
);
1395 /* DMASEV peripheral/event */
1396 off
+= _emit_SEV(dry_run
, &buf
[off
], thrd
->ev
);
1398 off
+= _emit_END(dry_run
, &buf
[off
]);
1403 static inline u32
_prepare_ccr(const struct pl330_reqcfg
*rqc
)
1413 /* We set same protection levels for Src and DST for now */
1414 if (rqc
->privileged
)
1415 ccr
|= CC_SRCPRI
| CC_DSTPRI
;
1417 ccr
|= CC_SRCNS
| CC_DSTNS
;
1418 if (rqc
->insnaccess
)
1419 ccr
|= CC_SRCIA
| CC_DSTIA
;
1421 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_SRCBRSTLEN_SHFT
);
1422 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_DSTBRSTLEN_SHFT
);
1424 ccr
|= (rqc
->brst_size
<< CC_SRCBRSTSIZE_SHFT
);
1425 ccr
|= (rqc
->brst_size
<< CC_DSTBRSTSIZE_SHFT
);
1427 ccr
|= (rqc
->scctl
<< CC_SRCCCTRL_SHFT
);
1428 ccr
|= (rqc
->dcctl
<< CC_DSTCCTRL_SHFT
);
1430 ccr
|= (rqc
->swap
<< CC_SWAP_SHFT
);
1435 static inline bool _is_valid(u32 ccr
)
1437 enum pl330_cachectrl dcctl
;
1438 enum pl330_cachectrl scctl
;
1440 dcctl
= (ccr
>> CC_DSTCCTRL_SHFT
) & CC_DRCCCTRL_MASK
;
1441 scctl
= (ccr
>> CC_SRCCCTRL_SHFT
) & CC_SRCCCTRL_MASK
;
1443 if (dcctl
== INVALID1
|| dcctl
== INVALID2
1444 || scctl
== INVALID1
|| scctl
== INVALID2
)
1451 * Submit a list of xfers after which the client wants notification.
1452 * Client is not notified after each xfer unit, just once after all
1453 * xfer units are done or some error occurs.
1455 static int pl330_submit_req(void *ch_id
, struct pl330_req
*r
)
1457 struct pl330_thread
*thrd
= ch_id
;
1458 struct pl330_dmac
*pl330
;
1459 struct pl330_info
*pi
;
1460 struct _xfer_spec xs
;
1461 unsigned long flags
;
1467 /* No Req or Unacquired Channel or DMAC */
1468 if (!r
|| !thrd
|| thrd
->free
)
1475 if (pl330
->state
== DYING
1476 || pl330
->dmac_tbd
.reset_chan
& (1 << thrd
->id
)) {
1477 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d\n",
1478 __func__
, __LINE__
);
1482 /* If request for non-existing peripheral */
1483 if (r
->rqtype
!= DMA_MEM_TO_MEM
&& r
->peri
>= pi
->pcfg
.num_peri
) {
1484 dev_info(thrd
->dmac
->pinfo
->dev
,
1485 "%s:%d Invalid peripheral(%u)!\n",
1486 __func__
, __LINE__
, r
->peri
);
1490 spin_lock_irqsave(&pl330
->lock
, flags
);
1492 if (_queue_full(thrd
)) {
1498 /* Use last settings, if not provided */
1500 /* Prefer Secure Channel */
1501 if (!_manager_ns(thrd
))
1502 r
->cfg
->nonsecure
= 0;
1504 r
->cfg
->nonsecure
= 1;
1506 ccr
= _prepare_ccr(r
->cfg
);
1508 ccr
= readl(regs
+ CC(thrd
->id
));
1511 /* If this req doesn't have valid xfer settings */
1512 if (!_is_valid(ccr
)) {
1514 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d Invalid CCR(%x)!\n",
1515 __func__
, __LINE__
, ccr
);
1519 idx
= IS_FREE(&thrd
->req
[0]) ? 0 : 1;
1524 /* First dry run to check if req is acceptable */
1525 ret
= _setup_req(1, thrd
, idx
, &xs
);
1529 if (ret
> pi
->mcbufsz
/ 2) {
1530 dev_info(thrd
->dmac
->pinfo
->dev
,
1531 "%s:%d Trying increasing mcbufsz\n",
1532 __func__
, __LINE__
);
1537 /* Hook the request */
1539 thrd
->req
[idx
].mc_len
= _setup_req(0, thrd
, idx
, &xs
);
1540 thrd
->req
[idx
].r
= r
;
1545 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1550 static void pl330_dotask(unsigned long data
)
1552 struct pl330_dmac
*pl330
= (struct pl330_dmac
*) data
;
1553 struct pl330_info
*pi
= pl330
->pinfo
;
1554 unsigned long flags
;
1557 spin_lock_irqsave(&pl330
->lock
, flags
);
1559 /* The DMAC itself gone nuts */
1560 if (pl330
->dmac_tbd
.reset_dmac
) {
1561 pl330
->state
= DYING
;
1562 /* Reset the manager too */
1563 pl330
->dmac_tbd
.reset_mngr
= true;
1564 /* Clear the reset flag */
1565 pl330
->dmac_tbd
.reset_dmac
= false;
1568 if (pl330
->dmac_tbd
.reset_mngr
) {
1569 _stop(pl330
->manager
);
1570 /* Reset all channels */
1571 pl330
->dmac_tbd
.reset_chan
= (1 << pi
->pcfg
.num_chan
) - 1;
1572 /* Clear the reset flag */
1573 pl330
->dmac_tbd
.reset_mngr
= false;
1576 for (i
= 0; i
< pi
->pcfg
.num_chan
; i
++) {
1578 if (pl330
->dmac_tbd
.reset_chan
& (1 << i
)) {
1579 struct pl330_thread
*thrd
= &pl330
->channels
[i
];
1580 void __iomem
*regs
= pi
->base
;
1581 enum pl330_op_err err
;
1585 if (readl(regs
+ FSC
) & (1 << thrd
->id
))
1586 err
= PL330_ERR_FAIL
;
1588 err
= PL330_ERR_ABORT
;
1590 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1592 _callback(thrd
->req
[1 - thrd
->lstenq
].r
, err
);
1593 _callback(thrd
->req
[thrd
->lstenq
].r
, err
);
1595 spin_lock_irqsave(&pl330
->lock
, flags
);
1597 thrd
->req
[0].r
= NULL
;
1598 thrd
->req
[1].r
= NULL
;
1602 /* Clear the reset flag */
1603 pl330
->dmac_tbd
.reset_chan
&= ~(1 << i
);
1607 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1612 /* Returns 1 if state was updated, 0 otherwise */
1613 static int pl330_update(const struct pl330_info
*pi
)
1615 struct pl330_req
*rqdone
, *tmp
;
1616 struct pl330_dmac
*pl330
;
1617 unsigned long flags
;
1620 int id
, ev
, ret
= 0;
1622 if (!pi
|| !pi
->pl330_data
)
1626 pl330
= pi
->pl330_data
;
1628 spin_lock_irqsave(&pl330
->lock
, flags
);
1630 val
= readl(regs
+ FSM
) & 0x1;
1632 pl330
->dmac_tbd
.reset_mngr
= true;
1634 pl330
->dmac_tbd
.reset_mngr
= false;
1636 val
= readl(regs
+ FSC
) & ((1 << pi
->pcfg
.num_chan
) - 1);
1637 pl330
->dmac_tbd
.reset_chan
|= val
;
1640 while (i
< pi
->pcfg
.num_chan
) {
1641 if (val
& (1 << i
)) {
1643 "Reset Channel-%d\t CS-%x FTC-%x\n",
1644 i
, readl(regs
+ CS(i
)),
1645 readl(regs
+ FTC(i
)));
1646 _stop(&pl330
->channels
[i
]);
1652 /* Check which event happened i.e, thread notified */
1653 val
= readl(regs
+ ES
);
1654 if (pi
->pcfg
.num_events
< 32
1655 && val
& ~((1 << pi
->pcfg
.num_events
) - 1)) {
1656 pl330
->dmac_tbd
.reset_dmac
= true;
1657 dev_err(pi
->dev
, "%s:%d Unexpected!\n", __func__
, __LINE__
);
1662 for (ev
= 0; ev
< pi
->pcfg
.num_events
; ev
++) {
1663 if (val
& (1 << ev
)) { /* Event occurred */
1664 struct pl330_thread
*thrd
;
1665 u32 inten
= readl(regs
+ INTEN
);
1668 /* Clear the event */
1669 if (inten
& (1 << ev
))
1670 writel(1 << ev
, regs
+ INTCLR
);
1674 id
= pl330
->events
[ev
];
1676 thrd
= &pl330
->channels
[id
];
1678 active
= thrd
->req_running
;
1679 if (active
== -1) /* Aborted */
1682 /* Detach the req */
1683 rqdone
= thrd
->req
[active
].r
;
1684 thrd
->req
[active
].r
= NULL
;
1686 mark_free(thrd
, active
);
1688 /* Get going again ASAP */
1691 /* For now, just make a list of callbacks to be done */
1692 list_add_tail(&rqdone
->rqd
, &pl330
->req_done
);
1696 /* Now that we are in no hurry, do the callbacks */
1697 list_for_each_entry_safe(rqdone
, tmp
, &pl330
->req_done
, rqd
) {
1698 list_del(&rqdone
->rqd
);
1700 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1701 _callback(rqdone
, PL330_ERR_NONE
);
1702 spin_lock_irqsave(&pl330
->lock
, flags
);
1706 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1708 if (pl330
->dmac_tbd
.reset_dmac
1709 || pl330
->dmac_tbd
.reset_mngr
1710 || pl330
->dmac_tbd
.reset_chan
) {
1712 tasklet_schedule(&pl330
->tasks
);
1718 static int pl330_chan_ctrl(void *ch_id
, enum pl330_chan_op op
)
1720 struct pl330_thread
*thrd
= ch_id
;
1721 struct pl330_dmac
*pl330
;
1722 unsigned long flags
;
1723 int ret
= 0, active
;
1725 if (!thrd
|| thrd
->free
|| thrd
->dmac
->state
== DYING
)
1729 active
= thrd
->req_running
;
1731 spin_lock_irqsave(&pl330
->lock
, flags
);
1734 case PL330_OP_FLUSH
:
1735 /* Make sure the channel is stopped */
1738 thrd
->req
[0].r
= NULL
;
1739 thrd
->req
[1].r
= NULL
;
1744 case PL330_OP_ABORT
:
1745 /* Make sure the channel is stopped */
1748 /* ABORT is only for the active req */
1752 thrd
->req
[active
].r
= NULL
;
1753 mark_free(thrd
, active
);
1755 /* Start the next */
1756 case PL330_OP_START
:
1757 if ((active
== -1) && !_start(thrd
))
1765 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1769 /* Reserve an event */
1770 static inline int _alloc_event(struct pl330_thread
*thrd
)
1772 struct pl330_dmac
*pl330
= thrd
->dmac
;
1773 struct pl330_info
*pi
= pl330
->pinfo
;
1776 for (ev
= 0; ev
< pi
->pcfg
.num_events
; ev
++)
1777 if (pl330
->events
[ev
] == -1) {
1778 pl330
->events
[ev
] = thrd
->id
;
1785 static bool _chan_ns(const struct pl330_info
*pi
, int i
)
1787 return pi
->pcfg
.irq_ns
& (1 << i
);
1790 /* Upon success, returns IdentityToken for the
1791 * allocated channel, NULL otherwise.
1793 static void *pl330_request_channel(const struct pl330_info
*pi
)
1795 struct pl330_thread
*thrd
= NULL
;
1796 struct pl330_dmac
*pl330
;
1797 unsigned long flags
;
1800 if (!pi
|| !pi
->pl330_data
)
1803 pl330
= pi
->pl330_data
;
1805 if (pl330
->state
== DYING
)
1808 chans
= pi
->pcfg
.num_chan
;
1810 spin_lock_irqsave(&pl330
->lock
, flags
);
1812 for (i
= 0; i
< chans
; i
++) {
1813 thrd
= &pl330
->channels
[i
];
1814 if ((thrd
->free
) && (!_manager_ns(thrd
) ||
1816 thrd
->ev
= _alloc_event(thrd
);
1817 if (thrd
->ev
>= 0) {
1820 thrd
->req
[0].r
= NULL
;
1822 thrd
->req
[1].r
= NULL
;
1830 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1835 /* Release an event */
1836 static inline void _free_event(struct pl330_thread
*thrd
, int ev
)
1838 struct pl330_dmac
*pl330
= thrd
->dmac
;
1839 struct pl330_info
*pi
= pl330
->pinfo
;
1841 /* If the event is valid and was held by the thread */
1842 if (ev
>= 0 && ev
< pi
->pcfg
.num_events
1843 && pl330
->events
[ev
] == thrd
->id
)
1844 pl330
->events
[ev
] = -1;
1847 static void pl330_release_channel(void *ch_id
)
1849 struct pl330_thread
*thrd
= ch_id
;
1850 struct pl330_dmac
*pl330
;
1851 unsigned long flags
;
1853 if (!thrd
|| thrd
->free
)
1858 _callback(thrd
->req
[1 - thrd
->lstenq
].r
, PL330_ERR_ABORT
);
1859 _callback(thrd
->req
[thrd
->lstenq
].r
, PL330_ERR_ABORT
);
1863 spin_lock_irqsave(&pl330
->lock
, flags
);
1864 _free_event(thrd
, thrd
->ev
);
1866 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1869 /* Initialize the structure for PL330 configuration, that can be used
1870 * by the client driver the make best use of the DMAC
1872 static void read_dmac_config(struct pl330_info
*pi
)
1874 void __iomem
*regs
= pi
->base
;
1877 val
= readl(regs
+ CRD
) >> CRD_DATA_WIDTH_SHIFT
;
1878 val
&= CRD_DATA_WIDTH_MASK
;
1879 pi
->pcfg
.data_bus_width
= 8 * (1 << val
);
1881 val
= readl(regs
+ CRD
) >> CRD_DATA_BUFF_SHIFT
;
1882 val
&= CRD_DATA_BUFF_MASK
;
1883 pi
->pcfg
.data_buf_dep
= val
+ 1;
1885 val
= readl(regs
+ CR0
) >> CR0_NUM_CHANS_SHIFT
;
1886 val
&= CR0_NUM_CHANS_MASK
;
1888 pi
->pcfg
.num_chan
= val
;
1890 val
= readl(regs
+ CR0
);
1891 if (val
& CR0_PERIPH_REQ_SET
) {
1892 val
= (val
>> CR0_NUM_PERIPH_SHIFT
) & CR0_NUM_PERIPH_MASK
;
1894 pi
->pcfg
.num_peri
= val
;
1895 pi
->pcfg
.peri_ns
= readl(regs
+ CR4
);
1897 pi
->pcfg
.num_peri
= 0;
1900 val
= readl(regs
+ CR0
);
1901 if (val
& CR0_BOOT_MAN_NS
)
1902 pi
->pcfg
.mode
|= DMAC_MODE_NS
;
1904 pi
->pcfg
.mode
&= ~DMAC_MODE_NS
;
1906 val
= readl(regs
+ CR0
) >> CR0_NUM_EVENTS_SHIFT
;
1907 val
&= CR0_NUM_EVENTS_MASK
;
1909 pi
->pcfg
.num_events
= val
;
1911 pi
->pcfg
.irq_ns
= readl(regs
+ CR3
);
1914 static inline void _reset_thread(struct pl330_thread
*thrd
)
1916 struct pl330_dmac
*pl330
= thrd
->dmac
;
1917 struct pl330_info
*pi
= pl330
->pinfo
;
1919 thrd
->req
[0].mc_cpu
= pl330
->mcode_cpu
1920 + (thrd
->id
* pi
->mcbufsz
);
1921 thrd
->req
[0].mc_bus
= pl330
->mcode_bus
1922 + (thrd
->id
* pi
->mcbufsz
);
1923 thrd
->req
[0].r
= NULL
;
1926 thrd
->req
[1].mc_cpu
= thrd
->req
[0].mc_cpu
1928 thrd
->req
[1].mc_bus
= thrd
->req
[0].mc_bus
1930 thrd
->req
[1].r
= NULL
;
1934 static int dmac_alloc_threads(struct pl330_dmac
*pl330
)
1936 struct pl330_info
*pi
= pl330
->pinfo
;
1937 int chans
= pi
->pcfg
.num_chan
;
1938 struct pl330_thread
*thrd
;
1941 /* Allocate 1 Manager and 'chans' Channel threads */
1942 pl330
->channels
= kzalloc((1 + chans
) * sizeof(*thrd
),
1944 if (!pl330
->channels
)
1947 /* Init Channel threads */
1948 for (i
= 0; i
< chans
; i
++) {
1949 thrd
= &pl330
->channels
[i
];
1952 _reset_thread(thrd
);
1956 /* MANAGER is indexed at the end */
1957 thrd
= &pl330
->channels
[chans
];
1961 pl330
->manager
= thrd
;
1966 static int dmac_alloc_resources(struct pl330_dmac
*pl330
)
1968 struct pl330_info
*pi
= pl330
->pinfo
;
1969 int chans
= pi
->pcfg
.num_chan
;
1973 * Alloc MicroCode buffer for 'chans' Channel threads.
1974 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1976 pl330
->mcode_cpu
= dma_alloc_coherent(pi
->dev
,
1977 chans
* pi
->mcbufsz
,
1978 &pl330
->mcode_bus
, GFP_KERNEL
);
1979 if (!pl330
->mcode_cpu
) {
1980 dev_err(pi
->dev
, "%s:%d Can't allocate memory!\n",
1981 __func__
, __LINE__
);
1985 ret
= dmac_alloc_threads(pl330
);
1987 dev_err(pi
->dev
, "%s:%d Can't to create channels for DMAC!\n",
1988 __func__
, __LINE__
);
1989 dma_free_coherent(pi
->dev
,
1990 chans
* pi
->mcbufsz
,
1991 pl330
->mcode_cpu
, pl330
->mcode_bus
);
1998 static int pl330_add(struct pl330_info
*pi
)
2000 struct pl330_dmac
*pl330
;
2004 if (!pi
|| !pi
->dev
)
2007 /* If already added */
2013 /* Check if we can handle this DMAC */
2014 if ((pi
->pcfg
.periph_id
& 0xfffff) != PERIPH_ID_VAL
) {
2015 dev_err(pi
->dev
, "PERIPH_ID 0x%x !\n", pi
->pcfg
.periph_id
);
2019 /* Read the configuration of the DMAC */
2020 read_dmac_config(pi
);
2022 if (pi
->pcfg
.num_events
== 0) {
2023 dev_err(pi
->dev
, "%s:%d Can't work without events!\n",
2024 __func__
, __LINE__
);
2028 pl330
= kzalloc(sizeof(*pl330
), GFP_KERNEL
);
2030 dev_err(pi
->dev
, "%s:%d Can't allocate memory!\n",
2031 __func__
, __LINE__
);
2035 /* Assign the info structure and private data */
2037 pi
->pl330_data
= pl330
;
2039 spin_lock_init(&pl330
->lock
);
2041 INIT_LIST_HEAD(&pl330
->req_done
);
2043 /* Use default MC buffer size if not provided */
2045 pi
->mcbufsz
= MCODE_BUFF_PER_REQ
* 2;
2047 /* Mark all events as free */
2048 for (i
= 0; i
< pi
->pcfg
.num_events
; i
++)
2049 pl330
->events
[i
] = -1;
2051 /* Allocate resources needed by the DMAC */
2052 ret
= dmac_alloc_resources(pl330
);
2054 dev_err(pi
->dev
, "Unable to create channels for DMAC\n");
2059 tasklet_init(&pl330
->tasks
, pl330_dotask
, (unsigned long) pl330
);
2061 pl330
->state
= INIT
;
2066 static int dmac_free_threads(struct pl330_dmac
*pl330
)
2068 struct pl330_info
*pi
= pl330
->pinfo
;
2069 int chans
= pi
->pcfg
.num_chan
;
2070 struct pl330_thread
*thrd
;
2073 /* Release Channel threads */
2074 for (i
= 0; i
< chans
; i
++) {
2075 thrd
= &pl330
->channels
[i
];
2076 pl330_release_channel((void *)thrd
);
2080 kfree(pl330
->channels
);
2085 static void dmac_free_resources(struct pl330_dmac
*pl330
)
2087 struct pl330_info
*pi
= pl330
->pinfo
;
2088 int chans
= pi
->pcfg
.num_chan
;
2090 dmac_free_threads(pl330
);
2092 dma_free_coherent(pi
->dev
, chans
* pi
->mcbufsz
,
2093 pl330
->mcode_cpu
, pl330
->mcode_bus
);
2096 static void pl330_del(struct pl330_info
*pi
)
2098 struct pl330_dmac
*pl330
;
2100 if (!pi
|| !pi
->pl330_data
)
2103 pl330
= pi
->pl330_data
;
2105 pl330
->state
= UNINIT
;
2107 tasklet_kill(&pl330
->tasks
);
2109 /* Free DMAC resources */
2110 dmac_free_resources(pl330
);
2113 pi
->pl330_data
= NULL
;
2116 /* forward declaration */
2117 static struct amba_driver pl330_driver
;
2119 static inline struct dma_pl330_chan
*
2120 to_pchan(struct dma_chan
*ch
)
2125 return container_of(ch
, struct dma_pl330_chan
, chan
);
2128 static inline struct dma_pl330_desc
*
2129 to_desc(struct dma_async_tx_descriptor
*tx
)
2131 return container_of(tx
, struct dma_pl330_desc
, txd
);
2134 static inline void fill_queue(struct dma_pl330_chan
*pch
)
2136 struct dma_pl330_desc
*desc
;
2139 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2141 /* If already submitted */
2142 if (desc
->status
== BUSY
)
2145 ret
= pl330_submit_req(pch
->pl330_chid
,
2148 desc
->status
= BUSY
;
2149 } else if (ret
== -EAGAIN
) {
2150 /* QFull or DMAC Dying */
2153 /* Unacceptable request */
2154 desc
->status
= DONE
;
2155 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Bad Desc(%d)\n",
2156 __func__
, __LINE__
, desc
->txd
.cookie
);
2157 tasklet_schedule(&pch
->task
);
2162 static void pl330_tasklet(unsigned long data
)
2164 struct dma_pl330_chan
*pch
= (struct dma_pl330_chan
*)data
;
2165 struct dma_pl330_desc
*desc
, *_dt
;
2166 unsigned long flags
;
2168 spin_lock_irqsave(&pch
->lock
, flags
);
2170 /* Pick up ripe tomatoes */
2171 list_for_each_entry_safe(desc
, _dt
, &pch
->work_list
, node
)
2172 if (desc
->status
== DONE
) {
2174 dma_cookie_complete(&desc
->txd
);
2175 list_move_tail(&desc
->node
, &pch
->completed_list
);
2178 /* Try to submit a req imm. next to the last completed cookie */
2181 /* Make sure the PL330 Channel thread is active */
2182 pl330_chan_ctrl(pch
->pl330_chid
, PL330_OP_START
);
2184 while (!list_empty(&pch
->completed_list
)) {
2185 dma_async_tx_callback callback
;
2186 void *callback_param
;
2188 desc
= list_first_entry(&pch
->completed_list
,
2189 struct dma_pl330_desc
, node
);
2191 callback
= desc
->txd
.callback
;
2192 callback_param
= desc
->txd
.callback_param
;
2195 desc
->status
= PREP
;
2196 list_move_tail(&desc
->node
, &pch
->work_list
);
2198 desc
->status
= FREE
;
2199 list_move_tail(&desc
->node
, &pch
->dmac
->desc_pool
);
2202 dma_descriptor_unmap(&desc
->txd
);
2205 spin_unlock_irqrestore(&pch
->lock
, flags
);
2206 callback(callback_param
);
2207 spin_lock_irqsave(&pch
->lock
, flags
);
2210 spin_unlock_irqrestore(&pch
->lock
, flags
);
2213 static void dma_pl330_rqcb(void *token
, enum pl330_op_err err
)
2215 struct dma_pl330_desc
*desc
= token
;
2216 struct dma_pl330_chan
*pch
= desc
->pchan
;
2217 unsigned long flags
;
2219 /* If desc aborted */
2223 spin_lock_irqsave(&pch
->lock
, flags
);
2225 desc
->status
= DONE
;
2227 spin_unlock_irqrestore(&pch
->lock
, flags
);
2229 tasklet_schedule(&pch
->task
);
2232 bool pl330_filter(struct dma_chan
*chan
, void *param
)
2236 if (chan
->device
->dev
->driver
!= &pl330_driver
.drv
)
2239 peri_id
= chan
->private;
2240 return *peri_id
== (unsigned long)param
;
2242 EXPORT_SYMBOL(pl330_filter
);
2244 static struct dma_chan
*of_dma_pl330_xlate(struct of_phandle_args
*dma_spec
,
2245 struct of_dma
*ofdma
)
2247 int count
= dma_spec
->args_count
;
2248 struct dma_pl330_dmac
*pdmac
= ofdma
->of_dma_data
;
2249 unsigned int chan_id
;
2254 chan_id
= dma_spec
->args
[0];
2255 if (chan_id
>= pdmac
->num_peripherals
)
2258 return dma_get_slave_channel(&pdmac
->peripherals
[chan_id
].chan
);
2261 static int pl330_alloc_chan_resources(struct dma_chan
*chan
)
2263 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2264 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2265 unsigned long flags
;
2267 spin_lock_irqsave(&pch
->lock
, flags
);
2269 dma_cookie_init(chan
);
2270 pch
->cyclic
= false;
2272 pch
->pl330_chid
= pl330_request_channel(&pdmac
->pif
);
2273 if (!pch
->pl330_chid
) {
2274 spin_unlock_irqrestore(&pch
->lock
, flags
);
2278 tasklet_init(&pch
->task
, pl330_tasklet
, (unsigned long) pch
);
2280 spin_unlock_irqrestore(&pch
->lock
, flags
);
2285 static int pl330_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
, unsigned long arg
)
2287 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2288 struct dma_pl330_desc
*desc
;
2289 unsigned long flags
;
2290 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2291 struct dma_slave_config
*slave_config
;
2295 case DMA_TERMINATE_ALL
:
2296 spin_lock_irqsave(&pch
->lock
, flags
);
2298 /* FLUSH the PL330 Channel thread */
2299 pl330_chan_ctrl(pch
->pl330_chid
, PL330_OP_FLUSH
);
2301 /* Mark all desc done */
2302 list_for_each_entry(desc
, &pch
->submitted_list
, node
) {
2303 desc
->status
= FREE
;
2304 dma_cookie_complete(&desc
->txd
);
2307 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2308 desc
->status
= FREE
;
2309 dma_cookie_complete(&desc
->txd
);
2312 list_for_each_entry(desc
, &pch
->completed_list
, node
) {
2313 desc
->status
= FREE
;
2314 dma_cookie_complete(&desc
->txd
);
2317 list_splice_tail_init(&pch
->submitted_list
, &pdmac
->desc_pool
);
2318 list_splice_tail_init(&pch
->work_list
, &pdmac
->desc_pool
);
2319 list_splice_tail_init(&pch
->completed_list
, &pdmac
->desc_pool
);
2320 spin_unlock_irqrestore(&pch
->lock
, flags
);
2322 case DMA_SLAVE_CONFIG
:
2323 slave_config
= (struct dma_slave_config
*)arg
;
2325 if (slave_config
->direction
== DMA_MEM_TO_DEV
) {
2326 if (slave_config
->dst_addr
)
2327 pch
->fifo_addr
= slave_config
->dst_addr
;
2328 if (slave_config
->dst_addr_width
)
2329 pch
->burst_sz
= __ffs(slave_config
->dst_addr_width
);
2330 if (slave_config
->dst_maxburst
)
2331 pch
->burst_len
= slave_config
->dst_maxburst
;
2332 } else if (slave_config
->direction
== DMA_DEV_TO_MEM
) {
2333 if (slave_config
->src_addr
)
2334 pch
->fifo_addr
= slave_config
->src_addr
;
2335 if (slave_config
->src_addr_width
)
2336 pch
->burst_sz
= __ffs(slave_config
->src_addr_width
);
2337 if (slave_config
->src_maxburst
)
2338 pch
->burst_len
= slave_config
->src_maxburst
;
2342 dev_err(pch
->dmac
->pif
.dev
, "Not supported command.\n");
2349 static void pl330_free_chan_resources(struct dma_chan
*chan
)
2351 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2352 unsigned long flags
;
2354 tasklet_kill(&pch
->task
);
2356 spin_lock_irqsave(&pch
->lock
, flags
);
2358 pl330_release_channel(pch
->pl330_chid
);
2359 pch
->pl330_chid
= NULL
;
2362 list_splice_tail_init(&pch
->work_list
, &pch
->dmac
->desc_pool
);
2364 spin_unlock_irqrestore(&pch
->lock
, flags
);
2367 static enum dma_status
2368 pl330_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
2369 struct dma_tx_state
*txstate
)
2371 return dma_cookie_status(chan
, cookie
, txstate
);
2374 static void pl330_issue_pending(struct dma_chan
*chan
)
2376 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2377 unsigned long flags
;
2379 spin_lock_irqsave(&pch
->lock
, flags
);
2380 list_splice_tail_init(&pch
->submitted_list
, &pch
->work_list
);
2381 spin_unlock_irqrestore(&pch
->lock
, flags
);
2383 pl330_tasklet((unsigned long)pch
);
2387 * We returned the last one of the circular list of descriptor(s)
2388 * from prep_xxx, so the argument to submit corresponds to the last
2389 * descriptor of the list.
2391 static dma_cookie_t
pl330_tx_submit(struct dma_async_tx_descriptor
*tx
)
2393 struct dma_pl330_desc
*desc
, *last
= to_desc(tx
);
2394 struct dma_pl330_chan
*pch
= to_pchan(tx
->chan
);
2395 dma_cookie_t cookie
;
2396 unsigned long flags
;
2398 spin_lock_irqsave(&pch
->lock
, flags
);
2400 /* Assign cookies to all nodes */
2401 while (!list_empty(&last
->node
)) {
2402 desc
= list_entry(last
->node
.next
, struct dma_pl330_desc
, node
);
2404 desc
->txd
.callback
= last
->txd
.callback
;
2405 desc
->txd
.callback_param
= last
->txd
.callback_param
;
2408 dma_cookie_assign(&desc
->txd
);
2410 list_move_tail(&desc
->node
, &pch
->submitted_list
);
2413 cookie
= dma_cookie_assign(&last
->txd
);
2414 list_add_tail(&last
->node
, &pch
->submitted_list
);
2415 spin_unlock_irqrestore(&pch
->lock
, flags
);
2420 static inline void _init_desc(struct dma_pl330_desc
*desc
)
2422 desc
->req
.x
= &desc
->px
;
2423 desc
->req
.token
= desc
;
2424 desc
->rqcfg
.swap
= SWAP_NO
;
2425 desc
->rqcfg
.scctl
= CCTRL0
;
2426 desc
->rqcfg
.dcctl
= CCTRL0
;
2427 desc
->req
.cfg
= &desc
->rqcfg
;
2428 desc
->req
.xfer_cb
= dma_pl330_rqcb
;
2429 desc
->txd
.tx_submit
= pl330_tx_submit
;
2431 INIT_LIST_HEAD(&desc
->node
);
2434 /* Returns the number of descriptors added to the DMAC pool */
2435 static int add_desc(struct dma_pl330_dmac
*pdmac
, gfp_t flg
, int count
)
2437 struct dma_pl330_desc
*desc
;
2438 unsigned long flags
;
2444 desc
= kcalloc(count
, sizeof(*desc
), flg
);
2448 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2450 for (i
= 0; i
< count
; i
++) {
2451 _init_desc(&desc
[i
]);
2452 list_add_tail(&desc
[i
].node
, &pdmac
->desc_pool
);
2455 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2460 static struct dma_pl330_desc
*
2461 pluck_desc(struct dma_pl330_dmac
*pdmac
)
2463 struct dma_pl330_desc
*desc
= NULL
;
2464 unsigned long flags
;
2469 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2471 if (!list_empty(&pdmac
->desc_pool
)) {
2472 desc
= list_entry(pdmac
->desc_pool
.next
,
2473 struct dma_pl330_desc
, node
);
2475 list_del_init(&desc
->node
);
2477 desc
->status
= PREP
;
2478 desc
->txd
.callback
= NULL
;
2481 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2486 static struct dma_pl330_desc
*pl330_get_desc(struct dma_pl330_chan
*pch
)
2488 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2489 u8
*peri_id
= pch
->chan
.private;
2490 struct dma_pl330_desc
*desc
;
2492 /* Pluck one desc from the pool of DMAC */
2493 desc
= pluck_desc(pdmac
);
2495 /* If the DMAC pool is empty, alloc new */
2497 if (!add_desc(pdmac
, GFP_ATOMIC
, 1))
2501 desc
= pluck_desc(pdmac
);
2503 dev_err(pch
->dmac
->pif
.dev
,
2504 "%s:%d ALERT!\n", __func__
, __LINE__
);
2509 /* Initialize the descriptor */
2511 desc
->txd
.cookie
= 0;
2512 async_tx_ack(&desc
->txd
);
2514 desc
->req
.peri
= peri_id
? pch
->chan
.chan_id
: 0;
2515 desc
->rqcfg
.pcfg
= &pch
->dmac
->pif
.pcfg
;
2517 dma_async_tx_descriptor_init(&desc
->txd
, &pch
->chan
);
2522 static inline void fill_px(struct pl330_xfer
*px
,
2523 dma_addr_t dst
, dma_addr_t src
, size_t len
)
2530 static struct dma_pl330_desc
*
2531 __pl330_prep_dma_memcpy(struct dma_pl330_chan
*pch
, dma_addr_t dst
,
2532 dma_addr_t src
, size_t len
)
2534 struct dma_pl330_desc
*desc
= pl330_get_desc(pch
);
2537 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Unable to fetch desc\n",
2538 __func__
, __LINE__
);
2543 * Ideally we should lookout for reqs bigger than
2544 * those that can be programmed with 256 bytes of
2545 * MC buffer, but considering a req size is seldom
2546 * going to be word-unaligned and more than 200MB,
2548 * Also, should the limit is reached we'd rather
2549 * have the platform increase MC buffer size than
2550 * complicating this API driver.
2552 fill_px(&desc
->px
, dst
, src
, len
);
2557 /* Call after fixing burst size */
2558 static inline int get_burst_len(struct dma_pl330_desc
*desc
, size_t len
)
2560 struct dma_pl330_chan
*pch
= desc
->pchan
;
2561 struct pl330_info
*pi
= &pch
->dmac
->pif
;
2564 burst_len
= pi
->pcfg
.data_bus_width
/ 8;
2565 burst_len
*= pi
->pcfg
.data_buf_dep
;
2566 burst_len
>>= desc
->rqcfg
.brst_size
;
2568 /* src/dst_burst_len can't be more than 16 */
2572 while (burst_len
> 1) {
2573 if (!(len
% (burst_len
<< desc
->rqcfg
.brst_size
)))
2581 static struct dma_async_tx_descriptor
*pl330_prep_dma_cyclic(
2582 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t len
,
2583 size_t period_len
, enum dma_transfer_direction direction
,
2584 unsigned long flags
, void *context
)
2586 struct dma_pl330_desc
*desc
= NULL
, *first
= NULL
;
2587 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2588 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2593 if (len
% period_len
!= 0)
2596 if (!is_slave_direction(direction
)) {
2597 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Invalid dma direction\n",
2598 __func__
, __LINE__
);
2602 for (i
= 0; i
< len
/ period_len
; i
++) {
2603 desc
= pl330_get_desc(pch
);
2605 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Unable to fetch desc\n",
2606 __func__
, __LINE__
);
2611 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2613 while (!list_empty(&first
->node
)) {
2614 desc
= list_entry(first
->node
.next
,
2615 struct dma_pl330_desc
, node
);
2616 list_move_tail(&desc
->node
, &pdmac
->desc_pool
);
2619 list_move_tail(&first
->node
, &pdmac
->desc_pool
);
2621 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2626 switch (direction
) {
2627 case DMA_MEM_TO_DEV
:
2628 desc
->rqcfg
.src_inc
= 1;
2629 desc
->rqcfg
.dst_inc
= 0;
2631 dst
= pch
->fifo_addr
;
2633 case DMA_DEV_TO_MEM
:
2634 desc
->rqcfg
.src_inc
= 0;
2635 desc
->rqcfg
.dst_inc
= 1;
2636 src
= pch
->fifo_addr
;
2643 desc
->req
.rqtype
= direction
;
2644 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2645 desc
->rqcfg
.brst_len
= 1;
2646 fill_px(&desc
->px
, dst
, src
, period_len
);
2651 list_add_tail(&desc
->node
, &first
->node
);
2653 dma_addr
+= period_len
;
2660 desc
->txd
.flags
= flags
;
2665 static struct dma_async_tx_descriptor
*
2666 pl330_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dst
,
2667 dma_addr_t src
, size_t len
, unsigned long flags
)
2669 struct dma_pl330_desc
*desc
;
2670 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2671 struct pl330_info
*pi
;
2674 if (unlikely(!pch
|| !len
))
2677 pi
= &pch
->dmac
->pif
;
2679 desc
= __pl330_prep_dma_memcpy(pch
, dst
, src
, len
);
2683 desc
->rqcfg
.src_inc
= 1;
2684 desc
->rqcfg
.dst_inc
= 1;
2685 desc
->req
.rqtype
= DMA_MEM_TO_MEM
;
2687 /* Select max possible burst size */
2688 burst
= pi
->pcfg
.data_bus_width
/ 8;
2696 desc
->rqcfg
.brst_size
= 0;
2697 while (burst
!= (1 << desc
->rqcfg
.brst_size
))
2698 desc
->rqcfg
.brst_size
++;
2700 desc
->rqcfg
.brst_len
= get_burst_len(desc
, len
);
2702 desc
->txd
.flags
= flags
;
2707 static void __pl330_giveback_desc(struct dma_pl330_dmac
*pdmac
,
2708 struct dma_pl330_desc
*first
)
2710 unsigned long flags
;
2711 struct dma_pl330_desc
*desc
;
2716 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2718 while (!list_empty(&first
->node
)) {
2719 desc
= list_entry(first
->node
.next
,
2720 struct dma_pl330_desc
, node
);
2721 list_move_tail(&desc
->node
, &pdmac
->desc_pool
);
2724 list_move_tail(&first
->node
, &pdmac
->desc_pool
);
2726 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2729 static struct dma_async_tx_descriptor
*
2730 pl330_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
2731 unsigned int sg_len
, enum dma_transfer_direction direction
,
2732 unsigned long flg
, void *context
)
2734 struct dma_pl330_desc
*first
, *desc
= NULL
;
2735 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2736 struct scatterlist
*sg
;
2740 if (unlikely(!pch
|| !sgl
|| !sg_len
))
2743 addr
= pch
->fifo_addr
;
2747 for_each_sg(sgl
, sg
, sg_len
, i
) {
2749 desc
= pl330_get_desc(pch
);
2751 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2753 dev_err(pch
->dmac
->pif
.dev
,
2754 "%s:%d Unable to fetch desc\n",
2755 __func__
, __LINE__
);
2756 __pl330_giveback_desc(pdmac
, first
);
2764 list_add_tail(&desc
->node
, &first
->node
);
2766 if (direction
== DMA_MEM_TO_DEV
) {
2767 desc
->rqcfg
.src_inc
= 1;
2768 desc
->rqcfg
.dst_inc
= 0;
2770 addr
, sg_dma_address(sg
), sg_dma_len(sg
));
2772 desc
->rqcfg
.src_inc
= 0;
2773 desc
->rqcfg
.dst_inc
= 1;
2775 sg_dma_address(sg
), addr
, sg_dma_len(sg
));
2778 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2779 desc
->rqcfg
.brst_len
= 1;
2780 desc
->req
.rqtype
= direction
;
2783 /* Return the last desc in the chain */
2784 desc
->txd
.flags
= flg
;
2788 static irqreturn_t
pl330_irq_handler(int irq
, void *data
)
2790 if (pl330_update(data
))
2796 #define PL330_DMA_BUSWIDTHS \
2797 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2798 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2799 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2800 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2801 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2803 static int pl330_dma_device_slave_caps(struct dma_chan
*dchan
,
2804 struct dma_slave_caps
*caps
)
2806 caps
->src_addr_widths
= PL330_DMA_BUSWIDTHS
;
2807 caps
->dstn_addr_widths
= PL330_DMA_BUSWIDTHS
;
2808 caps
->directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
2809 caps
->cmd_pause
= false;
2810 caps
->cmd_terminate
= true;
2811 caps
->residue_granularity
= DMA_RESIDUE_GRANULARITY_DESCRIPTOR
;
2817 pl330_probe(struct amba_device
*adev
, const struct amba_id
*id
)
2819 struct dma_pl330_platdata
*pdat
;
2820 struct dma_pl330_dmac
*pdmac
;
2821 struct dma_pl330_chan
*pch
, *_p
;
2822 struct pl330_info
*pi
;
2823 struct dma_device
*pd
;
2824 struct resource
*res
;
2828 pdat
= dev_get_platdata(&adev
->dev
);
2830 ret
= dma_set_mask_and_coherent(&adev
->dev
, DMA_BIT_MASK(32));
2834 /* Allocate a new DMAC and its Channels */
2835 pdmac
= devm_kzalloc(&adev
->dev
, sizeof(*pdmac
), GFP_KERNEL
);
2837 dev_err(&adev
->dev
, "unable to allocate mem\n");
2842 pi
->dev
= &adev
->dev
;
2843 pi
->pl330_data
= NULL
;
2844 pi
->mcbufsz
= pdat
? pdat
->mcbuf_sz
: 0;
2847 pi
->base
= devm_ioremap_resource(&adev
->dev
, res
);
2848 if (IS_ERR(pi
->base
))
2849 return PTR_ERR(pi
->base
);
2851 amba_set_drvdata(adev
, pdmac
);
2853 for (i
= 0; i
< AMBA_NR_IRQS
; i
++) {
2856 ret
= devm_request_irq(&adev
->dev
, irq
,
2857 pl330_irq_handler
, 0,
2858 dev_name(&adev
->dev
), pi
);
2866 pi
->pcfg
.periph_id
= adev
->periphid
;
2867 ret
= pl330_add(pi
);
2871 INIT_LIST_HEAD(&pdmac
->desc_pool
);
2872 spin_lock_init(&pdmac
->pool_lock
);
2874 /* Create a descriptor pool of default size */
2875 if (!add_desc(pdmac
, GFP_KERNEL
, NR_DEFAULT_DESC
))
2876 dev_warn(&adev
->dev
, "unable to allocate desc\n");
2879 INIT_LIST_HEAD(&pd
->channels
);
2881 /* Initialize channel parameters */
2883 num_chan
= max_t(int, pdat
->nr_valid_peri
, pi
->pcfg
.num_chan
);
2885 num_chan
= max_t(int, pi
->pcfg
.num_peri
, pi
->pcfg
.num_chan
);
2887 pdmac
->num_peripherals
= num_chan
;
2889 pdmac
->peripherals
= kzalloc(num_chan
* sizeof(*pch
), GFP_KERNEL
);
2890 if (!pdmac
->peripherals
) {
2892 dev_err(&adev
->dev
, "unable to allocate pdmac->peripherals\n");
2896 for (i
= 0; i
< num_chan
; i
++) {
2897 pch
= &pdmac
->peripherals
[i
];
2898 if (!adev
->dev
.of_node
)
2899 pch
->chan
.private = pdat
? &pdat
->peri_id
[i
] : NULL
;
2901 pch
->chan
.private = adev
->dev
.of_node
;
2903 INIT_LIST_HEAD(&pch
->submitted_list
);
2904 INIT_LIST_HEAD(&pch
->work_list
);
2905 INIT_LIST_HEAD(&pch
->completed_list
);
2906 spin_lock_init(&pch
->lock
);
2907 pch
->pl330_chid
= NULL
;
2908 pch
->chan
.device
= pd
;
2911 /* Add the channel to the DMAC list */
2912 list_add_tail(&pch
->chan
.device_node
, &pd
->channels
);
2915 pd
->dev
= &adev
->dev
;
2917 pd
->cap_mask
= pdat
->cap_mask
;
2919 dma_cap_set(DMA_MEMCPY
, pd
->cap_mask
);
2920 if (pi
->pcfg
.num_peri
) {
2921 dma_cap_set(DMA_SLAVE
, pd
->cap_mask
);
2922 dma_cap_set(DMA_CYCLIC
, pd
->cap_mask
);
2923 dma_cap_set(DMA_PRIVATE
, pd
->cap_mask
);
2927 pd
->device_alloc_chan_resources
= pl330_alloc_chan_resources
;
2928 pd
->device_free_chan_resources
= pl330_free_chan_resources
;
2929 pd
->device_prep_dma_memcpy
= pl330_prep_dma_memcpy
;
2930 pd
->device_prep_dma_cyclic
= pl330_prep_dma_cyclic
;
2931 pd
->device_tx_status
= pl330_tx_status
;
2932 pd
->device_prep_slave_sg
= pl330_prep_slave_sg
;
2933 pd
->device_control
= pl330_control
;
2934 pd
->device_issue_pending
= pl330_issue_pending
;
2935 pd
->device_slave_caps
= pl330_dma_device_slave_caps
;
2937 ret
= dma_async_device_register(pd
);
2939 dev_err(&adev
->dev
, "unable to register DMAC\n");
2943 if (adev
->dev
.of_node
) {
2944 ret
= of_dma_controller_register(adev
->dev
.of_node
,
2945 of_dma_pl330_xlate
, pdmac
);
2948 "unable to register DMA to the generic DT DMA helpers\n");
2952 adev
->dev
.dma_parms
= &pdmac
->dma_parms
;
2955 * This is the limit for transfers with a buswidth of 1, larger
2956 * buswidths will have larger limits.
2958 ret
= dma_set_max_seg_size(&adev
->dev
, 1900800);
2960 dev_err(&adev
->dev
, "unable to set the seg size\n");
2963 dev_info(&adev
->dev
,
2964 "Loaded driver for PL330 DMAC-%d\n", adev
->periphid
);
2965 dev_info(&adev
->dev
,
2966 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2967 pi
->pcfg
.data_buf_dep
,
2968 pi
->pcfg
.data_bus_width
/ 8, pi
->pcfg
.num_chan
,
2969 pi
->pcfg
.num_peri
, pi
->pcfg
.num_events
);
2974 list_for_each_entry_safe(pch
, _p
, &pdmac
->ddma
.channels
,
2977 /* Remove the channel */
2978 list_del(&pch
->chan
.device_node
);
2980 /* Flush the channel */
2981 pl330_control(&pch
->chan
, DMA_TERMINATE_ALL
, 0);
2982 pl330_free_chan_resources(&pch
->chan
);
2990 static int pl330_remove(struct amba_device
*adev
)
2992 struct dma_pl330_dmac
*pdmac
= amba_get_drvdata(adev
);
2993 struct dma_pl330_chan
*pch
, *_p
;
2994 struct pl330_info
*pi
;
2999 if (adev
->dev
.of_node
)
3000 of_dma_controller_free(adev
->dev
.of_node
);
3002 dma_async_device_unregister(&pdmac
->ddma
);
3005 list_for_each_entry_safe(pch
, _p
, &pdmac
->ddma
.channels
,
3008 /* Remove the channel */
3009 list_del(&pch
->chan
.device_node
);
3011 /* Flush the channel */
3012 pl330_control(&pch
->chan
, DMA_TERMINATE_ALL
, 0);
3013 pl330_free_chan_resources(&pch
->chan
);
3023 static struct amba_id pl330_ids
[] = {
3031 MODULE_DEVICE_TABLE(amba
, pl330_ids
);
3033 static struct amba_driver pl330_driver
= {
3035 .owner
= THIS_MODULE
,
3036 .name
= "dma-pl330",
3038 .id_table
= pl330_ids
,
3039 .probe
= pl330_probe
,
3040 .remove
= pl330_remove
,
3043 module_amba_driver(pl330_driver
);
3045 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
3046 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3047 MODULE_LICENSE("GPL");