2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
28 #include <linux/of_dma.h>
29 #include <linux/err.h>
31 #include "dmaengine.h"
32 #define PL330_MAX_CHAN 8
33 #define PL330_MAX_IRQS 32
34 #define PL330_MAX_PERI 32
36 enum pl330_cachectrl
{
37 CCTRL0
, /* Noncacheable and nonbufferable */
38 CCTRL1
, /* Bufferable only */
39 CCTRL2
, /* Cacheable, but do not allocate */
40 CCTRL3
, /* Cacheable and bufferable, but do not allocate */
41 INVALID1
, /* AWCACHE = 0x1000 */
43 CCTRL6
, /* Cacheable write-through, allocate on writes only */
44 CCTRL7
, /* Cacheable write-back, allocate on writes only */
55 /* Register and Bit field Definitions */
57 #define DS_ST_STOP 0x0
58 #define DS_ST_EXEC 0x1
59 #define DS_ST_CMISS 0x2
60 #define DS_ST_UPDTPC 0x3
62 #define DS_ST_ATBRR 0x5
63 #define DS_ST_QBUSY 0x6
65 #define DS_ST_KILL 0x8
66 #define DS_ST_CMPLT 0x9
67 #define DS_ST_FLTCMP 0xe
68 #define DS_ST_FAULT 0xf
73 #define INTSTATUS 0x28
80 #define FTC(n) (_FTC + (n)*0x4)
83 #define CS(n) (_CS + (n)*0x8)
84 #define CS_CNS (1 << 21)
87 #define CPC(n) (_CPC + (n)*0x8)
90 #define SA(n) (_SA + (n)*0x20)
93 #define DA(n) (_DA + (n)*0x20)
96 #define CC(n) (_CC + (n)*0x20)
98 #define CC_SRCINC (1 << 0)
99 #define CC_DSTINC (1 << 14)
100 #define CC_SRCPRI (1 << 8)
101 #define CC_DSTPRI (1 << 22)
102 #define CC_SRCNS (1 << 9)
103 #define CC_DSTNS (1 << 23)
104 #define CC_SRCIA (1 << 10)
105 #define CC_DSTIA (1 << 24)
106 #define CC_SRCBRSTLEN_SHFT 4
107 #define CC_DSTBRSTLEN_SHFT 18
108 #define CC_SRCBRSTSIZE_SHFT 1
109 #define CC_DSTBRSTSIZE_SHFT 15
110 #define CC_SRCCCTRL_SHFT 11
111 #define CC_SRCCCTRL_MASK 0x7
112 #define CC_DSTCCTRL_SHFT 25
113 #define CC_DRCCCTRL_MASK 0x7
114 #define CC_SWAP_SHFT 28
117 #define LC0(n) (_LC0 + (n)*0x20)
120 #define LC1(n) (_LC1 + (n)*0x20)
122 #define DBGSTATUS 0xd00
123 #define DBG_BUSY (1 << 0)
126 #define DBGINST0 0xd08
127 #define DBGINST1 0xd0c
136 #define PERIPH_ID 0xfe0
137 #define PERIPH_REV_SHIFT 20
138 #define PERIPH_REV_MASK 0xf
139 #define PERIPH_REV_R0P0 0
140 #define PERIPH_REV_R1P0 1
141 #define PERIPH_REV_R1P1 2
143 #define CR0_PERIPH_REQ_SET (1 << 0)
144 #define CR0_BOOT_EN_SET (1 << 1)
145 #define CR0_BOOT_MAN_NS (1 << 2)
146 #define CR0_NUM_CHANS_SHIFT 4
147 #define CR0_NUM_CHANS_MASK 0x7
148 #define CR0_NUM_PERIPH_SHIFT 12
149 #define CR0_NUM_PERIPH_MASK 0x1f
150 #define CR0_NUM_EVENTS_SHIFT 17
151 #define CR0_NUM_EVENTS_MASK 0x1f
153 #define CR1_ICACHE_LEN_SHIFT 0
154 #define CR1_ICACHE_LEN_MASK 0x7
155 #define CR1_NUM_ICACHELINES_SHIFT 4
156 #define CR1_NUM_ICACHELINES_MASK 0xf
158 #define CRD_DATA_WIDTH_SHIFT 0
159 #define CRD_DATA_WIDTH_MASK 0x7
160 #define CRD_WR_CAP_SHIFT 4
161 #define CRD_WR_CAP_MASK 0x7
162 #define CRD_WR_Q_DEP_SHIFT 8
163 #define CRD_WR_Q_DEP_MASK 0xf
164 #define CRD_RD_CAP_SHIFT 12
165 #define CRD_RD_CAP_MASK 0x7
166 #define CRD_RD_Q_DEP_SHIFT 16
167 #define CRD_RD_Q_DEP_MASK 0xf
168 #define CRD_DATA_BUFF_SHIFT 20
169 #define CRD_DATA_BUFF_MASK 0x3ff
172 #define DESIGNER 0x41
174 #define INTEG_CFG 0x0
175 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
177 #define PL330_STATE_STOPPED (1 << 0)
178 #define PL330_STATE_EXECUTING (1 << 1)
179 #define PL330_STATE_WFE (1 << 2)
180 #define PL330_STATE_FAULTING (1 << 3)
181 #define PL330_STATE_COMPLETING (1 << 4)
182 #define PL330_STATE_WFP (1 << 5)
183 #define PL330_STATE_KILLING (1 << 6)
184 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
185 #define PL330_STATE_CACHEMISS (1 << 8)
186 #define PL330_STATE_UPDTPC (1 << 9)
187 #define PL330_STATE_ATBARRIER (1 << 10)
188 #define PL330_STATE_QUEUEBUSY (1 << 11)
189 #define PL330_STATE_INVALID (1 << 15)
191 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
192 | PL330_STATE_WFE | PL330_STATE_FAULTING)
194 #define CMD_DMAADDH 0x54
195 #define CMD_DMAEND 0x00
196 #define CMD_DMAFLUSHP 0x35
197 #define CMD_DMAGO 0xa0
198 #define CMD_DMALD 0x04
199 #define CMD_DMALDP 0x25
200 #define CMD_DMALP 0x20
201 #define CMD_DMALPEND 0x28
202 #define CMD_DMAKILL 0x01
203 #define CMD_DMAMOV 0xbc
204 #define CMD_DMANOP 0x18
205 #define CMD_DMARMB 0x12
206 #define CMD_DMASEV 0x34
207 #define CMD_DMAST 0x08
208 #define CMD_DMASTP 0x29
209 #define CMD_DMASTZ 0x0c
210 #define CMD_DMAWFE 0x36
211 #define CMD_DMAWFP 0x30
212 #define CMD_DMAWMB 0x13
216 #define SZ_DMAFLUSHP 2
220 #define SZ_DMALPEND 2
234 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
235 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
237 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
238 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
241 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
242 * at 1byte/burst for P<->M and M<->M respectively.
243 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
244 * should be enough for P<->M and M<->M respectively.
246 #define MCODE_BUFF_PER_REQ 256
248 /* If the _pl330_req is available to the client */
249 #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
251 /* Use this _only_ to wait on transient states */
252 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254 #ifdef PL330_DEBUG_MCGEN
255 static unsigned cmd_line
;
256 #define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
261 #define PL330_DBGMC_START(addr) (cmd_line = addr)
263 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264 #define PL330_DBGMC_START(addr) do {} while (0)
267 /* The number of default descriptors */
269 #define NR_DEFAULT_DESC 16
271 /* Populated by the PL330 core driver for DMA API driver's info */
272 struct pl330_config
{
274 #define DMAC_MODE_NS (1 << 0)
276 unsigned int data_bus_width
:10; /* In number of bits */
277 unsigned int data_buf_dep
:10;
278 unsigned int num_chan
:4;
279 unsigned int num_peri
:6;
281 unsigned int num_events
:6;
285 /* Handle to the DMAC provided to the PL330 core */
289 /* Size of MicroCode buffers for each channel. */
291 /* ioremap'ed address of PL330 registers. */
293 /* PL330 core data, Client must not touch it. */
295 /* Populated by the PL330 core driver during pl330_add */
296 struct pl330_config pcfg
;
300 * Request Configuration.
301 * The PL330 core does not modify this and uses the last
302 * working configuration if the request doesn't provide any.
304 * The Client may want to provide this info only for the
305 * first request and a request with new settings.
307 struct pl330_reqcfg
{
308 /* Address Incrementing */
313 * For now, the SRC & DST protection levels
314 * and burst size/length are assumed same.
320 unsigned brst_size
:3; /* in power of 2 */
322 enum pl330_cachectrl dcctl
;
323 enum pl330_cachectrl scctl
;
324 enum pl330_byteswap swap
;
325 struct pl330_config
*pcfg
;
329 * One cycle of DMAC operation.
330 * There may be more than one xfer in a request.
339 /* The xfer callbacks are made with one of these arguments. */
341 /* The all xfers in the request were success. */
343 /* If req aborted due to global error. */
345 /* If req failed due to problem with Channel. */
349 /* A request defining Scatter-Gather List ending with NULL xfer. */
351 enum dma_transfer_direction rqtype
;
352 /* Index of peripheral for the xfer. */
354 /* Unique token for this xfer, set by the client. */
356 /* Callback to be called after xfer. */
357 void (*xfer_cb
)(void *token
, enum pl330_op_err err
);
358 /* If NULL, req will be done at last set parameters. */
359 struct pl330_reqcfg
*cfg
;
360 /* Pointer to first xfer in the request. */
361 struct pl330_xfer
*x
;
362 /* Hook to attach to DMAC's list of reqs with due callback */
363 struct list_head rqd
;
367 /* Start the channel */
369 /* Abort the active xfer */
371 /* Stop xfer and flush queue */
378 struct pl330_xfer
*x
;
404 /* ToBeDone for tasklet */
412 struct pl330_thread
{
415 /* If the channel is not yet acquired by any client */
418 struct pl330_dmac
*dmac
;
419 /* Only two at a time */
420 struct _pl330_req req
[2];
421 /* Index of the last enqueued request */
423 /* Index of the last submitted request or -1 if the DMA is stopped */
427 enum pl330_dmac_state
{
436 /* Holds list of reqs with due callbacks */
437 struct list_head req_done
;
438 /* Pointer to platform specific stuff */
439 struct pl330_info
*pinfo
;
440 /* Maximum possible events/irqs */
442 /* BUS address of MicroCode buffer */
443 dma_addr_t mcode_bus
;
444 /* CPU address of MicroCode buffer */
446 /* List of all Channel threads */
447 struct pl330_thread
*channels
;
448 /* Pointer to the MANAGER thread */
449 struct pl330_thread
*manager
;
450 /* To handle bad news in interrupt */
451 struct tasklet_struct tasks
;
452 struct _pl330_tbd dmac_tbd
;
453 /* State of DMAC operation */
454 enum pl330_dmac_state state
;
458 /* In the DMAC pool */
461 * Allocated to some channel during prep_xxx
462 * Also may be sitting on the work_list.
466 * Sitting on the work_list and already submitted
467 * to the PL330 core. Not more than two descriptors
468 * of a channel can be BUSY at any time.
472 * Sitting on the channel work_list but xfer done
478 struct dma_pl330_chan
{
479 /* Schedule desc completion */
480 struct tasklet_struct task
;
482 /* DMA-Engine Channel */
483 struct dma_chan chan
;
485 /* List of submitted descriptors */
486 struct list_head submitted_list
;
487 /* List of issued descriptors */
488 struct list_head work_list
;
489 /* List of completed descriptors */
490 struct list_head completed_list
;
492 /* Pointer to the DMAC that manages this channel,
493 * NULL if the channel is available to be acquired.
494 * As the parent, this DMAC also provides descriptors
497 struct dma_pl330_dmac
*dmac
;
499 /* To protect channel manipulation */
502 /* Token of a hardware channel thread of PL330 DMAC
503 * NULL if the channel is available to be acquired.
507 /* For D-to-M and M-to-D channels */
508 int burst_sz
; /* the peripheral fifo width */
509 int burst_len
; /* the number of burst */
510 dma_addr_t fifo_addr
;
512 /* for cyclic capability */
516 struct dma_pl330_dmac
{
517 struct pl330_info pif
;
519 /* DMA-Engine Device */
520 struct dma_device ddma
;
522 /* Holds info about sg limitations */
523 struct device_dma_parameters dma_parms
;
525 /* Pool of descriptors available for the DMAC's channels */
526 struct list_head desc_pool
;
527 /* To protect desc_pool manipulation */
528 spinlock_t pool_lock
;
530 /* Peripheral channels connected to this DMAC */
531 unsigned int num_peripherals
;
532 struct dma_pl330_chan
*peripherals
; /* keep at end */
535 struct dma_pl330_desc
{
536 /* To attach to a queue as child */
537 struct list_head node
;
539 /* Descriptor for the DMA Engine API */
540 struct dma_async_tx_descriptor txd
;
542 /* Xfer for PL330 core */
543 struct pl330_xfer px
;
545 struct pl330_reqcfg rqcfg
;
546 struct pl330_req req
;
548 enum desc_status status
;
550 /* The channel which currently holds this desc */
551 struct dma_pl330_chan
*pchan
;
554 static inline void _callback(struct pl330_req
*r
, enum pl330_op_err err
)
557 r
->xfer_cb(r
->token
, err
);
560 static inline bool _queue_empty(struct pl330_thread
*thrd
)
562 return (IS_FREE(&thrd
->req
[0]) && IS_FREE(&thrd
->req
[1]))
566 static inline bool _queue_full(struct pl330_thread
*thrd
)
568 return (IS_FREE(&thrd
->req
[0]) || IS_FREE(&thrd
->req
[1]))
572 static inline bool is_manager(struct pl330_thread
*thrd
)
574 struct pl330_dmac
*pl330
= thrd
->dmac
;
576 /* MANAGER is indexed at the end */
577 if (thrd
->id
== pl330
->pinfo
->pcfg
.num_chan
)
583 /* If manager of the thread is in Non-Secure mode */
584 static inline bool _manager_ns(struct pl330_thread
*thrd
)
586 struct pl330_dmac
*pl330
= thrd
->dmac
;
588 return (pl330
->pinfo
->pcfg
.mode
& DMAC_MODE_NS
) ? true : false;
591 static inline u32
get_revision(u32 periph_id
)
593 return (periph_id
>> PERIPH_REV_SHIFT
) & PERIPH_REV_MASK
;
596 static inline u32
_emit_ADDH(unsigned dry_run
, u8 buf
[],
597 enum pl330_dst da
, u16 val
)
602 buf
[0] = CMD_DMAADDH
;
604 *((u16
*)&buf
[1]) = val
;
606 PL330_DBGCMD_DUMP(SZ_DMAADDH
, "\tDMAADDH %s %u\n",
607 da
== 1 ? "DA" : "SA", val
);
612 static inline u32
_emit_END(unsigned dry_run
, u8 buf
[])
619 PL330_DBGCMD_DUMP(SZ_DMAEND
, "\tDMAEND\n");
624 static inline u32
_emit_FLUSHP(unsigned dry_run
, u8 buf
[], u8 peri
)
629 buf
[0] = CMD_DMAFLUSHP
;
635 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP
, "\tDMAFLUSHP %u\n", peri
>> 3);
640 static inline u32
_emit_LD(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
648 buf
[0] |= (0 << 1) | (1 << 0);
649 else if (cond
== BURST
)
650 buf
[0] |= (1 << 1) | (1 << 0);
652 PL330_DBGCMD_DUMP(SZ_DMALD
, "\tDMALD%c\n",
653 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
658 static inline u32
_emit_LDP(unsigned dry_run
, u8 buf
[],
659 enum pl330_cond cond
, u8 peri
)
673 PL330_DBGCMD_DUMP(SZ_DMALDP
, "\tDMALDP%c %u\n",
674 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
679 static inline u32
_emit_LP(unsigned dry_run
, u8 buf
[],
680 unsigned loop
, u8 cnt
)
690 cnt
--; /* DMAC increments by 1 internally */
693 PL330_DBGCMD_DUMP(SZ_DMALP
, "\tDMALP_%c %u\n", loop
? '1' : '0', cnt
);
699 enum pl330_cond cond
;
705 static inline u32
_emit_LPEND(unsigned dry_run
, u8 buf
[],
706 const struct _arg_LPEND
*arg
)
708 enum pl330_cond cond
= arg
->cond
;
709 bool forever
= arg
->forever
;
710 unsigned loop
= arg
->loop
;
711 u8 bjump
= arg
->bjump
;
716 buf
[0] = CMD_DMALPEND
;
725 buf
[0] |= (0 << 1) | (1 << 0);
726 else if (cond
== BURST
)
727 buf
[0] |= (1 << 1) | (1 << 0);
731 PL330_DBGCMD_DUMP(SZ_DMALPEND
, "\tDMALP%s%c_%c bjmpto_%x\n",
732 forever
? "FE" : "END",
733 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'),
740 static inline u32
_emit_KILL(unsigned dry_run
, u8 buf
[])
745 buf
[0] = CMD_DMAKILL
;
750 static inline u32
_emit_MOV(unsigned dry_run
, u8 buf
[],
751 enum dmamov_dst dst
, u32 val
)
758 *((u32
*)&buf
[2]) = val
;
760 PL330_DBGCMD_DUMP(SZ_DMAMOV
, "\tDMAMOV %s 0x%x\n",
761 dst
== SAR
? "SAR" : (dst
== DAR
? "DAR" : "CCR"), val
);
766 static inline u32
_emit_NOP(unsigned dry_run
, u8 buf
[])
773 PL330_DBGCMD_DUMP(SZ_DMANOP
, "\tDMANOP\n");
778 static inline u32
_emit_RMB(unsigned dry_run
, u8 buf
[])
785 PL330_DBGCMD_DUMP(SZ_DMARMB
, "\tDMARMB\n");
790 static inline u32
_emit_SEV(unsigned dry_run
, u8 buf
[], u8 ev
)
801 PL330_DBGCMD_DUMP(SZ_DMASEV
, "\tDMASEV %u\n", ev
>> 3);
806 static inline u32
_emit_ST(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
814 buf
[0] |= (0 << 1) | (1 << 0);
815 else if (cond
== BURST
)
816 buf
[0] |= (1 << 1) | (1 << 0);
818 PL330_DBGCMD_DUMP(SZ_DMAST
, "\tDMAST%c\n",
819 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
824 static inline u32
_emit_STP(unsigned dry_run
, u8 buf
[],
825 enum pl330_cond cond
, u8 peri
)
839 PL330_DBGCMD_DUMP(SZ_DMASTP
, "\tDMASTP%c %u\n",
840 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
845 static inline u32
_emit_STZ(unsigned dry_run
, u8 buf
[])
852 PL330_DBGCMD_DUMP(SZ_DMASTZ
, "\tDMASTZ\n");
857 static inline u32
_emit_WFE(unsigned dry_run
, u8 buf
[], u8 ev
,
872 PL330_DBGCMD_DUMP(SZ_DMAWFE
, "\tDMAWFE %u%s\n",
873 ev
>> 3, invalidate
? ", I" : "");
878 static inline u32
_emit_WFP(unsigned dry_run
, u8 buf
[],
879 enum pl330_cond cond
, u8 peri
)
887 buf
[0] |= (0 << 1) | (0 << 0);
888 else if (cond
== BURST
)
889 buf
[0] |= (1 << 1) | (0 << 0);
891 buf
[0] |= (0 << 1) | (1 << 0);
897 PL330_DBGCMD_DUMP(SZ_DMAWFP
, "\tDMAWFP%c %u\n",
898 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'P'), peri
>> 3);
903 static inline u32
_emit_WMB(unsigned dry_run
, u8 buf
[])
910 PL330_DBGCMD_DUMP(SZ_DMAWMB
, "\tDMAWMB\n");
921 static inline u32
_emit_GO(unsigned dry_run
, u8 buf
[],
922 const struct _arg_GO
*arg
)
925 u32 addr
= arg
->addr
;
926 unsigned ns
= arg
->ns
;
936 *((u32
*)&buf
[2]) = addr
;
941 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
943 /* Returns Time-Out */
944 static bool _until_dmac_idle(struct pl330_thread
*thrd
)
946 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
947 unsigned long loops
= msecs_to_loops(5);
950 /* Until Manager is Idle */
951 if (!(readl(regs
+ DBGSTATUS
) & DBG_BUSY
))
963 static inline void _execute_DBGINSN(struct pl330_thread
*thrd
,
964 u8 insn
[], bool as_manager
)
966 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
969 val
= (insn
[0] << 16) | (insn
[1] << 24);
972 val
|= (thrd
->id
<< 8); /* Channel Number */
974 writel(val
, regs
+ DBGINST0
);
976 val
= *((u32
*)&insn
[2]);
977 writel(val
, regs
+ DBGINST1
);
979 /* If timed out due to halted state-machine */
980 if (_until_dmac_idle(thrd
)) {
981 dev_err(thrd
->dmac
->pinfo
->dev
, "DMAC halted!\n");
986 writel(0, regs
+ DBGCMD
);
990 * Mark a _pl330_req as free.
991 * We do it by writing DMAEND as the first instruction
992 * because no valid request is going to have DMAEND as
993 * its first instruction to execute.
995 static void mark_free(struct pl330_thread
*thrd
, int idx
)
997 struct _pl330_req
*req
= &thrd
->req
[idx
];
999 _emit_END(0, req
->mc_cpu
);
1001 thrd
->req_running
= -1;
1004 static inline u32
_state(struct pl330_thread
*thrd
)
1006 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1009 if (is_manager(thrd
))
1010 val
= readl(regs
+ DS
) & 0xf;
1012 val
= readl(regs
+ CS(thrd
->id
)) & 0xf;
1016 return PL330_STATE_STOPPED
;
1018 return PL330_STATE_EXECUTING
;
1020 return PL330_STATE_CACHEMISS
;
1022 return PL330_STATE_UPDTPC
;
1024 return PL330_STATE_WFE
;
1026 return PL330_STATE_FAULTING
;
1028 if (is_manager(thrd
))
1029 return PL330_STATE_INVALID
;
1031 return PL330_STATE_ATBARRIER
;
1033 if (is_manager(thrd
))
1034 return PL330_STATE_INVALID
;
1036 return PL330_STATE_QUEUEBUSY
;
1038 if (is_manager(thrd
))
1039 return PL330_STATE_INVALID
;
1041 return PL330_STATE_WFP
;
1043 if (is_manager(thrd
))
1044 return PL330_STATE_INVALID
;
1046 return PL330_STATE_KILLING
;
1048 if (is_manager(thrd
))
1049 return PL330_STATE_INVALID
;
1051 return PL330_STATE_COMPLETING
;
1053 if (is_manager(thrd
))
1054 return PL330_STATE_INVALID
;
1056 return PL330_STATE_FAULT_COMPLETING
;
1058 return PL330_STATE_INVALID
;
1062 static void _stop(struct pl330_thread
*thrd
)
1064 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1065 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1067 if (_state(thrd
) == PL330_STATE_FAULT_COMPLETING
)
1068 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1070 /* Return if nothing needs to be done */
1071 if (_state(thrd
) == PL330_STATE_COMPLETING
1072 || _state(thrd
) == PL330_STATE_KILLING
1073 || _state(thrd
) == PL330_STATE_STOPPED
)
1076 _emit_KILL(0, insn
);
1078 /* Stop generating interrupts for SEV */
1079 writel(readl(regs
+ INTEN
) & ~(1 << thrd
->ev
), regs
+ INTEN
);
1081 _execute_DBGINSN(thrd
, insn
, is_manager(thrd
));
1084 /* Start doing req 'idx' of thread 'thrd' */
1085 static bool _trigger(struct pl330_thread
*thrd
)
1087 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1088 struct _pl330_req
*req
;
1089 struct pl330_req
*r
;
1092 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1095 /* Return if already ACTIVE */
1096 if (_state(thrd
) != PL330_STATE_STOPPED
)
1099 idx
= 1 - thrd
->lstenq
;
1100 if (!IS_FREE(&thrd
->req
[idx
]))
1101 req
= &thrd
->req
[idx
];
1104 if (!IS_FREE(&thrd
->req
[idx
]))
1105 req
= &thrd
->req
[idx
];
1110 /* Return if no request */
1111 if (!req
|| !req
->r
)
1117 ns
= r
->cfg
->nonsecure
? 1 : 0;
1118 else if (readl(regs
+ CS(thrd
->id
)) & CS_CNS
)
1123 /* See 'Abort Sources' point-4 at Page 2-25 */
1124 if (_manager_ns(thrd
) && !ns
)
1125 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d Recipe for ABORT!\n",
1126 __func__
, __LINE__
);
1129 go
.addr
= req
->mc_bus
;
1131 _emit_GO(0, insn
, &go
);
1133 /* Set to generate interrupts for SEV */
1134 writel(readl(regs
+ INTEN
) | (1 << thrd
->ev
), regs
+ INTEN
);
1136 /* Only manager can execute GO */
1137 _execute_DBGINSN(thrd
, insn
, true);
1139 thrd
->req_running
= idx
;
1144 static bool _start(struct pl330_thread
*thrd
)
1146 switch (_state(thrd
)) {
1147 case PL330_STATE_FAULT_COMPLETING
:
1148 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1150 if (_state(thrd
) == PL330_STATE_KILLING
)
1151 UNTIL(thrd
, PL330_STATE_STOPPED
)
1153 case PL330_STATE_FAULTING
:
1156 case PL330_STATE_KILLING
:
1157 case PL330_STATE_COMPLETING
:
1158 UNTIL(thrd
, PL330_STATE_STOPPED
)
1160 case PL330_STATE_STOPPED
:
1161 return _trigger(thrd
);
1163 case PL330_STATE_WFP
:
1164 case PL330_STATE_QUEUEBUSY
:
1165 case PL330_STATE_ATBARRIER
:
1166 case PL330_STATE_UPDTPC
:
1167 case PL330_STATE_CACHEMISS
:
1168 case PL330_STATE_EXECUTING
:
1171 case PL330_STATE_WFE
: /* For RESUME, nothing yet */
1177 static inline int _ldst_memtomem(unsigned dry_run
, u8 buf
[],
1178 const struct _xfer_spec
*pxs
, int cyc
)
1181 struct pl330_config
*pcfg
= pxs
->r
->cfg
->pcfg
;
1183 /* check lock-up free version */
1184 if (get_revision(pcfg
->periph_id
) >= PERIPH_REV_R1P0
) {
1186 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1187 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1191 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1192 off
+= _emit_RMB(dry_run
, &buf
[off
]);
1193 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1194 off
+= _emit_WMB(dry_run
, &buf
[off
]);
1201 static inline int _ldst_devtomem(unsigned dry_run
, u8 buf
[],
1202 const struct _xfer_spec
*pxs
, int cyc
)
1207 off
+= _emit_WFP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1208 off
+= _emit_LDP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1209 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1210 off
+= _emit_FLUSHP(dry_run
, &buf
[off
], pxs
->r
->peri
);
1216 static inline int _ldst_memtodev(unsigned dry_run
, u8 buf
[],
1217 const struct _xfer_spec
*pxs
, int cyc
)
1222 off
+= _emit_WFP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1223 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1224 off
+= _emit_STP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1225 off
+= _emit_FLUSHP(dry_run
, &buf
[off
], pxs
->r
->peri
);
1231 static int _bursts(unsigned dry_run
, u8 buf
[],
1232 const struct _xfer_spec
*pxs
, int cyc
)
1236 switch (pxs
->r
->rqtype
) {
1237 case DMA_MEM_TO_DEV
:
1238 off
+= _ldst_memtodev(dry_run
, &buf
[off
], pxs
, cyc
);
1240 case DMA_DEV_TO_MEM
:
1241 off
+= _ldst_devtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1243 case DMA_MEM_TO_MEM
:
1244 off
+= _ldst_memtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1247 off
+= 0x40000000; /* Scare off the Client */
1254 /* Returns bytes consumed and updates bursts */
1255 static inline int _loop(unsigned dry_run
, u8 buf
[],
1256 unsigned long *bursts
, const struct _xfer_spec
*pxs
)
1258 int cyc
, cycmax
, szlp
, szlpend
, szbrst
, off
;
1259 unsigned lcnt0
, lcnt1
, ljmp0
, ljmp1
;
1260 struct _arg_LPEND lpend
;
1262 /* Max iterations possible in DMALP is 256 */
1263 if (*bursts
>= 256*256) {
1266 cyc
= *bursts
/ lcnt1
/ lcnt0
;
1267 } else if (*bursts
> 256) {
1269 lcnt0
= *bursts
/ lcnt1
;
1277 szlp
= _emit_LP(1, buf
, 0, 0);
1278 szbrst
= _bursts(1, buf
, pxs
, 1);
1280 lpend
.cond
= ALWAYS
;
1281 lpend
.forever
= false;
1284 szlpend
= _emit_LPEND(1, buf
, &lpend
);
1292 * Max bursts that we can unroll due to limit on the
1293 * size of backward jump that can be encoded in DMALPEND
1294 * which is 8-bits and hence 255
1296 cycmax
= (255 - (szlp
+ szlpend
)) / szbrst
;
1298 cyc
= (cycmax
< cyc
) ? cycmax
: cyc
;
1303 off
+= _emit_LP(dry_run
, &buf
[off
], 0, lcnt0
);
1307 off
+= _emit_LP(dry_run
, &buf
[off
], 1, lcnt1
);
1310 off
+= _bursts(dry_run
, &buf
[off
], pxs
, cyc
);
1312 lpend
.cond
= ALWAYS
;
1313 lpend
.forever
= false;
1315 lpend
.bjump
= off
- ljmp1
;
1316 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1319 lpend
.cond
= ALWAYS
;
1320 lpend
.forever
= false;
1322 lpend
.bjump
= off
- ljmp0
;
1323 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1326 *bursts
= lcnt1
* cyc
;
1333 static inline int _setup_loops(unsigned dry_run
, u8 buf
[],
1334 const struct _xfer_spec
*pxs
)
1336 struct pl330_xfer
*x
= pxs
->x
;
1338 unsigned long c
, bursts
= BYTE_TO_BURST(x
->bytes
, ccr
);
1343 off
+= _loop(dry_run
, &buf
[off
], &c
, pxs
);
1350 static inline int _setup_xfer(unsigned dry_run
, u8 buf
[],
1351 const struct _xfer_spec
*pxs
)
1353 struct pl330_xfer
*x
= pxs
->x
;
1356 /* DMAMOV SAR, x->src_addr */
1357 off
+= _emit_MOV(dry_run
, &buf
[off
], SAR
, x
->src_addr
);
1358 /* DMAMOV DAR, x->dst_addr */
1359 off
+= _emit_MOV(dry_run
, &buf
[off
], DAR
, x
->dst_addr
);
1362 off
+= _setup_loops(dry_run
, &buf
[off
], pxs
);
1368 * A req is a sequence of one or more xfer units.
1369 * Returns the number of bytes taken to setup the MC for the req.
1371 static int _setup_req(unsigned dry_run
, struct pl330_thread
*thrd
,
1372 unsigned index
, struct _xfer_spec
*pxs
)
1374 struct _pl330_req
*req
= &thrd
->req
[index
];
1375 struct pl330_xfer
*x
;
1376 u8
*buf
= req
->mc_cpu
;
1379 PL330_DBGMC_START(req
->mc_bus
);
1381 /* DMAMOV CCR, ccr */
1382 off
+= _emit_MOV(dry_run
, &buf
[off
], CCR
, pxs
->ccr
);
1385 /* Error if xfer length is not aligned at burst size */
1386 if (x
->bytes
% (BRST_SIZE(pxs
->ccr
) * BRST_LEN(pxs
->ccr
)))
1390 off
+= _setup_xfer(dry_run
, &buf
[off
], pxs
);
1392 /* DMASEV peripheral/event */
1393 off
+= _emit_SEV(dry_run
, &buf
[off
], thrd
->ev
);
1395 off
+= _emit_END(dry_run
, &buf
[off
]);
1400 static inline u32
_prepare_ccr(const struct pl330_reqcfg
*rqc
)
1410 /* We set same protection levels for Src and DST for now */
1411 if (rqc
->privileged
)
1412 ccr
|= CC_SRCPRI
| CC_DSTPRI
;
1414 ccr
|= CC_SRCNS
| CC_DSTNS
;
1415 if (rqc
->insnaccess
)
1416 ccr
|= CC_SRCIA
| CC_DSTIA
;
1418 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_SRCBRSTLEN_SHFT
);
1419 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_DSTBRSTLEN_SHFT
);
1421 ccr
|= (rqc
->brst_size
<< CC_SRCBRSTSIZE_SHFT
);
1422 ccr
|= (rqc
->brst_size
<< CC_DSTBRSTSIZE_SHFT
);
1424 ccr
|= (rqc
->scctl
<< CC_SRCCCTRL_SHFT
);
1425 ccr
|= (rqc
->dcctl
<< CC_DSTCCTRL_SHFT
);
1427 ccr
|= (rqc
->swap
<< CC_SWAP_SHFT
);
1432 static inline bool _is_valid(u32 ccr
)
1434 enum pl330_cachectrl dcctl
;
1435 enum pl330_cachectrl scctl
;
1437 dcctl
= (ccr
>> CC_DSTCCTRL_SHFT
) & CC_DRCCCTRL_MASK
;
1438 scctl
= (ccr
>> CC_SRCCCTRL_SHFT
) & CC_SRCCCTRL_MASK
;
1440 if (dcctl
== INVALID1
|| dcctl
== INVALID2
1441 || scctl
== INVALID1
|| scctl
== INVALID2
)
1448 * Submit a list of xfers after which the client wants notification.
1449 * Client is not notified after each xfer unit, just once after all
1450 * xfer units are done or some error occurs.
1452 static int pl330_submit_req(void *ch_id
, struct pl330_req
*r
)
1454 struct pl330_thread
*thrd
= ch_id
;
1455 struct pl330_dmac
*pl330
;
1456 struct pl330_info
*pi
;
1457 struct _xfer_spec xs
;
1458 unsigned long flags
;
1464 /* No Req or Unacquired Channel or DMAC */
1465 if (!r
|| !thrd
|| thrd
->free
)
1472 if (pl330
->state
== DYING
1473 || pl330
->dmac_tbd
.reset_chan
& (1 << thrd
->id
)) {
1474 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d\n",
1475 __func__
, __LINE__
);
1479 /* If request for non-existing peripheral */
1480 if (r
->rqtype
!= DMA_MEM_TO_MEM
&& r
->peri
>= pi
->pcfg
.num_peri
) {
1481 dev_info(thrd
->dmac
->pinfo
->dev
,
1482 "%s:%d Invalid peripheral(%u)!\n",
1483 __func__
, __LINE__
, r
->peri
);
1487 spin_lock_irqsave(&pl330
->lock
, flags
);
1489 if (_queue_full(thrd
)) {
1495 /* Use last settings, if not provided */
1497 /* Prefer Secure Channel */
1498 if (!_manager_ns(thrd
))
1499 r
->cfg
->nonsecure
= 0;
1501 r
->cfg
->nonsecure
= 1;
1503 ccr
= _prepare_ccr(r
->cfg
);
1505 ccr
= readl(regs
+ CC(thrd
->id
));
1508 /* If this req doesn't have valid xfer settings */
1509 if (!_is_valid(ccr
)) {
1511 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d Invalid CCR(%x)!\n",
1512 __func__
, __LINE__
, ccr
);
1516 idx
= IS_FREE(&thrd
->req
[0]) ? 0 : 1;
1521 /* First dry run to check if req is acceptable */
1522 ret
= _setup_req(1, thrd
, idx
, &xs
);
1526 if (ret
> pi
->mcbufsz
/ 2) {
1527 dev_info(thrd
->dmac
->pinfo
->dev
,
1528 "%s:%d Trying increasing mcbufsz\n",
1529 __func__
, __LINE__
);
1534 /* Hook the request */
1536 thrd
->req
[idx
].r
= r
;
1537 _setup_req(0, thrd
, idx
, &xs
);
1542 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1547 static void pl330_dotask(unsigned long data
)
1549 struct pl330_dmac
*pl330
= (struct pl330_dmac
*) data
;
1550 struct pl330_info
*pi
= pl330
->pinfo
;
1551 unsigned long flags
;
1554 spin_lock_irqsave(&pl330
->lock
, flags
);
1556 /* The DMAC itself gone nuts */
1557 if (pl330
->dmac_tbd
.reset_dmac
) {
1558 pl330
->state
= DYING
;
1559 /* Reset the manager too */
1560 pl330
->dmac_tbd
.reset_mngr
= true;
1561 /* Clear the reset flag */
1562 pl330
->dmac_tbd
.reset_dmac
= false;
1565 if (pl330
->dmac_tbd
.reset_mngr
) {
1566 _stop(pl330
->manager
);
1567 /* Reset all channels */
1568 pl330
->dmac_tbd
.reset_chan
= (1 << pi
->pcfg
.num_chan
) - 1;
1569 /* Clear the reset flag */
1570 pl330
->dmac_tbd
.reset_mngr
= false;
1573 for (i
= 0; i
< pi
->pcfg
.num_chan
; i
++) {
1575 if (pl330
->dmac_tbd
.reset_chan
& (1 << i
)) {
1576 struct pl330_thread
*thrd
= &pl330
->channels
[i
];
1577 void __iomem
*regs
= pi
->base
;
1578 enum pl330_op_err err
;
1582 if (readl(regs
+ FSC
) & (1 << thrd
->id
))
1583 err
= PL330_ERR_FAIL
;
1585 err
= PL330_ERR_ABORT
;
1587 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1589 _callback(thrd
->req
[1 - thrd
->lstenq
].r
, err
);
1590 _callback(thrd
->req
[thrd
->lstenq
].r
, err
);
1592 spin_lock_irqsave(&pl330
->lock
, flags
);
1594 thrd
->req
[0].r
= NULL
;
1595 thrd
->req
[1].r
= NULL
;
1599 /* Clear the reset flag */
1600 pl330
->dmac_tbd
.reset_chan
&= ~(1 << i
);
1604 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1609 /* Returns 1 if state was updated, 0 otherwise */
1610 static int pl330_update(const struct pl330_info
*pi
)
1612 struct pl330_req
*rqdone
, *tmp
;
1613 struct pl330_dmac
*pl330
;
1614 unsigned long flags
;
1617 int id
, ev
, ret
= 0;
1619 if (!pi
|| !pi
->pl330_data
)
1623 pl330
= pi
->pl330_data
;
1625 spin_lock_irqsave(&pl330
->lock
, flags
);
1627 val
= readl(regs
+ FSM
) & 0x1;
1629 pl330
->dmac_tbd
.reset_mngr
= true;
1631 pl330
->dmac_tbd
.reset_mngr
= false;
1633 val
= readl(regs
+ FSC
) & ((1 << pi
->pcfg
.num_chan
) - 1);
1634 pl330
->dmac_tbd
.reset_chan
|= val
;
1637 while (i
< pi
->pcfg
.num_chan
) {
1638 if (val
& (1 << i
)) {
1640 "Reset Channel-%d\t CS-%x FTC-%x\n",
1641 i
, readl(regs
+ CS(i
)),
1642 readl(regs
+ FTC(i
)));
1643 _stop(&pl330
->channels
[i
]);
1649 /* Check which event happened i.e, thread notified */
1650 val
= readl(regs
+ ES
);
1651 if (pi
->pcfg
.num_events
< 32
1652 && val
& ~((1 << pi
->pcfg
.num_events
) - 1)) {
1653 pl330
->dmac_tbd
.reset_dmac
= true;
1654 dev_err(pi
->dev
, "%s:%d Unexpected!\n", __func__
, __LINE__
);
1659 for (ev
= 0; ev
< pi
->pcfg
.num_events
; ev
++) {
1660 if (val
& (1 << ev
)) { /* Event occurred */
1661 struct pl330_thread
*thrd
;
1662 u32 inten
= readl(regs
+ INTEN
);
1665 /* Clear the event */
1666 if (inten
& (1 << ev
))
1667 writel(1 << ev
, regs
+ INTCLR
);
1671 id
= pl330
->events
[ev
];
1673 thrd
= &pl330
->channels
[id
];
1675 active
= thrd
->req_running
;
1676 if (active
== -1) /* Aborted */
1679 /* Detach the req */
1680 rqdone
= thrd
->req
[active
].r
;
1681 thrd
->req
[active
].r
= NULL
;
1683 mark_free(thrd
, active
);
1685 /* Get going again ASAP */
1688 /* For now, just make a list of callbacks to be done */
1689 list_add_tail(&rqdone
->rqd
, &pl330
->req_done
);
1693 /* Now that we are in no hurry, do the callbacks */
1694 list_for_each_entry_safe(rqdone
, tmp
, &pl330
->req_done
, rqd
) {
1695 list_del(&rqdone
->rqd
);
1697 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1698 _callback(rqdone
, PL330_ERR_NONE
);
1699 spin_lock_irqsave(&pl330
->lock
, flags
);
1703 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1705 if (pl330
->dmac_tbd
.reset_dmac
1706 || pl330
->dmac_tbd
.reset_mngr
1707 || pl330
->dmac_tbd
.reset_chan
) {
1709 tasklet_schedule(&pl330
->tasks
);
1715 static int pl330_chan_ctrl(void *ch_id
, enum pl330_chan_op op
)
1717 struct pl330_thread
*thrd
= ch_id
;
1718 struct pl330_dmac
*pl330
;
1719 unsigned long flags
;
1720 int ret
= 0, active
;
1722 if (!thrd
|| thrd
->free
|| thrd
->dmac
->state
== DYING
)
1726 active
= thrd
->req_running
;
1728 spin_lock_irqsave(&pl330
->lock
, flags
);
1731 case PL330_OP_FLUSH
:
1732 /* Make sure the channel is stopped */
1735 thrd
->req
[0].r
= NULL
;
1736 thrd
->req
[1].r
= NULL
;
1741 case PL330_OP_ABORT
:
1742 /* Make sure the channel is stopped */
1745 /* ABORT is only for the active req */
1749 thrd
->req
[active
].r
= NULL
;
1750 mark_free(thrd
, active
);
1752 /* Start the next */
1753 case PL330_OP_START
:
1754 if ((active
== -1) && !_start(thrd
))
1762 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1766 /* Reserve an event */
1767 static inline int _alloc_event(struct pl330_thread
*thrd
)
1769 struct pl330_dmac
*pl330
= thrd
->dmac
;
1770 struct pl330_info
*pi
= pl330
->pinfo
;
1773 for (ev
= 0; ev
< pi
->pcfg
.num_events
; ev
++)
1774 if (pl330
->events
[ev
] == -1) {
1775 pl330
->events
[ev
] = thrd
->id
;
1782 static bool _chan_ns(const struct pl330_info
*pi
, int i
)
1784 return pi
->pcfg
.irq_ns
& (1 << i
);
1787 /* Upon success, returns IdentityToken for the
1788 * allocated channel, NULL otherwise.
1790 static void *pl330_request_channel(const struct pl330_info
*pi
)
1792 struct pl330_thread
*thrd
= NULL
;
1793 struct pl330_dmac
*pl330
;
1794 unsigned long flags
;
1797 if (!pi
|| !pi
->pl330_data
)
1800 pl330
= pi
->pl330_data
;
1802 if (pl330
->state
== DYING
)
1805 chans
= pi
->pcfg
.num_chan
;
1807 spin_lock_irqsave(&pl330
->lock
, flags
);
1809 for (i
= 0; i
< chans
; i
++) {
1810 thrd
= &pl330
->channels
[i
];
1811 if ((thrd
->free
) && (!_manager_ns(thrd
) ||
1813 thrd
->ev
= _alloc_event(thrd
);
1814 if (thrd
->ev
>= 0) {
1817 thrd
->req
[0].r
= NULL
;
1819 thrd
->req
[1].r
= NULL
;
1827 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1832 /* Release an event */
1833 static inline void _free_event(struct pl330_thread
*thrd
, int ev
)
1835 struct pl330_dmac
*pl330
= thrd
->dmac
;
1836 struct pl330_info
*pi
= pl330
->pinfo
;
1838 /* If the event is valid and was held by the thread */
1839 if (ev
>= 0 && ev
< pi
->pcfg
.num_events
1840 && pl330
->events
[ev
] == thrd
->id
)
1841 pl330
->events
[ev
] = -1;
1844 static void pl330_release_channel(void *ch_id
)
1846 struct pl330_thread
*thrd
= ch_id
;
1847 struct pl330_dmac
*pl330
;
1848 unsigned long flags
;
1850 if (!thrd
|| thrd
->free
)
1855 _callback(thrd
->req
[1 - thrd
->lstenq
].r
, PL330_ERR_ABORT
);
1856 _callback(thrd
->req
[thrd
->lstenq
].r
, PL330_ERR_ABORT
);
1860 spin_lock_irqsave(&pl330
->lock
, flags
);
1861 _free_event(thrd
, thrd
->ev
);
1863 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1866 /* Initialize the structure for PL330 configuration, that can be used
1867 * by the client driver the make best use of the DMAC
1869 static void read_dmac_config(struct pl330_info
*pi
)
1871 void __iomem
*regs
= pi
->base
;
1874 val
= readl(regs
+ CRD
) >> CRD_DATA_WIDTH_SHIFT
;
1875 val
&= CRD_DATA_WIDTH_MASK
;
1876 pi
->pcfg
.data_bus_width
= 8 * (1 << val
);
1878 val
= readl(regs
+ CRD
) >> CRD_DATA_BUFF_SHIFT
;
1879 val
&= CRD_DATA_BUFF_MASK
;
1880 pi
->pcfg
.data_buf_dep
= val
+ 1;
1882 val
= readl(regs
+ CR0
) >> CR0_NUM_CHANS_SHIFT
;
1883 val
&= CR0_NUM_CHANS_MASK
;
1885 pi
->pcfg
.num_chan
= val
;
1887 val
= readl(regs
+ CR0
);
1888 if (val
& CR0_PERIPH_REQ_SET
) {
1889 val
= (val
>> CR0_NUM_PERIPH_SHIFT
) & CR0_NUM_PERIPH_MASK
;
1891 pi
->pcfg
.num_peri
= val
;
1892 pi
->pcfg
.peri_ns
= readl(regs
+ CR4
);
1894 pi
->pcfg
.num_peri
= 0;
1897 val
= readl(regs
+ CR0
);
1898 if (val
& CR0_BOOT_MAN_NS
)
1899 pi
->pcfg
.mode
|= DMAC_MODE_NS
;
1901 pi
->pcfg
.mode
&= ~DMAC_MODE_NS
;
1903 val
= readl(regs
+ CR0
) >> CR0_NUM_EVENTS_SHIFT
;
1904 val
&= CR0_NUM_EVENTS_MASK
;
1906 pi
->pcfg
.num_events
= val
;
1908 pi
->pcfg
.irq_ns
= readl(regs
+ CR3
);
1911 static inline void _reset_thread(struct pl330_thread
*thrd
)
1913 struct pl330_dmac
*pl330
= thrd
->dmac
;
1914 struct pl330_info
*pi
= pl330
->pinfo
;
1916 thrd
->req
[0].mc_cpu
= pl330
->mcode_cpu
1917 + (thrd
->id
* pi
->mcbufsz
);
1918 thrd
->req
[0].mc_bus
= pl330
->mcode_bus
1919 + (thrd
->id
* pi
->mcbufsz
);
1920 thrd
->req
[0].r
= NULL
;
1923 thrd
->req
[1].mc_cpu
= thrd
->req
[0].mc_cpu
1925 thrd
->req
[1].mc_bus
= thrd
->req
[0].mc_bus
1927 thrd
->req
[1].r
= NULL
;
1931 static int dmac_alloc_threads(struct pl330_dmac
*pl330
)
1933 struct pl330_info
*pi
= pl330
->pinfo
;
1934 int chans
= pi
->pcfg
.num_chan
;
1935 struct pl330_thread
*thrd
;
1938 /* Allocate 1 Manager and 'chans' Channel threads */
1939 pl330
->channels
= kzalloc((1 + chans
) * sizeof(*thrd
),
1941 if (!pl330
->channels
)
1944 /* Init Channel threads */
1945 for (i
= 0; i
< chans
; i
++) {
1946 thrd
= &pl330
->channels
[i
];
1949 _reset_thread(thrd
);
1953 /* MANAGER is indexed at the end */
1954 thrd
= &pl330
->channels
[chans
];
1958 pl330
->manager
= thrd
;
1963 static int dmac_alloc_resources(struct pl330_dmac
*pl330
)
1965 struct pl330_info
*pi
= pl330
->pinfo
;
1966 int chans
= pi
->pcfg
.num_chan
;
1970 * Alloc MicroCode buffer for 'chans' Channel threads.
1971 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1973 pl330
->mcode_cpu
= dma_alloc_coherent(pi
->dev
,
1974 chans
* pi
->mcbufsz
,
1975 &pl330
->mcode_bus
, GFP_KERNEL
);
1976 if (!pl330
->mcode_cpu
) {
1977 dev_err(pi
->dev
, "%s:%d Can't allocate memory!\n",
1978 __func__
, __LINE__
);
1982 ret
= dmac_alloc_threads(pl330
);
1984 dev_err(pi
->dev
, "%s:%d Can't to create channels for DMAC!\n",
1985 __func__
, __LINE__
);
1986 dma_free_coherent(pi
->dev
,
1987 chans
* pi
->mcbufsz
,
1988 pl330
->mcode_cpu
, pl330
->mcode_bus
);
1995 static int pl330_add(struct pl330_info
*pi
)
1997 struct pl330_dmac
*pl330
;
2001 if (!pi
|| !pi
->dev
)
2004 /* If already added */
2010 /* Check if we can handle this DMAC */
2011 if ((pi
->pcfg
.periph_id
& 0xfffff) != PERIPH_ID_VAL
) {
2012 dev_err(pi
->dev
, "PERIPH_ID 0x%x !\n", pi
->pcfg
.periph_id
);
2016 /* Read the configuration of the DMAC */
2017 read_dmac_config(pi
);
2019 if (pi
->pcfg
.num_events
== 0) {
2020 dev_err(pi
->dev
, "%s:%d Can't work without events!\n",
2021 __func__
, __LINE__
);
2025 pl330
= kzalloc(sizeof(*pl330
), GFP_KERNEL
);
2027 dev_err(pi
->dev
, "%s:%d Can't allocate memory!\n",
2028 __func__
, __LINE__
);
2032 /* Assign the info structure and private data */
2034 pi
->pl330_data
= pl330
;
2036 spin_lock_init(&pl330
->lock
);
2038 INIT_LIST_HEAD(&pl330
->req_done
);
2040 /* Use default MC buffer size if not provided */
2042 pi
->mcbufsz
= MCODE_BUFF_PER_REQ
* 2;
2044 /* Mark all events as free */
2045 for (i
= 0; i
< pi
->pcfg
.num_events
; i
++)
2046 pl330
->events
[i
] = -1;
2048 /* Allocate resources needed by the DMAC */
2049 ret
= dmac_alloc_resources(pl330
);
2051 dev_err(pi
->dev
, "Unable to create channels for DMAC\n");
2056 tasklet_init(&pl330
->tasks
, pl330_dotask
, (unsigned long) pl330
);
2058 pl330
->state
= INIT
;
2063 static int dmac_free_threads(struct pl330_dmac
*pl330
)
2065 struct pl330_info
*pi
= pl330
->pinfo
;
2066 int chans
= pi
->pcfg
.num_chan
;
2067 struct pl330_thread
*thrd
;
2070 /* Release Channel threads */
2071 for (i
= 0; i
< chans
; i
++) {
2072 thrd
= &pl330
->channels
[i
];
2073 pl330_release_channel((void *)thrd
);
2077 kfree(pl330
->channels
);
2082 static void dmac_free_resources(struct pl330_dmac
*pl330
)
2084 struct pl330_info
*pi
= pl330
->pinfo
;
2085 int chans
= pi
->pcfg
.num_chan
;
2087 dmac_free_threads(pl330
);
2089 dma_free_coherent(pi
->dev
, chans
* pi
->mcbufsz
,
2090 pl330
->mcode_cpu
, pl330
->mcode_bus
);
2093 static void pl330_del(struct pl330_info
*pi
)
2095 struct pl330_dmac
*pl330
;
2097 if (!pi
|| !pi
->pl330_data
)
2100 pl330
= pi
->pl330_data
;
2102 pl330
->state
= UNINIT
;
2104 tasklet_kill(&pl330
->tasks
);
2106 /* Free DMAC resources */
2107 dmac_free_resources(pl330
);
2110 pi
->pl330_data
= NULL
;
2113 /* forward declaration */
2114 static struct amba_driver pl330_driver
;
2116 static inline struct dma_pl330_chan
*
2117 to_pchan(struct dma_chan
*ch
)
2122 return container_of(ch
, struct dma_pl330_chan
, chan
);
2125 static inline struct dma_pl330_desc
*
2126 to_desc(struct dma_async_tx_descriptor
*tx
)
2128 return container_of(tx
, struct dma_pl330_desc
, txd
);
2131 static inline void fill_queue(struct dma_pl330_chan
*pch
)
2133 struct dma_pl330_desc
*desc
;
2136 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2138 /* If already submitted */
2139 if (desc
->status
== BUSY
)
2142 ret
= pl330_submit_req(pch
->pl330_chid
,
2145 desc
->status
= BUSY
;
2146 } else if (ret
== -EAGAIN
) {
2147 /* QFull or DMAC Dying */
2150 /* Unacceptable request */
2151 desc
->status
= DONE
;
2152 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Bad Desc(%d)\n",
2153 __func__
, __LINE__
, desc
->txd
.cookie
);
2154 tasklet_schedule(&pch
->task
);
2159 static void pl330_tasklet(unsigned long data
)
2161 struct dma_pl330_chan
*pch
= (struct dma_pl330_chan
*)data
;
2162 struct dma_pl330_desc
*desc
, *_dt
;
2163 unsigned long flags
;
2165 spin_lock_irqsave(&pch
->lock
, flags
);
2167 /* Pick up ripe tomatoes */
2168 list_for_each_entry_safe(desc
, _dt
, &pch
->work_list
, node
)
2169 if (desc
->status
== DONE
) {
2171 dma_cookie_complete(&desc
->txd
);
2172 list_move_tail(&desc
->node
, &pch
->completed_list
);
2175 /* Try to submit a req imm. next to the last completed cookie */
2178 /* Make sure the PL330 Channel thread is active */
2179 pl330_chan_ctrl(pch
->pl330_chid
, PL330_OP_START
);
2181 while (!list_empty(&pch
->completed_list
)) {
2182 dma_async_tx_callback callback
;
2183 void *callback_param
;
2185 desc
= list_first_entry(&pch
->completed_list
,
2186 struct dma_pl330_desc
, node
);
2188 callback
= desc
->txd
.callback
;
2189 callback_param
= desc
->txd
.callback_param
;
2192 desc
->status
= PREP
;
2193 list_move_tail(&desc
->node
, &pch
->work_list
);
2195 desc
->status
= FREE
;
2196 list_move_tail(&desc
->node
, &pch
->dmac
->desc_pool
);
2199 dma_descriptor_unmap(&desc
->txd
);
2202 spin_unlock_irqrestore(&pch
->lock
, flags
);
2203 callback(callback_param
);
2204 spin_lock_irqsave(&pch
->lock
, flags
);
2207 spin_unlock_irqrestore(&pch
->lock
, flags
);
2210 static void dma_pl330_rqcb(void *token
, enum pl330_op_err err
)
2212 struct dma_pl330_desc
*desc
= token
;
2213 struct dma_pl330_chan
*pch
= desc
->pchan
;
2214 unsigned long flags
;
2216 /* If desc aborted */
2220 spin_lock_irqsave(&pch
->lock
, flags
);
2222 desc
->status
= DONE
;
2224 spin_unlock_irqrestore(&pch
->lock
, flags
);
2226 tasklet_schedule(&pch
->task
);
2229 bool pl330_filter(struct dma_chan
*chan
, void *param
)
2233 if (chan
->device
->dev
->driver
!= &pl330_driver
.drv
)
2236 peri_id
= chan
->private;
2237 return *peri_id
== (unsigned long)param
;
2239 EXPORT_SYMBOL(pl330_filter
);
2241 static struct dma_chan
*of_dma_pl330_xlate(struct of_phandle_args
*dma_spec
,
2242 struct of_dma
*ofdma
)
2244 int count
= dma_spec
->args_count
;
2245 struct dma_pl330_dmac
*pdmac
= ofdma
->of_dma_data
;
2246 unsigned int chan_id
;
2251 chan_id
= dma_spec
->args
[0];
2252 if (chan_id
>= pdmac
->num_peripherals
)
2255 return dma_get_slave_channel(&pdmac
->peripherals
[chan_id
].chan
);
2258 static int pl330_alloc_chan_resources(struct dma_chan
*chan
)
2260 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2261 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2262 unsigned long flags
;
2264 spin_lock_irqsave(&pch
->lock
, flags
);
2266 dma_cookie_init(chan
);
2267 pch
->cyclic
= false;
2269 pch
->pl330_chid
= pl330_request_channel(&pdmac
->pif
);
2270 if (!pch
->pl330_chid
) {
2271 spin_unlock_irqrestore(&pch
->lock
, flags
);
2275 tasklet_init(&pch
->task
, pl330_tasklet
, (unsigned long) pch
);
2277 spin_unlock_irqrestore(&pch
->lock
, flags
);
2282 static int pl330_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
, unsigned long arg
)
2284 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2285 struct dma_pl330_desc
*desc
;
2286 unsigned long flags
;
2287 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2288 struct dma_slave_config
*slave_config
;
2292 case DMA_TERMINATE_ALL
:
2293 spin_lock_irqsave(&pch
->lock
, flags
);
2295 /* FLUSH the PL330 Channel thread */
2296 pl330_chan_ctrl(pch
->pl330_chid
, PL330_OP_FLUSH
);
2298 /* Mark all desc done */
2299 list_for_each_entry(desc
, &pch
->submitted_list
, node
) {
2300 desc
->status
= FREE
;
2301 dma_cookie_complete(&desc
->txd
);
2304 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2305 desc
->status
= FREE
;
2306 dma_cookie_complete(&desc
->txd
);
2309 list_for_each_entry(desc
, &pch
->completed_list
, node
) {
2310 desc
->status
= FREE
;
2311 dma_cookie_complete(&desc
->txd
);
2314 list_splice_tail_init(&pch
->submitted_list
, &pdmac
->desc_pool
);
2315 list_splice_tail_init(&pch
->work_list
, &pdmac
->desc_pool
);
2316 list_splice_tail_init(&pch
->completed_list
, &pdmac
->desc_pool
);
2317 spin_unlock_irqrestore(&pch
->lock
, flags
);
2319 case DMA_SLAVE_CONFIG
:
2320 slave_config
= (struct dma_slave_config
*)arg
;
2322 if (slave_config
->direction
== DMA_MEM_TO_DEV
) {
2323 if (slave_config
->dst_addr
)
2324 pch
->fifo_addr
= slave_config
->dst_addr
;
2325 if (slave_config
->dst_addr_width
)
2326 pch
->burst_sz
= __ffs(slave_config
->dst_addr_width
);
2327 if (slave_config
->dst_maxburst
)
2328 pch
->burst_len
= slave_config
->dst_maxburst
;
2329 } else if (slave_config
->direction
== DMA_DEV_TO_MEM
) {
2330 if (slave_config
->src_addr
)
2331 pch
->fifo_addr
= slave_config
->src_addr
;
2332 if (slave_config
->src_addr_width
)
2333 pch
->burst_sz
= __ffs(slave_config
->src_addr_width
);
2334 if (slave_config
->src_maxburst
)
2335 pch
->burst_len
= slave_config
->src_maxburst
;
2339 dev_err(pch
->dmac
->pif
.dev
, "Not supported command.\n");
2346 static void pl330_free_chan_resources(struct dma_chan
*chan
)
2348 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2349 unsigned long flags
;
2351 tasklet_kill(&pch
->task
);
2353 spin_lock_irqsave(&pch
->lock
, flags
);
2355 pl330_release_channel(pch
->pl330_chid
);
2356 pch
->pl330_chid
= NULL
;
2359 list_splice_tail_init(&pch
->work_list
, &pch
->dmac
->desc_pool
);
2361 spin_unlock_irqrestore(&pch
->lock
, flags
);
2364 static enum dma_status
2365 pl330_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
2366 struct dma_tx_state
*txstate
)
2368 return dma_cookie_status(chan
, cookie
, txstate
);
2371 static void pl330_issue_pending(struct dma_chan
*chan
)
2373 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2374 unsigned long flags
;
2376 spin_lock_irqsave(&pch
->lock
, flags
);
2377 list_splice_tail_init(&pch
->submitted_list
, &pch
->work_list
);
2378 spin_unlock_irqrestore(&pch
->lock
, flags
);
2380 pl330_tasklet((unsigned long)pch
);
2384 * We returned the last one of the circular list of descriptor(s)
2385 * from prep_xxx, so the argument to submit corresponds to the last
2386 * descriptor of the list.
2388 static dma_cookie_t
pl330_tx_submit(struct dma_async_tx_descriptor
*tx
)
2390 struct dma_pl330_desc
*desc
, *last
= to_desc(tx
);
2391 struct dma_pl330_chan
*pch
= to_pchan(tx
->chan
);
2392 dma_cookie_t cookie
;
2393 unsigned long flags
;
2395 spin_lock_irqsave(&pch
->lock
, flags
);
2397 /* Assign cookies to all nodes */
2398 while (!list_empty(&last
->node
)) {
2399 desc
= list_entry(last
->node
.next
, struct dma_pl330_desc
, node
);
2401 desc
->txd
.callback
= last
->txd
.callback
;
2402 desc
->txd
.callback_param
= last
->txd
.callback_param
;
2405 dma_cookie_assign(&desc
->txd
);
2407 list_move_tail(&desc
->node
, &pch
->submitted_list
);
2410 cookie
= dma_cookie_assign(&last
->txd
);
2411 list_add_tail(&last
->node
, &pch
->submitted_list
);
2412 spin_unlock_irqrestore(&pch
->lock
, flags
);
2417 static inline void _init_desc(struct dma_pl330_desc
*desc
)
2419 desc
->req
.x
= &desc
->px
;
2420 desc
->req
.token
= desc
;
2421 desc
->rqcfg
.swap
= SWAP_NO
;
2422 desc
->rqcfg
.scctl
= CCTRL0
;
2423 desc
->rqcfg
.dcctl
= CCTRL0
;
2424 desc
->req
.cfg
= &desc
->rqcfg
;
2425 desc
->req
.xfer_cb
= dma_pl330_rqcb
;
2426 desc
->txd
.tx_submit
= pl330_tx_submit
;
2428 INIT_LIST_HEAD(&desc
->node
);
2431 /* Returns the number of descriptors added to the DMAC pool */
2432 static int add_desc(struct dma_pl330_dmac
*pdmac
, gfp_t flg
, int count
)
2434 struct dma_pl330_desc
*desc
;
2435 unsigned long flags
;
2441 desc
= kcalloc(count
, sizeof(*desc
), flg
);
2445 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2447 for (i
= 0; i
< count
; i
++) {
2448 _init_desc(&desc
[i
]);
2449 list_add_tail(&desc
[i
].node
, &pdmac
->desc_pool
);
2452 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2457 static struct dma_pl330_desc
*
2458 pluck_desc(struct dma_pl330_dmac
*pdmac
)
2460 struct dma_pl330_desc
*desc
= NULL
;
2461 unsigned long flags
;
2466 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2468 if (!list_empty(&pdmac
->desc_pool
)) {
2469 desc
= list_entry(pdmac
->desc_pool
.next
,
2470 struct dma_pl330_desc
, node
);
2472 list_del_init(&desc
->node
);
2474 desc
->status
= PREP
;
2475 desc
->txd
.callback
= NULL
;
2478 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2483 static struct dma_pl330_desc
*pl330_get_desc(struct dma_pl330_chan
*pch
)
2485 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2486 u8
*peri_id
= pch
->chan
.private;
2487 struct dma_pl330_desc
*desc
;
2489 /* Pluck one desc from the pool of DMAC */
2490 desc
= pluck_desc(pdmac
);
2492 /* If the DMAC pool is empty, alloc new */
2494 if (!add_desc(pdmac
, GFP_ATOMIC
, 1))
2498 desc
= pluck_desc(pdmac
);
2500 dev_err(pch
->dmac
->pif
.dev
,
2501 "%s:%d ALERT!\n", __func__
, __LINE__
);
2506 /* Initialize the descriptor */
2508 desc
->txd
.cookie
= 0;
2509 async_tx_ack(&desc
->txd
);
2511 desc
->req
.peri
= peri_id
? pch
->chan
.chan_id
: 0;
2512 desc
->rqcfg
.pcfg
= &pch
->dmac
->pif
.pcfg
;
2514 dma_async_tx_descriptor_init(&desc
->txd
, &pch
->chan
);
2519 static inline void fill_px(struct pl330_xfer
*px
,
2520 dma_addr_t dst
, dma_addr_t src
, size_t len
)
2527 static struct dma_pl330_desc
*
2528 __pl330_prep_dma_memcpy(struct dma_pl330_chan
*pch
, dma_addr_t dst
,
2529 dma_addr_t src
, size_t len
)
2531 struct dma_pl330_desc
*desc
= pl330_get_desc(pch
);
2534 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Unable to fetch desc\n",
2535 __func__
, __LINE__
);
2540 * Ideally we should lookout for reqs bigger than
2541 * those that can be programmed with 256 bytes of
2542 * MC buffer, but considering a req size is seldom
2543 * going to be word-unaligned and more than 200MB,
2545 * Also, should the limit is reached we'd rather
2546 * have the platform increase MC buffer size than
2547 * complicating this API driver.
2549 fill_px(&desc
->px
, dst
, src
, len
);
2554 /* Call after fixing burst size */
2555 static inline int get_burst_len(struct dma_pl330_desc
*desc
, size_t len
)
2557 struct dma_pl330_chan
*pch
= desc
->pchan
;
2558 struct pl330_info
*pi
= &pch
->dmac
->pif
;
2561 burst_len
= pi
->pcfg
.data_bus_width
/ 8;
2562 burst_len
*= pi
->pcfg
.data_buf_dep
;
2563 burst_len
>>= desc
->rqcfg
.brst_size
;
2565 /* src/dst_burst_len can't be more than 16 */
2569 while (burst_len
> 1) {
2570 if (!(len
% (burst_len
<< desc
->rqcfg
.brst_size
)))
2578 static struct dma_async_tx_descriptor
*pl330_prep_dma_cyclic(
2579 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t len
,
2580 size_t period_len
, enum dma_transfer_direction direction
,
2581 unsigned long flags
, void *context
)
2583 struct dma_pl330_desc
*desc
= NULL
, *first
= NULL
;
2584 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2585 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2590 if (len
% period_len
!= 0)
2593 if (!is_slave_direction(direction
)) {
2594 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Invalid dma direction\n",
2595 __func__
, __LINE__
);
2599 for (i
= 0; i
< len
/ period_len
; i
++) {
2600 desc
= pl330_get_desc(pch
);
2602 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Unable to fetch desc\n",
2603 __func__
, __LINE__
);
2608 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2610 while (!list_empty(&first
->node
)) {
2611 desc
= list_entry(first
->node
.next
,
2612 struct dma_pl330_desc
, node
);
2613 list_move_tail(&desc
->node
, &pdmac
->desc_pool
);
2616 list_move_tail(&first
->node
, &pdmac
->desc_pool
);
2618 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2623 switch (direction
) {
2624 case DMA_MEM_TO_DEV
:
2625 desc
->rqcfg
.src_inc
= 1;
2626 desc
->rqcfg
.dst_inc
= 0;
2628 dst
= pch
->fifo_addr
;
2630 case DMA_DEV_TO_MEM
:
2631 desc
->rqcfg
.src_inc
= 0;
2632 desc
->rqcfg
.dst_inc
= 1;
2633 src
= pch
->fifo_addr
;
2640 desc
->req
.rqtype
= direction
;
2641 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2642 desc
->rqcfg
.brst_len
= 1;
2643 fill_px(&desc
->px
, dst
, src
, period_len
);
2648 list_add_tail(&desc
->node
, &first
->node
);
2650 dma_addr
+= period_len
;
2657 desc
->txd
.flags
= flags
;
2662 static struct dma_async_tx_descriptor
*
2663 pl330_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dst
,
2664 dma_addr_t src
, size_t len
, unsigned long flags
)
2666 struct dma_pl330_desc
*desc
;
2667 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2668 struct pl330_info
*pi
;
2671 if (unlikely(!pch
|| !len
))
2674 pi
= &pch
->dmac
->pif
;
2676 desc
= __pl330_prep_dma_memcpy(pch
, dst
, src
, len
);
2680 desc
->rqcfg
.src_inc
= 1;
2681 desc
->rqcfg
.dst_inc
= 1;
2682 desc
->req
.rqtype
= DMA_MEM_TO_MEM
;
2684 /* Select max possible burst size */
2685 burst
= pi
->pcfg
.data_bus_width
/ 8;
2693 desc
->rqcfg
.brst_size
= 0;
2694 while (burst
!= (1 << desc
->rqcfg
.brst_size
))
2695 desc
->rqcfg
.brst_size
++;
2697 desc
->rqcfg
.brst_len
= get_burst_len(desc
, len
);
2699 desc
->txd
.flags
= flags
;
2704 static void __pl330_giveback_desc(struct dma_pl330_dmac
*pdmac
,
2705 struct dma_pl330_desc
*first
)
2707 unsigned long flags
;
2708 struct dma_pl330_desc
*desc
;
2713 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2715 while (!list_empty(&first
->node
)) {
2716 desc
= list_entry(first
->node
.next
,
2717 struct dma_pl330_desc
, node
);
2718 list_move_tail(&desc
->node
, &pdmac
->desc_pool
);
2721 list_move_tail(&first
->node
, &pdmac
->desc_pool
);
2723 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2726 static struct dma_async_tx_descriptor
*
2727 pl330_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
2728 unsigned int sg_len
, enum dma_transfer_direction direction
,
2729 unsigned long flg
, void *context
)
2731 struct dma_pl330_desc
*first
, *desc
= NULL
;
2732 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2733 struct scatterlist
*sg
;
2737 if (unlikely(!pch
|| !sgl
|| !sg_len
))
2740 addr
= pch
->fifo_addr
;
2744 for_each_sg(sgl
, sg
, sg_len
, i
) {
2746 desc
= pl330_get_desc(pch
);
2748 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2750 dev_err(pch
->dmac
->pif
.dev
,
2751 "%s:%d Unable to fetch desc\n",
2752 __func__
, __LINE__
);
2753 __pl330_giveback_desc(pdmac
, first
);
2761 list_add_tail(&desc
->node
, &first
->node
);
2763 if (direction
== DMA_MEM_TO_DEV
) {
2764 desc
->rqcfg
.src_inc
= 1;
2765 desc
->rqcfg
.dst_inc
= 0;
2767 addr
, sg_dma_address(sg
), sg_dma_len(sg
));
2769 desc
->rqcfg
.src_inc
= 0;
2770 desc
->rqcfg
.dst_inc
= 1;
2772 sg_dma_address(sg
), addr
, sg_dma_len(sg
));
2775 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2776 desc
->rqcfg
.brst_len
= 1;
2777 desc
->req
.rqtype
= direction
;
2780 /* Return the last desc in the chain */
2781 desc
->txd
.flags
= flg
;
2785 static irqreturn_t
pl330_irq_handler(int irq
, void *data
)
2787 if (pl330_update(data
))
2793 #define PL330_DMA_BUSWIDTHS \
2794 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2795 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2796 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2797 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2798 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2800 static int pl330_dma_device_slave_caps(struct dma_chan
*dchan
,
2801 struct dma_slave_caps
*caps
)
2803 caps
->src_addr_widths
= PL330_DMA_BUSWIDTHS
;
2804 caps
->dstn_addr_widths
= PL330_DMA_BUSWIDTHS
;
2805 caps
->directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
2806 caps
->cmd_pause
= false;
2807 caps
->cmd_terminate
= true;
2808 caps
->residue_granularity
= DMA_RESIDUE_GRANULARITY_DESCRIPTOR
;
2814 pl330_probe(struct amba_device
*adev
, const struct amba_id
*id
)
2816 struct dma_pl330_platdata
*pdat
;
2817 struct dma_pl330_dmac
*pdmac
;
2818 struct dma_pl330_chan
*pch
, *_p
;
2819 struct pl330_info
*pi
;
2820 struct dma_device
*pd
;
2821 struct resource
*res
;
2825 pdat
= dev_get_platdata(&adev
->dev
);
2827 ret
= dma_set_mask_and_coherent(&adev
->dev
, DMA_BIT_MASK(32));
2831 /* Allocate a new DMAC and its Channels */
2832 pdmac
= devm_kzalloc(&adev
->dev
, sizeof(*pdmac
), GFP_KERNEL
);
2834 dev_err(&adev
->dev
, "unable to allocate mem\n");
2839 pi
->dev
= &adev
->dev
;
2840 pi
->pl330_data
= NULL
;
2841 pi
->mcbufsz
= pdat
? pdat
->mcbuf_sz
: 0;
2844 pi
->base
= devm_ioremap_resource(&adev
->dev
, res
);
2845 if (IS_ERR(pi
->base
))
2846 return PTR_ERR(pi
->base
);
2848 amba_set_drvdata(adev
, pdmac
);
2850 for (i
= 0; i
< AMBA_NR_IRQS
; i
++) {
2853 ret
= devm_request_irq(&adev
->dev
, irq
,
2854 pl330_irq_handler
, 0,
2855 dev_name(&adev
->dev
), pi
);
2863 pi
->pcfg
.periph_id
= adev
->periphid
;
2864 ret
= pl330_add(pi
);
2868 INIT_LIST_HEAD(&pdmac
->desc_pool
);
2869 spin_lock_init(&pdmac
->pool_lock
);
2871 /* Create a descriptor pool of default size */
2872 if (!add_desc(pdmac
, GFP_KERNEL
, NR_DEFAULT_DESC
))
2873 dev_warn(&adev
->dev
, "unable to allocate desc\n");
2876 INIT_LIST_HEAD(&pd
->channels
);
2878 /* Initialize channel parameters */
2880 num_chan
= max_t(int, pdat
->nr_valid_peri
, pi
->pcfg
.num_chan
);
2882 num_chan
= max_t(int, pi
->pcfg
.num_peri
, pi
->pcfg
.num_chan
);
2884 pdmac
->num_peripherals
= num_chan
;
2886 pdmac
->peripherals
= kzalloc(num_chan
* sizeof(*pch
), GFP_KERNEL
);
2887 if (!pdmac
->peripherals
) {
2889 dev_err(&adev
->dev
, "unable to allocate pdmac->peripherals\n");
2893 for (i
= 0; i
< num_chan
; i
++) {
2894 pch
= &pdmac
->peripherals
[i
];
2895 if (!adev
->dev
.of_node
)
2896 pch
->chan
.private = pdat
? &pdat
->peri_id
[i
] : NULL
;
2898 pch
->chan
.private = adev
->dev
.of_node
;
2900 INIT_LIST_HEAD(&pch
->submitted_list
);
2901 INIT_LIST_HEAD(&pch
->work_list
);
2902 INIT_LIST_HEAD(&pch
->completed_list
);
2903 spin_lock_init(&pch
->lock
);
2904 pch
->pl330_chid
= NULL
;
2905 pch
->chan
.device
= pd
;
2908 /* Add the channel to the DMAC list */
2909 list_add_tail(&pch
->chan
.device_node
, &pd
->channels
);
2912 pd
->dev
= &adev
->dev
;
2914 pd
->cap_mask
= pdat
->cap_mask
;
2916 dma_cap_set(DMA_MEMCPY
, pd
->cap_mask
);
2917 if (pi
->pcfg
.num_peri
) {
2918 dma_cap_set(DMA_SLAVE
, pd
->cap_mask
);
2919 dma_cap_set(DMA_CYCLIC
, pd
->cap_mask
);
2920 dma_cap_set(DMA_PRIVATE
, pd
->cap_mask
);
2924 pd
->device_alloc_chan_resources
= pl330_alloc_chan_resources
;
2925 pd
->device_free_chan_resources
= pl330_free_chan_resources
;
2926 pd
->device_prep_dma_memcpy
= pl330_prep_dma_memcpy
;
2927 pd
->device_prep_dma_cyclic
= pl330_prep_dma_cyclic
;
2928 pd
->device_tx_status
= pl330_tx_status
;
2929 pd
->device_prep_slave_sg
= pl330_prep_slave_sg
;
2930 pd
->device_control
= pl330_control
;
2931 pd
->device_issue_pending
= pl330_issue_pending
;
2932 pd
->device_slave_caps
= pl330_dma_device_slave_caps
;
2934 ret
= dma_async_device_register(pd
);
2936 dev_err(&adev
->dev
, "unable to register DMAC\n");
2940 if (adev
->dev
.of_node
) {
2941 ret
= of_dma_controller_register(adev
->dev
.of_node
,
2942 of_dma_pl330_xlate
, pdmac
);
2945 "unable to register DMA to the generic DT DMA helpers\n");
2949 adev
->dev
.dma_parms
= &pdmac
->dma_parms
;
2952 * This is the limit for transfers with a buswidth of 1, larger
2953 * buswidths will have larger limits.
2955 ret
= dma_set_max_seg_size(&adev
->dev
, 1900800);
2957 dev_err(&adev
->dev
, "unable to set the seg size\n");
2960 dev_info(&adev
->dev
,
2961 "Loaded driver for PL330 DMAC-%d\n", adev
->periphid
);
2962 dev_info(&adev
->dev
,
2963 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2964 pi
->pcfg
.data_buf_dep
,
2965 pi
->pcfg
.data_bus_width
/ 8, pi
->pcfg
.num_chan
,
2966 pi
->pcfg
.num_peri
, pi
->pcfg
.num_events
);
2971 list_for_each_entry_safe(pch
, _p
, &pdmac
->ddma
.channels
,
2974 /* Remove the channel */
2975 list_del(&pch
->chan
.device_node
);
2977 /* Flush the channel */
2978 pl330_control(&pch
->chan
, DMA_TERMINATE_ALL
, 0);
2979 pl330_free_chan_resources(&pch
->chan
);
2987 static int pl330_remove(struct amba_device
*adev
)
2989 struct dma_pl330_dmac
*pdmac
= amba_get_drvdata(adev
);
2990 struct dma_pl330_chan
*pch
, *_p
;
2991 struct pl330_info
*pi
;
2996 if (adev
->dev
.of_node
)
2997 of_dma_controller_free(adev
->dev
.of_node
);
2999 dma_async_device_unregister(&pdmac
->ddma
);
3002 list_for_each_entry_safe(pch
, _p
, &pdmac
->ddma
.channels
,
3005 /* Remove the channel */
3006 list_del(&pch
->chan
.device_node
);
3008 /* Flush the channel */
3009 pl330_control(&pch
->chan
, DMA_TERMINATE_ALL
, 0);
3010 pl330_free_chan_resources(&pch
->chan
);
3020 static struct amba_id pl330_ids
[] = {
3028 MODULE_DEVICE_TABLE(amba
, pl330_ids
);
3030 static struct amba_driver pl330_driver
= {
3032 .owner
= THIS_MODULE
,
3033 .name
= "dma-pl330",
3035 .id_table
= pl330_ids
,
3036 .probe
= pl330_probe
,
3037 .remove
= pl330_remove
,
3040 module_amba_driver(pl330_driver
);
3042 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
3043 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3044 MODULE_LICENSE("GPL");