2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
9 #include <linux/kernel.h>
10 #include <linux/slab.h>
11 #include <linux/dmaengine.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
17 #include <plat/ste_dma40.h>
19 #include "ste_dma40_ll.h"
21 #define D40_NAME "dma40"
23 #define D40_PHY_CHAN -1
25 /* For masking out/in 2 bit channel positions */
26 #define D40_CHAN_POS(chan) (2 * (chan / 2))
27 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
29 /* Maximum iterations taken before giving up suspending a channel */
30 #define D40_SUSPEND_MAX_IT 500
32 /* Hardware requirement on LCLA alignment */
33 #define LCLA_ALIGNMENT 0x40000
35 /* Max number of links per event group */
36 #define D40_LCLA_LINK_PER_EVENT_GRP 128
37 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
39 /* Attempts before giving up to trying to get pages that are aligned */
40 #define MAX_LCLA_ALLOC_ATTEMPTS 256
42 /* Bit markings for allocation map */
43 #define D40_ALLOC_FREE (1 << 31)
44 #define D40_ALLOC_PHY (1 << 30)
45 #define D40_ALLOC_LOG_FREE 0
47 /* Hardware designer of the block */
48 #define D40_HW_DESIGNER 0x8
51 * enum 40_command - The different commands and/or statuses.
53 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
61 D40_DMA_SUSPEND_REQ
= 2,
66 * struct d40_lli_pool - Structure for keeping LLIs in memory
68 * @base: Pointer to memory area when the pre_alloc_lli's are not large
69 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70 * pre_alloc_lli is used.
71 * @dma_addr: DMA address, if mapped
72 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
73 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
74 * one buffer to one buffer.
80 /* Space for dst and src, plus an extra for padding */
81 u8 pre_alloc_lli
[3 * sizeof(struct d40_phy_lli
)];
85 * struct d40_desc - A descriptor is one DMA job.
87 * @lli_phy: LLI settings for physical channel. Both src and dst=
88 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
90 * @lli_log: Same as above but for logical channels.
91 * @lli_pool: The pool with two entries pre-allocated.
92 * @lli_len: Number of llis of current descriptor.
93 * @lli_current: Number of transfered llis.
94 * @lcla_alloc: Number of LCLA entries allocated.
95 * @txd: DMA engine struct. Used for among other things for communication
98 * @is_in_client_list: true if the client owns this descriptor.
101 * This descriptor is used for both logical and physical transfers.
105 struct d40_phy_lli_bidir lli_phy
;
107 struct d40_log_lli_bidir lli_log
;
109 struct d40_lli_pool lli_pool
;
114 struct dma_async_tx_descriptor txd
;
115 struct list_head node
;
117 bool is_in_client_list
;
121 * struct d40_lcla_pool - LCLA pool settings and data.
123 * @base: The virtual address of LCLA. 18 bit aligned.
124 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
125 * This pointer is only there for clean-up on error.
126 * @pages: The number of pages needed for all physical channels.
127 * Only used later for clean-up on error
128 * @lock: Lock to protect the content in this struct.
129 * @alloc_map: big map over which LCLA entry is own by which job.
131 struct d40_lcla_pool
{
134 void *base_unaligned
;
137 struct d40_desc
**alloc_map
;
141 * struct d40_phy_res - struct for handling eventlines mapped to physical
144 * @lock: A lock protection this entity.
145 * @num: The physical channel number of this entity.
146 * @allocated_src: Bit mapped to show which src event line's are mapped to
147 * this physical channel. Can also be free or physically allocated.
148 * @allocated_dst: Same as for src but is dst.
149 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
162 * struct d40_chan - Struct that describes a channel.
164 * @lock: A spinlock to protect this struct.
165 * @log_num: The logical number, if any of this channel.
166 * @completed: Starts with 1, after first interrupt it is set to dma engine's
168 * @pending_tx: The number of pending transfers. Used between interrupt handler
170 * @busy: Set to true when transfer is ongoing on this channel.
171 * @phy_chan: Pointer to physical channel which this instance runs on. If this
172 * point is NULL, then the channel is not allocated.
173 * @chan: DMA engine handle.
174 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
175 * transfer and call client callback.
176 * @client: Cliented owned descriptor list.
177 * @active: Active descriptor.
178 * @queue: Queued jobs.
179 * @dma_cfg: The client configuration of this dma channel.
180 * @configured: whether the dma_cfg configuration is valid
181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
188 * This struct can either "be" a logical or a physical channel.
193 /* ID of the most recent completed transfer */
197 struct d40_phy_res
*phy_chan
;
198 struct dma_chan chan
;
199 struct tasklet_struct tasklet
;
200 struct list_head client
;
201 struct list_head active
;
202 struct list_head queue
;
203 struct stedma40_chan_cfg dma_cfg
;
205 struct d40_base
*base
;
206 /* Default register configurations */
209 struct d40_def_lcsp log_def
;
210 struct d40_log_lli_full
*lcpa
;
211 /* Runtime reconfiguration */
212 dma_addr_t runtime_addr
;
213 enum dma_data_direction runtime_direction
;
217 * struct d40_base - The big global struct, one for each probe'd instance.
219 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
220 * @execmd_lock: Lock for execute command usage since several channels share
221 * the same physical register.
222 * @dev: The device structure.
223 * @virtbase: The virtual base address of the DMA's register.
224 * @rev: silicon revision detected.
225 * @clk: Pointer to the DMA clock structure.
226 * @phy_start: Physical memory start of the DMA registers.
227 * @phy_size: Size of the DMA register map.
228 * @irq: The IRQ number.
229 * @num_phy_chans: The number of physical channels. Read from HW. This
230 * is the number of available channels for this driver, not counting "Secure
231 * mode" allocated physical channels.
232 * @num_log_chans: The number of logical channels. Calculated from
234 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
235 * @dma_slave: dma_device channels that can do only do slave transfers.
236 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
237 * @log_chans: Room for all possible logical channels in system.
238 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
239 * to log_chans entries.
240 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
241 * to phy_chans entries.
242 * @plat_data: Pointer to provided platform_data which is the driver
244 * @phy_res: Vector containing all physical channels.
245 * @lcla_pool: lcla pool settings and data.
246 * @lcpa_base: The virtual mapped address of LCPA.
247 * @phy_lcpa: The physical address of the LCPA.
248 * @lcpa_size: The size of the LCPA area.
249 * @desc_slab: cache for descriptors.
252 spinlock_t interrupt_lock
;
253 spinlock_t execmd_lock
;
255 void __iomem
*virtbase
;
258 phys_addr_t phy_start
;
259 resource_size_t phy_size
;
263 struct dma_device dma_both
;
264 struct dma_device dma_slave
;
265 struct dma_device dma_memcpy
;
266 struct d40_chan
*phy_chans
;
267 struct d40_chan
*log_chans
;
268 struct d40_chan
**lookup_log_chans
;
269 struct d40_chan
**lookup_phy_chans
;
270 struct stedma40_platform_data
*plat_data
;
271 /* Physical half channels */
272 struct d40_phy_res
*phy_res
;
273 struct d40_lcla_pool lcla_pool
;
276 resource_size_t lcpa_size
;
277 struct kmem_cache
*desc_slab
;
281 * struct d40_interrupt_lookup - lookup table for interrupt handler
283 * @src: Interrupt mask register.
284 * @clr: Interrupt clear register.
285 * @is_error: true if this is an error interrupt.
286 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
287 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
289 struct d40_interrupt_lookup
{
297 * struct d40_reg_val - simple lookup struct
299 * @reg: The register.
300 * @val: The value that belongs to the register in reg.
307 static struct device
*chan2dev(struct d40_chan
*d40c
)
309 return &d40c
->chan
.dev
->device
;
312 static bool chan_is_physical(struct d40_chan
*chan
)
314 return chan
->log_num
== D40_PHY_CHAN
;
317 static bool chan_is_logical(struct d40_chan
*chan
)
319 return !chan_is_physical(chan
);
322 static void __iomem
*chan_base(struct d40_chan
*chan
)
324 return chan
->base
->virtbase
+ D40_DREG_PCBASE
+
325 chan
->phy_chan
->num
* D40_DREG_PCDELTA
;
328 #define d40_err(dev, format, arg...) \
329 dev_err(dev, "[%s] " format, __func__, ## arg)
331 #define chan_err(d40c, format, arg...) \
332 d40_err(chan2dev(d40c), format, ## arg)
334 static int d40_pool_lli_alloc(struct d40_chan
*d40c
, struct d40_desc
*d40d
,
337 bool is_log
= chan_is_logical(d40c
);
342 align
= sizeof(struct d40_log_lli
);
344 align
= sizeof(struct d40_phy_lli
);
347 base
= d40d
->lli_pool
.pre_alloc_lli
;
348 d40d
->lli_pool
.size
= sizeof(d40d
->lli_pool
.pre_alloc_lli
);
349 d40d
->lli_pool
.base
= NULL
;
351 d40d
->lli_pool
.size
= lli_len
* 2 * align
;
353 base
= kmalloc(d40d
->lli_pool
.size
+ align
, GFP_NOWAIT
);
354 d40d
->lli_pool
.base
= base
;
356 if (d40d
->lli_pool
.base
== NULL
)
361 d40d
->lli_log
.src
= PTR_ALIGN(base
, align
);
362 d40d
->lli_log
.dst
= d40d
->lli_log
.src
+ lli_len
;
364 d40d
->lli_pool
.dma_addr
= 0;
366 d40d
->lli_phy
.src
= PTR_ALIGN(base
, align
);
367 d40d
->lli_phy
.dst
= d40d
->lli_phy
.src
+ lli_len
;
369 d40d
->lli_pool
.dma_addr
= dma_map_single(d40c
->base
->dev
,
374 if (dma_mapping_error(d40c
->base
->dev
,
375 d40d
->lli_pool
.dma_addr
)) {
376 kfree(d40d
->lli_pool
.base
);
377 d40d
->lli_pool
.base
= NULL
;
378 d40d
->lli_pool
.dma_addr
= 0;
386 static void d40_pool_lli_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
388 if (d40d
->lli_pool
.dma_addr
)
389 dma_unmap_single(d40c
->base
->dev
, d40d
->lli_pool
.dma_addr
,
390 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
392 kfree(d40d
->lli_pool
.base
);
393 d40d
->lli_pool
.base
= NULL
;
394 d40d
->lli_pool
.size
= 0;
395 d40d
->lli_log
.src
= NULL
;
396 d40d
->lli_log
.dst
= NULL
;
397 d40d
->lli_phy
.src
= NULL
;
398 d40d
->lli_phy
.dst
= NULL
;
401 static int d40_lcla_alloc_one(struct d40_chan
*d40c
,
402 struct d40_desc
*d40d
)
409 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
411 p
= d40c
->phy_chan
->num
* D40_LCLA_LINK_PER_EVENT_GRP
;
414 * Allocate both src and dst at the same time, therefore the half
415 * start on 1 since 0 can't be used since zero is used as end marker.
417 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
418 if (!d40c
->base
->lcla_pool
.alloc_map
[p
+ i
]) {
419 d40c
->base
->lcla_pool
.alloc_map
[p
+ i
] = d40d
;
426 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
431 static int d40_lcla_free_all(struct d40_chan
*d40c
,
432 struct d40_desc
*d40d
)
438 if (chan_is_physical(d40c
))
441 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
443 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
444 if (d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
445 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] == d40d
) {
446 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
447 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] = NULL
;
449 if (d40d
->lcla_alloc
== 0) {
456 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
462 static void d40_desc_remove(struct d40_desc
*d40d
)
464 list_del(&d40d
->node
);
467 static struct d40_desc
*d40_desc_get(struct d40_chan
*d40c
)
469 struct d40_desc
*desc
= NULL
;
471 if (!list_empty(&d40c
->client
)) {
475 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
)
476 if (async_tx_test_ack(&d
->txd
)) {
477 d40_pool_lli_free(d40c
, d
);
480 memset(desc
, 0, sizeof(*desc
));
486 desc
= kmem_cache_zalloc(d40c
->base
->desc_slab
, GFP_NOWAIT
);
489 INIT_LIST_HEAD(&desc
->node
);
494 static void d40_desc_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
497 d40_pool_lli_free(d40c
, d40d
);
498 d40_lcla_free_all(d40c
, d40d
);
499 kmem_cache_free(d40c
->base
->desc_slab
, d40d
);
502 static void d40_desc_submit(struct d40_chan
*d40c
, struct d40_desc
*desc
)
504 list_add_tail(&desc
->node
, &d40c
->active
);
507 static void d40_desc_load(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
509 int curr_lcla
= -EINVAL
, next_lcla
;
511 if (chan_is_physical(d40c
)) {
512 d40_phy_lli_write(d40c
->base
->virtbase
,
516 d40d
->lli_current
= d40d
->lli_len
;
519 if ((d40d
->lli_len
- d40d
->lli_current
) > 1)
520 curr_lcla
= d40_lcla_alloc_one(d40c
, d40d
);
522 d40_log_lli_lcpa_write(d40c
->lcpa
,
523 &d40d
->lli_log
.dst
[d40d
->lli_current
],
524 &d40d
->lli_log
.src
[d40d
->lli_current
],
528 for (; d40d
->lli_current
< d40d
->lli_len
; d40d
->lli_current
++) {
529 unsigned int lcla_offset
= d40c
->phy_chan
->num
* 1024 +
531 struct d40_lcla_pool
*pool
= &d40c
->base
->lcla_pool
;
532 struct d40_log_lli
*lcla
= pool
->base
+ lcla_offset
;
534 if (d40d
->lli_current
+ 1 < d40d
->lli_len
)
535 next_lcla
= d40_lcla_alloc_one(d40c
, d40d
);
539 d40_log_lli_lcla_write(lcla
,
540 &d40d
->lli_log
.dst
[d40d
->lli_current
],
541 &d40d
->lli_log
.src
[d40d
->lli_current
],
544 dma_sync_single_range_for_device(d40c
->base
->dev
,
545 pool
->dma_addr
, lcla_offset
,
546 2 * sizeof(struct d40_log_lli
),
549 curr_lcla
= next_lcla
;
551 if (curr_lcla
== -EINVAL
) {
560 static struct d40_desc
*d40_first_active_get(struct d40_chan
*d40c
)
564 if (list_empty(&d40c
->active
))
567 d
= list_first_entry(&d40c
->active
,
573 static void d40_desc_queue(struct d40_chan
*d40c
, struct d40_desc
*desc
)
575 list_add_tail(&desc
->node
, &d40c
->queue
);
578 static struct d40_desc
*d40_first_queued(struct d40_chan
*d40c
)
582 if (list_empty(&d40c
->queue
))
585 d
= list_first_entry(&d40c
->queue
,
591 static int d40_psize_2_burst_size(bool is_log
, int psize
)
594 if (psize
== STEDMA40_PSIZE_LOG_1
)
597 if (psize
== STEDMA40_PSIZE_PHY_1
)
605 * The dma only supports transmitting packages up to
606 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
607 * dma elements required to send the entire sg list
609 static int d40_size_2_dmalen(int size
, u32 data_width1
, u32 data_width2
)
612 u32 max_w
= max(data_width1
, data_width2
);
613 u32 min_w
= min(data_width1
, data_width2
);
614 u32 seg_max
= ALIGN(STEDMA40_MAX_SEG_SIZE
<< min_w
, 1 << max_w
);
616 if (seg_max
> STEDMA40_MAX_SEG_SIZE
)
617 seg_max
-= (1 << max_w
);
619 if (!IS_ALIGNED(size
, 1 << max_w
))
625 dmalen
= size
/ seg_max
;
626 if (dmalen
* seg_max
< size
)
632 static int d40_sg_2_dmalen(struct scatterlist
*sgl
, int sg_len
,
633 u32 data_width1
, u32 data_width2
)
635 struct scatterlist
*sg
;
640 for_each_sg(sgl
, sg
, sg_len
, i
) {
641 ret
= d40_size_2_dmalen(sg_dma_len(sg
),
642 data_width1
, data_width2
);
650 /* Support functions for logical channels */
652 static int d40_channel_execute_command(struct d40_chan
*d40c
,
653 enum d40_command command
)
657 void __iomem
*active_reg
;
662 spin_lock_irqsave(&d40c
->base
->execmd_lock
, flags
);
664 if (d40c
->phy_chan
->num
% 2 == 0)
665 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
667 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
669 if (command
== D40_DMA_SUSPEND_REQ
) {
670 status
= (readl(active_reg
) &
671 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
672 D40_CHAN_POS(d40c
->phy_chan
->num
);
674 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
678 wmask
= 0xffffffff & ~(D40_CHAN_POS_MASK(d40c
->phy_chan
->num
));
679 writel(wmask
| (command
<< D40_CHAN_POS(d40c
->phy_chan
->num
)),
682 if (command
== D40_DMA_SUSPEND_REQ
) {
684 for (i
= 0 ; i
< D40_SUSPEND_MAX_IT
; i
++) {
685 status
= (readl(active_reg
) &
686 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
687 D40_CHAN_POS(d40c
->phy_chan
->num
);
691 * Reduce the number of bus accesses while
692 * waiting for the DMA to suspend.
696 if (status
== D40_DMA_STOP
||
697 status
== D40_DMA_SUSPENDED
)
701 if (i
== D40_SUSPEND_MAX_IT
) {
703 "unable to suspend the chl %d (log: %d) status %x\n",
704 d40c
->phy_chan
->num
, d40c
->log_num
,
712 spin_unlock_irqrestore(&d40c
->base
->execmd_lock
, flags
);
716 static void d40_term_all(struct d40_chan
*d40c
)
718 struct d40_desc
*d40d
;
720 /* Release active descriptors */
721 while ((d40d
= d40_first_active_get(d40c
))) {
722 d40_desc_remove(d40d
);
723 d40_desc_free(d40c
, d40d
);
726 /* Release queued descriptors waiting for transfer */
727 while ((d40d
= d40_first_queued(d40c
))) {
728 d40_desc_remove(d40d
);
729 d40_desc_free(d40c
, d40d
);
733 d40c
->pending_tx
= 0;
737 static void __d40_config_set_event(struct d40_chan
*d40c
, bool enable
,
740 void __iomem
*addr
= chan_base(d40c
) + reg
;
744 writel((D40_DEACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
))
745 | ~D40_EVENTLINE_MASK(event
), addr
);
750 * The hardware sometimes doesn't register the enable when src and dst
751 * event lines are active on the same logical channel. Retry to ensure
752 * it does. Usually only one retry is sufficient.
756 writel((D40_ACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
))
757 | ~D40_EVENTLINE_MASK(event
), addr
);
759 if (readl(addr
) & D40_EVENTLINE_MASK(event
))
764 dev_dbg(chan2dev(d40c
),
765 "[%s] workaround enable S%cLNK (%d tries)\n",
766 __func__
, reg
== D40_CHAN_REG_SSLNK
? 'S' : 'D',
772 static void d40_config_set_event(struct d40_chan
*d40c
, bool do_enable
)
776 spin_lock_irqsave(&d40c
->phy_chan
->lock
, flags
);
778 /* Enable event line connected to device (or memcpy) */
779 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
780 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
)) {
781 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
783 __d40_config_set_event(d40c
, do_enable
, event
,
787 if (d40c
->dma_cfg
.dir
!= STEDMA40_PERIPH_TO_MEM
) {
788 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
790 __d40_config_set_event(d40c
, do_enable
, event
,
794 spin_unlock_irqrestore(&d40c
->phy_chan
->lock
, flags
);
797 static u32
d40_chan_has_events(struct d40_chan
*d40c
)
799 void __iomem
*chanbase
= chan_base(d40c
);
802 val
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
803 val
|= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
808 static u32
d40_get_prmo(struct d40_chan
*d40c
)
810 static const unsigned int phy_map
[] = {
811 [STEDMA40_PCHAN_BASIC_MODE
]
812 = D40_DREG_PRMO_PCHAN_BASIC
,
813 [STEDMA40_PCHAN_MODULO_MODE
]
814 = D40_DREG_PRMO_PCHAN_MODULO
,
815 [STEDMA40_PCHAN_DOUBLE_DST_MODE
]
816 = D40_DREG_PRMO_PCHAN_DOUBLE_DST
,
818 static const unsigned int log_map
[] = {
819 [STEDMA40_LCHAN_SRC_PHY_DST_LOG
]
820 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG
,
821 [STEDMA40_LCHAN_SRC_LOG_DST_PHY
]
822 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY
,
823 [STEDMA40_LCHAN_SRC_LOG_DST_LOG
]
824 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG
,
827 if (chan_is_physical(d40c
))
828 return phy_map
[d40c
->dma_cfg
.mode_opt
];
830 return log_map
[d40c
->dma_cfg
.mode_opt
];
833 static void d40_config_write(struct d40_chan
*d40c
)
838 /* Odd addresses are even addresses + 4 */
839 addr_base
= (d40c
->phy_chan
->num
% 2) * 4;
840 /* Setup channel mode to logical or physical */
841 var
= ((u32
)(chan_is_logical(d40c
)) + 1) <<
842 D40_CHAN_POS(d40c
->phy_chan
->num
);
843 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMSE
+ addr_base
);
845 /* Setup operational mode option register */
846 var
= d40_get_prmo(d40c
) << D40_CHAN_POS(d40c
->phy_chan
->num
);
848 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMOE
+ addr_base
);
850 if (chan_is_logical(d40c
)) {
851 int lidx
= (d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
)
852 & D40_SREG_ELEM_LOG_LIDX_MASK
;
853 void __iomem
*chanbase
= chan_base(d40c
);
855 /* Set default config for CFG reg */
856 writel(d40c
->src_def_cfg
, chanbase
+ D40_CHAN_REG_SSCFG
);
857 writel(d40c
->dst_def_cfg
, chanbase
+ D40_CHAN_REG_SDCFG
);
859 /* Set LIDX for lcla */
860 writel(lidx
, chanbase
+ D40_CHAN_REG_SSELT
);
861 writel(lidx
, chanbase
+ D40_CHAN_REG_SDELT
);
865 static u32
d40_residue(struct d40_chan
*d40c
)
869 if (chan_is_logical(d40c
))
870 num_elt
= (readl(&d40c
->lcpa
->lcsp2
) & D40_MEM_LCSP2_ECNT_MASK
)
871 >> D40_MEM_LCSP2_ECNT_POS
;
873 u32 val
= readl(chan_base(d40c
) + D40_CHAN_REG_SDELT
);
874 num_elt
= (val
& D40_SREG_ELEM_PHY_ECNT_MASK
)
875 >> D40_SREG_ELEM_PHY_ECNT_POS
;
878 return num_elt
* (1 << d40c
->dma_cfg
.dst_info
.data_width
);
881 static bool d40_tx_is_linked(struct d40_chan
*d40c
)
885 if (chan_is_logical(d40c
))
886 is_link
= readl(&d40c
->lcpa
->lcsp3
) & D40_MEM_LCSP3_DLOS_MASK
;
888 is_link
= readl(chan_base(d40c
) + D40_CHAN_REG_SDLNK
)
889 & D40_SREG_LNK_PHYS_LNK_MASK
;
894 static int d40_pause(struct dma_chan
*chan
)
896 struct d40_chan
*d40c
=
897 container_of(chan
, struct d40_chan
, chan
);
904 spin_lock_irqsave(&d40c
->lock
, flags
);
906 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
908 if (chan_is_logical(d40c
)) {
909 d40_config_set_event(d40c
, false);
910 /* Resume the other logical channels if any */
911 if (d40_chan_has_events(d40c
))
912 res
= d40_channel_execute_command(d40c
,
917 spin_unlock_irqrestore(&d40c
->lock
, flags
);
921 static int d40_resume(struct dma_chan
*chan
)
923 struct d40_chan
*d40c
=
924 container_of(chan
, struct d40_chan
, chan
);
931 spin_lock_irqsave(&d40c
->lock
, flags
);
933 if (d40c
->base
->rev
== 0)
934 if (chan_is_logical(d40c
)) {
935 res
= d40_channel_execute_command(d40c
,
936 D40_DMA_SUSPEND_REQ
);
940 /* If bytes left to transfer or linked tx resume job */
941 if (d40_residue(d40c
) || d40_tx_is_linked(d40c
)) {
943 if (chan_is_logical(d40c
))
944 d40_config_set_event(d40c
, true);
946 res
= d40_channel_execute_command(d40c
, D40_DMA_RUN
);
950 spin_unlock_irqrestore(&d40c
->lock
, flags
);
954 static dma_cookie_t
d40_tx_submit(struct dma_async_tx_descriptor
*tx
)
956 struct d40_chan
*d40c
= container_of(tx
->chan
,
959 struct d40_desc
*d40d
= container_of(tx
, struct d40_desc
, txd
);
962 spin_lock_irqsave(&d40c
->lock
, flags
);
966 if (d40c
->chan
.cookie
< 0)
967 d40c
->chan
.cookie
= 1;
969 d40d
->txd
.cookie
= d40c
->chan
.cookie
;
971 d40_desc_queue(d40c
, d40d
);
973 spin_unlock_irqrestore(&d40c
->lock
, flags
);
978 static int d40_start(struct d40_chan
*d40c
)
980 if (d40c
->base
->rev
== 0) {
983 if (chan_is_logical(d40c
)) {
984 err
= d40_channel_execute_command(d40c
,
985 D40_DMA_SUSPEND_REQ
);
991 if (chan_is_logical(d40c
))
992 d40_config_set_event(d40c
, true);
994 return d40_channel_execute_command(d40c
, D40_DMA_RUN
);
997 static struct d40_desc
*d40_queue_start(struct d40_chan
*d40c
)
999 struct d40_desc
*d40d
;
1002 /* Start queued jobs, if any */
1003 d40d
= d40_first_queued(d40c
);
1008 /* Remove from queue */
1009 d40_desc_remove(d40d
);
1011 /* Add to active queue */
1012 d40_desc_submit(d40c
, d40d
);
1014 /* Initiate DMA job */
1015 d40_desc_load(d40c
, d40d
);
1018 err
= d40_start(d40c
);
1027 /* called from interrupt context */
1028 static void dma_tc_handle(struct d40_chan
*d40c
)
1030 struct d40_desc
*d40d
;
1032 /* Get first active entry from list */
1033 d40d
= d40_first_active_get(d40c
);
1038 d40_lcla_free_all(d40c
, d40d
);
1040 if (d40d
->lli_current
< d40d
->lli_len
) {
1041 d40_desc_load(d40c
, d40d
);
1043 (void) d40_start(d40c
);
1047 if (d40_queue_start(d40c
) == NULL
)
1051 tasklet_schedule(&d40c
->tasklet
);
1055 static void dma_tasklet(unsigned long data
)
1057 struct d40_chan
*d40c
= (struct d40_chan
*) data
;
1058 struct d40_desc
*d40d
;
1059 unsigned long flags
;
1060 dma_async_tx_callback callback
;
1061 void *callback_param
;
1063 spin_lock_irqsave(&d40c
->lock
, flags
);
1065 /* Get first active entry from list */
1066 d40d
= d40_first_active_get(d40c
);
1071 d40c
->completed
= d40d
->txd
.cookie
;
1074 * If terminating a channel pending_tx is set to zero.
1075 * This prevents any finished active jobs to return to the client.
1077 if (d40c
->pending_tx
== 0) {
1078 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1082 /* Callback to client */
1083 callback
= d40d
->txd
.callback
;
1084 callback_param
= d40d
->txd
.callback_param
;
1086 if (async_tx_test_ack(&d40d
->txd
)) {
1087 d40_pool_lli_free(d40c
, d40d
);
1088 d40_desc_remove(d40d
);
1089 d40_desc_free(d40c
, d40d
);
1091 if (!d40d
->is_in_client_list
) {
1092 d40_desc_remove(d40d
);
1093 d40_lcla_free_all(d40c
, d40d
);
1094 list_add_tail(&d40d
->node
, &d40c
->client
);
1095 d40d
->is_in_client_list
= true;
1101 if (d40c
->pending_tx
)
1102 tasklet_schedule(&d40c
->tasklet
);
1104 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1106 if (callback
&& (d40d
->txd
.flags
& DMA_PREP_INTERRUPT
))
1107 callback(callback_param
);
1112 /* Rescue manouver if receiving double interrupts */
1113 if (d40c
->pending_tx
> 0)
1115 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1118 static irqreturn_t
d40_handle_interrupt(int irq
, void *data
)
1120 static const struct d40_interrupt_lookup il
[] = {
1121 {D40_DREG_LCTIS0
, D40_DREG_LCICR0
, false, 0},
1122 {D40_DREG_LCTIS1
, D40_DREG_LCICR1
, false, 32},
1123 {D40_DREG_LCTIS2
, D40_DREG_LCICR2
, false, 64},
1124 {D40_DREG_LCTIS3
, D40_DREG_LCICR3
, false, 96},
1125 {D40_DREG_LCEIS0
, D40_DREG_LCICR0
, true, 0},
1126 {D40_DREG_LCEIS1
, D40_DREG_LCICR1
, true, 32},
1127 {D40_DREG_LCEIS2
, D40_DREG_LCICR2
, true, 64},
1128 {D40_DREG_LCEIS3
, D40_DREG_LCICR3
, true, 96},
1129 {D40_DREG_PCTIS
, D40_DREG_PCICR
, false, D40_PHY_CHAN
},
1130 {D40_DREG_PCEIS
, D40_DREG_PCICR
, true, D40_PHY_CHAN
},
1134 u32 regs
[ARRAY_SIZE(il
)];
1138 struct d40_chan
*d40c
;
1139 unsigned long flags
;
1140 struct d40_base
*base
= data
;
1142 spin_lock_irqsave(&base
->interrupt_lock
, flags
);
1144 /* Read interrupt status of both logical and physical channels */
1145 for (i
= 0; i
< ARRAY_SIZE(il
); i
++)
1146 regs
[i
] = readl(base
->virtbase
+ il
[i
].src
);
1150 chan
= find_next_bit((unsigned long *)regs
,
1151 BITS_PER_LONG
* ARRAY_SIZE(il
), chan
+ 1);
1153 /* No more set bits found? */
1154 if (chan
== BITS_PER_LONG
* ARRAY_SIZE(il
))
1157 row
= chan
/ BITS_PER_LONG
;
1158 idx
= chan
& (BITS_PER_LONG
- 1);
1161 writel(1 << idx
, base
->virtbase
+ il
[row
].clr
);
1163 if (il
[row
].offset
== D40_PHY_CHAN
)
1164 d40c
= base
->lookup_phy_chans
[idx
];
1166 d40c
= base
->lookup_log_chans
[il
[row
].offset
+ idx
];
1167 spin_lock(&d40c
->lock
);
1169 if (!il
[row
].is_error
)
1170 dma_tc_handle(d40c
);
1172 d40_err(base
->dev
, "IRQ chan: %ld offset %d idx %d\n",
1173 chan
, il
[row
].offset
, idx
);
1175 spin_unlock(&d40c
->lock
);
1178 spin_unlock_irqrestore(&base
->interrupt_lock
, flags
);
1183 static int d40_validate_conf(struct d40_chan
*d40c
,
1184 struct stedma40_chan_cfg
*conf
)
1187 u32 dst_event_group
= D40_TYPE_TO_GROUP(conf
->dst_dev_type
);
1188 u32 src_event_group
= D40_TYPE_TO_GROUP(conf
->src_dev_type
);
1189 bool is_log
= conf
->mode
== STEDMA40_MODE_LOGICAL
;
1192 chan_err(d40c
, "Invalid direction.\n");
1196 if (conf
->dst_dev_type
!= STEDMA40_DEV_DST_MEMORY
&&
1197 d40c
->base
->plat_data
->dev_tx
[conf
->dst_dev_type
] == 0 &&
1198 d40c
->runtime_addr
== 0) {
1200 chan_err(d40c
, "Invalid TX channel address (%d)\n",
1201 conf
->dst_dev_type
);
1205 if (conf
->src_dev_type
!= STEDMA40_DEV_SRC_MEMORY
&&
1206 d40c
->base
->plat_data
->dev_rx
[conf
->src_dev_type
] == 0 &&
1207 d40c
->runtime_addr
== 0) {
1208 chan_err(d40c
, "Invalid RX channel address (%d)\n",
1209 conf
->src_dev_type
);
1213 if (conf
->dir
== STEDMA40_MEM_TO_PERIPH
&&
1214 dst_event_group
== STEDMA40_DEV_DST_MEMORY
) {
1215 chan_err(d40c
, "Invalid dst\n");
1219 if (conf
->dir
== STEDMA40_PERIPH_TO_MEM
&&
1220 src_event_group
== STEDMA40_DEV_SRC_MEMORY
) {
1221 chan_err(d40c
, "Invalid src\n");
1225 if (src_event_group
== STEDMA40_DEV_SRC_MEMORY
&&
1226 dst_event_group
== STEDMA40_DEV_DST_MEMORY
&& is_log
) {
1227 chan_err(d40c
, "No event line\n");
1231 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
&&
1232 (src_event_group
!= dst_event_group
)) {
1233 chan_err(d40c
, "Invalid event group\n");
1237 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
) {
1239 * DMAC HW supports it. Will be added to this driver,
1240 * in case any dma client requires it.
1242 chan_err(d40c
, "periph to periph not supported\n");
1246 if (d40_psize_2_burst_size(is_log
, conf
->src_info
.psize
) *
1247 (1 << conf
->src_info
.data_width
) !=
1248 d40_psize_2_burst_size(is_log
, conf
->dst_info
.psize
) *
1249 (1 << conf
->dst_info
.data_width
)) {
1251 * The DMAC hardware only supports
1252 * src (burst x width) == dst (burst x width)
1255 chan_err(d40c
, "src (burst x width) != dst (burst x width)\n");
1262 static bool d40_alloc_mask_set(struct d40_phy_res
*phy
, bool is_src
,
1263 int log_event_line
, bool is_log
)
1265 unsigned long flags
;
1266 spin_lock_irqsave(&phy
->lock
, flags
);
1268 /* Physical interrupts are masked per physical full channel */
1269 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1270 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1271 phy
->allocated_dst
= D40_ALLOC_PHY
;
1272 phy
->allocated_src
= D40_ALLOC_PHY
;
1278 /* Logical channel */
1280 if (phy
->allocated_src
== D40_ALLOC_PHY
)
1283 if (phy
->allocated_src
== D40_ALLOC_FREE
)
1284 phy
->allocated_src
= D40_ALLOC_LOG_FREE
;
1286 if (!(phy
->allocated_src
& (1 << log_event_line
))) {
1287 phy
->allocated_src
|= 1 << log_event_line
;
1292 if (phy
->allocated_dst
== D40_ALLOC_PHY
)
1295 if (phy
->allocated_dst
== D40_ALLOC_FREE
)
1296 phy
->allocated_dst
= D40_ALLOC_LOG_FREE
;
1298 if (!(phy
->allocated_dst
& (1 << log_event_line
))) {
1299 phy
->allocated_dst
|= 1 << log_event_line
;
1306 spin_unlock_irqrestore(&phy
->lock
, flags
);
1309 spin_unlock_irqrestore(&phy
->lock
, flags
);
1313 static bool d40_alloc_mask_free(struct d40_phy_res
*phy
, bool is_src
,
1316 unsigned long flags
;
1317 bool is_free
= false;
1319 spin_lock_irqsave(&phy
->lock
, flags
);
1320 if (!log_event_line
) {
1321 phy
->allocated_dst
= D40_ALLOC_FREE
;
1322 phy
->allocated_src
= D40_ALLOC_FREE
;
1327 /* Logical channel */
1329 phy
->allocated_src
&= ~(1 << log_event_line
);
1330 if (phy
->allocated_src
== D40_ALLOC_LOG_FREE
)
1331 phy
->allocated_src
= D40_ALLOC_FREE
;
1333 phy
->allocated_dst
&= ~(1 << log_event_line
);
1334 if (phy
->allocated_dst
== D40_ALLOC_LOG_FREE
)
1335 phy
->allocated_dst
= D40_ALLOC_FREE
;
1338 is_free
= ((phy
->allocated_src
| phy
->allocated_dst
) ==
1342 spin_unlock_irqrestore(&phy
->lock
, flags
);
1347 static int d40_allocate_channel(struct d40_chan
*d40c
)
1352 struct d40_phy_res
*phys
;
1357 bool is_log
= d40c
->dma_cfg
.mode
== STEDMA40_MODE_LOGICAL
;
1359 phys
= d40c
->base
->phy_res
;
1361 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1362 dev_type
= d40c
->dma_cfg
.src_dev_type
;
1363 log_num
= 2 * dev_type
;
1365 } else if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1366 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1367 /* dst event lines are used for logical memcpy */
1368 dev_type
= d40c
->dma_cfg
.dst_dev_type
;
1369 log_num
= 2 * dev_type
+ 1;
1374 event_group
= D40_TYPE_TO_GROUP(dev_type
);
1375 event_line
= D40_TYPE_TO_EVENT(dev_type
);
1378 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1379 /* Find physical half channel */
1380 for (i
= 0; i
< d40c
->base
->num_phy_chans
; i
++) {
1382 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1387 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1388 int phy_num
= j
+ event_group
* 2;
1389 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1390 if (d40_alloc_mask_set(&phys
[i
],
1399 d40c
->phy_chan
= &phys
[i
];
1400 d40c
->log_num
= D40_PHY_CHAN
;
1406 /* Find logical channel */
1407 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1408 int phy_num
= j
+ event_group
* 2;
1410 * Spread logical channels across all available physical rather
1411 * than pack every logical channel at the first available phy
1415 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1416 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1417 event_line
, is_log
))
1421 for (i
= phy_num
+ 1; i
>= phy_num
; i
--) {
1422 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1423 event_line
, is_log
))
1431 d40c
->phy_chan
= &phys
[i
];
1432 d40c
->log_num
= log_num
;
1436 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = d40c
;
1438 d40c
->base
->lookup_phy_chans
[d40c
->phy_chan
->num
] = d40c
;
1444 static int d40_config_memcpy(struct d40_chan
*d40c
)
1446 dma_cap_mask_t cap
= d40c
->chan
.device
->cap_mask
;
1448 if (dma_has_cap(DMA_MEMCPY
, cap
) && !dma_has_cap(DMA_SLAVE
, cap
)) {
1449 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_log
;
1450 d40c
->dma_cfg
.src_dev_type
= STEDMA40_DEV_SRC_MEMORY
;
1451 d40c
->dma_cfg
.dst_dev_type
= d40c
->base
->plat_data
->
1452 memcpy
[d40c
->chan
.chan_id
];
1454 } else if (dma_has_cap(DMA_MEMCPY
, cap
) &&
1455 dma_has_cap(DMA_SLAVE
, cap
)) {
1456 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_phy
;
1458 chan_err(d40c
, "No memcpy\n");
1466 static int d40_free_dma(struct d40_chan
*d40c
)
1471 struct d40_phy_res
*phy
= d40c
->phy_chan
;
1474 struct d40_desc
*_d
;
1477 /* Terminate all queued and active transfers */
1480 /* Release client owned descriptors */
1481 if (!list_empty(&d40c
->client
))
1482 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
) {
1483 d40_pool_lli_free(d40c
, d
);
1485 d40_desc_free(d40c
, d
);
1489 chan_err(d40c
, "phy == null\n");
1493 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1494 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1495 chan_err(d40c
, "channel already free\n");
1499 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1500 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1501 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1503 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1504 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1507 chan_err(d40c
, "Unknown direction\n");
1511 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1513 chan_err(d40c
, "suspend failed\n");
1517 if (chan_is_logical(d40c
)) {
1518 /* Release logical channel, deactivate the event line */
1520 d40_config_set_event(d40c
, false);
1521 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = NULL
;
1524 * Check if there are more logical allocation
1525 * on this phy channel.
1527 if (!d40_alloc_mask_free(phy
, is_src
, event
)) {
1528 /* Resume the other logical channels if any */
1529 if (d40_chan_has_events(d40c
)) {
1530 res
= d40_channel_execute_command(d40c
,
1534 "Executing RUN command\n");
1541 (void) d40_alloc_mask_free(phy
, is_src
, 0);
1544 /* Release physical channel */
1545 res
= d40_channel_execute_command(d40c
, D40_DMA_STOP
);
1547 chan_err(d40c
, "Failed to stop channel\n");
1550 d40c
->phy_chan
= NULL
;
1551 d40c
->configured
= false;
1552 d40c
->base
->lookup_phy_chans
[phy
->num
] = NULL
;
1557 static bool d40_is_paused(struct d40_chan
*d40c
)
1559 void __iomem
*chanbase
= chan_base(d40c
);
1560 bool is_paused
= false;
1561 unsigned long flags
;
1562 void __iomem
*active_reg
;
1566 spin_lock_irqsave(&d40c
->lock
, flags
);
1568 if (chan_is_physical(d40c
)) {
1569 if (d40c
->phy_chan
->num
% 2 == 0)
1570 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
1572 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
1574 status
= (readl(active_reg
) &
1575 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
1576 D40_CHAN_POS(d40c
->phy_chan
->num
);
1577 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
1583 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1584 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1585 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1586 status
= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
1587 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1588 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1589 status
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
1591 chan_err(d40c
, "Unknown direction\n");
1595 status
= (status
& D40_EVENTLINE_MASK(event
)) >>
1596 D40_EVENTLINE_POS(event
);
1598 if (status
!= D40_DMA_RUN
)
1601 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1607 static u32
stedma40_residue(struct dma_chan
*chan
)
1609 struct d40_chan
*d40c
=
1610 container_of(chan
, struct d40_chan
, chan
);
1612 unsigned long flags
;
1614 spin_lock_irqsave(&d40c
->lock
, flags
);
1615 bytes_left
= d40_residue(d40c
);
1616 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1622 d40_prep_sg_log(struct d40_chan
*chan
, struct d40_desc
*desc
,
1623 struct scatterlist
*sg_src
, struct scatterlist
*sg_dst
,
1624 unsigned int sg_len
, enum dma_data_direction direction
,
1625 dma_addr_t dev_addr
)
1627 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
1628 struct stedma40_half_channel_info
*src_info
= &cfg
->src_info
;
1629 struct stedma40_half_channel_info
*dst_info
= &cfg
->dst_info
;
1631 if (direction
== DMA_NONE
) {
1633 (void) d40_log_sg_to_lli(sg_src
, sg_len
,
1635 chan
->log_def
.lcsp1
,
1636 src_info
->data_width
,
1637 dst_info
->data_width
);
1639 (void) d40_log_sg_to_lli(sg_dst
, sg_len
,
1641 chan
->log_def
.lcsp3
,
1642 dst_info
->data_width
,
1643 src_info
->data_width
);
1645 unsigned int total_size
;
1647 total_size
= d40_log_sg_to_dev(sg_src
, sg_len
,
1650 src_info
->data_width
,
1651 dst_info
->data_width
,
1652 direction
, dev_addr
);
1661 d40_prep_sg_phy(struct d40_chan
*chan
, struct d40_desc
*desc
,
1662 struct scatterlist
*sg_src
, struct scatterlist
*sg_dst
,
1663 unsigned int sg_len
, enum dma_data_direction direction
,
1664 dma_addr_t dev_addr
)
1666 dma_addr_t src_dev_addr
= direction
== DMA_FROM_DEVICE
? dev_addr
: 0;
1667 dma_addr_t dst_dev_addr
= direction
== DMA_TO_DEVICE
? dev_addr
: 0;
1668 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
1669 struct stedma40_half_channel_info
*src_info
= &cfg
->src_info
;
1670 struct stedma40_half_channel_info
*dst_info
= &cfg
->dst_info
;
1673 ret
= d40_phy_sg_to_lli(sg_src
, sg_len
, src_dev_addr
,
1675 virt_to_phys(desc
->lli_phy
.src
),
1677 src_info
->data_width
,
1678 dst_info
->data_width
,
1681 ret
= d40_phy_sg_to_lli(sg_dst
, sg_len
, dst_dev_addr
,
1683 virt_to_phys(desc
->lli_phy
.dst
),
1685 dst_info
->data_width
,
1686 src_info
->data_width
,
1689 dma_sync_single_for_device(chan
->base
->dev
, desc
->lli_pool
.dma_addr
,
1690 desc
->lli_pool
.size
, DMA_TO_DEVICE
);
1692 return ret
< 0 ? ret
: 0;
1696 static struct d40_desc
*
1697 d40_prep_desc(struct d40_chan
*chan
, struct scatterlist
*sg
,
1698 unsigned int sg_len
, unsigned long dma_flags
)
1700 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
1701 struct d40_desc
*desc
;
1704 desc
= d40_desc_get(chan
);
1708 desc
->lli_len
= d40_sg_2_dmalen(sg
, sg_len
, cfg
->src_info
.data_width
,
1709 cfg
->dst_info
.data_width
);
1710 if (desc
->lli_len
< 0) {
1711 chan_err(chan
, "Unaligned size\n");
1715 ret
= d40_pool_lli_alloc(chan
, desc
, desc
->lli_len
);
1717 chan_err(chan
, "Could not allocate lli\n");
1722 desc
->lli_current
= 0;
1723 desc
->txd
.flags
= dma_flags
;
1724 desc
->txd
.tx_submit
= d40_tx_submit
;
1726 dma_async_tx_descriptor_init(&desc
->txd
, &chan
->chan
);
1731 d40_desc_free(chan
, desc
);
1735 struct dma_async_tx_descriptor
*stedma40_memcpy_sg(struct dma_chan
*chan
,
1736 static struct dma_async_tx_descriptor
*stedma40_memcpy_sg(struct dma_chan
*chan
,
1737 struct scatterlist
*sgl_dst
,
1738 struct scatterlist
*sgl_src
,
1739 unsigned int sgl_len
,
1740 unsigned long dma_flags
)
1742 struct d40_desc
*d40d
;
1743 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1745 unsigned long flags
;
1747 if (d40c
->phy_chan
== NULL
) {
1748 chan_err(d40c
, "Unallocated channel.\n");
1749 return ERR_PTR(-EINVAL
);
1752 spin_lock_irqsave(&d40c
->lock
, flags
);
1754 d40d
= d40_prep_desc(d40c
, sgl_dst
, sgl_len
, dma_flags
);
1758 if (chan_is_logical(d40c
)) {
1759 d40_prep_sg_log(d40c
, d40d
, sgl_src
, sgl_dst
,
1760 sgl_len
, DMA_NONE
, 0);
1762 d40_prep_sg_phy(d40c
, d40d
, sgl_src
, sgl_dst
,
1763 sgl_len
, DMA_NONE
, 0);
1766 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1771 d40_desc_free(d40c
, d40d
);
1772 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1776 bool stedma40_filter(struct dma_chan
*chan
, void *data
)
1778 struct stedma40_chan_cfg
*info
= data
;
1779 struct d40_chan
*d40c
=
1780 container_of(chan
, struct d40_chan
, chan
);
1784 err
= d40_validate_conf(d40c
, info
);
1786 d40c
->dma_cfg
= *info
;
1788 err
= d40_config_memcpy(d40c
);
1791 d40c
->configured
= true;
1795 EXPORT_SYMBOL(stedma40_filter
);
1797 static void __d40_set_prio_rt(struct d40_chan
*d40c
, int dev_type
, bool src
)
1799 bool realtime
= d40c
->dma_cfg
.realtime
;
1800 bool highprio
= d40c
->dma_cfg
.high_priority
;
1801 u32 prioreg
= highprio
? D40_DREG_PSEG1
: D40_DREG_PCEG1
;
1802 u32 rtreg
= realtime
? D40_DREG_RSEG1
: D40_DREG_RCEG1
;
1803 u32 event
= D40_TYPE_TO_EVENT(dev_type
);
1804 u32 group
= D40_TYPE_TO_GROUP(dev_type
);
1805 u32 bit
= 1 << event
;
1807 /* Destination event lines are stored in the upper halfword */
1811 writel(bit
, d40c
->base
->virtbase
+ prioreg
+ group
* 4);
1812 writel(bit
, d40c
->base
->virtbase
+ rtreg
+ group
* 4);
1815 static void d40_set_prio_realtime(struct d40_chan
*d40c
)
1817 if (d40c
->base
->rev
< 3)
1820 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
1821 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
1822 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.src_dev_type
, true);
1824 if ((d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
) ||
1825 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
1826 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.dst_dev_type
, false);
1829 /* DMA ENGINE functions */
1830 static int d40_alloc_chan_resources(struct dma_chan
*chan
)
1833 unsigned long flags
;
1834 struct d40_chan
*d40c
=
1835 container_of(chan
, struct d40_chan
, chan
);
1837 spin_lock_irqsave(&d40c
->lock
, flags
);
1839 d40c
->completed
= chan
->cookie
= 1;
1841 /* If no dma configuration is set use default configuration (memcpy) */
1842 if (!d40c
->configured
) {
1843 err
= d40_config_memcpy(d40c
);
1845 chan_err(d40c
, "Failed to configure memcpy channel\n");
1849 is_free_phy
= (d40c
->phy_chan
== NULL
);
1851 err
= d40_allocate_channel(d40c
);
1853 chan_err(d40c
, "Failed to allocate channel\n");
1857 /* Fill in basic CFG register values */
1858 d40_phy_cfg(&d40c
->dma_cfg
, &d40c
->src_def_cfg
,
1859 &d40c
->dst_def_cfg
, chan_is_logical(d40c
));
1861 d40_set_prio_realtime(d40c
);
1863 if (chan_is_logical(d40c
)) {
1864 d40_log_cfg(&d40c
->dma_cfg
,
1865 &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
1867 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
1868 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1869 d40c
->dma_cfg
.src_dev_type
* D40_LCPA_CHAN_SIZE
;
1871 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1872 d40c
->dma_cfg
.dst_dev_type
*
1873 D40_LCPA_CHAN_SIZE
+ D40_LCPA_CHAN_DST_DELTA
;
1877 * Only write channel configuration to the DMA if the physical
1878 * resource is free. In case of multiple logical channels
1879 * on the same physical resource, only the first write is necessary.
1882 d40_config_write(d40c
);
1884 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1888 static void d40_free_chan_resources(struct dma_chan
*chan
)
1890 struct d40_chan
*d40c
=
1891 container_of(chan
, struct d40_chan
, chan
);
1893 unsigned long flags
;
1895 if (d40c
->phy_chan
== NULL
) {
1896 chan_err(d40c
, "Cannot free unallocated channel\n");
1901 spin_lock_irqsave(&d40c
->lock
, flags
);
1903 err
= d40_free_dma(d40c
);
1906 chan_err(d40c
, "Failed to free channel\n");
1907 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1910 static struct dma_async_tx_descriptor
*d40_prep_memcpy(struct dma_chan
*chan
,
1914 unsigned long dma_flags
)
1916 struct scatterlist dst_sg
;
1917 struct scatterlist src_sg
;
1919 sg_init_table(&dst_sg
, 1);
1920 sg_init_table(&src_sg
, 1);
1922 sg_dma_address(&dst_sg
) = dst
;
1923 sg_dma_address(&src_sg
) = src
;
1925 sg_dma_len(&dst_sg
) = size
;
1926 sg_dma_len(&src_sg
) = size
;
1928 return stedma40_memcpy_sg(chan
, &dst_sg
, &src_sg
, 1, dma_flags
);
1931 static struct dma_async_tx_descriptor
*
1932 d40_prep_sg(struct dma_chan
*chan
,
1933 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
1934 struct scatterlist
*src_sg
, unsigned int src_nents
,
1935 unsigned long dma_flags
)
1937 if (dst_nents
!= src_nents
)
1940 return stedma40_memcpy_sg(chan
, dst_sg
, src_sg
, dst_nents
, dma_flags
);
1944 d40_get_dev_addr(struct d40_chan
*chan
, enum dma_data_direction direction
)
1946 struct stedma40_platform_data
*plat
= chan
->base
->plat_data
;
1947 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
1950 if (chan
->runtime_addr
)
1951 return chan
->runtime_addr
;
1953 if (direction
== DMA_FROM_DEVICE
)
1954 addr
= plat
->dev_rx
[cfg
->src_dev_type
];
1955 else if (direction
== DMA_TO_DEVICE
)
1956 addr
= plat
->dev_tx
[cfg
->dst_dev_type
];
1961 static struct dma_async_tx_descriptor
*d40_prep_slave_sg(struct dma_chan
*chan
,
1962 struct scatterlist
*sgl
,
1963 unsigned int sg_len
,
1964 enum dma_data_direction direction
,
1965 unsigned long dma_flags
)
1967 struct d40_desc
*d40d
;
1968 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1970 dma_addr_t dev_addr
;
1971 unsigned long flags
;
1974 if (d40c
->phy_chan
== NULL
) {
1975 chan_err(d40c
, "Cannot prepare unallocated channel\n");
1976 return ERR_PTR(-EINVAL
);
1979 if (direction
!= DMA_FROM_DEVICE
&& direction
!= DMA_TO_DEVICE
)
1982 spin_lock_irqsave(&d40c
->lock
, flags
);
1984 d40d
= d40_prep_desc(d40c
, sgl
, sg_len
, dma_flags
);
1988 dev_addr
= d40_get_dev_addr(d40c
, direction
);
1990 if (chan_is_logical(d40c
))
1991 err
= d40_prep_sg_log(d40c
, d40d
, sgl
, NULL
,
1992 sg_len
, direction
, dev_addr
);
1994 err
= d40_prep_sg_phy(d40c
, d40d
, sgl
, NULL
,
1995 sg_len
, direction
, dev_addr
);
1998 chan_err(d40c
, "Failed to prepare %s slave sg job: %d\n",
1999 chan_is_logical(d40c
) ? "log" : "phy", err
);
2003 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2008 d40_desc_free(d40c
, d40d
);
2009 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2013 static enum dma_status
d40_tx_status(struct dma_chan
*chan
,
2014 dma_cookie_t cookie
,
2015 struct dma_tx_state
*txstate
)
2017 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2018 dma_cookie_t last_used
;
2019 dma_cookie_t last_complete
;
2022 if (d40c
->phy_chan
== NULL
) {
2023 chan_err(d40c
, "Cannot read status of unallocated channel\n");
2027 last_complete
= d40c
->completed
;
2028 last_used
= chan
->cookie
;
2030 if (d40_is_paused(d40c
))
2033 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
2035 dma_set_tx_state(txstate
, last_complete
, last_used
,
2036 stedma40_residue(chan
));
2041 static void d40_issue_pending(struct dma_chan
*chan
)
2043 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2044 unsigned long flags
;
2046 if (d40c
->phy_chan
== NULL
) {
2047 chan_err(d40c
, "Channel is not allocated!\n");
2051 spin_lock_irqsave(&d40c
->lock
, flags
);
2053 /* Busy means that pending jobs are already being processed */
2055 (void) d40_queue_start(d40c
);
2057 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2060 /* Runtime reconfiguration extension */
2061 static void d40_set_runtime_config(struct dma_chan
*chan
,
2062 struct dma_slave_config
*config
)
2064 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2065 struct stedma40_chan_cfg
*cfg
= &d40c
->dma_cfg
;
2066 enum dma_slave_buswidth config_addr_width
;
2067 dma_addr_t config_addr
;
2068 u32 config_maxburst
;
2069 enum stedma40_periph_data_width addr_width
;
2072 if (config
->direction
== DMA_FROM_DEVICE
) {
2073 dma_addr_t dev_addr_rx
=
2074 d40c
->base
->plat_data
->dev_rx
[cfg
->src_dev_type
];
2076 config_addr
= config
->src_addr
;
2078 dev_dbg(d40c
->base
->dev
,
2079 "channel has a pre-wired RX address %08x "
2080 "overriding with %08x\n",
2081 dev_addr_rx
, config_addr
);
2082 if (cfg
->dir
!= STEDMA40_PERIPH_TO_MEM
)
2083 dev_dbg(d40c
->base
->dev
,
2084 "channel was not configured for peripheral "
2085 "to memory transfer (%d) overriding\n",
2087 cfg
->dir
= STEDMA40_PERIPH_TO_MEM
;
2089 config_addr_width
= config
->src_addr_width
;
2090 config_maxburst
= config
->src_maxburst
;
2092 } else if (config
->direction
== DMA_TO_DEVICE
) {
2093 dma_addr_t dev_addr_tx
=
2094 d40c
->base
->plat_data
->dev_tx
[cfg
->dst_dev_type
];
2096 config_addr
= config
->dst_addr
;
2098 dev_dbg(d40c
->base
->dev
,
2099 "channel has a pre-wired TX address %08x "
2100 "overriding with %08x\n",
2101 dev_addr_tx
, config_addr
);
2102 if (cfg
->dir
!= STEDMA40_MEM_TO_PERIPH
)
2103 dev_dbg(d40c
->base
->dev
,
2104 "channel was not configured for memory "
2105 "to peripheral transfer (%d) overriding\n",
2107 cfg
->dir
= STEDMA40_MEM_TO_PERIPH
;
2109 config_addr_width
= config
->dst_addr_width
;
2110 config_maxburst
= config
->dst_maxburst
;
2113 dev_err(d40c
->base
->dev
,
2114 "unrecognized channel direction %d\n",
2119 switch (config_addr_width
) {
2120 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
2121 addr_width
= STEDMA40_BYTE_WIDTH
;
2123 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
2124 addr_width
= STEDMA40_HALFWORD_WIDTH
;
2126 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
2127 addr_width
= STEDMA40_WORD_WIDTH
;
2129 case DMA_SLAVE_BUSWIDTH_8_BYTES
:
2130 addr_width
= STEDMA40_DOUBLEWORD_WIDTH
;
2133 dev_err(d40c
->base
->dev
,
2134 "illegal peripheral address width "
2136 config
->src_addr_width
);
2140 if (chan_is_logical(d40c
)) {
2141 if (config_maxburst
>= 16)
2142 psize
= STEDMA40_PSIZE_LOG_16
;
2143 else if (config_maxburst
>= 8)
2144 psize
= STEDMA40_PSIZE_LOG_8
;
2145 else if (config_maxburst
>= 4)
2146 psize
= STEDMA40_PSIZE_LOG_4
;
2148 psize
= STEDMA40_PSIZE_LOG_1
;
2150 if (config_maxburst
>= 16)
2151 psize
= STEDMA40_PSIZE_PHY_16
;
2152 else if (config_maxburst
>= 8)
2153 psize
= STEDMA40_PSIZE_PHY_8
;
2154 else if (config_maxburst
>= 4)
2155 psize
= STEDMA40_PSIZE_PHY_4
;
2156 else if (config_maxburst
>= 2)
2157 psize
= STEDMA40_PSIZE_PHY_2
;
2159 psize
= STEDMA40_PSIZE_PHY_1
;
2162 /* Set up all the endpoint configs */
2163 cfg
->src_info
.data_width
= addr_width
;
2164 cfg
->src_info
.psize
= psize
;
2165 cfg
->src_info
.big_endian
= false;
2166 cfg
->src_info
.flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2167 cfg
->dst_info
.data_width
= addr_width
;
2168 cfg
->dst_info
.psize
= psize
;
2169 cfg
->dst_info
.big_endian
= false;
2170 cfg
->dst_info
.flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2172 /* Fill in register values */
2173 if (chan_is_logical(d40c
))
2174 d40_log_cfg(cfg
, &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
2176 d40_phy_cfg(cfg
, &d40c
->src_def_cfg
,
2177 &d40c
->dst_def_cfg
, false);
2179 /* These settings will take precedence later */
2180 d40c
->runtime_addr
= config_addr
;
2181 d40c
->runtime_direction
= config
->direction
;
2182 dev_dbg(d40c
->base
->dev
,
2183 "configured channel %s for %s, data width %d, "
2184 "maxburst %d bytes, LE, no flow control\n",
2185 dma_chan_name(chan
),
2186 (config
->direction
== DMA_FROM_DEVICE
) ? "RX" : "TX",
2191 static int d40_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
2194 unsigned long flags
;
2195 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2197 if (d40c
->phy_chan
== NULL
) {
2198 chan_err(d40c
, "Channel is not allocated!\n");
2203 case DMA_TERMINATE_ALL
:
2204 spin_lock_irqsave(&d40c
->lock
, flags
);
2206 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2209 return d40_pause(chan
);
2211 return d40_resume(chan
);
2212 case DMA_SLAVE_CONFIG
:
2213 d40_set_runtime_config(chan
,
2214 (struct dma_slave_config
*) arg
);
2220 /* Other commands are unimplemented */
2224 /* Initialization functions */
2226 static void __init
d40_chan_init(struct d40_base
*base
, struct dma_device
*dma
,
2227 struct d40_chan
*chans
, int offset
,
2231 struct d40_chan
*d40c
;
2233 INIT_LIST_HEAD(&dma
->channels
);
2235 for (i
= offset
; i
< offset
+ num_chans
; i
++) {
2238 d40c
->chan
.device
= dma
;
2240 spin_lock_init(&d40c
->lock
);
2242 d40c
->log_num
= D40_PHY_CHAN
;
2244 INIT_LIST_HEAD(&d40c
->active
);
2245 INIT_LIST_HEAD(&d40c
->queue
);
2246 INIT_LIST_HEAD(&d40c
->client
);
2248 tasklet_init(&d40c
->tasklet
, dma_tasklet
,
2249 (unsigned long) d40c
);
2251 list_add_tail(&d40c
->chan
.device_node
,
2256 static int __init
d40_dmaengine_init(struct d40_base
*base
,
2257 int num_reserved_chans
)
2261 d40_chan_init(base
, &base
->dma_slave
, base
->log_chans
,
2262 0, base
->num_log_chans
);
2264 dma_cap_zero(base
->dma_slave
.cap_mask
);
2265 dma_cap_set(DMA_SLAVE
, base
->dma_slave
.cap_mask
);
2267 base
->dma_slave
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2268 base
->dma_slave
.device_free_chan_resources
= d40_free_chan_resources
;
2269 base
->dma_slave
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2270 base
->dma_slave
.device_prep_dma_sg
= d40_prep_sg
;
2271 base
->dma_slave
.device_prep_slave_sg
= d40_prep_slave_sg
;
2272 base
->dma_slave
.device_tx_status
= d40_tx_status
;
2273 base
->dma_slave
.device_issue_pending
= d40_issue_pending
;
2274 base
->dma_slave
.device_control
= d40_control
;
2275 base
->dma_slave
.dev
= base
->dev
;
2277 err
= dma_async_device_register(&base
->dma_slave
);
2280 d40_err(base
->dev
, "Failed to register slave channels\n");
2284 d40_chan_init(base
, &base
->dma_memcpy
, base
->log_chans
,
2285 base
->num_log_chans
, base
->plat_data
->memcpy_len
);
2287 dma_cap_zero(base
->dma_memcpy
.cap_mask
);
2288 dma_cap_set(DMA_MEMCPY
, base
->dma_memcpy
.cap_mask
);
2289 dma_cap_set(DMA_SG
, base
->dma_slave
.cap_mask
);
2291 base
->dma_memcpy
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2292 base
->dma_memcpy
.device_free_chan_resources
= d40_free_chan_resources
;
2293 base
->dma_memcpy
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2294 base
->dma_slave
.device_prep_dma_sg
= d40_prep_sg
;
2295 base
->dma_memcpy
.device_prep_slave_sg
= d40_prep_slave_sg
;
2296 base
->dma_memcpy
.device_tx_status
= d40_tx_status
;
2297 base
->dma_memcpy
.device_issue_pending
= d40_issue_pending
;
2298 base
->dma_memcpy
.device_control
= d40_control
;
2299 base
->dma_memcpy
.dev
= base
->dev
;
2301 * This controller can only access address at even
2302 * 32bit boundaries, i.e. 2^2
2304 base
->dma_memcpy
.copy_align
= 2;
2306 err
= dma_async_device_register(&base
->dma_memcpy
);
2310 "Failed to regsiter memcpy only channels\n");
2314 d40_chan_init(base
, &base
->dma_both
, base
->phy_chans
,
2315 0, num_reserved_chans
);
2317 dma_cap_zero(base
->dma_both
.cap_mask
);
2318 dma_cap_set(DMA_SLAVE
, base
->dma_both
.cap_mask
);
2319 dma_cap_set(DMA_MEMCPY
, base
->dma_both
.cap_mask
);
2320 dma_cap_set(DMA_SG
, base
->dma_slave
.cap_mask
);
2322 base
->dma_both
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2323 base
->dma_both
.device_free_chan_resources
= d40_free_chan_resources
;
2324 base
->dma_both
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2325 base
->dma_slave
.device_prep_dma_sg
= d40_prep_sg
;
2326 base
->dma_both
.device_prep_slave_sg
= d40_prep_slave_sg
;
2327 base
->dma_both
.device_tx_status
= d40_tx_status
;
2328 base
->dma_both
.device_issue_pending
= d40_issue_pending
;
2329 base
->dma_both
.device_control
= d40_control
;
2330 base
->dma_both
.dev
= base
->dev
;
2331 base
->dma_both
.copy_align
= 2;
2332 err
= dma_async_device_register(&base
->dma_both
);
2336 "Failed to register logical and physical capable channels\n");
2341 dma_async_device_unregister(&base
->dma_memcpy
);
2343 dma_async_device_unregister(&base
->dma_slave
);
2348 /* Initialization functions. */
2350 static int __init
d40_phy_res_init(struct d40_base
*base
)
2353 int num_phy_chans_avail
= 0;
2355 int odd_even_bit
= -2;
2357 val
[0] = readl(base
->virtbase
+ D40_DREG_PRSME
);
2358 val
[1] = readl(base
->virtbase
+ D40_DREG_PRSMO
);
2360 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2361 base
->phy_res
[i
].num
= i
;
2362 odd_even_bit
+= 2 * ((i
% 2) == 0);
2363 if (((val
[i
% 2] >> odd_even_bit
) & 3) == 1) {
2364 /* Mark security only channels as occupied */
2365 base
->phy_res
[i
].allocated_src
= D40_ALLOC_PHY
;
2366 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_PHY
;
2368 base
->phy_res
[i
].allocated_src
= D40_ALLOC_FREE
;
2369 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_FREE
;
2370 num_phy_chans_avail
++;
2372 spin_lock_init(&base
->phy_res
[i
].lock
);
2375 /* Mark disabled channels as occupied */
2376 for (i
= 0; base
->plat_data
->disabled_channels
[i
] != -1; i
++) {
2377 int chan
= base
->plat_data
->disabled_channels
[i
];
2379 base
->phy_res
[chan
].allocated_src
= D40_ALLOC_PHY
;
2380 base
->phy_res
[chan
].allocated_dst
= D40_ALLOC_PHY
;
2381 num_phy_chans_avail
--;
2384 dev_info(base
->dev
, "%d of %d physical DMA channels available\n",
2385 num_phy_chans_avail
, base
->num_phy_chans
);
2387 /* Verify settings extended vs standard */
2388 val
[0] = readl(base
->virtbase
+ D40_DREG_PRTYP
);
2390 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2392 if (base
->phy_res
[i
].allocated_src
== D40_ALLOC_FREE
&&
2393 (val
[0] & 0x3) != 1)
2395 "[%s] INFO: channel %d is misconfigured (%d)\n",
2396 __func__
, i
, val
[0] & 0x3);
2398 val
[0] = val
[0] >> 2;
2401 return num_phy_chans_avail
;
2404 static struct d40_base
* __init
d40_hw_detect_init(struct platform_device
*pdev
)
2406 static const struct d40_reg_val dma_id_regs
[] = {
2408 { .reg
= D40_DREG_PERIPHID0
, .val
= 0x0040},
2409 { .reg
= D40_DREG_PERIPHID1
, .val
= 0x0000},
2411 * D40_DREG_PERIPHID2 Depends on HW revision:
2412 * DB8500ed has 0x0008,
2414 * DB8500v1 has 0x0028
2415 * DB8500v2 has 0x0038
2417 { .reg
= D40_DREG_PERIPHID3
, .val
= 0x0000},
2420 { .reg
= D40_DREG_CELLID0
, .val
= 0x000d},
2421 { .reg
= D40_DREG_CELLID1
, .val
= 0x00f0},
2422 { .reg
= D40_DREG_CELLID2
, .val
= 0x0005},
2423 { .reg
= D40_DREG_CELLID3
, .val
= 0x00b1}
2425 struct stedma40_platform_data
*plat_data
;
2426 struct clk
*clk
= NULL
;
2427 void __iomem
*virtbase
= NULL
;
2428 struct resource
*res
= NULL
;
2429 struct d40_base
*base
= NULL
;
2430 int num_log_chans
= 0;
2436 clk
= clk_get(&pdev
->dev
, NULL
);
2439 d40_err(&pdev
->dev
, "No matching clock found\n");
2445 /* Get IO for DMAC base address */
2446 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "base");
2450 if (request_mem_region(res
->start
, resource_size(res
),
2451 D40_NAME
" I/O base") == NULL
)
2454 virtbase
= ioremap(res
->start
, resource_size(res
));
2458 /* HW version check */
2459 for (i
= 0; i
< ARRAY_SIZE(dma_id_regs
); i
++) {
2460 if (dma_id_regs
[i
].val
!=
2461 readl(virtbase
+ dma_id_regs
[i
].reg
)) {
2463 "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2466 readl(virtbase
+ dma_id_regs
[i
].reg
));
2471 /* Get silicon revision and designer */
2472 val
= readl(virtbase
+ D40_DREG_PERIPHID2
);
2474 if ((val
& D40_DREG_PERIPHID2_DESIGNER_MASK
) !=
2476 d40_err(&pdev
->dev
, "Unknown designer! Got %x wanted %x\n",
2477 val
& D40_DREG_PERIPHID2_DESIGNER_MASK
,
2482 rev
= (val
& D40_DREG_PERIPHID2_REV_MASK
) >>
2483 D40_DREG_PERIPHID2_REV_POS
;
2485 /* The number of physical channels on this HW */
2486 num_phy_chans
= 4 * (readl(virtbase
+ D40_DREG_ICFG
) & 0x7) + 4;
2488 dev_info(&pdev
->dev
, "hardware revision: %d @ 0x%x\n",
2491 plat_data
= pdev
->dev
.platform_data
;
2493 /* Count the number of logical channels in use */
2494 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2495 if (plat_data
->dev_rx
[i
] != 0)
2498 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2499 if (plat_data
->dev_tx
[i
] != 0)
2502 base
= kzalloc(ALIGN(sizeof(struct d40_base
), 4) +
2503 (num_phy_chans
+ num_log_chans
+ plat_data
->memcpy_len
) *
2504 sizeof(struct d40_chan
), GFP_KERNEL
);
2507 d40_err(&pdev
->dev
, "Out of memory\n");
2513 base
->num_phy_chans
= num_phy_chans
;
2514 base
->num_log_chans
= num_log_chans
;
2515 base
->phy_start
= res
->start
;
2516 base
->phy_size
= resource_size(res
);
2517 base
->virtbase
= virtbase
;
2518 base
->plat_data
= plat_data
;
2519 base
->dev
= &pdev
->dev
;
2520 base
->phy_chans
= ((void *)base
) + ALIGN(sizeof(struct d40_base
), 4);
2521 base
->log_chans
= &base
->phy_chans
[num_phy_chans
];
2523 base
->phy_res
= kzalloc(num_phy_chans
* sizeof(struct d40_phy_res
),
2528 base
->lookup_phy_chans
= kzalloc(num_phy_chans
*
2529 sizeof(struct d40_chan
*),
2531 if (!base
->lookup_phy_chans
)
2534 if (num_log_chans
+ plat_data
->memcpy_len
) {
2536 * The max number of logical channels are event lines for all
2537 * src devices and dst devices
2539 base
->lookup_log_chans
= kzalloc(plat_data
->dev_len
* 2 *
2540 sizeof(struct d40_chan
*),
2542 if (!base
->lookup_log_chans
)
2546 base
->lcla_pool
.alloc_map
= kzalloc(num_phy_chans
*
2547 sizeof(struct d40_desc
*) *
2548 D40_LCLA_LINK_PER_EVENT_GRP
,
2550 if (!base
->lcla_pool
.alloc_map
)
2553 base
->desc_slab
= kmem_cache_create(D40_NAME
, sizeof(struct d40_desc
),
2554 0, SLAB_HWCACHE_ALIGN
,
2556 if (base
->desc_slab
== NULL
)
2569 release_mem_region(res
->start
,
2570 resource_size(res
));
2575 kfree(base
->lcla_pool
.alloc_map
);
2576 kfree(base
->lookup_log_chans
);
2577 kfree(base
->lookup_phy_chans
);
2578 kfree(base
->phy_res
);
2585 static void __init
d40_hw_init(struct d40_base
*base
)
2588 static const struct d40_reg_val dma_init_reg
[] = {
2589 /* Clock every part of the DMA block from start */
2590 { .reg
= D40_DREG_GCC
, .val
= 0x0000ff01},
2592 /* Interrupts on all logical channels */
2593 { .reg
= D40_DREG_LCMIS0
, .val
= 0xFFFFFFFF},
2594 { .reg
= D40_DREG_LCMIS1
, .val
= 0xFFFFFFFF},
2595 { .reg
= D40_DREG_LCMIS2
, .val
= 0xFFFFFFFF},
2596 { .reg
= D40_DREG_LCMIS3
, .val
= 0xFFFFFFFF},
2597 { .reg
= D40_DREG_LCICR0
, .val
= 0xFFFFFFFF},
2598 { .reg
= D40_DREG_LCICR1
, .val
= 0xFFFFFFFF},
2599 { .reg
= D40_DREG_LCICR2
, .val
= 0xFFFFFFFF},
2600 { .reg
= D40_DREG_LCICR3
, .val
= 0xFFFFFFFF},
2601 { .reg
= D40_DREG_LCTIS0
, .val
= 0xFFFFFFFF},
2602 { .reg
= D40_DREG_LCTIS1
, .val
= 0xFFFFFFFF},
2603 { .reg
= D40_DREG_LCTIS2
, .val
= 0xFFFFFFFF},
2604 { .reg
= D40_DREG_LCTIS3
, .val
= 0xFFFFFFFF}
2607 u32 prmseo
[2] = {0, 0};
2608 u32 activeo
[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2612 for (i
= 0; i
< ARRAY_SIZE(dma_init_reg
); i
++)
2613 writel(dma_init_reg
[i
].val
,
2614 base
->virtbase
+ dma_init_reg
[i
].reg
);
2616 /* Configure all our dma channels to default settings */
2617 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2619 activeo
[i
% 2] = activeo
[i
% 2] << 2;
2621 if (base
->phy_res
[base
->num_phy_chans
- i
- 1].allocated_src
2623 activeo
[i
% 2] |= 3;
2627 /* Enable interrupt # */
2628 pcmis
= (pcmis
<< 1) | 1;
2630 /* Clear interrupt # */
2631 pcicr
= (pcicr
<< 1) | 1;
2633 /* Set channel to physical mode */
2634 prmseo
[i
% 2] = prmseo
[i
% 2] << 2;
2639 writel(prmseo
[1], base
->virtbase
+ D40_DREG_PRMSE
);
2640 writel(prmseo
[0], base
->virtbase
+ D40_DREG_PRMSO
);
2641 writel(activeo
[1], base
->virtbase
+ D40_DREG_ACTIVE
);
2642 writel(activeo
[0], base
->virtbase
+ D40_DREG_ACTIVO
);
2644 /* Write which interrupt to enable */
2645 writel(pcmis
, base
->virtbase
+ D40_DREG_PCMIS
);
2647 /* Write which interrupt to clear */
2648 writel(pcicr
, base
->virtbase
+ D40_DREG_PCICR
);
2652 static int __init
d40_lcla_allocate(struct d40_base
*base
)
2654 struct d40_lcla_pool
*pool
= &base
->lcla_pool
;
2655 unsigned long *page_list
;
2660 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2661 * To full fill this hardware requirement without wasting 256 kb
2662 * we allocate pages until we get an aligned one.
2664 page_list
= kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS
,
2672 /* Calculating how many pages that are required */
2673 base
->lcla_pool
.pages
= SZ_1K
* base
->num_phy_chans
/ PAGE_SIZE
;
2675 for (i
= 0; i
< MAX_LCLA_ALLOC_ATTEMPTS
; i
++) {
2676 page_list
[i
] = __get_free_pages(GFP_KERNEL
,
2677 base
->lcla_pool
.pages
);
2678 if (!page_list
[i
]) {
2680 d40_err(base
->dev
, "Failed to allocate %d pages.\n",
2681 base
->lcla_pool
.pages
);
2683 for (j
= 0; j
< i
; j
++)
2684 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2688 if ((virt_to_phys((void *)page_list
[i
]) &
2689 (LCLA_ALIGNMENT
- 1)) == 0)
2693 for (j
= 0; j
< i
; j
++)
2694 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2696 if (i
< MAX_LCLA_ALLOC_ATTEMPTS
) {
2697 base
->lcla_pool
.base
= (void *)page_list
[i
];
2700 * After many attempts and no succees with finding the correct
2701 * alignment, try with allocating a big buffer.
2704 "[%s] Failed to get %d pages @ 18 bit align.\n",
2705 __func__
, base
->lcla_pool
.pages
);
2706 base
->lcla_pool
.base_unaligned
= kmalloc(SZ_1K
*
2707 base
->num_phy_chans
+
2710 if (!base
->lcla_pool
.base_unaligned
) {
2715 base
->lcla_pool
.base
= PTR_ALIGN(base
->lcla_pool
.base_unaligned
,
2719 pool
->dma_addr
= dma_map_single(base
->dev
, pool
->base
,
2720 SZ_1K
* base
->num_phy_chans
,
2722 if (dma_mapping_error(base
->dev
, pool
->dma_addr
)) {
2728 writel(virt_to_phys(base
->lcla_pool
.base
),
2729 base
->virtbase
+ D40_DREG_LCLA
);
2735 static int __init
d40_probe(struct platform_device
*pdev
)
2739 struct d40_base
*base
;
2740 struct resource
*res
= NULL
;
2741 int num_reserved_chans
;
2744 base
= d40_hw_detect_init(pdev
);
2749 num_reserved_chans
= d40_phy_res_init(base
);
2751 platform_set_drvdata(pdev
, base
);
2753 spin_lock_init(&base
->interrupt_lock
);
2754 spin_lock_init(&base
->execmd_lock
);
2756 /* Get IO for logical channel parameter address */
2757 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "lcpa");
2760 d40_err(&pdev
->dev
, "No \"lcpa\" memory resource\n");
2763 base
->lcpa_size
= resource_size(res
);
2764 base
->phy_lcpa
= res
->start
;
2766 if (request_mem_region(res
->start
, resource_size(res
),
2767 D40_NAME
" I/O lcpa") == NULL
) {
2770 "Failed to request LCPA region 0x%x-0x%x\n",
2771 res
->start
, res
->end
);
2775 /* We make use of ESRAM memory for this. */
2776 val
= readl(base
->virtbase
+ D40_DREG_LCPA
);
2777 if (res
->start
!= val
&& val
!= 0) {
2778 dev_warn(&pdev
->dev
,
2779 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2780 __func__
, val
, res
->start
);
2782 writel(res
->start
, base
->virtbase
+ D40_DREG_LCPA
);
2784 base
->lcpa_base
= ioremap(res
->start
, resource_size(res
));
2785 if (!base
->lcpa_base
) {
2787 d40_err(&pdev
->dev
, "Failed to ioremap LCPA region\n");
2791 ret
= d40_lcla_allocate(base
);
2793 d40_err(&pdev
->dev
, "Failed to allocate LCLA area\n");
2797 spin_lock_init(&base
->lcla_pool
.lock
);
2799 base
->irq
= platform_get_irq(pdev
, 0);
2801 ret
= request_irq(base
->irq
, d40_handle_interrupt
, 0, D40_NAME
, base
);
2803 d40_err(&pdev
->dev
, "No IRQ defined\n");
2807 err
= d40_dmaengine_init(base
, num_reserved_chans
);
2813 dev_info(base
->dev
, "initialized\n");
2818 if (base
->desc_slab
)
2819 kmem_cache_destroy(base
->desc_slab
);
2821 iounmap(base
->virtbase
);
2823 if (base
->lcla_pool
.dma_addr
)
2824 dma_unmap_single(base
->dev
, base
->lcla_pool
.dma_addr
,
2825 SZ_1K
* base
->num_phy_chans
,
2828 if (!base
->lcla_pool
.base_unaligned
&& base
->lcla_pool
.base
)
2829 free_pages((unsigned long)base
->lcla_pool
.base
,
2830 base
->lcla_pool
.pages
);
2832 kfree(base
->lcla_pool
.base_unaligned
);
2835 release_mem_region(base
->phy_lcpa
,
2837 if (base
->phy_start
)
2838 release_mem_region(base
->phy_start
,
2841 clk_disable(base
->clk
);
2845 kfree(base
->lcla_pool
.alloc_map
);
2846 kfree(base
->lookup_log_chans
);
2847 kfree(base
->lookup_phy_chans
);
2848 kfree(base
->phy_res
);
2852 d40_err(&pdev
->dev
, "probe failed\n");
2856 static struct platform_driver d40_driver
= {
2858 .owner
= THIS_MODULE
,
2863 static int __init
stedma40_init(void)
2865 return platform_driver_probe(&d40_driver
, d40_probe
);
2867 arch_initcall(stedma40_init
);