2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
9 #include <linux/dma-mapping.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/export.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/err.h>
20 #include <linux/amba/bus.h>
22 #include <plat/ste_dma40.h>
24 #include "dmaengine.h"
25 #include "ste_dma40_ll.h"
27 #define D40_NAME "dma40"
29 #define D40_PHY_CHAN -1
31 /* For masking out/in 2 bit channel positions */
32 #define D40_CHAN_POS(chan) (2 * (chan / 2))
33 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
35 /* Maximum iterations taken before giving up suspending a channel */
36 #define D40_SUSPEND_MAX_IT 500
39 #define DMA40_AUTOSUSPEND_DELAY 100
41 /* Hardware requirement on LCLA alignment */
42 #define LCLA_ALIGNMENT 0x40000
44 /* Max number of links per event group */
45 #define D40_LCLA_LINK_PER_EVENT_GRP 128
46 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
48 /* Attempts before giving up to trying to get pages that are aligned */
49 #define MAX_LCLA_ALLOC_ATTEMPTS 256
51 /* Bit markings for allocation map */
52 #define D40_ALLOC_FREE (1 << 31)
53 #define D40_ALLOC_PHY (1 << 30)
54 #define D40_ALLOC_LOG_FREE 0
57 * enum 40_command - The different commands and/or statuses.
59 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
60 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
61 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
62 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
67 D40_DMA_SUSPEND_REQ
= 2,
72 * These are the registers that has to be saved and later restored
73 * when the DMA hw is powered off.
74 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
76 static u32 d40_backup_regs
[] = {
85 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
87 /* TODO: Check if all these registers have to be saved/restored on dma40 v3 */
88 static u32 d40_backup_regs_v3
[] = {
107 #define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3)
109 static u32 d40_backup_regs_chan
[] = {
121 * struct d40_lli_pool - Structure for keeping LLIs in memory
123 * @base: Pointer to memory area when the pre_alloc_lli's are not large
124 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
125 * pre_alloc_lli is used.
126 * @dma_addr: DMA address, if mapped
127 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
128 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
129 * one buffer to one buffer.
131 struct d40_lli_pool
{
135 /* Space for dst and src, plus an extra for padding */
136 u8 pre_alloc_lli
[3 * sizeof(struct d40_phy_lli
)];
140 * struct d40_desc - A descriptor is one DMA job.
142 * @lli_phy: LLI settings for physical channel. Both src and dst=
143 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
144 * lli_len equals one.
145 * @lli_log: Same as above but for logical channels.
146 * @lli_pool: The pool with two entries pre-allocated.
147 * @lli_len: Number of llis of current descriptor.
148 * @lli_current: Number of transferred llis.
149 * @lcla_alloc: Number of LCLA entries allocated.
150 * @txd: DMA engine struct. Used for among other things for communication
153 * @is_in_client_list: true if the client owns this descriptor.
154 * @cyclic: true if this is a cyclic job
156 * This descriptor is used for both logical and physical transfers.
160 struct d40_phy_lli_bidir lli_phy
;
162 struct d40_log_lli_bidir lli_log
;
164 struct d40_lli_pool lli_pool
;
169 struct dma_async_tx_descriptor txd
;
170 struct list_head node
;
172 bool is_in_client_list
;
177 * struct d40_lcla_pool - LCLA pool settings and data.
179 * @base: The virtual address of LCLA. 18 bit aligned.
180 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
181 * This pointer is only there for clean-up on error.
182 * @pages: The number of pages needed for all physical channels.
183 * Only used later for clean-up on error
184 * @lock: Lock to protect the content in this struct.
185 * @alloc_map: big map over which LCLA entry is own by which job.
187 struct d40_lcla_pool
{
190 void *base_unaligned
;
193 struct d40_desc
**alloc_map
;
197 * struct d40_phy_res - struct for handling eventlines mapped to physical
200 * @lock: A lock protection this entity.
201 * @reserved: True if used by secure world or otherwise.
202 * @num: The physical channel number of this entity.
203 * @allocated_src: Bit mapped to show which src event line's are mapped to
204 * this physical channel. Can also be free or physically allocated.
205 * @allocated_dst: Same as for src but is dst.
206 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
220 * struct d40_chan - Struct that describes a channel.
222 * @lock: A spinlock to protect this struct.
223 * @log_num: The logical number, if any of this channel.
224 * @pending_tx: The number of pending transfers. Used between interrupt handler
226 * @busy: Set to true when transfer is ongoing on this channel.
227 * @phy_chan: Pointer to physical channel which this instance runs on. If this
228 * point is NULL, then the channel is not allocated.
229 * @chan: DMA engine handle.
230 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
231 * transfer and call client callback.
232 * @client: Cliented owned descriptor list.
233 * @pending_queue: Submitted jobs, to be issued by issue_pending()
234 * @active: Active descriptor.
235 * @queue: Queued jobs.
236 * @prepare_queue: Prepared jobs.
237 * @dma_cfg: The client configuration of this dma channel.
238 * @configured: whether the dma_cfg configuration is valid
239 * @base: Pointer to the device instance struct.
240 * @src_def_cfg: Default cfg register setting for src.
241 * @dst_def_cfg: Default cfg register setting for dst.
242 * @log_def: Default logical channel settings.
243 * @lcpa: Pointer to dst and src lcpa settings.
244 * @runtime_addr: runtime configured address.
245 * @runtime_direction: runtime configured direction.
247 * This struct can either "be" a logical or a physical channel.
254 struct d40_phy_res
*phy_chan
;
255 struct dma_chan chan
;
256 struct tasklet_struct tasklet
;
257 struct list_head client
;
258 struct list_head pending_queue
;
259 struct list_head active
;
260 struct list_head queue
;
261 struct list_head prepare_queue
;
262 struct stedma40_chan_cfg dma_cfg
;
264 struct d40_base
*base
;
265 /* Default register configurations */
268 struct d40_def_lcsp log_def
;
269 struct d40_log_lli_full
*lcpa
;
270 /* Runtime reconfiguration */
271 dma_addr_t runtime_addr
;
272 enum dma_transfer_direction runtime_direction
;
276 * struct d40_base - The big global struct, one for each probe'd instance.
278 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
279 * @execmd_lock: Lock for execute command usage since several channels share
280 * the same physical register.
281 * @dev: The device structure.
282 * @virtbase: The virtual base address of the DMA's register.
283 * @rev: silicon revision detected.
284 * @clk: Pointer to the DMA clock structure.
285 * @phy_start: Physical memory start of the DMA registers.
286 * @phy_size: Size of the DMA register map.
287 * @irq: The IRQ number.
288 * @num_phy_chans: The number of physical channels. Read from HW. This
289 * is the number of available channels for this driver, not counting "Secure
290 * mode" allocated physical channels.
291 * @num_log_chans: The number of logical channels. Calculated from
293 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
294 * @dma_slave: dma_device channels that can do only do slave transfers.
295 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
296 * @phy_chans: Room for all possible physical channels in system.
297 * @log_chans: Room for all possible logical channels in system.
298 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
299 * to log_chans entries.
300 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
301 * to phy_chans entries.
302 * @plat_data: Pointer to provided platform_data which is the driver
304 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
305 * @phy_res: Vector containing all physical channels.
306 * @lcla_pool: lcla pool settings and data.
307 * @lcpa_base: The virtual mapped address of LCPA.
308 * @phy_lcpa: The physical address of the LCPA.
309 * @lcpa_size: The size of the LCPA area.
310 * @desc_slab: cache for descriptors.
311 * @reg_val_backup: Here the values of some hardware registers are stored
312 * before the DMA is powered off. They are restored when the power is back on.
313 * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and
315 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
316 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
317 * @initialized: true if the dma has been initialized
320 spinlock_t interrupt_lock
;
321 spinlock_t execmd_lock
;
323 void __iomem
*virtbase
;
326 phys_addr_t phy_start
;
327 resource_size_t phy_size
;
331 struct dma_device dma_both
;
332 struct dma_device dma_slave
;
333 struct dma_device dma_memcpy
;
334 struct d40_chan
*phy_chans
;
335 struct d40_chan
*log_chans
;
336 struct d40_chan
**lookup_log_chans
;
337 struct d40_chan
**lookup_phy_chans
;
338 struct stedma40_platform_data
*plat_data
;
339 struct regulator
*lcpa_regulator
;
340 /* Physical half channels */
341 struct d40_phy_res
*phy_res
;
342 struct d40_lcla_pool lcla_pool
;
345 resource_size_t lcpa_size
;
346 struct kmem_cache
*desc_slab
;
347 u32 reg_val_backup
[BACKUP_REGS_SZ
];
348 u32 reg_val_backup_v3
[BACKUP_REGS_SZ_V3
];
349 u32
*reg_val_backup_chan
;
350 u16 gcc_pwr_off_mask
;
355 * struct d40_interrupt_lookup - lookup table for interrupt handler
357 * @src: Interrupt mask register.
358 * @clr: Interrupt clear register.
359 * @is_error: true if this is an error interrupt.
360 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
361 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
363 struct d40_interrupt_lookup
{
371 * struct d40_reg_val - simple lookup struct
373 * @reg: The register.
374 * @val: The value that belongs to the register in reg.
381 static struct device
*chan2dev(struct d40_chan
*d40c
)
383 return &d40c
->chan
.dev
->device
;
386 static bool chan_is_physical(struct d40_chan
*chan
)
388 return chan
->log_num
== D40_PHY_CHAN
;
391 static bool chan_is_logical(struct d40_chan
*chan
)
393 return !chan_is_physical(chan
);
396 static void __iomem
*chan_base(struct d40_chan
*chan
)
398 return chan
->base
->virtbase
+ D40_DREG_PCBASE
+
399 chan
->phy_chan
->num
* D40_DREG_PCDELTA
;
402 #define d40_err(dev, format, arg...) \
403 dev_err(dev, "[%s] " format, __func__, ## arg)
405 #define chan_err(d40c, format, arg...) \
406 d40_err(chan2dev(d40c), format, ## arg)
408 static int d40_pool_lli_alloc(struct d40_chan
*d40c
, struct d40_desc
*d40d
,
411 bool is_log
= chan_is_logical(d40c
);
416 align
= sizeof(struct d40_log_lli
);
418 align
= sizeof(struct d40_phy_lli
);
421 base
= d40d
->lli_pool
.pre_alloc_lli
;
422 d40d
->lli_pool
.size
= sizeof(d40d
->lli_pool
.pre_alloc_lli
);
423 d40d
->lli_pool
.base
= NULL
;
425 d40d
->lli_pool
.size
= lli_len
* 2 * align
;
427 base
= kmalloc(d40d
->lli_pool
.size
+ align
, GFP_NOWAIT
);
428 d40d
->lli_pool
.base
= base
;
430 if (d40d
->lli_pool
.base
== NULL
)
435 d40d
->lli_log
.src
= PTR_ALIGN(base
, align
);
436 d40d
->lli_log
.dst
= d40d
->lli_log
.src
+ lli_len
;
438 d40d
->lli_pool
.dma_addr
= 0;
440 d40d
->lli_phy
.src
= PTR_ALIGN(base
, align
);
441 d40d
->lli_phy
.dst
= d40d
->lli_phy
.src
+ lli_len
;
443 d40d
->lli_pool
.dma_addr
= dma_map_single(d40c
->base
->dev
,
448 if (dma_mapping_error(d40c
->base
->dev
,
449 d40d
->lli_pool
.dma_addr
)) {
450 kfree(d40d
->lli_pool
.base
);
451 d40d
->lli_pool
.base
= NULL
;
452 d40d
->lli_pool
.dma_addr
= 0;
460 static void d40_pool_lli_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
462 if (d40d
->lli_pool
.dma_addr
)
463 dma_unmap_single(d40c
->base
->dev
, d40d
->lli_pool
.dma_addr
,
464 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
466 kfree(d40d
->lli_pool
.base
);
467 d40d
->lli_pool
.base
= NULL
;
468 d40d
->lli_pool
.size
= 0;
469 d40d
->lli_log
.src
= NULL
;
470 d40d
->lli_log
.dst
= NULL
;
471 d40d
->lli_phy
.src
= NULL
;
472 d40d
->lli_phy
.dst
= NULL
;
475 static int d40_lcla_alloc_one(struct d40_chan
*d40c
,
476 struct d40_desc
*d40d
)
483 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
485 p
= d40c
->phy_chan
->num
* D40_LCLA_LINK_PER_EVENT_GRP
;
488 * Allocate both src and dst at the same time, therefore the half
489 * start on 1 since 0 can't be used since zero is used as end marker.
491 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
492 if (!d40c
->base
->lcla_pool
.alloc_map
[p
+ i
]) {
493 d40c
->base
->lcla_pool
.alloc_map
[p
+ i
] = d40d
;
500 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
505 static int d40_lcla_free_all(struct d40_chan
*d40c
,
506 struct d40_desc
*d40d
)
512 if (chan_is_physical(d40c
))
515 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
517 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
518 if (d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
519 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] == d40d
) {
520 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
521 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] = NULL
;
523 if (d40d
->lcla_alloc
== 0) {
530 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
536 static void d40_desc_remove(struct d40_desc
*d40d
)
538 list_del(&d40d
->node
);
541 static struct d40_desc
*d40_desc_get(struct d40_chan
*d40c
)
543 struct d40_desc
*desc
= NULL
;
545 if (!list_empty(&d40c
->client
)) {
549 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
) {
550 if (async_tx_test_ack(&d
->txd
)) {
553 memset(desc
, 0, sizeof(*desc
));
560 desc
= kmem_cache_zalloc(d40c
->base
->desc_slab
, GFP_NOWAIT
);
563 INIT_LIST_HEAD(&desc
->node
);
568 static void d40_desc_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
571 d40_pool_lli_free(d40c
, d40d
);
572 d40_lcla_free_all(d40c
, d40d
);
573 kmem_cache_free(d40c
->base
->desc_slab
, d40d
);
576 static void d40_desc_submit(struct d40_chan
*d40c
, struct d40_desc
*desc
)
578 list_add_tail(&desc
->node
, &d40c
->active
);
581 static void d40_phy_lli_load(struct d40_chan
*chan
, struct d40_desc
*desc
)
583 struct d40_phy_lli
*lli_dst
= desc
->lli_phy
.dst
;
584 struct d40_phy_lli
*lli_src
= desc
->lli_phy
.src
;
585 void __iomem
*base
= chan_base(chan
);
587 writel(lli_src
->reg_cfg
, base
+ D40_CHAN_REG_SSCFG
);
588 writel(lli_src
->reg_elt
, base
+ D40_CHAN_REG_SSELT
);
589 writel(lli_src
->reg_ptr
, base
+ D40_CHAN_REG_SSPTR
);
590 writel(lli_src
->reg_lnk
, base
+ D40_CHAN_REG_SSLNK
);
592 writel(lli_dst
->reg_cfg
, base
+ D40_CHAN_REG_SDCFG
);
593 writel(lli_dst
->reg_elt
, base
+ D40_CHAN_REG_SDELT
);
594 writel(lli_dst
->reg_ptr
, base
+ D40_CHAN_REG_SDPTR
);
595 writel(lli_dst
->reg_lnk
, base
+ D40_CHAN_REG_SDLNK
);
598 static void d40_log_lli_to_lcxa(struct d40_chan
*chan
, struct d40_desc
*desc
)
600 struct d40_lcla_pool
*pool
= &chan
->base
->lcla_pool
;
601 struct d40_log_lli_bidir
*lli
= &desc
->lli_log
;
602 int lli_current
= desc
->lli_current
;
603 int lli_len
= desc
->lli_len
;
604 bool cyclic
= desc
->cyclic
;
605 int curr_lcla
= -EINVAL
;
607 bool use_esram_lcla
= chan
->base
->plat_data
->use_esram_lcla
;
611 * We may have partially running cyclic transfers, in case we did't get
612 * enough LCLA entries.
614 linkback
= cyclic
&& lli_current
== 0;
617 * For linkback, we need one LCLA even with only one link, because we
618 * can't link back to the one in LCPA space
620 if (linkback
|| (lli_len
- lli_current
> 1)) {
621 curr_lcla
= d40_lcla_alloc_one(chan
, desc
);
622 first_lcla
= curr_lcla
;
626 * For linkback, we normally load the LCPA in the loop since we need to
627 * link it to the second LCLA and not the first. However, if we
628 * couldn't even get a first LCLA, then we have to run in LCPA and
631 if (!linkback
|| curr_lcla
== -EINVAL
) {
632 unsigned int flags
= 0;
634 if (curr_lcla
== -EINVAL
)
635 flags
|= LLI_TERM_INT
;
637 d40_log_lli_lcpa_write(chan
->lcpa
,
638 &lli
->dst
[lli_current
],
639 &lli
->src
[lli_current
],
648 for (; lli_current
< lli_len
; lli_current
++) {
649 unsigned int lcla_offset
= chan
->phy_chan
->num
* 1024 +
651 struct d40_log_lli
*lcla
= pool
->base
+ lcla_offset
;
652 unsigned int flags
= 0;
655 if (lli_current
+ 1 < lli_len
)
656 next_lcla
= d40_lcla_alloc_one(chan
, desc
);
658 next_lcla
= linkback
? first_lcla
: -EINVAL
;
660 if (cyclic
|| next_lcla
== -EINVAL
)
661 flags
|= LLI_TERM_INT
;
663 if (linkback
&& curr_lcla
== first_lcla
) {
664 /* First link goes in both LCPA and LCLA */
665 d40_log_lli_lcpa_write(chan
->lcpa
,
666 &lli
->dst
[lli_current
],
667 &lli
->src
[lli_current
],
672 * One unused LCLA in the cyclic case if the very first
675 d40_log_lli_lcla_write(lcla
,
676 &lli
->dst
[lli_current
],
677 &lli
->src
[lli_current
],
681 * Cache maintenance is not needed if lcla is
684 if (!use_esram_lcla
) {
685 dma_sync_single_range_for_device(chan
->base
->dev
,
686 pool
->dma_addr
, lcla_offset
,
687 2 * sizeof(struct d40_log_lli
),
690 curr_lcla
= next_lcla
;
692 if (curr_lcla
== -EINVAL
|| curr_lcla
== first_lcla
) {
699 desc
->lli_current
= lli_current
;
702 static void d40_desc_load(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
704 if (chan_is_physical(d40c
)) {
705 d40_phy_lli_load(d40c
, d40d
);
706 d40d
->lli_current
= d40d
->lli_len
;
708 d40_log_lli_to_lcxa(d40c
, d40d
);
711 static struct d40_desc
*d40_first_active_get(struct d40_chan
*d40c
)
715 if (list_empty(&d40c
->active
))
718 d
= list_first_entry(&d40c
->active
,
724 /* remove desc from current queue and add it to the pending_queue */
725 static void d40_desc_queue(struct d40_chan
*d40c
, struct d40_desc
*desc
)
727 d40_desc_remove(desc
);
728 desc
->is_in_client_list
= false;
729 list_add_tail(&desc
->node
, &d40c
->pending_queue
);
732 static struct d40_desc
*d40_first_pending(struct d40_chan
*d40c
)
736 if (list_empty(&d40c
->pending_queue
))
739 d
= list_first_entry(&d40c
->pending_queue
,
745 static struct d40_desc
*d40_first_queued(struct d40_chan
*d40c
)
749 if (list_empty(&d40c
->queue
))
752 d
= list_first_entry(&d40c
->queue
,
758 static int d40_psize_2_burst_size(bool is_log
, int psize
)
761 if (psize
== STEDMA40_PSIZE_LOG_1
)
764 if (psize
== STEDMA40_PSIZE_PHY_1
)
772 * The dma only supports transmitting packages up to
773 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
774 * dma elements required to send the entire sg list
776 static int d40_size_2_dmalen(int size
, u32 data_width1
, u32 data_width2
)
779 u32 max_w
= max(data_width1
, data_width2
);
780 u32 min_w
= min(data_width1
, data_width2
);
781 u32 seg_max
= ALIGN(STEDMA40_MAX_SEG_SIZE
<< min_w
, 1 << max_w
);
783 if (seg_max
> STEDMA40_MAX_SEG_SIZE
)
784 seg_max
-= (1 << max_w
);
786 if (!IS_ALIGNED(size
, 1 << max_w
))
792 dmalen
= size
/ seg_max
;
793 if (dmalen
* seg_max
< size
)
799 static int d40_sg_2_dmalen(struct scatterlist
*sgl
, int sg_len
,
800 u32 data_width1
, u32 data_width2
)
802 struct scatterlist
*sg
;
807 for_each_sg(sgl
, sg
, sg_len
, i
) {
808 ret
= d40_size_2_dmalen(sg_dma_len(sg
),
809 data_width1
, data_width2
);
819 static void dma40_backup(void __iomem
*baseaddr
, u32
*backup
,
820 u32
*regaddr
, int num
, bool save
)
824 for (i
= 0; i
< num
; i
++) {
825 void __iomem
*addr
= baseaddr
+ regaddr
[i
];
828 backup
[i
] = readl_relaxed(addr
);
830 writel_relaxed(backup
[i
], addr
);
834 static void d40_save_restore_registers(struct d40_base
*base
, bool save
)
838 /* Save/Restore channel specific registers */
839 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
843 if (base
->phy_res
[i
].reserved
)
846 addr
= base
->virtbase
+ D40_DREG_PCBASE
+ i
* D40_DREG_PCDELTA
;
847 idx
= i
* ARRAY_SIZE(d40_backup_regs_chan
);
849 dma40_backup(addr
, &base
->reg_val_backup_chan
[idx
],
850 d40_backup_regs_chan
,
851 ARRAY_SIZE(d40_backup_regs_chan
),
855 /* Save/Restore global registers */
856 dma40_backup(base
->virtbase
, base
->reg_val_backup
,
857 d40_backup_regs
, ARRAY_SIZE(d40_backup_regs
),
860 /* Save/Restore registers only existing on dma40 v3 and later */
862 dma40_backup(base
->virtbase
, base
->reg_val_backup_v3
,
864 ARRAY_SIZE(d40_backup_regs_v3
),
868 static void d40_save_restore_registers(struct d40_base
*base
, bool save
)
873 static int d40_channel_execute_command(struct d40_chan
*d40c
,
874 enum d40_command command
)
878 void __iomem
*active_reg
;
883 spin_lock_irqsave(&d40c
->base
->execmd_lock
, flags
);
885 if (d40c
->phy_chan
->num
% 2 == 0)
886 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
888 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
890 if (command
== D40_DMA_SUSPEND_REQ
) {
891 status
= (readl(active_reg
) &
892 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
893 D40_CHAN_POS(d40c
->phy_chan
->num
);
895 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
899 wmask
= 0xffffffff & ~(D40_CHAN_POS_MASK(d40c
->phy_chan
->num
));
900 writel(wmask
| (command
<< D40_CHAN_POS(d40c
->phy_chan
->num
)),
903 if (command
== D40_DMA_SUSPEND_REQ
) {
905 for (i
= 0 ; i
< D40_SUSPEND_MAX_IT
; i
++) {
906 status
= (readl(active_reg
) &
907 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
908 D40_CHAN_POS(d40c
->phy_chan
->num
);
912 * Reduce the number of bus accesses while
913 * waiting for the DMA to suspend.
917 if (status
== D40_DMA_STOP
||
918 status
== D40_DMA_SUSPENDED
)
922 if (i
== D40_SUSPEND_MAX_IT
) {
924 "unable to suspend the chl %d (log: %d) status %x\n",
925 d40c
->phy_chan
->num
, d40c
->log_num
,
933 spin_unlock_irqrestore(&d40c
->base
->execmd_lock
, flags
);
937 static void d40_term_all(struct d40_chan
*d40c
)
939 struct d40_desc
*d40d
;
942 /* Release active descriptors */
943 while ((d40d
= d40_first_active_get(d40c
))) {
944 d40_desc_remove(d40d
);
945 d40_desc_free(d40c
, d40d
);
948 /* Release queued descriptors waiting for transfer */
949 while ((d40d
= d40_first_queued(d40c
))) {
950 d40_desc_remove(d40d
);
951 d40_desc_free(d40c
, d40d
);
954 /* Release pending descriptors */
955 while ((d40d
= d40_first_pending(d40c
))) {
956 d40_desc_remove(d40d
);
957 d40_desc_free(d40c
, d40d
);
960 /* Release client owned descriptors */
961 if (!list_empty(&d40c
->client
))
962 list_for_each_entry_safe(d40d
, _d
, &d40c
->client
, node
) {
963 d40_desc_remove(d40d
);
964 d40_desc_free(d40c
, d40d
);
967 /* Release descriptors in prepare queue */
968 if (!list_empty(&d40c
->prepare_queue
))
969 list_for_each_entry_safe(d40d
, _d
,
970 &d40c
->prepare_queue
, node
) {
971 d40_desc_remove(d40d
);
972 d40_desc_free(d40c
, d40d
);
975 d40c
->pending_tx
= 0;
979 static void __d40_config_set_event(struct d40_chan
*d40c
, bool enable
,
982 void __iomem
*addr
= chan_base(d40c
) + reg
;
986 writel((D40_DEACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
))
987 | ~D40_EVENTLINE_MASK(event
), addr
);
992 * The hardware sometimes doesn't register the enable when src and dst
993 * event lines are active on the same logical channel. Retry to ensure
994 * it does. Usually only one retry is sufficient.
998 writel((D40_ACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
))
999 | ~D40_EVENTLINE_MASK(event
), addr
);
1001 if (readl(addr
) & D40_EVENTLINE_MASK(event
))
1006 dev_dbg(chan2dev(d40c
),
1007 "[%s] workaround enable S%cLNK (%d tries)\n",
1008 __func__
, reg
== D40_CHAN_REG_SSLNK
? 'S' : 'D',
1014 static void d40_config_set_event(struct d40_chan
*d40c
, bool do_enable
)
1016 unsigned long flags
;
1018 spin_lock_irqsave(&d40c
->phy_chan
->lock
, flags
);
1020 /* Enable event line connected to device (or memcpy) */
1021 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
1022 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
)) {
1023 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1025 __d40_config_set_event(d40c
, do_enable
, event
,
1026 D40_CHAN_REG_SSLNK
);
1029 if (d40c
->dma_cfg
.dir
!= STEDMA40_PERIPH_TO_MEM
) {
1030 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1032 __d40_config_set_event(d40c
, do_enable
, event
,
1033 D40_CHAN_REG_SDLNK
);
1036 spin_unlock_irqrestore(&d40c
->phy_chan
->lock
, flags
);
1039 static u32
d40_chan_has_events(struct d40_chan
*d40c
)
1041 void __iomem
*chanbase
= chan_base(d40c
);
1044 val
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
1045 val
|= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
1050 static u32
d40_get_prmo(struct d40_chan
*d40c
)
1052 static const unsigned int phy_map
[] = {
1053 [STEDMA40_PCHAN_BASIC_MODE
]
1054 = D40_DREG_PRMO_PCHAN_BASIC
,
1055 [STEDMA40_PCHAN_MODULO_MODE
]
1056 = D40_DREG_PRMO_PCHAN_MODULO
,
1057 [STEDMA40_PCHAN_DOUBLE_DST_MODE
]
1058 = D40_DREG_PRMO_PCHAN_DOUBLE_DST
,
1060 static const unsigned int log_map
[] = {
1061 [STEDMA40_LCHAN_SRC_PHY_DST_LOG
]
1062 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG
,
1063 [STEDMA40_LCHAN_SRC_LOG_DST_PHY
]
1064 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY
,
1065 [STEDMA40_LCHAN_SRC_LOG_DST_LOG
]
1066 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG
,
1069 if (chan_is_physical(d40c
))
1070 return phy_map
[d40c
->dma_cfg
.mode_opt
];
1072 return log_map
[d40c
->dma_cfg
.mode_opt
];
1075 static void d40_config_write(struct d40_chan
*d40c
)
1080 /* Odd addresses are even addresses + 4 */
1081 addr_base
= (d40c
->phy_chan
->num
% 2) * 4;
1082 /* Setup channel mode to logical or physical */
1083 var
= ((u32
)(chan_is_logical(d40c
)) + 1) <<
1084 D40_CHAN_POS(d40c
->phy_chan
->num
);
1085 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMSE
+ addr_base
);
1087 /* Setup operational mode option register */
1088 var
= d40_get_prmo(d40c
) << D40_CHAN_POS(d40c
->phy_chan
->num
);
1090 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMOE
+ addr_base
);
1092 if (chan_is_logical(d40c
)) {
1093 int lidx
= (d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
)
1094 & D40_SREG_ELEM_LOG_LIDX_MASK
;
1095 void __iomem
*chanbase
= chan_base(d40c
);
1097 /* Set default config for CFG reg */
1098 writel(d40c
->src_def_cfg
, chanbase
+ D40_CHAN_REG_SSCFG
);
1099 writel(d40c
->dst_def_cfg
, chanbase
+ D40_CHAN_REG_SDCFG
);
1101 /* Set LIDX for lcla */
1102 writel(lidx
, chanbase
+ D40_CHAN_REG_SSELT
);
1103 writel(lidx
, chanbase
+ D40_CHAN_REG_SDELT
);
1105 /* Clear LNK which will be used by d40_chan_has_events() */
1106 writel(0, chanbase
+ D40_CHAN_REG_SSLNK
);
1107 writel(0, chanbase
+ D40_CHAN_REG_SDLNK
);
1111 static u32
d40_residue(struct d40_chan
*d40c
)
1115 if (chan_is_logical(d40c
))
1116 num_elt
= (readl(&d40c
->lcpa
->lcsp2
) & D40_MEM_LCSP2_ECNT_MASK
)
1117 >> D40_MEM_LCSP2_ECNT_POS
;
1119 u32 val
= readl(chan_base(d40c
) + D40_CHAN_REG_SDELT
);
1120 num_elt
= (val
& D40_SREG_ELEM_PHY_ECNT_MASK
)
1121 >> D40_SREG_ELEM_PHY_ECNT_POS
;
1124 return num_elt
* (1 << d40c
->dma_cfg
.dst_info
.data_width
);
1127 static bool d40_tx_is_linked(struct d40_chan
*d40c
)
1131 if (chan_is_logical(d40c
))
1132 is_link
= readl(&d40c
->lcpa
->lcsp3
) & D40_MEM_LCSP3_DLOS_MASK
;
1134 is_link
= readl(chan_base(d40c
) + D40_CHAN_REG_SDLNK
)
1135 & D40_SREG_LNK_PHYS_LNK_MASK
;
1140 static int d40_pause(struct d40_chan
*d40c
)
1143 unsigned long flags
;
1148 pm_runtime_get_sync(d40c
->base
->dev
);
1149 spin_lock_irqsave(&d40c
->lock
, flags
);
1151 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1153 if (chan_is_logical(d40c
)) {
1154 d40_config_set_event(d40c
, false);
1155 /* Resume the other logical channels if any */
1156 if (d40_chan_has_events(d40c
))
1157 res
= d40_channel_execute_command(d40c
,
1161 pm_runtime_mark_last_busy(d40c
->base
->dev
);
1162 pm_runtime_put_autosuspend(d40c
->base
->dev
);
1163 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1167 static int d40_resume(struct d40_chan
*d40c
)
1170 unsigned long flags
;
1175 spin_lock_irqsave(&d40c
->lock
, flags
);
1176 pm_runtime_get_sync(d40c
->base
->dev
);
1177 if (d40c
->base
->rev
== 0)
1178 if (chan_is_logical(d40c
)) {
1179 res
= d40_channel_execute_command(d40c
,
1180 D40_DMA_SUSPEND_REQ
);
1184 /* If bytes left to transfer or linked tx resume job */
1185 if (d40_residue(d40c
) || d40_tx_is_linked(d40c
)) {
1187 if (chan_is_logical(d40c
))
1188 d40_config_set_event(d40c
, true);
1190 res
= d40_channel_execute_command(d40c
, D40_DMA_RUN
);
1194 pm_runtime_mark_last_busy(d40c
->base
->dev
);
1195 pm_runtime_put_autosuspend(d40c
->base
->dev
);
1196 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1200 static int d40_terminate_all(struct d40_chan
*chan
)
1202 unsigned long flags
;
1205 ret
= d40_pause(chan
);
1206 if (!ret
&& chan_is_physical(chan
))
1207 ret
= d40_channel_execute_command(chan
, D40_DMA_STOP
);
1209 spin_lock_irqsave(&chan
->lock
, flags
);
1211 spin_unlock_irqrestore(&chan
->lock
, flags
);
1216 static dma_cookie_t
d40_tx_submit(struct dma_async_tx_descriptor
*tx
)
1218 struct d40_chan
*d40c
= container_of(tx
->chan
,
1221 struct d40_desc
*d40d
= container_of(tx
, struct d40_desc
, txd
);
1222 unsigned long flags
;
1224 spin_lock_irqsave(&d40c
->lock
, flags
);
1226 d40c
->chan
.cookie
++;
1228 if (d40c
->chan
.cookie
< 0)
1229 d40c
->chan
.cookie
= 1;
1231 d40d
->txd
.cookie
= d40c
->chan
.cookie
;
1233 d40_desc_queue(d40c
, d40d
);
1235 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1240 static int d40_start(struct d40_chan
*d40c
)
1242 if (d40c
->base
->rev
== 0) {
1245 if (chan_is_logical(d40c
)) {
1246 err
= d40_channel_execute_command(d40c
,
1247 D40_DMA_SUSPEND_REQ
);
1253 if (chan_is_logical(d40c
))
1254 d40_config_set_event(d40c
, true);
1256 return d40_channel_execute_command(d40c
, D40_DMA_RUN
);
1259 static struct d40_desc
*d40_queue_start(struct d40_chan
*d40c
)
1261 struct d40_desc
*d40d
;
1264 /* Start queued jobs, if any */
1265 d40d
= d40_first_queued(d40c
);
1271 pm_runtime_get_sync(d40c
->base
->dev
);
1273 /* Remove from queue */
1274 d40_desc_remove(d40d
);
1276 /* Add to active queue */
1277 d40_desc_submit(d40c
, d40d
);
1279 /* Initiate DMA job */
1280 d40_desc_load(d40c
, d40d
);
1283 err
= d40_start(d40c
);
1292 /* called from interrupt context */
1293 static void dma_tc_handle(struct d40_chan
*d40c
)
1295 struct d40_desc
*d40d
;
1297 /* Get first active entry from list */
1298 d40d
= d40_first_active_get(d40c
);
1305 * If this was a paritially loaded list, we need to reloaded
1306 * it, and only when the list is completed. We need to check
1307 * for done because the interrupt will hit for every link, and
1308 * not just the last one.
1310 if (d40d
->lli_current
< d40d
->lli_len
1311 && !d40_tx_is_linked(d40c
)
1312 && !d40_residue(d40c
)) {
1313 d40_lcla_free_all(d40c
, d40d
);
1314 d40_desc_load(d40c
, d40d
);
1315 (void) d40_start(d40c
);
1317 if (d40d
->lli_current
== d40d
->lli_len
)
1318 d40d
->lli_current
= 0;
1321 d40_lcla_free_all(d40c
, d40d
);
1323 if (d40d
->lli_current
< d40d
->lli_len
) {
1324 d40_desc_load(d40c
, d40d
);
1326 (void) d40_start(d40c
);
1330 if (d40_queue_start(d40c
) == NULL
)
1332 pm_runtime_mark_last_busy(d40c
->base
->dev
);
1333 pm_runtime_put_autosuspend(d40c
->base
->dev
);
1337 tasklet_schedule(&d40c
->tasklet
);
1341 static void dma_tasklet(unsigned long data
)
1343 struct d40_chan
*d40c
= (struct d40_chan
*) data
;
1344 struct d40_desc
*d40d
;
1345 unsigned long flags
;
1346 dma_async_tx_callback callback
;
1347 void *callback_param
;
1349 spin_lock_irqsave(&d40c
->lock
, flags
);
1351 /* Get first active entry from list */
1352 d40d
= d40_first_active_get(d40c
);
1357 d40c
->chan
.completed_cookie
= d40d
->txd
.cookie
;
1360 * If terminating a channel pending_tx is set to zero.
1361 * This prevents any finished active jobs to return to the client.
1363 if (d40c
->pending_tx
== 0) {
1364 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1368 /* Callback to client */
1369 callback
= d40d
->txd
.callback
;
1370 callback_param
= d40d
->txd
.callback_param
;
1372 if (!d40d
->cyclic
) {
1373 if (async_tx_test_ack(&d40d
->txd
)) {
1374 d40_desc_remove(d40d
);
1375 d40_desc_free(d40c
, d40d
);
1377 if (!d40d
->is_in_client_list
) {
1378 d40_desc_remove(d40d
);
1379 d40_lcla_free_all(d40c
, d40d
);
1380 list_add_tail(&d40d
->node
, &d40c
->client
);
1381 d40d
->is_in_client_list
= true;
1388 if (d40c
->pending_tx
)
1389 tasklet_schedule(&d40c
->tasklet
);
1391 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1393 if (callback
&& (d40d
->txd
.flags
& DMA_PREP_INTERRUPT
))
1394 callback(callback_param
);
1399 /* Rescue manoeuvre if receiving double interrupts */
1400 if (d40c
->pending_tx
> 0)
1402 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1405 static irqreturn_t
d40_handle_interrupt(int irq
, void *data
)
1407 static const struct d40_interrupt_lookup il
[] = {
1408 {D40_DREG_LCTIS0
, D40_DREG_LCICR0
, false, 0},
1409 {D40_DREG_LCTIS1
, D40_DREG_LCICR1
, false, 32},
1410 {D40_DREG_LCTIS2
, D40_DREG_LCICR2
, false, 64},
1411 {D40_DREG_LCTIS3
, D40_DREG_LCICR3
, false, 96},
1412 {D40_DREG_LCEIS0
, D40_DREG_LCICR0
, true, 0},
1413 {D40_DREG_LCEIS1
, D40_DREG_LCICR1
, true, 32},
1414 {D40_DREG_LCEIS2
, D40_DREG_LCICR2
, true, 64},
1415 {D40_DREG_LCEIS3
, D40_DREG_LCICR3
, true, 96},
1416 {D40_DREG_PCTIS
, D40_DREG_PCICR
, false, D40_PHY_CHAN
},
1417 {D40_DREG_PCEIS
, D40_DREG_PCICR
, true, D40_PHY_CHAN
},
1421 u32 regs
[ARRAY_SIZE(il
)];
1425 struct d40_chan
*d40c
;
1426 unsigned long flags
;
1427 struct d40_base
*base
= data
;
1429 spin_lock_irqsave(&base
->interrupt_lock
, flags
);
1431 /* Read interrupt status of both logical and physical channels */
1432 for (i
= 0; i
< ARRAY_SIZE(il
); i
++)
1433 regs
[i
] = readl(base
->virtbase
+ il
[i
].src
);
1437 chan
= find_next_bit((unsigned long *)regs
,
1438 BITS_PER_LONG
* ARRAY_SIZE(il
), chan
+ 1);
1440 /* No more set bits found? */
1441 if (chan
== BITS_PER_LONG
* ARRAY_SIZE(il
))
1444 row
= chan
/ BITS_PER_LONG
;
1445 idx
= chan
& (BITS_PER_LONG
- 1);
1448 writel(1 << idx
, base
->virtbase
+ il
[row
].clr
);
1450 if (il
[row
].offset
== D40_PHY_CHAN
)
1451 d40c
= base
->lookup_phy_chans
[idx
];
1453 d40c
= base
->lookup_log_chans
[il
[row
].offset
+ idx
];
1454 spin_lock(&d40c
->lock
);
1456 if (!il
[row
].is_error
)
1457 dma_tc_handle(d40c
);
1459 d40_err(base
->dev
, "IRQ chan: %ld offset %d idx %d\n",
1460 chan
, il
[row
].offset
, idx
);
1462 spin_unlock(&d40c
->lock
);
1465 spin_unlock_irqrestore(&base
->interrupt_lock
, flags
);
1470 static int d40_validate_conf(struct d40_chan
*d40c
,
1471 struct stedma40_chan_cfg
*conf
)
1474 u32 dst_event_group
= D40_TYPE_TO_GROUP(conf
->dst_dev_type
);
1475 u32 src_event_group
= D40_TYPE_TO_GROUP(conf
->src_dev_type
);
1476 bool is_log
= conf
->mode
== STEDMA40_MODE_LOGICAL
;
1479 chan_err(d40c
, "Invalid direction.\n");
1483 if (conf
->dst_dev_type
!= STEDMA40_DEV_DST_MEMORY
&&
1484 d40c
->base
->plat_data
->dev_tx
[conf
->dst_dev_type
] == 0 &&
1485 d40c
->runtime_addr
== 0) {
1487 chan_err(d40c
, "Invalid TX channel address (%d)\n",
1488 conf
->dst_dev_type
);
1492 if (conf
->src_dev_type
!= STEDMA40_DEV_SRC_MEMORY
&&
1493 d40c
->base
->plat_data
->dev_rx
[conf
->src_dev_type
] == 0 &&
1494 d40c
->runtime_addr
== 0) {
1495 chan_err(d40c
, "Invalid RX channel address (%d)\n",
1496 conf
->src_dev_type
);
1500 if (conf
->dir
== STEDMA40_MEM_TO_PERIPH
&&
1501 dst_event_group
== STEDMA40_DEV_DST_MEMORY
) {
1502 chan_err(d40c
, "Invalid dst\n");
1506 if (conf
->dir
== STEDMA40_PERIPH_TO_MEM
&&
1507 src_event_group
== STEDMA40_DEV_SRC_MEMORY
) {
1508 chan_err(d40c
, "Invalid src\n");
1512 if (src_event_group
== STEDMA40_DEV_SRC_MEMORY
&&
1513 dst_event_group
== STEDMA40_DEV_DST_MEMORY
&& is_log
) {
1514 chan_err(d40c
, "No event line\n");
1518 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
&&
1519 (src_event_group
!= dst_event_group
)) {
1520 chan_err(d40c
, "Invalid event group\n");
1524 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
) {
1526 * DMAC HW supports it. Will be added to this driver,
1527 * in case any dma client requires it.
1529 chan_err(d40c
, "periph to periph not supported\n");
1533 if (d40_psize_2_burst_size(is_log
, conf
->src_info
.psize
) *
1534 (1 << conf
->src_info
.data_width
) !=
1535 d40_psize_2_burst_size(is_log
, conf
->dst_info
.psize
) *
1536 (1 << conf
->dst_info
.data_width
)) {
1538 * The DMAC hardware only supports
1539 * src (burst x width) == dst (burst x width)
1542 chan_err(d40c
, "src (burst x width) != dst (burst x width)\n");
1549 static bool d40_alloc_mask_set(struct d40_phy_res
*phy
,
1550 bool is_src
, int log_event_line
, bool is_log
,
1553 unsigned long flags
;
1554 spin_lock_irqsave(&phy
->lock
, flags
);
1556 *first_user
= ((phy
->allocated_src
| phy
->allocated_dst
)
1560 /* Physical interrupts are masked per physical full channel */
1561 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1562 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1563 phy
->allocated_dst
= D40_ALLOC_PHY
;
1564 phy
->allocated_src
= D40_ALLOC_PHY
;
1570 /* Logical channel */
1572 if (phy
->allocated_src
== D40_ALLOC_PHY
)
1575 if (phy
->allocated_src
== D40_ALLOC_FREE
)
1576 phy
->allocated_src
= D40_ALLOC_LOG_FREE
;
1578 if (!(phy
->allocated_src
& (1 << log_event_line
))) {
1579 phy
->allocated_src
|= 1 << log_event_line
;
1584 if (phy
->allocated_dst
== D40_ALLOC_PHY
)
1587 if (phy
->allocated_dst
== D40_ALLOC_FREE
)
1588 phy
->allocated_dst
= D40_ALLOC_LOG_FREE
;
1590 if (!(phy
->allocated_dst
& (1 << log_event_line
))) {
1591 phy
->allocated_dst
|= 1 << log_event_line
;
1598 spin_unlock_irqrestore(&phy
->lock
, flags
);
1601 spin_unlock_irqrestore(&phy
->lock
, flags
);
1605 static bool d40_alloc_mask_free(struct d40_phy_res
*phy
, bool is_src
,
1608 unsigned long flags
;
1609 bool is_free
= false;
1611 spin_lock_irqsave(&phy
->lock
, flags
);
1612 if (!log_event_line
) {
1613 phy
->allocated_dst
= D40_ALLOC_FREE
;
1614 phy
->allocated_src
= D40_ALLOC_FREE
;
1619 /* Logical channel */
1621 phy
->allocated_src
&= ~(1 << log_event_line
);
1622 if (phy
->allocated_src
== D40_ALLOC_LOG_FREE
)
1623 phy
->allocated_src
= D40_ALLOC_FREE
;
1625 phy
->allocated_dst
&= ~(1 << log_event_line
);
1626 if (phy
->allocated_dst
== D40_ALLOC_LOG_FREE
)
1627 phy
->allocated_dst
= D40_ALLOC_FREE
;
1630 is_free
= ((phy
->allocated_src
| phy
->allocated_dst
) ==
1634 spin_unlock_irqrestore(&phy
->lock
, flags
);
1639 static int d40_allocate_channel(struct d40_chan
*d40c
, bool *first_phy_user
)
1644 struct d40_phy_res
*phys
;
1649 bool is_log
= d40c
->dma_cfg
.mode
== STEDMA40_MODE_LOGICAL
;
1651 phys
= d40c
->base
->phy_res
;
1653 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1654 dev_type
= d40c
->dma_cfg
.src_dev_type
;
1655 log_num
= 2 * dev_type
;
1657 } else if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1658 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1659 /* dst event lines are used for logical memcpy */
1660 dev_type
= d40c
->dma_cfg
.dst_dev_type
;
1661 log_num
= 2 * dev_type
+ 1;
1666 event_group
= D40_TYPE_TO_GROUP(dev_type
);
1667 event_line
= D40_TYPE_TO_EVENT(dev_type
);
1670 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1671 /* Find physical half channel */
1672 for (i
= 0; i
< d40c
->base
->num_phy_chans
; i
++) {
1674 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1680 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1681 int phy_num
= j
+ event_group
* 2;
1682 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1683 if (d40_alloc_mask_set(&phys
[i
],
1693 d40c
->phy_chan
= &phys
[i
];
1694 d40c
->log_num
= D40_PHY_CHAN
;
1700 /* Find logical channel */
1701 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1702 int phy_num
= j
+ event_group
* 2;
1704 if (d40c
->dma_cfg
.use_fixed_channel
) {
1705 i
= d40c
->dma_cfg
.phy_channel
;
1707 if ((i
!= phy_num
) && (i
!= phy_num
+ 1)) {
1708 dev_err(chan2dev(d40c
),
1709 "invalid fixed phy channel %d\n", i
);
1713 if (d40_alloc_mask_set(&phys
[i
], is_src
, event_line
,
1714 is_log
, first_phy_user
))
1717 dev_err(chan2dev(d40c
),
1718 "could not allocate fixed phy channel %d\n", i
);
1723 * Spread logical channels across all available physical rather
1724 * than pack every logical channel at the first available phy
1728 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1729 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1735 for (i
= phy_num
+ 1; i
>= phy_num
; i
--) {
1736 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1746 d40c
->phy_chan
= &phys
[i
];
1747 d40c
->log_num
= log_num
;
1751 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = d40c
;
1753 d40c
->base
->lookup_phy_chans
[d40c
->phy_chan
->num
] = d40c
;
1759 static int d40_config_memcpy(struct d40_chan
*d40c
)
1761 dma_cap_mask_t cap
= d40c
->chan
.device
->cap_mask
;
1763 if (dma_has_cap(DMA_MEMCPY
, cap
) && !dma_has_cap(DMA_SLAVE
, cap
)) {
1764 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_log
;
1765 d40c
->dma_cfg
.src_dev_type
= STEDMA40_DEV_SRC_MEMORY
;
1766 d40c
->dma_cfg
.dst_dev_type
= d40c
->base
->plat_data
->
1767 memcpy
[d40c
->chan
.chan_id
];
1769 } else if (dma_has_cap(DMA_MEMCPY
, cap
) &&
1770 dma_has_cap(DMA_SLAVE
, cap
)) {
1771 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_phy
;
1773 chan_err(d40c
, "No memcpy\n");
1781 static int d40_free_dma(struct d40_chan
*d40c
)
1786 struct d40_phy_res
*phy
= d40c
->phy_chan
;
1789 /* Terminate all queued and active transfers */
1793 chan_err(d40c
, "phy == null\n");
1797 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1798 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1799 chan_err(d40c
, "channel already free\n");
1803 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1804 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1805 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1807 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1808 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1811 chan_err(d40c
, "Unknown direction\n");
1815 pm_runtime_get_sync(d40c
->base
->dev
);
1816 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1818 chan_err(d40c
, "suspend failed\n");
1822 if (chan_is_logical(d40c
)) {
1823 /* Release logical channel, deactivate the event line */
1825 d40_config_set_event(d40c
, false);
1826 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = NULL
;
1829 * Check if there are more logical allocation
1830 * on this phy channel.
1832 if (!d40_alloc_mask_free(phy
, is_src
, event
)) {
1833 /* Resume the other logical channels if any */
1834 if (d40_chan_has_events(d40c
)) {
1835 res
= d40_channel_execute_command(d40c
,
1839 "Executing RUN command\n");
1844 (void) d40_alloc_mask_free(phy
, is_src
, 0);
1847 /* Release physical channel */
1848 res
= d40_channel_execute_command(d40c
, D40_DMA_STOP
);
1850 chan_err(d40c
, "Failed to stop channel\n");
1855 pm_runtime_mark_last_busy(d40c
->base
->dev
);
1856 pm_runtime_put_autosuspend(d40c
->base
->dev
);
1860 d40c
->phy_chan
= NULL
;
1861 d40c
->configured
= false;
1862 d40c
->base
->lookup_phy_chans
[phy
->num
] = NULL
;
1865 pm_runtime_mark_last_busy(d40c
->base
->dev
);
1866 pm_runtime_put_autosuspend(d40c
->base
->dev
);
1870 static bool d40_is_paused(struct d40_chan
*d40c
)
1872 void __iomem
*chanbase
= chan_base(d40c
);
1873 bool is_paused
= false;
1874 unsigned long flags
;
1875 void __iomem
*active_reg
;
1879 spin_lock_irqsave(&d40c
->lock
, flags
);
1881 if (chan_is_physical(d40c
)) {
1882 if (d40c
->phy_chan
->num
% 2 == 0)
1883 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
1885 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
1887 status
= (readl(active_reg
) &
1888 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
1889 D40_CHAN_POS(d40c
->phy_chan
->num
);
1890 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
1896 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1897 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1898 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1899 status
= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
1900 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1901 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1902 status
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
1904 chan_err(d40c
, "Unknown direction\n");
1908 status
= (status
& D40_EVENTLINE_MASK(event
)) >>
1909 D40_EVENTLINE_POS(event
);
1911 if (status
!= D40_DMA_RUN
)
1914 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1920 static u32
stedma40_residue(struct dma_chan
*chan
)
1922 struct d40_chan
*d40c
=
1923 container_of(chan
, struct d40_chan
, chan
);
1925 unsigned long flags
;
1927 spin_lock_irqsave(&d40c
->lock
, flags
);
1928 bytes_left
= d40_residue(d40c
);
1929 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1935 d40_prep_sg_log(struct d40_chan
*chan
, struct d40_desc
*desc
,
1936 struct scatterlist
*sg_src
, struct scatterlist
*sg_dst
,
1937 unsigned int sg_len
, dma_addr_t src_dev_addr
,
1938 dma_addr_t dst_dev_addr
)
1940 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
1941 struct stedma40_half_channel_info
*src_info
= &cfg
->src_info
;
1942 struct stedma40_half_channel_info
*dst_info
= &cfg
->dst_info
;
1945 ret
= d40_log_sg_to_lli(sg_src
, sg_len
,
1948 chan
->log_def
.lcsp1
,
1949 src_info
->data_width
,
1950 dst_info
->data_width
);
1952 ret
= d40_log_sg_to_lli(sg_dst
, sg_len
,
1955 chan
->log_def
.lcsp3
,
1956 dst_info
->data_width
,
1957 src_info
->data_width
);
1959 return ret
< 0 ? ret
: 0;
1963 d40_prep_sg_phy(struct d40_chan
*chan
, struct d40_desc
*desc
,
1964 struct scatterlist
*sg_src
, struct scatterlist
*sg_dst
,
1965 unsigned int sg_len
, dma_addr_t src_dev_addr
,
1966 dma_addr_t dst_dev_addr
)
1968 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
1969 struct stedma40_half_channel_info
*src_info
= &cfg
->src_info
;
1970 struct stedma40_half_channel_info
*dst_info
= &cfg
->dst_info
;
1971 unsigned long flags
= 0;
1975 flags
|= LLI_CYCLIC
| LLI_TERM_INT
;
1977 ret
= d40_phy_sg_to_lli(sg_src
, sg_len
, src_dev_addr
,
1979 virt_to_phys(desc
->lli_phy
.src
),
1981 src_info
, dst_info
, flags
);
1983 ret
= d40_phy_sg_to_lli(sg_dst
, sg_len
, dst_dev_addr
,
1985 virt_to_phys(desc
->lli_phy
.dst
),
1987 dst_info
, src_info
, flags
);
1989 dma_sync_single_for_device(chan
->base
->dev
, desc
->lli_pool
.dma_addr
,
1990 desc
->lli_pool
.size
, DMA_TO_DEVICE
);
1992 return ret
< 0 ? ret
: 0;
1996 static struct d40_desc
*
1997 d40_prep_desc(struct d40_chan
*chan
, struct scatterlist
*sg
,
1998 unsigned int sg_len
, unsigned long dma_flags
)
2000 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
2001 struct d40_desc
*desc
;
2004 desc
= d40_desc_get(chan
);
2008 desc
->lli_len
= d40_sg_2_dmalen(sg
, sg_len
, cfg
->src_info
.data_width
,
2009 cfg
->dst_info
.data_width
);
2010 if (desc
->lli_len
< 0) {
2011 chan_err(chan
, "Unaligned size\n");
2015 ret
= d40_pool_lli_alloc(chan
, desc
, desc
->lli_len
);
2017 chan_err(chan
, "Could not allocate lli\n");
2022 desc
->lli_current
= 0;
2023 desc
->txd
.flags
= dma_flags
;
2024 desc
->txd
.tx_submit
= d40_tx_submit
;
2026 dma_async_tx_descriptor_init(&desc
->txd
, &chan
->chan
);
2031 d40_desc_free(chan
, desc
);
2036 d40_get_dev_addr(struct d40_chan
*chan
, enum dma_transfer_direction direction
)
2038 struct stedma40_platform_data
*plat
= chan
->base
->plat_data
;
2039 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
2040 dma_addr_t addr
= 0;
2042 if (chan
->runtime_addr
)
2043 return chan
->runtime_addr
;
2045 if (direction
== DMA_DEV_TO_MEM
)
2046 addr
= plat
->dev_rx
[cfg
->src_dev_type
];
2047 else if (direction
== DMA_MEM_TO_DEV
)
2048 addr
= plat
->dev_tx
[cfg
->dst_dev_type
];
2053 static struct dma_async_tx_descriptor
*
2054 d40_prep_sg(struct dma_chan
*dchan
, struct scatterlist
*sg_src
,
2055 struct scatterlist
*sg_dst
, unsigned int sg_len
,
2056 enum dma_transfer_direction direction
, unsigned long dma_flags
)
2058 struct d40_chan
*chan
= container_of(dchan
, struct d40_chan
, chan
);
2059 dma_addr_t src_dev_addr
= 0;
2060 dma_addr_t dst_dev_addr
= 0;
2061 struct d40_desc
*desc
;
2062 unsigned long flags
;
2065 if (!chan
->phy_chan
) {
2066 chan_err(chan
, "Cannot prepare unallocated channel\n");
2071 spin_lock_irqsave(&chan
->lock
, flags
);
2073 desc
= d40_prep_desc(chan
, sg_src
, sg_len
, dma_flags
);
2077 if (sg_next(&sg_src
[sg_len
- 1]) == sg_src
)
2078 desc
->cyclic
= true;
2080 if (direction
!= DMA_NONE
) {
2081 dma_addr_t dev_addr
= d40_get_dev_addr(chan
, direction
);
2083 if (direction
== DMA_DEV_TO_MEM
)
2084 src_dev_addr
= dev_addr
;
2085 else if (direction
== DMA_MEM_TO_DEV
)
2086 dst_dev_addr
= dev_addr
;
2089 if (chan_is_logical(chan
))
2090 ret
= d40_prep_sg_log(chan
, desc
, sg_src
, sg_dst
,
2091 sg_len
, src_dev_addr
, dst_dev_addr
);
2093 ret
= d40_prep_sg_phy(chan
, desc
, sg_src
, sg_dst
,
2094 sg_len
, src_dev_addr
, dst_dev_addr
);
2097 chan_err(chan
, "Failed to prepare %s sg job: %d\n",
2098 chan_is_logical(chan
) ? "log" : "phy", ret
);
2103 * add descriptor to the prepare queue in order to be able
2104 * to free them later in terminate_all
2106 list_add_tail(&desc
->node
, &chan
->prepare_queue
);
2108 spin_unlock_irqrestore(&chan
->lock
, flags
);
2114 d40_desc_free(chan
, desc
);
2115 spin_unlock_irqrestore(&chan
->lock
, flags
);
2119 bool stedma40_filter(struct dma_chan
*chan
, void *data
)
2121 struct stedma40_chan_cfg
*info
= data
;
2122 struct d40_chan
*d40c
=
2123 container_of(chan
, struct d40_chan
, chan
);
2127 err
= d40_validate_conf(d40c
, info
);
2129 d40c
->dma_cfg
= *info
;
2131 err
= d40_config_memcpy(d40c
);
2134 d40c
->configured
= true;
2138 EXPORT_SYMBOL(stedma40_filter
);
2140 static void __d40_set_prio_rt(struct d40_chan
*d40c
, int dev_type
, bool src
)
2142 bool realtime
= d40c
->dma_cfg
.realtime
;
2143 bool highprio
= d40c
->dma_cfg
.high_priority
;
2144 u32 prioreg
= highprio
? D40_DREG_PSEG1
: D40_DREG_PCEG1
;
2145 u32 rtreg
= realtime
? D40_DREG_RSEG1
: D40_DREG_RCEG1
;
2146 u32 event
= D40_TYPE_TO_EVENT(dev_type
);
2147 u32 group
= D40_TYPE_TO_GROUP(dev_type
);
2148 u32 bit
= 1 << event
;
2150 /* Destination event lines are stored in the upper halfword */
2154 writel(bit
, d40c
->base
->virtbase
+ prioreg
+ group
* 4);
2155 writel(bit
, d40c
->base
->virtbase
+ rtreg
+ group
* 4);
2158 static void d40_set_prio_realtime(struct d40_chan
*d40c
)
2160 if (d40c
->base
->rev
< 3)
2163 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
2164 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
2165 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.src_dev_type
, true);
2167 if ((d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
) ||
2168 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
2169 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.dst_dev_type
, false);
2172 /* DMA ENGINE functions */
2173 static int d40_alloc_chan_resources(struct dma_chan
*chan
)
2176 unsigned long flags
;
2177 struct d40_chan
*d40c
=
2178 container_of(chan
, struct d40_chan
, chan
);
2180 spin_lock_irqsave(&d40c
->lock
, flags
);
2182 chan
->completed_cookie
= chan
->cookie
= 1;
2184 /* If no dma configuration is set use default configuration (memcpy) */
2185 if (!d40c
->configured
) {
2186 err
= d40_config_memcpy(d40c
);
2188 chan_err(d40c
, "Failed to configure memcpy channel\n");
2193 err
= d40_allocate_channel(d40c
, &is_free_phy
);
2195 chan_err(d40c
, "Failed to allocate channel\n");
2196 d40c
->configured
= false;
2200 pm_runtime_get_sync(d40c
->base
->dev
);
2201 /* Fill in basic CFG register values */
2202 d40_phy_cfg(&d40c
->dma_cfg
, &d40c
->src_def_cfg
,
2203 &d40c
->dst_def_cfg
, chan_is_logical(d40c
));
2205 d40_set_prio_realtime(d40c
);
2207 if (chan_is_logical(d40c
)) {
2208 d40_log_cfg(&d40c
->dma_cfg
,
2209 &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
2211 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
2212 d40c
->lcpa
= d40c
->base
->lcpa_base
+
2213 d40c
->dma_cfg
.src_dev_type
* D40_LCPA_CHAN_SIZE
;
2215 d40c
->lcpa
= d40c
->base
->lcpa_base
+
2216 d40c
->dma_cfg
.dst_dev_type
*
2217 D40_LCPA_CHAN_SIZE
+ D40_LCPA_CHAN_DST_DELTA
;
2220 dev_dbg(chan2dev(d40c
), "allocated %s channel (phy %d%s)\n",
2221 chan_is_logical(d40c
) ? "logical" : "physical",
2222 d40c
->phy_chan
->num
,
2223 d40c
->dma_cfg
.use_fixed_channel
? ", fixed" : "");
2227 * Only write channel configuration to the DMA if the physical
2228 * resource is free. In case of multiple logical channels
2229 * on the same physical resource, only the first write is necessary.
2232 d40_config_write(d40c
);
2234 pm_runtime_mark_last_busy(d40c
->base
->dev
);
2235 pm_runtime_put_autosuspend(d40c
->base
->dev
);
2236 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2240 static void d40_free_chan_resources(struct dma_chan
*chan
)
2242 struct d40_chan
*d40c
=
2243 container_of(chan
, struct d40_chan
, chan
);
2245 unsigned long flags
;
2247 if (d40c
->phy_chan
== NULL
) {
2248 chan_err(d40c
, "Cannot free unallocated channel\n");
2253 spin_lock_irqsave(&d40c
->lock
, flags
);
2255 err
= d40_free_dma(d40c
);
2258 chan_err(d40c
, "Failed to free channel\n");
2259 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2262 static struct dma_async_tx_descriptor
*d40_prep_memcpy(struct dma_chan
*chan
,
2266 unsigned long dma_flags
)
2268 struct scatterlist dst_sg
;
2269 struct scatterlist src_sg
;
2271 sg_init_table(&dst_sg
, 1);
2272 sg_init_table(&src_sg
, 1);
2274 sg_dma_address(&dst_sg
) = dst
;
2275 sg_dma_address(&src_sg
) = src
;
2277 sg_dma_len(&dst_sg
) = size
;
2278 sg_dma_len(&src_sg
) = size
;
2280 return d40_prep_sg(chan
, &src_sg
, &dst_sg
, 1, DMA_NONE
, dma_flags
);
2283 static struct dma_async_tx_descriptor
*
2284 d40_prep_memcpy_sg(struct dma_chan
*chan
,
2285 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
2286 struct scatterlist
*src_sg
, unsigned int src_nents
,
2287 unsigned long dma_flags
)
2289 if (dst_nents
!= src_nents
)
2292 return d40_prep_sg(chan
, src_sg
, dst_sg
, src_nents
, DMA_NONE
, dma_flags
);
2295 static struct dma_async_tx_descriptor
*d40_prep_slave_sg(struct dma_chan
*chan
,
2296 struct scatterlist
*sgl
,
2297 unsigned int sg_len
,
2298 enum dma_transfer_direction direction
,
2299 unsigned long dma_flags
)
2301 if (direction
!= DMA_DEV_TO_MEM
&& direction
!= DMA_MEM_TO_DEV
)
2304 return d40_prep_sg(chan
, sgl
, sgl
, sg_len
, direction
, dma_flags
);
2307 static struct dma_async_tx_descriptor
*
2308 dma40_prep_dma_cyclic(struct dma_chan
*chan
, dma_addr_t dma_addr
,
2309 size_t buf_len
, size_t period_len
,
2310 enum dma_transfer_direction direction
)
2312 unsigned int periods
= buf_len
/ period_len
;
2313 struct dma_async_tx_descriptor
*txd
;
2314 struct scatterlist
*sg
;
2317 sg
= kcalloc(periods
+ 1, sizeof(struct scatterlist
), GFP_NOWAIT
);
2318 for (i
= 0; i
< periods
; i
++) {
2319 sg_dma_address(&sg
[i
]) = dma_addr
;
2320 sg_dma_len(&sg
[i
]) = period_len
;
2321 dma_addr
+= period_len
;
2324 sg
[periods
].offset
= 0;
2325 sg
[periods
].length
= 0;
2326 sg
[periods
].page_link
=
2327 ((unsigned long)sg
| 0x01) & ~0x02;
2329 txd
= d40_prep_sg(chan
, sg
, sg
, periods
, direction
,
2330 DMA_PREP_INTERRUPT
);
2337 static enum dma_status
d40_tx_status(struct dma_chan
*chan
,
2338 dma_cookie_t cookie
,
2339 struct dma_tx_state
*txstate
)
2341 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2342 dma_cookie_t last_used
;
2343 dma_cookie_t last_complete
;
2346 if (d40c
->phy_chan
== NULL
) {
2347 chan_err(d40c
, "Cannot read status of unallocated channel\n");
2351 last_complete
= chan
->completed_cookie
;
2352 last_used
= chan
->cookie
;
2354 if (d40_is_paused(d40c
))
2357 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
2359 dma_set_tx_state(txstate
, last_complete
, last_used
,
2360 stedma40_residue(chan
));
2365 static void d40_issue_pending(struct dma_chan
*chan
)
2367 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2368 unsigned long flags
;
2370 if (d40c
->phy_chan
== NULL
) {
2371 chan_err(d40c
, "Channel is not allocated!\n");
2375 spin_lock_irqsave(&d40c
->lock
, flags
);
2377 list_splice_tail_init(&d40c
->pending_queue
, &d40c
->queue
);
2379 /* Busy means that queued jobs are already being processed */
2381 (void) d40_queue_start(d40c
);
2383 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2387 dma40_config_to_halfchannel(struct d40_chan
*d40c
,
2388 struct stedma40_half_channel_info
*info
,
2389 enum dma_slave_buswidth width
,
2392 enum stedma40_periph_data_width addr_width
;
2396 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
2397 addr_width
= STEDMA40_BYTE_WIDTH
;
2399 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
2400 addr_width
= STEDMA40_HALFWORD_WIDTH
;
2402 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
2403 addr_width
= STEDMA40_WORD_WIDTH
;
2405 case DMA_SLAVE_BUSWIDTH_8_BYTES
:
2406 addr_width
= STEDMA40_DOUBLEWORD_WIDTH
;
2409 dev_err(d40c
->base
->dev
,
2410 "illegal peripheral address width "
2416 if (chan_is_logical(d40c
)) {
2418 psize
= STEDMA40_PSIZE_LOG_16
;
2419 else if (maxburst
>= 8)
2420 psize
= STEDMA40_PSIZE_LOG_8
;
2421 else if (maxburst
>= 4)
2422 psize
= STEDMA40_PSIZE_LOG_4
;
2424 psize
= STEDMA40_PSIZE_LOG_1
;
2427 psize
= STEDMA40_PSIZE_PHY_16
;
2428 else if (maxburst
>= 8)
2429 psize
= STEDMA40_PSIZE_PHY_8
;
2430 else if (maxburst
>= 4)
2431 psize
= STEDMA40_PSIZE_PHY_4
;
2433 psize
= STEDMA40_PSIZE_PHY_1
;
2436 info
->data_width
= addr_width
;
2437 info
->psize
= psize
;
2438 info
->flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2443 /* Runtime reconfiguration extension */
2444 static int d40_set_runtime_config(struct dma_chan
*chan
,
2445 struct dma_slave_config
*config
)
2447 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2448 struct stedma40_chan_cfg
*cfg
= &d40c
->dma_cfg
;
2449 enum dma_slave_buswidth src_addr_width
, dst_addr_width
;
2450 dma_addr_t config_addr
;
2451 u32 src_maxburst
, dst_maxburst
;
2454 src_addr_width
= config
->src_addr_width
;
2455 src_maxburst
= config
->src_maxburst
;
2456 dst_addr_width
= config
->dst_addr_width
;
2457 dst_maxburst
= config
->dst_maxburst
;
2459 if (config
->direction
== DMA_DEV_TO_MEM
) {
2460 dma_addr_t dev_addr_rx
=
2461 d40c
->base
->plat_data
->dev_rx
[cfg
->src_dev_type
];
2463 config_addr
= config
->src_addr
;
2465 dev_dbg(d40c
->base
->dev
,
2466 "channel has a pre-wired RX address %08x "
2467 "overriding with %08x\n",
2468 dev_addr_rx
, config_addr
);
2469 if (cfg
->dir
!= STEDMA40_PERIPH_TO_MEM
)
2470 dev_dbg(d40c
->base
->dev
,
2471 "channel was not configured for peripheral "
2472 "to memory transfer (%d) overriding\n",
2474 cfg
->dir
= STEDMA40_PERIPH_TO_MEM
;
2476 /* Configure the memory side */
2477 if (dst_addr_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
)
2478 dst_addr_width
= src_addr_width
;
2479 if (dst_maxburst
== 0)
2480 dst_maxburst
= src_maxburst
;
2482 } else if (config
->direction
== DMA_MEM_TO_DEV
) {
2483 dma_addr_t dev_addr_tx
=
2484 d40c
->base
->plat_data
->dev_tx
[cfg
->dst_dev_type
];
2486 config_addr
= config
->dst_addr
;
2488 dev_dbg(d40c
->base
->dev
,
2489 "channel has a pre-wired TX address %08x "
2490 "overriding with %08x\n",
2491 dev_addr_tx
, config_addr
);
2492 if (cfg
->dir
!= STEDMA40_MEM_TO_PERIPH
)
2493 dev_dbg(d40c
->base
->dev
,
2494 "channel was not configured for memory "
2495 "to peripheral transfer (%d) overriding\n",
2497 cfg
->dir
= STEDMA40_MEM_TO_PERIPH
;
2499 /* Configure the memory side */
2500 if (src_addr_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
)
2501 src_addr_width
= dst_addr_width
;
2502 if (src_maxburst
== 0)
2503 src_maxburst
= dst_maxburst
;
2505 dev_err(d40c
->base
->dev
,
2506 "unrecognized channel direction %d\n",
2511 if (src_maxburst
* src_addr_width
!= dst_maxburst
* dst_addr_width
) {
2512 dev_err(d40c
->base
->dev
,
2513 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2521 ret
= dma40_config_to_halfchannel(d40c
, &cfg
->src_info
,
2527 ret
= dma40_config_to_halfchannel(d40c
, &cfg
->dst_info
,
2533 /* Fill in register values */
2534 if (chan_is_logical(d40c
))
2535 d40_log_cfg(cfg
, &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
2537 d40_phy_cfg(cfg
, &d40c
->src_def_cfg
,
2538 &d40c
->dst_def_cfg
, false);
2540 /* These settings will take precedence later */
2541 d40c
->runtime_addr
= config_addr
;
2542 d40c
->runtime_direction
= config
->direction
;
2543 dev_dbg(d40c
->base
->dev
,
2544 "configured channel %s for %s, data width %d/%d, "
2545 "maxburst %d/%d elements, LE, no flow control\n",
2546 dma_chan_name(chan
),
2547 (config
->direction
== DMA_DEV_TO_MEM
) ? "RX" : "TX",
2548 src_addr_width
, dst_addr_width
,
2549 src_maxburst
, dst_maxburst
);
2554 static int d40_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
2557 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2559 if (d40c
->phy_chan
== NULL
) {
2560 chan_err(d40c
, "Channel is not allocated!\n");
2565 case DMA_TERMINATE_ALL
:
2566 return d40_terminate_all(d40c
);
2568 return d40_pause(d40c
);
2570 return d40_resume(d40c
);
2571 case DMA_SLAVE_CONFIG
:
2572 return d40_set_runtime_config(chan
,
2573 (struct dma_slave_config
*) arg
);
2578 /* Other commands are unimplemented */
2582 /* Initialization functions */
2584 static void __init
d40_chan_init(struct d40_base
*base
, struct dma_device
*dma
,
2585 struct d40_chan
*chans
, int offset
,
2589 struct d40_chan
*d40c
;
2591 INIT_LIST_HEAD(&dma
->channels
);
2593 for (i
= offset
; i
< offset
+ num_chans
; i
++) {
2596 d40c
->chan
.device
= dma
;
2598 spin_lock_init(&d40c
->lock
);
2600 d40c
->log_num
= D40_PHY_CHAN
;
2602 INIT_LIST_HEAD(&d40c
->active
);
2603 INIT_LIST_HEAD(&d40c
->queue
);
2604 INIT_LIST_HEAD(&d40c
->pending_queue
);
2605 INIT_LIST_HEAD(&d40c
->client
);
2606 INIT_LIST_HEAD(&d40c
->prepare_queue
);
2608 tasklet_init(&d40c
->tasklet
, dma_tasklet
,
2609 (unsigned long) d40c
);
2611 list_add_tail(&d40c
->chan
.device_node
,
2616 static void d40_ops_init(struct d40_base
*base
, struct dma_device
*dev
)
2618 if (dma_has_cap(DMA_SLAVE
, dev
->cap_mask
))
2619 dev
->device_prep_slave_sg
= d40_prep_slave_sg
;
2621 if (dma_has_cap(DMA_MEMCPY
, dev
->cap_mask
)) {
2622 dev
->device_prep_dma_memcpy
= d40_prep_memcpy
;
2625 * This controller can only access address at even
2626 * 32bit boundaries, i.e. 2^2
2628 dev
->copy_align
= 2;
2631 if (dma_has_cap(DMA_SG
, dev
->cap_mask
))
2632 dev
->device_prep_dma_sg
= d40_prep_memcpy_sg
;
2634 if (dma_has_cap(DMA_CYCLIC
, dev
->cap_mask
))
2635 dev
->device_prep_dma_cyclic
= dma40_prep_dma_cyclic
;
2637 dev
->device_alloc_chan_resources
= d40_alloc_chan_resources
;
2638 dev
->device_free_chan_resources
= d40_free_chan_resources
;
2639 dev
->device_issue_pending
= d40_issue_pending
;
2640 dev
->device_tx_status
= d40_tx_status
;
2641 dev
->device_control
= d40_control
;
2642 dev
->dev
= base
->dev
;
2645 static int __init
d40_dmaengine_init(struct d40_base
*base
,
2646 int num_reserved_chans
)
2650 d40_chan_init(base
, &base
->dma_slave
, base
->log_chans
,
2651 0, base
->num_log_chans
);
2653 dma_cap_zero(base
->dma_slave
.cap_mask
);
2654 dma_cap_set(DMA_SLAVE
, base
->dma_slave
.cap_mask
);
2655 dma_cap_set(DMA_CYCLIC
, base
->dma_slave
.cap_mask
);
2657 d40_ops_init(base
, &base
->dma_slave
);
2659 err
= dma_async_device_register(&base
->dma_slave
);
2662 d40_err(base
->dev
, "Failed to register slave channels\n");
2666 d40_chan_init(base
, &base
->dma_memcpy
, base
->log_chans
,
2667 base
->num_log_chans
, base
->plat_data
->memcpy_len
);
2669 dma_cap_zero(base
->dma_memcpy
.cap_mask
);
2670 dma_cap_set(DMA_MEMCPY
, base
->dma_memcpy
.cap_mask
);
2671 dma_cap_set(DMA_SG
, base
->dma_memcpy
.cap_mask
);
2673 d40_ops_init(base
, &base
->dma_memcpy
);
2675 err
= dma_async_device_register(&base
->dma_memcpy
);
2679 "Failed to regsiter memcpy only channels\n");
2683 d40_chan_init(base
, &base
->dma_both
, base
->phy_chans
,
2684 0, num_reserved_chans
);
2686 dma_cap_zero(base
->dma_both
.cap_mask
);
2687 dma_cap_set(DMA_SLAVE
, base
->dma_both
.cap_mask
);
2688 dma_cap_set(DMA_MEMCPY
, base
->dma_both
.cap_mask
);
2689 dma_cap_set(DMA_SG
, base
->dma_both
.cap_mask
);
2690 dma_cap_set(DMA_CYCLIC
, base
->dma_slave
.cap_mask
);
2692 d40_ops_init(base
, &base
->dma_both
);
2693 err
= dma_async_device_register(&base
->dma_both
);
2697 "Failed to register logical and physical capable channels\n");
2702 dma_async_device_unregister(&base
->dma_memcpy
);
2704 dma_async_device_unregister(&base
->dma_slave
);
2709 /* Suspend resume functionality */
2711 static int dma40_pm_suspend(struct device
*dev
)
2713 struct platform_device
*pdev
= to_platform_device(dev
);
2714 struct d40_base
*base
= platform_get_drvdata(pdev
);
2716 if (!pm_runtime_suspended(dev
))
2719 if (base
->lcpa_regulator
)
2720 ret
= regulator_disable(base
->lcpa_regulator
);
2724 static int dma40_runtime_suspend(struct device
*dev
)
2726 struct platform_device
*pdev
= to_platform_device(dev
);
2727 struct d40_base
*base
= platform_get_drvdata(pdev
);
2729 d40_save_restore_registers(base
, true);
2731 /* Don't disable/enable clocks for v1 due to HW bugs */
2733 writel_relaxed(base
->gcc_pwr_off_mask
,
2734 base
->virtbase
+ D40_DREG_GCC
);
2739 static int dma40_runtime_resume(struct device
*dev
)
2741 struct platform_device
*pdev
= to_platform_device(dev
);
2742 struct d40_base
*base
= platform_get_drvdata(pdev
);
2744 if (base
->initialized
)
2745 d40_save_restore_registers(base
, false);
2747 writel_relaxed(D40_DREG_GCC_ENABLE_ALL
,
2748 base
->virtbase
+ D40_DREG_GCC
);
2752 static int dma40_resume(struct device
*dev
)
2754 struct platform_device
*pdev
= to_platform_device(dev
);
2755 struct d40_base
*base
= platform_get_drvdata(pdev
);
2758 if (base
->lcpa_regulator
)
2759 ret
= regulator_enable(base
->lcpa_regulator
);
2764 static const struct dev_pm_ops dma40_pm_ops
= {
2765 .suspend
= dma40_pm_suspend
,
2766 .runtime_suspend
= dma40_runtime_suspend
,
2767 .runtime_resume
= dma40_runtime_resume
,
2768 .resume
= dma40_resume
,
2770 #define DMA40_PM_OPS (&dma40_pm_ops)
2772 #define DMA40_PM_OPS NULL
2775 /* Initialization functions. */
2777 static int __init
d40_phy_res_init(struct d40_base
*base
)
2780 int num_phy_chans_avail
= 0;
2782 int odd_even_bit
= -2;
2783 int gcc
= D40_DREG_GCC_ENA
;
2785 val
[0] = readl(base
->virtbase
+ D40_DREG_PRSME
);
2786 val
[1] = readl(base
->virtbase
+ D40_DREG_PRSMO
);
2788 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2789 base
->phy_res
[i
].num
= i
;
2790 odd_even_bit
+= 2 * ((i
% 2) == 0);
2791 if (((val
[i
% 2] >> odd_even_bit
) & 3) == 1) {
2792 /* Mark security only channels as occupied */
2793 base
->phy_res
[i
].allocated_src
= D40_ALLOC_PHY
;
2794 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_PHY
;
2795 base
->phy_res
[i
].reserved
= true;
2796 gcc
|= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i
),
2798 gcc
|= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i
),
2803 base
->phy_res
[i
].allocated_src
= D40_ALLOC_FREE
;
2804 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_FREE
;
2805 base
->phy_res
[i
].reserved
= false;
2806 num_phy_chans_avail
++;
2808 spin_lock_init(&base
->phy_res
[i
].lock
);
2811 /* Mark disabled channels as occupied */
2812 for (i
= 0; base
->plat_data
->disabled_channels
[i
] != -1; i
++) {
2813 int chan
= base
->plat_data
->disabled_channels
[i
];
2815 base
->phy_res
[chan
].allocated_src
= D40_ALLOC_PHY
;
2816 base
->phy_res
[chan
].allocated_dst
= D40_ALLOC_PHY
;
2817 base
->phy_res
[chan
].reserved
= true;
2818 gcc
|= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan
),
2820 gcc
|= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan
),
2822 num_phy_chans_avail
--;
2825 dev_info(base
->dev
, "%d of %d physical DMA channels available\n",
2826 num_phy_chans_avail
, base
->num_phy_chans
);
2828 /* Verify settings extended vs standard */
2829 val
[0] = readl(base
->virtbase
+ D40_DREG_PRTYP
);
2831 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2833 if (base
->phy_res
[i
].allocated_src
== D40_ALLOC_FREE
&&
2834 (val
[0] & 0x3) != 1)
2836 "[%s] INFO: channel %d is misconfigured (%d)\n",
2837 __func__
, i
, val
[0] & 0x3);
2839 val
[0] = val
[0] >> 2;
2843 * To keep things simple, Enable all clocks initially.
2844 * The clocks will get managed later post channel allocation.
2845 * The clocks for the event lines on which reserved channels exists
2846 * are not managed here.
2848 writel(D40_DREG_GCC_ENABLE_ALL
, base
->virtbase
+ D40_DREG_GCC
);
2849 base
->gcc_pwr_off_mask
= gcc
;
2851 return num_phy_chans_avail
;
2854 static struct d40_base
* __init
d40_hw_detect_init(struct platform_device
*pdev
)
2856 struct stedma40_platform_data
*plat_data
;
2857 struct clk
*clk
= NULL
;
2858 void __iomem
*virtbase
= NULL
;
2859 struct resource
*res
= NULL
;
2860 struct d40_base
*base
= NULL
;
2861 int num_log_chans
= 0;
2868 clk
= clk_get(&pdev
->dev
, NULL
);
2871 d40_err(&pdev
->dev
, "No matching clock found\n");
2877 /* Get IO for DMAC base address */
2878 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "base");
2882 if (request_mem_region(res
->start
, resource_size(res
),
2883 D40_NAME
" I/O base") == NULL
)
2886 virtbase
= ioremap(res
->start
, resource_size(res
));
2890 /* This is just a regular AMBA PrimeCell ID actually */
2891 for (pid
= 0, i
= 0; i
< 4; i
++)
2892 pid
|= (readl(virtbase
+ resource_size(res
) - 0x20 + 4 * i
)
2894 for (cid
= 0, i
= 0; i
< 4; i
++)
2895 cid
|= (readl(virtbase
+ resource_size(res
) - 0x10 + 4 * i
)
2898 if (cid
!= AMBA_CID
) {
2899 d40_err(&pdev
->dev
, "Unknown hardware! No PrimeCell ID\n");
2902 if (AMBA_MANF_BITS(pid
) != AMBA_VENDOR_ST
) {
2903 d40_err(&pdev
->dev
, "Unknown designer! Got %x wanted %x\n",
2904 AMBA_MANF_BITS(pid
),
2910 * DB8500ed has revision 0
2912 * DB8500v1 has revision 2
2913 * DB8500v2 has revision 3
2915 rev
= AMBA_REV_BITS(pid
);
2917 /* The number of physical channels on this HW */
2918 num_phy_chans
= 4 * (readl(virtbase
+ D40_DREG_ICFG
) & 0x7) + 4;
2920 dev_info(&pdev
->dev
, "hardware revision: %d @ 0x%x\n",
2923 plat_data
= pdev
->dev
.platform_data
;
2925 /* Count the number of logical channels in use */
2926 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2927 if (plat_data
->dev_rx
[i
] != 0)
2930 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2931 if (plat_data
->dev_tx
[i
] != 0)
2934 base
= kzalloc(ALIGN(sizeof(struct d40_base
), 4) +
2935 (num_phy_chans
+ num_log_chans
+ plat_data
->memcpy_len
) *
2936 sizeof(struct d40_chan
), GFP_KERNEL
);
2939 d40_err(&pdev
->dev
, "Out of memory\n");
2945 base
->num_phy_chans
= num_phy_chans
;
2946 base
->num_log_chans
= num_log_chans
;
2947 base
->phy_start
= res
->start
;
2948 base
->phy_size
= resource_size(res
);
2949 base
->virtbase
= virtbase
;
2950 base
->plat_data
= plat_data
;
2951 base
->dev
= &pdev
->dev
;
2952 base
->phy_chans
= ((void *)base
) + ALIGN(sizeof(struct d40_base
), 4);
2953 base
->log_chans
= &base
->phy_chans
[num_phy_chans
];
2955 base
->phy_res
= kzalloc(num_phy_chans
* sizeof(struct d40_phy_res
),
2960 base
->lookup_phy_chans
= kzalloc(num_phy_chans
*
2961 sizeof(struct d40_chan
*),
2963 if (!base
->lookup_phy_chans
)
2966 if (num_log_chans
+ plat_data
->memcpy_len
) {
2968 * The max number of logical channels are event lines for all
2969 * src devices and dst devices
2971 base
->lookup_log_chans
= kzalloc(plat_data
->dev_len
* 2 *
2972 sizeof(struct d40_chan
*),
2974 if (!base
->lookup_log_chans
)
2978 base
->reg_val_backup_chan
= kmalloc(base
->num_phy_chans
*
2979 sizeof(d40_backup_regs_chan
),
2981 if (!base
->reg_val_backup_chan
)
2984 base
->lcla_pool
.alloc_map
=
2985 kzalloc(num_phy_chans
* sizeof(struct d40_desc
*)
2986 * D40_LCLA_LINK_PER_EVENT_GRP
, GFP_KERNEL
);
2987 if (!base
->lcla_pool
.alloc_map
)
2990 base
->desc_slab
= kmem_cache_create(D40_NAME
, sizeof(struct d40_desc
),
2991 0, SLAB_HWCACHE_ALIGN
,
2993 if (base
->desc_slab
== NULL
)
3006 release_mem_region(res
->start
,
3007 resource_size(res
));
3012 kfree(base
->lcla_pool
.alloc_map
);
3013 kfree(base
->lookup_log_chans
);
3014 kfree(base
->lookup_phy_chans
);
3015 kfree(base
->phy_res
);
3022 static void __init
d40_hw_init(struct d40_base
*base
)
3025 static struct d40_reg_val dma_init_reg
[] = {
3026 /* Clock every part of the DMA block from start */
3027 { .reg
= D40_DREG_GCC
, .val
= D40_DREG_GCC_ENABLE_ALL
},
3029 /* Interrupts on all logical channels */
3030 { .reg
= D40_DREG_LCMIS0
, .val
= 0xFFFFFFFF},
3031 { .reg
= D40_DREG_LCMIS1
, .val
= 0xFFFFFFFF},
3032 { .reg
= D40_DREG_LCMIS2
, .val
= 0xFFFFFFFF},
3033 { .reg
= D40_DREG_LCMIS3
, .val
= 0xFFFFFFFF},
3034 { .reg
= D40_DREG_LCICR0
, .val
= 0xFFFFFFFF},
3035 { .reg
= D40_DREG_LCICR1
, .val
= 0xFFFFFFFF},
3036 { .reg
= D40_DREG_LCICR2
, .val
= 0xFFFFFFFF},
3037 { .reg
= D40_DREG_LCICR3
, .val
= 0xFFFFFFFF},
3038 { .reg
= D40_DREG_LCTIS0
, .val
= 0xFFFFFFFF},
3039 { .reg
= D40_DREG_LCTIS1
, .val
= 0xFFFFFFFF},
3040 { .reg
= D40_DREG_LCTIS2
, .val
= 0xFFFFFFFF},
3041 { .reg
= D40_DREG_LCTIS3
, .val
= 0xFFFFFFFF}
3044 u32 prmseo
[2] = {0, 0};
3045 u32 activeo
[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3049 for (i
= 0; i
< ARRAY_SIZE(dma_init_reg
); i
++)
3050 writel(dma_init_reg
[i
].val
,
3051 base
->virtbase
+ dma_init_reg
[i
].reg
);
3053 /* Configure all our dma channels to default settings */
3054 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
3056 activeo
[i
% 2] = activeo
[i
% 2] << 2;
3058 if (base
->phy_res
[base
->num_phy_chans
- i
- 1].allocated_src
3060 activeo
[i
% 2] |= 3;
3064 /* Enable interrupt # */
3065 pcmis
= (pcmis
<< 1) | 1;
3067 /* Clear interrupt # */
3068 pcicr
= (pcicr
<< 1) | 1;
3070 /* Set channel to physical mode */
3071 prmseo
[i
% 2] = prmseo
[i
% 2] << 2;
3076 writel(prmseo
[1], base
->virtbase
+ D40_DREG_PRMSE
);
3077 writel(prmseo
[0], base
->virtbase
+ D40_DREG_PRMSO
);
3078 writel(activeo
[1], base
->virtbase
+ D40_DREG_ACTIVE
);
3079 writel(activeo
[0], base
->virtbase
+ D40_DREG_ACTIVO
);
3081 /* Write which interrupt to enable */
3082 writel(pcmis
, base
->virtbase
+ D40_DREG_PCMIS
);
3084 /* Write which interrupt to clear */
3085 writel(pcicr
, base
->virtbase
+ D40_DREG_PCICR
);
3089 static int __init
d40_lcla_allocate(struct d40_base
*base
)
3091 struct d40_lcla_pool
*pool
= &base
->lcla_pool
;
3092 unsigned long *page_list
;
3097 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3098 * To full fill this hardware requirement without wasting 256 kb
3099 * we allocate pages until we get an aligned one.
3101 page_list
= kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS
,
3109 /* Calculating how many pages that are required */
3110 base
->lcla_pool
.pages
= SZ_1K
* base
->num_phy_chans
/ PAGE_SIZE
;
3112 for (i
= 0; i
< MAX_LCLA_ALLOC_ATTEMPTS
; i
++) {
3113 page_list
[i
] = __get_free_pages(GFP_KERNEL
,
3114 base
->lcla_pool
.pages
);
3115 if (!page_list
[i
]) {
3117 d40_err(base
->dev
, "Failed to allocate %d pages.\n",
3118 base
->lcla_pool
.pages
);
3120 for (j
= 0; j
< i
; j
++)
3121 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
3125 if ((virt_to_phys((void *)page_list
[i
]) &
3126 (LCLA_ALIGNMENT
- 1)) == 0)
3130 for (j
= 0; j
< i
; j
++)
3131 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
3133 if (i
< MAX_LCLA_ALLOC_ATTEMPTS
) {
3134 base
->lcla_pool
.base
= (void *)page_list
[i
];
3137 * After many attempts and no succees with finding the correct
3138 * alignment, try with allocating a big buffer.
3141 "[%s] Failed to get %d pages @ 18 bit align.\n",
3142 __func__
, base
->lcla_pool
.pages
);
3143 base
->lcla_pool
.base_unaligned
= kmalloc(SZ_1K
*
3144 base
->num_phy_chans
+
3147 if (!base
->lcla_pool
.base_unaligned
) {
3152 base
->lcla_pool
.base
= PTR_ALIGN(base
->lcla_pool
.base_unaligned
,
3156 pool
->dma_addr
= dma_map_single(base
->dev
, pool
->base
,
3157 SZ_1K
* base
->num_phy_chans
,
3159 if (dma_mapping_error(base
->dev
, pool
->dma_addr
)) {
3165 writel(virt_to_phys(base
->lcla_pool
.base
),
3166 base
->virtbase
+ D40_DREG_LCLA
);
3172 static int __init
d40_probe(struct platform_device
*pdev
)
3176 struct d40_base
*base
;
3177 struct resource
*res
= NULL
;
3178 int num_reserved_chans
;
3181 base
= d40_hw_detect_init(pdev
);
3186 num_reserved_chans
= d40_phy_res_init(base
);
3188 platform_set_drvdata(pdev
, base
);
3190 spin_lock_init(&base
->interrupt_lock
);
3191 spin_lock_init(&base
->execmd_lock
);
3193 /* Get IO for logical channel parameter address */
3194 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "lcpa");
3197 d40_err(&pdev
->dev
, "No \"lcpa\" memory resource\n");
3200 base
->lcpa_size
= resource_size(res
);
3201 base
->phy_lcpa
= res
->start
;
3203 if (request_mem_region(res
->start
, resource_size(res
),
3204 D40_NAME
" I/O lcpa") == NULL
) {
3207 "Failed to request LCPA region 0x%x-0x%x\n",
3208 res
->start
, res
->end
);
3212 /* We make use of ESRAM memory for this. */
3213 val
= readl(base
->virtbase
+ D40_DREG_LCPA
);
3214 if (res
->start
!= val
&& val
!= 0) {
3215 dev_warn(&pdev
->dev
,
3216 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
3217 __func__
, val
, res
->start
);
3219 writel(res
->start
, base
->virtbase
+ D40_DREG_LCPA
);
3221 base
->lcpa_base
= ioremap(res
->start
, resource_size(res
));
3222 if (!base
->lcpa_base
) {
3224 d40_err(&pdev
->dev
, "Failed to ioremap LCPA region\n");
3227 /* If lcla has to be located in ESRAM we don't need to allocate */
3228 if (base
->plat_data
->use_esram_lcla
) {
3229 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
3234 "No \"lcla_esram\" memory resource\n");
3237 base
->lcla_pool
.base
= ioremap(res
->start
,
3238 resource_size(res
));
3239 if (!base
->lcla_pool
.base
) {
3241 d40_err(&pdev
->dev
, "Failed to ioremap LCLA region\n");
3244 writel(res
->start
, base
->virtbase
+ D40_DREG_LCLA
);
3247 ret
= d40_lcla_allocate(base
);
3249 d40_err(&pdev
->dev
, "Failed to allocate LCLA area\n");
3254 spin_lock_init(&base
->lcla_pool
.lock
);
3256 base
->irq
= platform_get_irq(pdev
, 0);
3258 ret
= request_irq(base
->irq
, d40_handle_interrupt
, 0, D40_NAME
, base
);
3260 d40_err(&pdev
->dev
, "No IRQ defined\n");
3264 pm_runtime_irq_safe(base
->dev
);
3265 pm_runtime_set_autosuspend_delay(base
->dev
, DMA40_AUTOSUSPEND_DELAY
);
3266 pm_runtime_use_autosuspend(base
->dev
);
3267 pm_runtime_enable(base
->dev
);
3268 pm_runtime_resume(base
->dev
);
3270 if (base
->plat_data
->use_esram_lcla
) {
3272 base
->lcpa_regulator
= regulator_get(base
->dev
, "lcla_esram");
3273 if (IS_ERR(base
->lcpa_regulator
)) {
3274 d40_err(&pdev
->dev
, "Failed to get lcpa_regulator\n");
3275 base
->lcpa_regulator
= NULL
;
3279 ret
= regulator_enable(base
->lcpa_regulator
);
3282 "Failed to enable lcpa_regulator\n");
3283 regulator_put(base
->lcpa_regulator
);
3284 base
->lcpa_regulator
= NULL
;
3289 base
->initialized
= true;
3290 err
= d40_dmaengine_init(base
, num_reserved_chans
);
3296 dev_info(base
->dev
, "initialized\n");
3301 if (base
->desc_slab
)
3302 kmem_cache_destroy(base
->desc_slab
);
3304 iounmap(base
->virtbase
);
3306 if (base
->lcla_pool
.base
&& base
->plat_data
->use_esram_lcla
) {
3307 iounmap(base
->lcla_pool
.base
);
3308 base
->lcla_pool
.base
= NULL
;
3311 if (base
->lcla_pool
.dma_addr
)
3312 dma_unmap_single(base
->dev
, base
->lcla_pool
.dma_addr
,
3313 SZ_1K
* base
->num_phy_chans
,
3316 if (!base
->lcla_pool
.base_unaligned
&& base
->lcla_pool
.base
)
3317 free_pages((unsigned long)base
->lcla_pool
.base
,
3318 base
->lcla_pool
.pages
);
3320 kfree(base
->lcla_pool
.base_unaligned
);
3323 release_mem_region(base
->phy_lcpa
,
3325 if (base
->phy_start
)
3326 release_mem_region(base
->phy_start
,
3329 clk_disable(base
->clk
);
3333 if (base
->lcpa_regulator
) {
3334 regulator_disable(base
->lcpa_regulator
);
3335 regulator_put(base
->lcpa_regulator
);
3338 kfree(base
->lcla_pool
.alloc_map
);
3339 kfree(base
->lookup_log_chans
);
3340 kfree(base
->lookup_phy_chans
);
3341 kfree(base
->phy_res
);
3345 d40_err(&pdev
->dev
, "probe failed\n");
3349 static struct platform_driver d40_driver
= {
3351 .owner
= THIS_MODULE
,
3357 static int __init
stedma40_init(void)
3359 return platform_driver_probe(&d40_driver
, d40_probe
);
3361 subsys_initcall(stedma40_init
);