2 * driver/dma/ste_dma40.c
4 * Copyright (C) ST-Ericsson 2007-2010
5 * License terms: GNU General Public License (GPL) version 2
6 * Author: Per Friden <per.friden@stericsson.com>
7 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
18 #include <plat/ste_dma40.h>
20 #include "ste_dma40_ll.h"
22 #define D40_NAME "dma40"
24 #define D40_PHY_CHAN -1
26 /* For masking out/in 2 bit channel positions */
27 #define D40_CHAN_POS(chan) (2 * (chan / 2))
28 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
30 /* Maximum iterations taken before giving up suspending a channel */
31 #define D40_SUSPEND_MAX_IT 500
33 #define D40_ALLOC_FREE (1 << 31)
34 #define D40_ALLOC_PHY (1 << 30)
35 #define D40_ALLOC_LOG_FREE 0
37 /* Hardware designer of the block */
38 #define D40_PERIPHID2_DESIGNER 0x8
41 * enum 40_command - The different commands and/or statuses.
43 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
44 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
45 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
46 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
51 D40_DMA_SUSPEND_REQ
= 2,
56 * struct d40_lli_pool - Structure for keeping LLIs in memory
58 * @base: Pointer to memory area when the pre_alloc_lli's are not large
59 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
60 * pre_alloc_lli is used.
61 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
62 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
63 * one buffer to one buffer.
68 /* Space for dst and src, plus an extra for padding */
69 u8 pre_alloc_lli
[3 * sizeof(struct d40_phy_lli
)];
73 * struct d40_desc - A descriptor is one DMA job.
75 * @lli_phy: LLI settings for physical channel. Both src and dst=
76 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
78 * @lli_log: Same as above but for logical channels.
79 * @lli_pool: The pool with two entries pre-allocated.
80 * @lli_len: Number of llis of current descriptor.
81 * @lli_count: Number of transfered llis.
82 * @lli_tx_len: Max number of LLIs per transfer, there can be
83 * many transfer for one descriptor.
84 * @txd: DMA engine struct. Used for among other things for communication
87 * @dir: The transfer direction of this job.
88 * @is_in_client_list: true if the client owns this descriptor.
90 * This descriptor is used for both logical and physical transfers.
95 struct d40_phy_lli_bidir lli_phy
;
97 struct d40_log_lli_bidir lli_log
;
99 struct d40_lli_pool lli_pool
;
104 struct dma_async_tx_descriptor txd
;
105 struct list_head node
;
107 enum dma_data_direction dir
;
108 bool is_in_client_list
;
112 * struct d40_lcla_pool - LCLA pool settings and data.
114 * @base: The virtual address of LCLA.
115 * @phy: Physical base address of LCLA.
116 * @base_size: size of lcla.
117 * @lock: Lock to protect the content in this struct.
118 * @alloc_map: Mapping between physical channel and LCLA entries.
119 * @num_blocks: The number of entries of alloc_map. Equals to the
120 * number of physical channels.
122 struct d40_lcla_pool
{
125 resource_size_t base_size
;
132 * struct d40_phy_res - struct for handling eventlines mapped to physical
135 * @lock: A lock protection this entity.
136 * @num: The physical channel number of this entity.
137 * @allocated_src: Bit mapped to show which src event line's are mapped to
138 * this physical channel. Can also be free or physically allocated.
139 * @allocated_dst: Same as for src but is dst.
140 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
141 * event line number. Both allocated_src and allocated_dst can not be
142 * allocated to a physical channel, since the interrupt handler has then
143 * no way of figure out which one the interrupt belongs to.
155 * struct d40_chan - Struct that describes a channel.
157 * @lock: A spinlock to protect this struct.
158 * @log_num: The logical number, if any of this channel.
159 * @completed: Starts with 1, after first interrupt it is set to dma engine's
161 * @pending_tx: The number of pending transfers. Used between interrupt handler
163 * @busy: Set to true when transfer is ongoing on this channel.
164 * @phy_chan: Pointer to physical channel which this instance runs on.
165 * @chan: DMA engine handle.
166 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
167 * transfer and call client callback.
168 * @client: Cliented owned descriptor list.
169 * @active: Active descriptor.
170 * @queue: Queued jobs.
171 * @dma_cfg: The client configuration of this dma channel.
172 * @base: Pointer to the device instance struct.
173 * @src_def_cfg: Default cfg register setting for src.
174 * @dst_def_cfg: Default cfg register setting for dst.
175 * @log_def: Default logical channel settings.
176 * @lcla: Space for one dst src pair for logical channel transfers.
177 * @lcpa: Pointer to dst and src lcpa settings.
179 * This struct can either "be" a logical or a physical channel.
184 /* ID of the most recent completed transfer */
188 struct d40_phy_res
*phy_chan
;
189 struct dma_chan chan
;
190 struct tasklet_struct tasklet
;
191 struct list_head client
;
192 struct list_head active
;
193 struct list_head queue
;
194 struct stedma40_chan_cfg dma_cfg
;
195 struct d40_base
*base
;
196 /* Default register configurations */
199 struct d40_def_lcsp log_def
;
200 struct d40_lcla_elem lcla
;
201 struct d40_log_lli_full
*lcpa
;
205 * struct d40_base - The big global struct, one for each probe'd instance.
207 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
208 * @execmd_lock: Lock for execute command usage since several channels share
209 * the same physical register.
210 * @dev: The device structure.
211 * @virtbase: The virtual base address of the DMA's register.
212 * @clk: Pointer to the DMA clock structure.
213 * @phy_start: Physical memory start of the DMA registers.
214 * @phy_size: Size of the DMA register map.
215 * @irq: The IRQ number.
216 * @num_phy_chans: The number of physical channels. Read from HW. This
217 * is the number of available channels for this driver, not counting "Secure
218 * mode" allocated physical channels.
219 * @num_log_chans: The number of logical channels. Calculated from
221 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
222 * @dma_slave: dma_device channels that can do only do slave transfers.
223 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
224 * @phy_chans: Room for all possible physical channels in system.
225 * @log_chans: Room for all possible logical channels in system.
226 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
227 * to log_chans entries.
228 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
229 * to phy_chans entries.
230 * @plat_data: Pointer to provided platform_data which is the driver
232 * @phy_res: Vector containing all physical channels.
233 * @lcla_pool: lcla pool settings and data.
234 * @lcpa_base: The virtual mapped address of LCPA.
235 * @phy_lcpa: The physical address of the LCPA.
236 * @lcpa_size: The size of the LCPA area.
237 * @desc_slab: cache for descriptors.
240 spinlock_t interrupt_lock
;
241 spinlock_t execmd_lock
;
243 void __iomem
*virtbase
;
245 phys_addr_t phy_start
;
246 resource_size_t phy_size
;
250 struct dma_device dma_both
;
251 struct dma_device dma_slave
;
252 struct dma_device dma_memcpy
;
253 struct d40_chan
*phy_chans
;
254 struct d40_chan
*log_chans
;
255 struct d40_chan
**lookup_log_chans
;
256 struct d40_chan
**lookup_phy_chans
;
257 struct stedma40_platform_data
*plat_data
;
258 /* Physical half channels */
259 struct d40_phy_res
*phy_res
;
260 struct d40_lcla_pool lcla_pool
;
263 resource_size_t lcpa_size
;
264 struct kmem_cache
*desc_slab
;
268 * struct d40_interrupt_lookup - lookup table for interrupt handler
270 * @src: Interrupt mask register.
271 * @clr: Interrupt clear register.
272 * @is_error: true if this is an error interrupt.
273 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
274 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
276 struct d40_interrupt_lookup
{
284 * struct d40_reg_val - simple lookup struct
286 * @reg: The register.
287 * @val: The value that belongs to the register in reg.
294 static int d40_pool_lli_alloc(struct d40_desc
*d40d
,
295 int lli_len
, bool is_log
)
301 align
= sizeof(struct d40_log_lli
);
303 align
= sizeof(struct d40_phy_lli
);
306 base
= d40d
->lli_pool
.pre_alloc_lli
;
307 d40d
->lli_pool
.size
= sizeof(d40d
->lli_pool
.pre_alloc_lli
);
308 d40d
->lli_pool
.base
= NULL
;
310 d40d
->lli_pool
.size
= ALIGN(lli_len
* 2 * align
, align
);
312 base
= kmalloc(d40d
->lli_pool
.size
+ align
, GFP_NOWAIT
);
313 d40d
->lli_pool
.base
= base
;
315 if (d40d
->lli_pool
.base
== NULL
)
320 d40d
->lli_log
.src
= PTR_ALIGN((struct d40_log_lli
*) base
,
322 d40d
->lli_log
.dst
= PTR_ALIGN(d40d
->lli_log
.src
+ lli_len
,
325 d40d
->lli_phy
.src
= PTR_ALIGN((struct d40_phy_lli
*)base
,
327 d40d
->lli_phy
.dst
= PTR_ALIGN(d40d
->lli_phy
.src
+ lli_len
,
330 d40d
->lli_phy
.src_addr
= virt_to_phys(d40d
->lli_phy
.src
);
331 d40d
->lli_phy
.dst_addr
= virt_to_phys(d40d
->lli_phy
.dst
);
337 static void d40_pool_lli_free(struct d40_desc
*d40d
)
339 kfree(d40d
->lli_pool
.base
);
340 d40d
->lli_pool
.base
= NULL
;
341 d40d
->lli_pool
.size
= 0;
342 d40d
->lli_log
.src
= NULL
;
343 d40d
->lli_log
.dst
= NULL
;
344 d40d
->lli_phy
.src
= NULL
;
345 d40d
->lli_phy
.dst
= NULL
;
346 d40d
->lli_phy
.src_addr
= 0;
347 d40d
->lli_phy
.dst_addr
= 0;
350 static dma_cookie_t
d40_assign_cookie(struct d40_chan
*d40c
,
351 struct d40_desc
*desc
)
353 dma_cookie_t cookie
= d40c
->chan
.cookie
;
358 d40c
->chan
.cookie
= cookie
;
359 desc
->txd
.cookie
= cookie
;
364 static void d40_desc_remove(struct d40_desc
*d40d
)
366 list_del(&d40d
->node
);
369 static struct d40_desc
*d40_desc_get(struct d40_chan
*d40c
)
374 if (!list_empty(&d40c
->client
)) {
375 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
)
376 if (async_tx_test_ack(&d
->txd
)) {
377 d40_pool_lli_free(d
);
382 d
= kmem_cache_alloc(d40c
->base
->desc_slab
, GFP_NOWAIT
);
384 memset(d
, 0, sizeof(struct d40_desc
));
385 INIT_LIST_HEAD(&d
->node
);
391 static void d40_desc_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
393 kmem_cache_free(d40c
->base
->desc_slab
, d40d
);
396 static void d40_desc_submit(struct d40_chan
*d40c
, struct d40_desc
*desc
)
398 list_add_tail(&desc
->node
, &d40c
->active
);
401 static struct d40_desc
*d40_first_active_get(struct d40_chan
*d40c
)
405 if (list_empty(&d40c
->active
))
408 d
= list_first_entry(&d40c
->active
,
414 static void d40_desc_queue(struct d40_chan
*d40c
, struct d40_desc
*desc
)
416 list_add_tail(&desc
->node
, &d40c
->queue
);
419 static struct d40_desc
*d40_first_queued(struct d40_chan
*d40c
)
423 if (list_empty(&d40c
->queue
))
426 d
= list_first_entry(&d40c
->queue
,
432 /* Support functions for logical channels */
434 static int d40_lcla_id_get(struct d40_chan
*d40c
,
435 struct d40_lcla_pool
*pool
)
439 struct d40_log_lli
*lcla_lidx_base
=
440 pool
->base
+ d40c
->phy_chan
->num
* 1024;
442 int lli_per_log
= d40c
->base
->plat_data
->llis_per_log
;
444 if (d40c
->lcla
.src_id
>= 0 && d40c
->lcla
.dst_id
>= 0)
447 if (pool
->num_blocks
> 32)
450 spin_lock(&pool
->lock
);
452 for (i
= 0; i
< pool
->num_blocks
; i
++) {
453 if (!(pool
->alloc_map
[d40c
->phy_chan
->num
] & (0x1 << i
))) {
454 pool
->alloc_map
[d40c
->phy_chan
->num
] |= (0x1 << i
);
459 if (src_id
>= pool
->num_blocks
)
462 for (; i
< pool
->num_blocks
; i
++) {
463 if (!(pool
->alloc_map
[d40c
->phy_chan
->num
] & (0x1 << i
))) {
464 pool
->alloc_map
[d40c
->phy_chan
->num
] |= (0x1 << i
);
470 if (dst_id
== src_id
)
473 d40c
->lcla
.src_id
= src_id
;
474 d40c
->lcla
.dst_id
= dst_id
;
475 d40c
->lcla
.dst
= lcla_lidx_base
+ dst_id
* lli_per_log
+ 1;
476 d40c
->lcla
.src
= lcla_lidx_base
+ src_id
* lli_per_log
+ 1;
479 spin_unlock(&pool
->lock
);
482 spin_unlock(&pool
->lock
);
486 static void d40_lcla_id_put(struct d40_chan
*d40c
,
487 struct d40_lcla_pool
*pool
,
493 d40c
->lcla
.src_id
= -1;
494 d40c
->lcla
.dst_id
= -1;
496 spin_lock(&pool
->lock
);
497 pool
->alloc_map
[d40c
->phy_chan
->num
] &= (~(0x1 << id
));
498 spin_unlock(&pool
->lock
);
501 static int d40_channel_execute_command(struct d40_chan
*d40c
,
502 enum d40_command command
)
505 void __iomem
*active_reg
;
509 spin_lock_irqsave(&d40c
->base
->execmd_lock
, flags
);
511 if (d40c
->phy_chan
->num
% 2 == 0)
512 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
514 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
516 if (command
== D40_DMA_SUSPEND_REQ
) {
517 status
= (readl(active_reg
) &
518 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
519 D40_CHAN_POS(d40c
->phy_chan
->num
);
521 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
525 writel(command
<< D40_CHAN_POS(d40c
->phy_chan
->num
), active_reg
);
527 if (command
== D40_DMA_SUSPEND_REQ
) {
529 for (i
= 0 ; i
< D40_SUSPEND_MAX_IT
; i
++) {
530 status
= (readl(active_reg
) &
531 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
532 D40_CHAN_POS(d40c
->phy_chan
->num
);
536 * Reduce the number of bus accesses while
537 * waiting for the DMA to suspend.
541 if (status
== D40_DMA_STOP
||
542 status
== D40_DMA_SUSPENDED
)
546 if (i
== D40_SUSPEND_MAX_IT
) {
547 dev_err(&d40c
->chan
.dev
->device
,
548 "[%s]: unable to suspend the chl %d (log: %d) status %x\n",
549 __func__
, d40c
->phy_chan
->num
, d40c
->log_num
,
557 spin_unlock_irqrestore(&d40c
->base
->execmd_lock
, flags
);
561 static void d40_term_all(struct d40_chan
*d40c
)
563 struct d40_desc
*d40d
;
565 /* Release active descriptors */
566 while ((d40d
= d40_first_active_get(d40c
))) {
567 d40_desc_remove(d40d
);
569 /* Return desc to free-list */
570 d40_desc_free(d40c
, d40d
);
573 /* Release queued descriptors waiting for transfer */
574 while ((d40d
= d40_first_queued(d40c
))) {
575 d40_desc_remove(d40d
);
577 /* Return desc to free-list */
578 d40_desc_free(d40c
, d40d
);
581 d40_lcla_id_put(d40c
, &d40c
->base
->lcla_pool
,
583 d40_lcla_id_put(d40c
, &d40c
->base
->lcla_pool
,
586 d40c
->pending_tx
= 0;
590 static void d40_config_set_event(struct d40_chan
*d40c
, bool do_enable
)
596 val
= D40_ACTIVATE_EVENTLINE
;
598 val
= D40_DEACTIVATE_EVENTLINE
;
600 spin_lock_irqsave(&d40c
->phy_chan
->lock
, flags
);
602 /* Enable event line connected to device (or memcpy) */
603 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
604 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
)) {
605 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
607 writel((val
<< D40_EVENTLINE_POS(event
)) |
608 ~D40_EVENTLINE_MASK(event
),
609 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
610 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
613 if (d40c
->dma_cfg
.dir
!= STEDMA40_PERIPH_TO_MEM
) {
614 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
616 writel((val
<< D40_EVENTLINE_POS(event
)) |
617 ~D40_EVENTLINE_MASK(event
),
618 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
619 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
623 spin_unlock_irqrestore(&d40c
->phy_chan
->lock
, flags
);
626 static u32
d40_chan_has_events(struct d40_chan
*d40c
)
630 /* If SSLNK or SDLNK is zero all events are disabled */
631 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
632 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
633 val
= readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
634 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
637 if (d40c
->dma_cfg
.dir
!= STEDMA40_PERIPH_TO_MEM
)
638 val
= readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
639 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
644 static void d40_config_enable_lidx(struct d40_chan
*d40c
)
646 /* Set LIDX for lcla */
647 writel((d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
) &
648 D40_SREG_ELEM_LOG_LIDX_MASK
,
649 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
650 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+ D40_CHAN_REG_SDELT
);
652 writel((d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
) &
653 D40_SREG_ELEM_LOG_LIDX_MASK
,
654 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
655 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+ D40_CHAN_REG_SSELT
);
658 static int d40_config_write(struct d40_chan
*d40c
)
664 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
668 /* Odd addresses are even addresses + 4 */
669 addr_base
= (d40c
->phy_chan
->num
% 2) * 4;
670 /* Setup channel mode to logical or physical */
671 var
= ((u32
)(d40c
->log_num
!= D40_PHY_CHAN
) + 1) <<
672 D40_CHAN_POS(d40c
->phy_chan
->num
);
673 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMSE
+ addr_base
);
675 /* Setup operational mode option register */
676 var
= ((d40c
->dma_cfg
.channel_type
>> STEDMA40_INFO_CH_MODE_OPT_POS
) &
677 0x3) << D40_CHAN_POS(d40c
->phy_chan
->num
);
679 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMOE
+ addr_base
);
681 if (d40c
->log_num
!= D40_PHY_CHAN
) {
682 /* Set default config for CFG reg */
683 writel(d40c
->src_def_cfg
,
684 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
685 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
687 writel(d40c
->dst_def_cfg
,
688 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
689 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
692 d40_config_enable_lidx(d40c
);
697 static void d40_desc_load(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
700 if (d40d
->lli_phy
.dst
&& d40d
->lli_phy
.src
) {
701 d40_phy_lli_write(d40c
->base
->virtbase
,
705 } else if (d40d
->lli_log
.dst
&& d40d
->lli_log
.src
) {
706 struct d40_log_lli
*src
= d40d
->lli_log
.src
;
707 struct d40_log_lli
*dst
= d40d
->lli_log
.dst
;
709 src
+= d40d
->lli_count
;
710 dst
+= d40d
->lli_count
;
711 d40_log_lli_write(d40c
->lcpa
, d40c
->lcla
.src
,
714 d40c
->base
->plat_data
->llis_per_log
);
716 d40d
->lli_count
+= d40d
->lli_tx_len
;
719 static dma_cookie_t
d40_tx_submit(struct dma_async_tx_descriptor
*tx
)
721 struct d40_chan
*d40c
= container_of(tx
->chan
,
724 struct d40_desc
*d40d
= container_of(tx
, struct d40_desc
, txd
);
727 spin_lock_irqsave(&d40c
->lock
, flags
);
729 tx
->cookie
= d40_assign_cookie(d40c
, d40d
);
731 d40_desc_queue(d40c
, d40d
);
733 spin_unlock_irqrestore(&d40c
->lock
, flags
);
738 static int d40_start(struct d40_chan
*d40c
)
742 if (d40c
->log_num
!= D40_PHY_CHAN
) {
743 err
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
746 d40_config_set_event(d40c
, true);
749 err
= d40_channel_execute_command(d40c
, D40_DMA_RUN
);
754 static struct d40_desc
*d40_queue_start(struct d40_chan
*d40c
)
756 struct d40_desc
*d40d
;
759 /* Start queued jobs, if any */
760 d40d
= d40_first_queued(d40c
);
765 /* Remove from queue */
766 d40_desc_remove(d40d
);
768 /* Add to active queue */
769 d40_desc_submit(d40c
, d40d
);
771 /* Initiate DMA job */
772 d40_desc_load(d40c
, d40d
);
775 err
= d40_start(d40c
);
784 /* called from interrupt context */
785 static void dma_tc_handle(struct d40_chan
*d40c
)
787 struct d40_desc
*d40d
;
792 /* Get first active entry from list */
793 d40d
= d40_first_active_get(d40c
);
798 if (d40d
->lli_count
< d40d
->lli_len
) {
800 d40_desc_load(d40c
, d40d
);
802 (void) d40_start(d40c
);
806 if (d40_queue_start(d40c
) == NULL
)
810 tasklet_schedule(&d40c
->tasklet
);
814 static void dma_tasklet(unsigned long data
)
816 struct d40_chan
*d40c
= (struct d40_chan
*) data
;
817 struct d40_desc
*d40d_fin
;
819 dma_async_tx_callback callback
;
820 void *callback_param
;
822 spin_lock_irqsave(&d40c
->lock
, flags
);
824 /* Get first active entry from list */
825 d40d_fin
= d40_first_active_get(d40c
);
827 if (d40d_fin
== NULL
)
830 d40c
->completed
= d40d_fin
->txd
.cookie
;
833 * If terminating a channel pending_tx is set to zero.
834 * This prevents any finished active jobs to return to the client.
836 if (d40c
->pending_tx
== 0) {
837 spin_unlock_irqrestore(&d40c
->lock
, flags
);
841 /* Callback to client */
842 callback
= d40d_fin
->txd
.callback
;
843 callback_param
= d40d_fin
->txd
.callback_param
;
845 if (async_tx_test_ack(&d40d_fin
->txd
)) {
846 d40_pool_lli_free(d40d_fin
);
847 d40_desc_remove(d40d_fin
);
848 /* Return desc to free-list */
849 d40_desc_free(d40c
, d40d_fin
);
851 if (!d40d_fin
->is_in_client_list
) {
852 d40_desc_remove(d40d_fin
);
853 list_add_tail(&d40d_fin
->node
, &d40c
->client
);
854 d40d_fin
->is_in_client_list
= true;
860 if (d40c
->pending_tx
)
861 tasklet_schedule(&d40c
->tasklet
);
863 spin_unlock_irqrestore(&d40c
->lock
, flags
);
866 callback(callback_param
);
871 /* Rescue manouver if receiving double interrupts */
872 if (d40c
->pending_tx
> 0)
874 spin_unlock_irqrestore(&d40c
->lock
, flags
);
877 static irqreturn_t
d40_handle_interrupt(int irq
, void *data
)
879 static const struct d40_interrupt_lookup il
[] = {
880 {D40_DREG_LCTIS0
, D40_DREG_LCICR0
, false, 0},
881 {D40_DREG_LCTIS1
, D40_DREG_LCICR1
, false, 32},
882 {D40_DREG_LCTIS2
, D40_DREG_LCICR2
, false, 64},
883 {D40_DREG_LCTIS3
, D40_DREG_LCICR3
, false, 96},
884 {D40_DREG_LCEIS0
, D40_DREG_LCICR0
, true, 0},
885 {D40_DREG_LCEIS1
, D40_DREG_LCICR1
, true, 32},
886 {D40_DREG_LCEIS2
, D40_DREG_LCICR2
, true, 64},
887 {D40_DREG_LCEIS3
, D40_DREG_LCICR3
, true, 96},
888 {D40_DREG_PCTIS
, D40_DREG_PCICR
, false, D40_PHY_CHAN
},
889 {D40_DREG_PCEIS
, D40_DREG_PCICR
, true, D40_PHY_CHAN
},
893 u32 regs
[ARRAY_SIZE(il
)];
898 struct d40_chan
*d40c
;
900 struct d40_base
*base
= data
;
902 spin_lock_irqsave(&base
->interrupt_lock
, flags
);
904 /* Read interrupt status of both logical and physical channels */
905 for (i
= 0; i
< ARRAY_SIZE(il
); i
++)
906 regs
[i
] = readl(base
->virtbase
+ il
[i
].src
);
910 chan
= find_next_bit((unsigned long *)regs
,
911 BITS_PER_LONG
* ARRAY_SIZE(il
), chan
+ 1);
913 /* No more set bits found? */
914 if (chan
== BITS_PER_LONG
* ARRAY_SIZE(il
))
917 row
= chan
/ BITS_PER_LONG
;
918 idx
= chan
& (BITS_PER_LONG
- 1);
921 tmp
= readl(base
->virtbase
+ il
[row
].clr
);
923 writel(tmp
, base
->virtbase
+ il
[row
].clr
);
925 if (il
[row
].offset
== D40_PHY_CHAN
)
926 d40c
= base
->lookup_phy_chans
[idx
];
928 d40c
= base
->lookup_log_chans
[il
[row
].offset
+ idx
];
929 spin_lock(&d40c
->lock
);
931 if (!il
[row
].is_error
)
934 dev_err(base
->dev
, "[%s] IRQ chan: %ld offset %d idx %d\n",
935 __func__
, chan
, il
[row
].offset
, idx
);
937 spin_unlock(&d40c
->lock
);
940 spin_unlock_irqrestore(&base
->interrupt_lock
, flags
);
946 static int d40_validate_conf(struct d40_chan
*d40c
,
947 struct stedma40_chan_cfg
*conf
)
950 u32 dst_event_group
= D40_TYPE_TO_GROUP(conf
->dst_dev_type
);
951 u32 src_event_group
= D40_TYPE_TO_GROUP(conf
->src_dev_type
);
952 bool is_log
= (conf
->channel_type
& STEDMA40_CHANNEL_IN_OPER_MODE
)
953 == STEDMA40_CHANNEL_IN_LOG_MODE
;
955 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
&&
956 dst_event_group
== STEDMA40_DEV_DST_MEMORY
) {
957 dev_err(&d40c
->chan
.dev
->device
, "[%s] Invalid dst\n",
962 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
&&
963 src_event_group
== STEDMA40_DEV_SRC_MEMORY
) {
964 dev_err(&d40c
->chan
.dev
->device
, "[%s] Invalid src\n",
969 if (src_event_group
== STEDMA40_DEV_SRC_MEMORY
&&
970 dst_event_group
== STEDMA40_DEV_DST_MEMORY
&& is_log
) {
971 dev_err(&d40c
->chan
.dev
->device
,
972 "[%s] No event line\n", __func__
);
976 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
&&
977 (src_event_group
!= dst_event_group
)) {
978 dev_err(&d40c
->chan
.dev
->device
,
979 "[%s] Invalid event group\n", __func__
);
983 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
) {
985 * DMAC HW supports it. Will be added to this driver,
986 * in case any dma client requires it.
988 dev_err(&d40c
->chan
.dev
->device
,
989 "[%s] periph to periph not supported\n",
997 static bool d40_alloc_mask_set(struct d40_phy_res
*phy
, bool is_src
,
998 int log_event_line
, bool is_log
)
1000 unsigned long flags
;
1001 spin_lock_irqsave(&phy
->lock
, flags
);
1003 /* Physical interrupts are masked per physical full channel */
1004 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1005 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1006 phy
->allocated_dst
= D40_ALLOC_PHY
;
1007 phy
->allocated_src
= D40_ALLOC_PHY
;
1013 /* Logical channel */
1015 if (phy
->allocated_src
== D40_ALLOC_PHY
)
1018 if (phy
->allocated_src
== D40_ALLOC_FREE
)
1019 phy
->allocated_src
= D40_ALLOC_LOG_FREE
;
1021 if (!(phy
->allocated_src
& (1 << log_event_line
))) {
1022 phy
->allocated_src
|= 1 << log_event_line
;
1027 if (phy
->allocated_dst
== D40_ALLOC_PHY
)
1030 if (phy
->allocated_dst
== D40_ALLOC_FREE
)
1031 phy
->allocated_dst
= D40_ALLOC_LOG_FREE
;
1033 if (!(phy
->allocated_dst
& (1 << log_event_line
))) {
1034 phy
->allocated_dst
|= 1 << log_event_line
;
1041 spin_unlock_irqrestore(&phy
->lock
, flags
);
1044 spin_unlock_irqrestore(&phy
->lock
, flags
);
1048 static bool d40_alloc_mask_free(struct d40_phy_res
*phy
, bool is_src
,
1051 unsigned long flags
;
1052 bool is_free
= false;
1054 spin_lock_irqsave(&phy
->lock
, flags
);
1055 if (!log_event_line
) {
1056 /* Physical interrupts are masked per physical full channel */
1057 phy
->allocated_dst
= D40_ALLOC_FREE
;
1058 phy
->allocated_src
= D40_ALLOC_FREE
;
1063 /* Logical channel */
1065 phy
->allocated_src
&= ~(1 << log_event_line
);
1066 if (phy
->allocated_src
== D40_ALLOC_LOG_FREE
)
1067 phy
->allocated_src
= D40_ALLOC_FREE
;
1069 phy
->allocated_dst
&= ~(1 << log_event_line
);
1070 if (phy
->allocated_dst
== D40_ALLOC_LOG_FREE
)
1071 phy
->allocated_dst
= D40_ALLOC_FREE
;
1074 is_free
= ((phy
->allocated_src
| phy
->allocated_dst
) ==
1078 spin_unlock_irqrestore(&phy
->lock
, flags
);
1083 static int d40_allocate_channel(struct d40_chan
*d40c
)
1088 struct d40_phy_res
*phys
;
1093 bool is_log
= (d40c
->dma_cfg
.channel_type
& STEDMA40_CHANNEL_IN_OPER_MODE
)
1094 == STEDMA40_CHANNEL_IN_LOG_MODE
;
1097 phys
= d40c
->base
->phy_res
;
1099 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1100 dev_type
= d40c
->dma_cfg
.src_dev_type
;
1101 log_num
= 2 * dev_type
;
1103 } else if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1104 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1105 /* dst event lines are used for logical memcpy */
1106 dev_type
= d40c
->dma_cfg
.dst_dev_type
;
1107 log_num
= 2 * dev_type
+ 1;
1112 event_group
= D40_TYPE_TO_GROUP(dev_type
);
1113 event_line
= D40_TYPE_TO_EVENT(dev_type
);
1116 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1117 /* Find physical half channel */
1118 for (i
= 0; i
< d40c
->base
->num_phy_chans
; i
++) {
1120 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1125 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1126 int phy_num
= j
+ event_group
* 2;
1127 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1128 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1135 d40c
->phy_chan
= &phys
[i
];
1136 d40c
->log_num
= D40_PHY_CHAN
;
1142 /* Find logical channel */
1143 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1144 int phy_num
= j
+ event_group
* 2;
1146 * Spread logical channels across all available physical rather
1147 * than pack every logical channel at the first available phy
1151 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1152 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1153 event_line
, is_log
))
1157 for (i
= phy_num
+ 1; i
>= phy_num
; i
--) {
1158 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1159 event_line
, is_log
))
1167 d40c
->phy_chan
= &phys
[i
];
1168 d40c
->log_num
= log_num
;
1172 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = d40c
;
1174 d40c
->base
->lookup_phy_chans
[d40c
->phy_chan
->num
] = d40c
;
1180 static int d40_config_memcpy(struct d40_chan
*d40c
)
1182 dma_cap_mask_t cap
= d40c
->chan
.device
->cap_mask
;
1184 if (dma_has_cap(DMA_MEMCPY
, cap
) && !dma_has_cap(DMA_SLAVE
, cap
)) {
1185 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_log
;
1186 d40c
->dma_cfg
.src_dev_type
= STEDMA40_DEV_SRC_MEMORY
;
1187 d40c
->dma_cfg
.dst_dev_type
= d40c
->base
->plat_data
->
1188 memcpy
[d40c
->chan
.chan_id
];
1190 } else if (dma_has_cap(DMA_MEMCPY
, cap
) &&
1191 dma_has_cap(DMA_SLAVE
, cap
)) {
1192 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_phy
;
1194 dev_err(&d40c
->chan
.dev
->device
, "[%s] No memcpy\n",
1203 static int d40_free_dma(struct d40_chan
*d40c
)
1208 struct d40_phy_res
*phy
= d40c
->phy_chan
;
1211 struct d40_desc
*_d
;
1214 /* Terminate all queued and active transfers */
1217 /* Release client owned descriptors */
1218 if (!list_empty(&d40c
->client
))
1219 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
) {
1220 d40_pool_lli_free(d
);
1222 /* Return desc to free-list */
1223 d40_desc_free(d40c
, d
);
1227 dev_err(&d40c
->chan
.dev
->device
, "[%s] phy == null\n",
1232 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1233 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1234 dev_err(&d40c
->chan
.dev
->device
, "[%s] channel already free\n",
1240 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1242 dev_err(&d40c
->chan
.dev
->device
, "[%s] suspend failed\n",
1247 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1248 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1249 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1250 dir
= D40_CHAN_REG_SDLNK
;
1252 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1253 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1254 dir
= D40_CHAN_REG_SSLNK
;
1257 dev_err(&d40c
->chan
.dev
->device
,
1258 "[%s] Unknown direction\n", __func__
);
1262 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1264 * Release logical channel, deactivate the event line during
1265 * the time physical res is suspended.
1267 writel((D40_DEACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
)) &
1268 D40_EVENTLINE_MASK(event
),
1269 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
1270 phy
->num
* D40_DREG_PCDELTA
+ dir
);
1272 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = NULL
;
1275 * Check if there are more logical allocation
1276 * on this phy channel.
1278 if (!d40_alloc_mask_free(phy
, is_src
, event
)) {
1279 /* Resume the other logical channels if any */
1280 if (d40_chan_has_events(d40c
)) {
1281 res
= d40_channel_execute_command(d40c
,
1284 dev_err(&d40c
->chan
.dev
->device
,
1285 "[%s] Executing RUN command\n",
1293 d40_alloc_mask_free(phy
, is_src
, 0);
1295 /* Release physical channel */
1296 res
= d40_channel_execute_command(d40c
, D40_DMA_STOP
);
1298 dev_err(&d40c
->chan
.dev
->device
,
1299 "[%s] Failed to stop channel\n", __func__
);
1302 d40c
->phy_chan
= NULL
;
1303 /* Invalidate channel type */
1304 d40c
->dma_cfg
.channel_type
= 0;
1305 d40c
->base
->lookup_phy_chans
[phy
->num
] = NULL
;
1312 static int d40_pause(struct dma_chan
*chan
)
1314 struct d40_chan
*d40c
=
1315 container_of(chan
, struct d40_chan
, chan
);
1318 unsigned long flags
;
1320 spin_lock_irqsave(&d40c
->lock
, flags
);
1322 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1324 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1325 d40_config_set_event(d40c
, false);
1326 /* Resume the other logical channels if any */
1327 if (d40_chan_has_events(d40c
))
1328 res
= d40_channel_execute_command(d40c
,
1333 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1337 static bool d40_is_paused(struct d40_chan
*d40c
)
1339 bool is_paused
= false;
1340 unsigned long flags
;
1341 void __iomem
*active_reg
;
1346 spin_lock_irqsave(&d40c
->lock
, flags
);
1348 if (d40c
->log_num
== D40_PHY_CHAN
) {
1349 if (d40c
->phy_chan
->num
% 2 == 0)
1350 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
1352 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
1354 status
= (readl(active_reg
) &
1355 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
1356 D40_CHAN_POS(d40c
->phy_chan
->num
);
1357 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
1363 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1367 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1368 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
)
1369 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1370 else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
1371 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1373 dev_err(&d40c
->chan
.dev
->device
,
1374 "[%s] Unknown direction\n", __func__
);
1377 status
= d40_chan_has_events(d40c
);
1378 status
= (status
& D40_EVENTLINE_MASK(event
)) >>
1379 D40_EVENTLINE_POS(event
);
1381 if (status
!= D40_DMA_RUN
)
1384 /* Resume the other logical channels if any */
1385 if (d40_chan_has_events(d40c
))
1386 res
= d40_channel_execute_command(d40c
,
1390 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1396 static bool d40_tx_is_linked(struct d40_chan
*d40c
)
1400 if (d40c
->log_num
!= D40_PHY_CHAN
)
1401 is_link
= readl(&d40c
->lcpa
->lcsp3
) & D40_MEM_LCSP3_DLOS_MASK
;
1403 is_link
= readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
1404 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
1405 D40_CHAN_REG_SDLNK
) &
1406 D40_SREG_LNK_PHYS_LNK_MASK
;
1410 static u32
d40_residue(struct d40_chan
*d40c
)
1414 if (d40c
->log_num
!= D40_PHY_CHAN
)
1415 num_elt
= (readl(&d40c
->lcpa
->lcsp2
) & D40_MEM_LCSP2_ECNT_MASK
)
1416 >> D40_MEM_LCSP2_ECNT_POS
;
1418 num_elt
= (readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
1419 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
1420 D40_CHAN_REG_SDELT
) &
1421 D40_SREG_ELEM_PHY_ECNT_MASK
) >> D40_SREG_ELEM_PHY_ECNT_POS
;
1422 return num_elt
* (1 << d40c
->dma_cfg
.dst_info
.data_width
);
1425 static int d40_resume(struct dma_chan
*chan
)
1427 struct d40_chan
*d40c
=
1428 container_of(chan
, struct d40_chan
, chan
);
1430 unsigned long flags
;
1432 spin_lock_irqsave(&d40c
->lock
, flags
);
1434 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1435 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1439 /* If bytes left to transfer or linked tx resume job */
1440 if (d40_residue(d40c
) || d40_tx_is_linked(d40c
)) {
1441 d40_config_set_event(d40c
, true);
1442 res
= d40_channel_execute_command(d40c
, D40_DMA_RUN
);
1444 } else if (d40_residue(d40c
) || d40_tx_is_linked(d40c
))
1445 res
= d40_channel_execute_command(d40c
, D40_DMA_RUN
);
1448 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1452 static u32
stedma40_residue(struct dma_chan
*chan
)
1454 struct d40_chan
*d40c
=
1455 container_of(chan
, struct d40_chan
, chan
);
1457 unsigned long flags
;
1459 spin_lock_irqsave(&d40c
->lock
, flags
);
1460 bytes_left
= d40_residue(d40c
);
1461 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1466 /* Public DMA functions in addition to the DMA engine framework */
1468 int stedma40_set_psize(struct dma_chan
*chan
,
1472 struct d40_chan
*d40c
=
1473 container_of(chan
, struct d40_chan
, chan
);
1474 unsigned long flags
;
1476 spin_lock_irqsave(&d40c
->lock
, flags
);
1478 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1479 d40c
->log_def
.lcsp1
&= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK
;
1480 d40c
->log_def
.lcsp3
&= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK
;
1481 d40c
->log_def
.lcsp1
|= src_psize
<< D40_MEM_LCSP1_SCFG_PSIZE_POS
;
1482 d40c
->log_def
.lcsp3
|= dst_psize
<< D40_MEM_LCSP1_SCFG_PSIZE_POS
;
1486 if (src_psize
== STEDMA40_PSIZE_PHY_1
)
1487 d40c
->src_def_cfg
&= ~(1 << D40_SREG_CFG_PHY_PEN_POS
);
1489 d40c
->src_def_cfg
|= 1 << D40_SREG_CFG_PHY_PEN_POS
;
1490 d40c
->src_def_cfg
&= ~(STEDMA40_PSIZE_PHY_16
<<
1491 D40_SREG_CFG_PSIZE_POS
);
1492 d40c
->src_def_cfg
|= src_psize
<< D40_SREG_CFG_PSIZE_POS
;
1495 if (dst_psize
== STEDMA40_PSIZE_PHY_1
)
1496 d40c
->dst_def_cfg
&= ~(1 << D40_SREG_CFG_PHY_PEN_POS
);
1498 d40c
->dst_def_cfg
|= 1 << D40_SREG_CFG_PHY_PEN_POS
;
1499 d40c
->dst_def_cfg
&= ~(STEDMA40_PSIZE_PHY_16
<<
1500 D40_SREG_CFG_PSIZE_POS
);
1501 d40c
->dst_def_cfg
|= dst_psize
<< D40_SREG_CFG_PSIZE_POS
;
1504 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1507 EXPORT_SYMBOL(stedma40_set_psize
);
1509 struct dma_async_tx_descriptor
*stedma40_memcpy_sg(struct dma_chan
*chan
,
1510 struct scatterlist
*sgl_dst
,
1511 struct scatterlist
*sgl_src
,
1512 unsigned int sgl_len
,
1513 unsigned long flags
)
1516 struct d40_desc
*d40d
;
1517 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1522 spin_lock_irqsave(&d40c
->lock
, flg
);
1523 d40d
= d40_desc_get(d40c
);
1528 memset(d40d
, 0, sizeof(struct d40_desc
));
1529 d40d
->lli_len
= sgl_len
;
1530 d40d
->lli_tx_len
= d40d
->lli_len
;
1531 d40d
->txd
.flags
= flags
;
1533 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1534 if (d40d
->lli_len
> d40c
->base
->plat_data
->llis_per_log
)
1535 d40d
->lli_tx_len
= d40c
->base
->plat_data
->llis_per_log
;
1539 * Check if there is space available in lcla. If not,
1540 * split list into 1-length and run only in lcpa
1543 if (d40_lcla_id_get(d40c
,
1544 &d40c
->base
->lcla_pool
) != 0)
1545 d40d
->lli_tx_len
= 1;
1547 if (d40_pool_lli_alloc(d40d
, sgl_len
, true) < 0) {
1548 dev_err(&d40c
->chan
.dev
->device
,
1549 "[%s] Out of memory\n", __func__
);
1553 (void) d40_log_sg_to_lli(d40c
->lcla
.src_id
,
1557 d40c
->log_def
.lcsp1
,
1558 d40c
->dma_cfg
.src_info
.data_width
,
1559 flags
& DMA_PREP_INTERRUPT
,
1561 d40c
->base
->plat_data
->llis_per_log
);
1563 (void) d40_log_sg_to_lli(d40c
->lcla
.dst_id
,
1567 d40c
->log_def
.lcsp3
,
1568 d40c
->dma_cfg
.dst_info
.data_width
,
1569 flags
& DMA_PREP_INTERRUPT
,
1571 d40c
->base
->plat_data
->llis_per_log
);
1575 if (d40_pool_lli_alloc(d40d
, sgl_len
, false) < 0) {
1576 dev_err(&d40c
->chan
.dev
->device
,
1577 "[%s] Out of memory\n", __func__
);
1581 res
= d40_phy_sg_to_lli(sgl_src
,
1585 d40d
->lli_phy
.src_addr
,
1587 d40c
->dma_cfg
.src_info
.data_width
,
1588 d40c
->dma_cfg
.src_info
.psize
,
1594 res
= d40_phy_sg_to_lli(sgl_dst
,
1598 d40d
->lli_phy
.dst_addr
,
1600 d40c
->dma_cfg
.dst_info
.data_width
,
1601 d40c
->dma_cfg
.dst_info
.psize
,
1607 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
1608 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1611 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1613 d40d
->txd
.tx_submit
= d40_tx_submit
;
1615 spin_unlock_irqrestore(&d40c
->lock
, flg
);
1619 spin_unlock_irqrestore(&d40c
->lock
, flg
);
1622 EXPORT_SYMBOL(stedma40_memcpy_sg
);
1624 bool stedma40_filter(struct dma_chan
*chan
, void *data
)
1626 struct stedma40_chan_cfg
*info
= data
;
1627 struct d40_chan
*d40c
=
1628 container_of(chan
, struct d40_chan
, chan
);
1632 err
= d40_validate_conf(d40c
, info
);
1634 d40c
->dma_cfg
= *info
;
1636 err
= d40_config_memcpy(d40c
);
1640 EXPORT_SYMBOL(stedma40_filter
);
1642 /* DMA ENGINE functions */
1643 static int d40_alloc_chan_resources(struct dma_chan
*chan
)
1646 unsigned long flags
;
1647 struct d40_chan
*d40c
=
1648 container_of(chan
, struct d40_chan
, chan
);
1650 spin_lock_irqsave(&d40c
->lock
, flags
);
1652 d40c
->completed
= chan
->cookie
= 1;
1655 * If no dma configuration is set (channel_type == 0)
1656 * use default configuration (memcpy)
1658 if (d40c
->dma_cfg
.channel_type
== 0) {
1659 err
= d40_config_memcpy(d40c
);
1661 dev_err(&d40c
->chan
.dev
->device
,
1662 "[%s] Failed to configure memcpy channel\n",
1667 is_free_phy
= (d40c
->phy_chan
== NULL
);
1669 err
= d40_allocate_channel(d40c
);
1671 dev_err(&d40c
->chan
.dev
->device
,
1672 "[%s] Failed to allocate channel\n", __func__
);
1676 /* Fill in basic CFG register values */
1677 d40_phy_cfg(&d40c
->dma_cfg
, &d40c
->src_def_cfg
,
1678 &d40c
->dst_def_cfg
, d40c
->log_num
!= D40_PHY_CHAN
);
1680 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1681 d40_log_cfg(&d40c
->dma_cfg
,
1682 &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
1684 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
1685 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1686 d40c
->dma_cfg
.src_dev_type
* D40_LCPA_CHAN_SIZE
;
1688 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1689 d40c
->dma_cfg
.dst_dev_type
*
1690 D40_LCPA_CHAN_SIZE
+ D40_LCPA_CHAN_DST_DELTA
;
1694 * Only write channel configuration to the DMA if the physical
1695 * resource is free. In case of multiple logical channels
1696 * on the same physical resource, only the first write is necessary.
1699 err
= d40_config_write(d40c
);
1701 dev_err(&d40c
->chan
.dev
->device
,
1702 "[%s] Failed to configure channel\n",
1707 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1711 static void d40_free_chan_resources(struct dma_chan
*chan
)
1713 struct d40_chan
*d40c
=
1714 container_of(chan
, struct d40_chan
, chan
);
1716 unsigned long flags
;
1718 spin_lock_irqsave(&d40c
->lock
, flags
);
1720 err
= d40_free_dma(d40c
);
1723 dev_err(&d40c
->chan
.dev
->device
,
1724 "[%s] Failed to free channel\n", __func__
);
1725 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1728 static struct dma_async_tx_descriptor
*d40_prep_memcpy(struct dma_chan
*chan
,
1732 unsigned long flags
)
1734 struct d40_desc
*d40d
;
1735 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1740 spin_lock_irqsave(&d40c
->lock
, flg
);
1741 d40d
= d40_desc_get(d40c
);
1744 dev_err(&d40c
->chan
.dev
->device
,
1745 "[%s] Descriptor is NULL\n", __func__
);
1749 memset(d40d
, 0, sizeof(struct d40_desc
));
1751 d40d
->txd
.flags
= flags
;
1753 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1755 d40d
->txd
.tx_submit
= d40_tx_submit
;
1757 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1759 if (d40_pool_lli_alloc(d40d
, 1, true) < 0) {
1760 dev_err(&d40c
->chan
.dev
->device
,
1761 "[%s] Out of memory\n", __func__
);
1765 d40d
->lli_tx_len
= 1;
1767 d40_log_fill_lli(d40d
->lli_log
.src
,
1771 d40c
->log_def
.lcsp1
,
1772 d40c
->dma_cfg
.src_info
.data_width
,
1775 d40_log_fill_lli(d40d
->lli_log
.dst
,
1779 d40c
->log_def
.lcsp3
,
1780 d40c
->dma_cfg
.dst_info
.data_width
,
1785 if (d40_pool_lli_alloc(d40d
, 1, false) < 0) {
1786 dev_err(&d40c
->chan
.dev
->device
,
1787 "[%s] Out of memory\n", __func__
);
1791 err
= d40_phy_fill_lli(d40d
->lli_phy
.src
,
1794 d40c
->dma_cfg
.src_info
.psize
,
1798 d40c
->dma_cfg
.src_info
.data_width
,
1803 err
= d40_phy_fill_lli(d40d
->lli_phy
.dst
,
1806 d40c
->dma_cfg
.dst_info
.psize
,
1810 d40c
->dma_cfg
.dst_info
.data_width
,
1816 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
1817 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1820 spin_unlock_irqrestore(&d40c
->lock
, flg
);
1824 dev_err(&d40c
->chan
.dev
->device
,
1825 "[%s] Failed filling in PHY LLI\n", __func__
);
1826 d40_pool_lli_free(d40d
);
1828 spin_unlock_irqrestore(&d40c
->lock
, flg
);
1832 static int d40_prep_slave_sg_log(struct d40_desc
*d40d
,
1833 struct d40_chan
*d40c
,
1834 struct scatterlist
*sgl
,
1835 unsigned int sg_len
,
1836 enum dma_data_direction direction
,
1837 unsigned long flags
)
1839 dma_addr_t dev_addr
= 0;
1842 if (d40_pool_lli_alloc(d40d
, sg_len
, true) < 0) {
1843 dev_err(&d40c
->chan
.dev
->device
,
1844 "[%s] Out of memory\n", __func__
);
1848 d40d
->lli_len
= sg_len
;
1849 if (d40d
->lli_len
<= d40c
->base
->plat_data
->llis_per_log
)
1850 d40d
->lli_tx_len
= d40d
->lli_len
;
1852 d40d
->lli_tx_len
= d40c
->base
->plat_data
->llis_per_log
;
1856 * Check if there is space available in lcla.
1857 * If not, split list into 1-length and run only
1860 if (d40_lcla_id_get(d40c
, &d40c
->base
->lcla_pool
) != 0)
1861 d40d
->lli_tx_len
= 1;
1863 if (direction
== DMA_FROM_DEVICE
) {
1864 dev_addr
= d40c
->base
->plat_data
->dev_rx
[d40c
->dma_cfg
.src_dev_type
];
1865 total_size
= d40_log_sg_to_dev(&d40c
->lcla
,
1869 d40c
->dma_cfg
.src_info
.data_width
,
1870 d40c
->dma_cfg
.dst_info
.data_width
,
1872 flags
& DMA_PREP_INTERRUPT
,
1873 dev_addr
, d40d
->lli_tx_len
,
1874 d40c
->base
->plat_data
->llis_per_log
);
1875 } else if (direction
== DMA_TO_DEVICE
) {
1876 dev_addr
= d40c
->base
->plat_data
->dev_tx
[d40c
->dma_cfg
.dst_dev_type
];
1877 total_size
= d40_log_sg_to_dev(&d40c
->lcla
,
1881 d40c
->dma_cfg
.src_info
.data_width
,
1882 d40c
->dma_cfg
.dst_info
.data_width
,
1884 flags
& DMA_PREP_INTERRUPT
,
1885 dev_addr
, d40d
->lli_tx_len
,
1886 d40c
->base
->plat_data
->llis_per_log
);
1895 static int d40_prep_slave_sg_phy(struct d40_desc
*d40d
,
1896 struct d40_chan
*d40c
,
1897 struct scatterlist
*sgl
,
1898 unsigned int sgl_len
,
1899 enum dma_data_direction direction
,
1900 unsigned long flags
)
1902 dma_addr_t src_dev_addr
;
1903 dma_addr_t dst_dev_addr
;
1906 if (d40_pool_lli_alloc(d40d
, sgl_len
, false) < 0) {
1907 dev_err(&d40c
->chan
.dev
->device
,
1908 "[%s] Out of memory\n", __func__
);
1912 d40d
->lli_len
= sgl_len
;
1913 d40d
->lli_tx_len
= sgl_len
;
1915 if (direction
== DMA_FROM_DEVICE
) {
1917 src_dev_addr
= d40c
->base
->plat_data
->dev_rx
[d40c
->dma_cfg
.src_dev_type
];
1918 } else if (direction
== DMA_TO_DEVICE
) {
1919 dst_dev_addr
= d40c
->base
->plat_data
->dev_tx
[d40c
->dma_cfg
.dst_dev_type
];
1924 res
= d40_phy_sg_to_lli(sgl
,
1928 d40d
->lli_phy
.src_addr
,
1930 d40c
->dma_cfg
.src_info
.data_width
,
1931 d40c
->dma_cfg
.src_info
.psize
,
1936 res
= d40_phy_sg_to_lli(sgl
,
1940 d40d
->lli_phy
.dst_addr
,
1942 d40c
->dma_cfg
.dst_info
.data_width
,
1943 d40c
->dma_cfg
.dst_info
.psize
,
1948 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
1949 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1953 static struct dma_async_tx_descriptor
*d40_prep_slave_sg(struct dma_chan
*chan
,
1954 struct scatterlist
*sgl
,
1955 unsigned int sg_len
,
1956 enum dma_data_direction direction
,
1957 unsigned long flags
)
1959 struct d40_desc
*d40d
;
1960 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1965 if (d40c
->dma_cfg
.pre_transfer
)
1966 d40c
->dma_cfg
.pre_transfer(chan
,
1967 d40c
->dma_cfg
.pre_transfer_data
,
1970 spin_lock_irqsave(&d40c
->lock
, flg
);
1971 d40d
= d40_desc_get(d40c
);
1972 spin_unlock_irqrestore(&d40c
->lock
, flg
);
1977 memset(d40d
, 0, sizeof(struct d40_desc
));
1979 if (d40c
->log_num
!= D40_PHY_CHAN
)
1980 err
= d40_prep_slave_sg_log(d40d
, d40c
, sgl
, sg_len
,
1983 err
= d40_prep_slave_sg_phy(d40d
, d40c
, sgl
, sg_len
,
1986 dev_err(&d40c
->chan
.dev
->device
,
1987 "[%s] Failed to prepare %s slave sg job: %d\n",
1989 d40c
->log_num
!= D40_PHY_CHAN
? "log" : "phy", err
);
1993 d40d
->txd
.flags
= flags
;
1995 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1997 d40d
->txd
.tx_submit
= d40_tx_submit
;
2002 static enum dma_status
d40_tx_status(struct dma_chan
*chan
,
2003 dma_cookie_t cookie
,
2004 struct dma_tx_state
*txstate
)
2006 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2007 dma_cookie_t last_used
;
2008 dma_cookie_t last_complete
;
2011 last_complete
= d40c
->completed
;
2012 last_used
= chan
->cookie
;
2014 if (d40_is_paused(d40c
))
2017 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
2019 dma_set_tx_state(txstate
, last_complete
, last_used
,
2020 stedma40_residue(chan
));
2025 static void d40_issue_pending(struct dma_chan
*chan
)
2027 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2028 unsigned long flags
;
2030 spin_lock_irqsave(&d40c
->lock
, flags
);
2032 /* Busy means that pending jobs are already being processed */
2034 (void) d40_queue_start(d40c
);
2036 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2039 static int d40_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
2042 unsigned long flags
;
2043 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2046 case DMA_TERMINATE_ALL
:
2047 spin_lock_irqsave(&d40c
->lock
, flags
);
2049 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2052 return d40_pause(chan
);
2054 return d40_resume(chan
);
2057 /* Other commands are unimplemented */
2061 /* Initialization functions */
2063 static void __init
d40_chan_init(struct d40_base
*base
, struct dma_device
*dma
,
2064 struct d40_chan
*chans
, int offset
,
2068 struct d40_chan
*d40c
;
2070 INIT_LIST_HEAD(&dma
->channels
);
2072 for (i
= offset
; i
< offset
+ num_chans
; i
++) {
2075 d40c
->chan
.device
= dma
;
2077 /* Invalidate lcla element */
2078 d40c
->lcla
.src_id
= -1;
2079 d40c
->lcla
.dst_id
= -1;
2081 spin_lock_init(&d40c
->lock
);
2083 d40c
->log_num
= D40_PHY_CHAN
;
2085 INIT_LIST_HEAD(&d40c
->active
);
2086 INIT_LIST_HEAD(&d40c
->queue
);
2087 INIT_LIST_HEAD(&d40c
->client
);
2089 tasklet_init(&d40c
->tasklet
, dma_tasklet
,
2090 (unsigned long) d40c
);
2092 list_add_tail(&d40c
->chan
.device_node
,
2097 static int __init
d40_dmaengine_init(struct d40_base
*base
,
2098 int num_reserved_chans
)
2102 d40_chan_init(base
, &base
->dma_slave
, base
->log_chans
,
2103 0, base
->num_log_chans
);
2105 dma_cap_zero(base
->dma_slave
.cap_mask
);
2106 dma_cap_set(DMA_SLAVE
, base
->dma_slave
.cap_mask
);
2108 base
->dma_slave
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2109 base
->dma_slave
.device_free_chan_resources
= d40_free_chan_resources
;
2110 base
->dma_slave
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2111 base
->dma_slave
.device_prep_slave_sg
= d40_prep_slave_sg
;
2112 base
->dma_slave
.device_tx_status
= d40_tx_status
;
2113 base
->dma_slave
.device_issue_pending
= d40_issue_pending
;
2114 base
->dma_slave
.device_control
= d40_control
;
2115 base
->dma_slave
.dev
= base
->dev
;
2117 err
= dma_async_device_register(&base
->dma_slave
);
2121 "[%s] Failed to register slave channels\n",
2126 d40_chan_init(base
, &base
->dma_memcpy
, base
->log_chans
,
2127 base
->num_log_chans
, base
->plat_data
->memcpy_len
);
2129 dma_cap_zero(base
->dma_memcpy
.cap_mask
);
2130 dma_cap_set(DMA_MEMCPY
, base
->dma_memcpy
.cap_mask
);
2132 base
->dma_memcpy
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2133 base
->dma_memcpy
.device_free_chan_resources
= d40_free_chan_resources
;
2134 base
->dma_memcpy
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2135 base
->dma_memcpy
.device_prep_slave_sg
= d40_prep_slave_sg
;
2136 base
->dma_memcpy
.device_tx_status
= d40_tx_status
;
2137 base
->dma_memcpy
.device_issue_pending
= d40_issue_pending
;
2138 base
->dma_memcpy
.device_control
= d40_control
;
2139 base
->dma_memcpy
.dev
= base
->dev
;
2141 * This controller can only access address at even
2142 * 32bit boundaries, i.e. 2^2
2144 base
->dma_memcpy
.copy_align
= 2;
2146 err
= dma_async_device_register(&base
->dma_memcpy
);
2150 "[%s] Failed to regsiter memcpy only channels\n",
2155 d40_chan_init(base
, &base
->dma_both
, base
->phy_chans
,
2156 0, num_reserved_chans
);
2158 dma_cap_zero(base
->dma_both
.cap_mask
);
2159 dma_cap_set(DMA_SLAVE
, base
->dma_both
.cap_mask
);
2160 dma_cap_set(DMA_MEMCPY
, base
->dma_both
.cap_mask
);
2162 base
->dma_both
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2163 base
->dma_both
.device_free_chan_resources
= d40_free_chan_resources
;
2164 base
->dma_both
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2165 base
->dma_both
.device_prep_slave_sg
= d40_prep_slave_sg
;
2166 base
->dma_both
.device_tx_status
= d40_tx_status
;
2167 base
->dma_both
.device_issue_pending
= d40_issue_pending
;
2168 base
->dma_both
.device_control
= d40_control
;
2169 base
->dma_both
.dev
= base
->dev
;
2170 base
->dma_both
.copy_align
= 2;
2171 err
= dma_async_device_register(&base
->dma_both
);
2175 "[%s] Failed to register logical and physical capable channels\n",
2181 dma_async_device_unregister(&base
->dma_memcpy
);
2183 dma_async_device_unregister(&base
->dma_slave
);
2188 /* Initialization functions. */
2190 static int __init
d40_phy_res_init(struct d40_base
*base
)
2193 int num_phy_chans_avail
= 0;
2195 int odd_even_bit
= -2;
2197 val
[0] = readl(base
->virtbase
+ D40_DREG_PRSME
);
2198 val
[1] = readl(base
->virtbase
+ D40_DREG_PRSMO
);
2200 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2201 base
->phy_res
[i
].num
= i
;
2202 odd_even_bit
+= 2 * ((i
% 2) == 0);
2203 if (((val
[i
% 2] >> odd_even_bit
) & 3) == 1) {
2204 /* Mark security only channels as occupied */
2205 base
->phy_res
[i
].allocated_src
= D40_ALLOC_PHY
;
2206 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_PHY
;
2208 base
->phy_res
[i
].allocated_src
= D40_ALLOC_FREE
;
2209 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_FREE
;
2210 num_phy_chans_avail
++;
2212 spin_lock_init(&base
->phy_res
[i
].lock
);
2214 dev_info(base
->dev
, "%d of %d physical DMA channels available\n",
2215 num_phy_chans_avail
, base
->num_phy_chans
);
2217 /* Verify settings extended vs standard */
2218 val
[0] = readl(base
->virtbase
+ D40_DREG_PRTYP
);
2220 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2222 if (base
->phy_res
[i
].allocated_src
== D40_ALLOC_FREE
&&
2223 (val
[0] & 0x3) != 1)
2225 "[%s] INFO: channel %d is misconfigured (%d)\n",
2226 __func__
, i
, val
[0] & 0x3);
2228 val
[0] = val
[0] >> 2;
2231 return num_phy_chans_avail
;
2234 static struct d40_base
* __init
d40_hw_detect_init(struct platform_device
*pdev
)
2236 static const struct d40_reg_val dma_id_regs
[] = {
2238 { .reg
= D40_DREG_PERIPHID0
, .val
= 0x0040},
2239 { .reg
= D40_DREG_PERIPHID1
, .val
= 0x0000},
2241 * D40_DREG_PERIPHID2 Depends on HW revision:
2242 * MOP500/HREF ED has 0x0008,
2244 * HREF V1 has 0x0028
2246 { .reg
= D40_DREG_PERIPHID3
, .val
= 0x0000},
2249 { .reg
= D40_DREG_CELLID0
, .val
= 0x000d},
2250 { .reg
= D40_DREG_CELLID1
, .val
= 0x00f0},
2251 { .reg
= D40_DREG_CELLID2
, .val
= 0x0005},
2252 { .reg
= D40_DREG_CELLID3
, .val
= 0x00b1}
2254 struct stedma40_platform_data
*plat_data
;
2255 struct clk
*clk
= NULL
;
2256 void __iomem
*virtbase
= NULL
;
2257 struct resource
*res
= NULL
;
2258 struct d40_base
*base
= NULL
;
2259 int num_log_chans
= 0;
2263 clk
= clk_get(&pdev
->dev
, NULL
);
2266 dev_err(&pdev
->dev
, "[%s] No matching clock found\n",
2273 /* Get IO for DMAC base address */
2274 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "base");
2278 if (request_mem_region(res
->start
, resource_size(res
),
2279 D40_NAME
" I/O base") == NULL
)
2282 virtbase
= ioremap(res
->start
, resource_size(res
));
2286 /* HW version check */
2287 for (i
= 0; i
< ARRAY_SIZE(dma_id_regs
); i
++) {
2288 if (dma_id_regs
[i
].val
!=
2289 readl(virtbase
+ dma_id_regs
[i
].reg
)) {
2291 "[%s] Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2295 readl(virtbase
+ dma_id_regs
[i
].reg
));
2300 i
= readl(virtbase
+ D40_DREG_PERIPHID2
);
2302 if ((i
& 0xf) != D40_PERIPHID2_DESIGNER
) {
2304 "[%s] Unknown designer! Got %x wanted %x\n",
2305 __func__
, i
& 0xf, D40_PERIPHID2_DESIGNER
);
2309 /* The number of physical channels on this HW */
2310 num_phy_chans
= 4 * (readl(virtbase
+ D40_DREG_ICFG
) & 0x7) + 4;
2312 dev_info(&pdev
->dev
, "hardware revision: %d @ 0x%x\n",
2313 (i
>> 4) & 0xf, res
->start
);
2315 plat_data
= pdev
->dev
.platform_data
;
2317 /* Count the number of logical channels in use */
2318 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2319 if (plat_data
->dev_rx
[i
] != 0)
2322 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2323 if (plat_data
->dev_tx
[i
] != 0)
2326 base
= kzalloc(ALIGN(sizeof(struct d40_base
), 4) +
2327 (num_phy_chans
+ num_log_chans
+ plat_data
->memcpy_len
) *
2328 sizeof(struct d40_chan
), GFP_KERNEL
);
2331 dev_err(&pdev
->dev
, "[%s] Out of memory\n", __func__
);
2336 base
->num_phy_chans
= num_phy_chans
;
2337 base
->num_log_chans
= num_log_chans
;
2338 base
->phy_start
= res
->start
;
2339 base
->phy_size
= resource_size(res
);
2340 base
->virtbase
= virtbase
;
2341 base
->plat_data
= plat_data
;
2342 base
->dev
= &pdev
->dev
;
2343 base
->phy_chans
= ((void *)base
) + ALIGN(sizeof(struct d40_base
), 4);
2344 base
->log_chans
= &base
->phy_chans
[num_phy_chans
];
2346 base
->phy_res
= kzalloc(num_phy_chans
* sizeof(struct d40_phy_res
),
2351 base
->lookup_phy_chans
= kzalloc(num_phy_chans
*
2352 sizeof(struct d40_chan
*),
2354 if (!base
->lookup_phy_chans
)
2357 if (num_log_chans
+ plat_data
->memcpy_len
) {
2359 * The max number of logical channels are event lines for all
2360 * src devices and dst devices
2362 base
->lookup_log_chans
= kzalloc(plat_data
->dev_len
* 2 *
2363 sizeof(struct d40_chan
*),
2365 if (!base
->lookup_log_chans
)
2368 base
->lcla_pool
.alloc_map
= kzalloc(num_phy_chans
* sizeof(u32
),
2370 if (!base
->lcla_pool
.alloc_map
)
2373 base
->desc_slab
= kmem_cache_create(D40_NAME
, sizeof(struct d40_desc
),
2374 0, SLAB_HWCACHE_ALIGN
,
2376 if (base
->desc_slab
== NULL
)
2389 release_mem_region(res
->start
,
2390 resource_size(res
));
2395 kfree(base
->lcla_pool
.alloc_map
);
2396 kfree(base
->lookup_log_chans
);
2397 kfree(base
->lookup_phy_chans
);
2398 kfree(base
->phy_res
);
2405 static void __init
d40_hw_init(struct d40_base
*base
)
2408 static const struct d40_reg_val dma_init_reg
[] = {
2409 /* Clock every part of the DMA block from start */
2410 { .reg
= D40_DREG_GCC
, .val
= 0x0000ff01},
2412 /* Interrupts on all logical channels */
2413 { .reg
= D40_DREG_LCMIS0
, .val
= 0xFFFFFFFF},
2414 { .reg
= D40_DREG_LCMIS1
, .val
= 0xFFFFFFFF},
2415 { .reg
= D40_DREG_LCMIS2
, .val
= 0xFFFFFFFF},
2416 { .reg
= D40_DREG_LCMIS3
, .val
= 0xFFFFFFFF},
2417 { .reg
= D40_DREG_LCICR0
, .val
= 0xFFFFFFFF},
2418 { .reg
= D40_DREG_LCICR1
, .val
= 0xFFFFFFFF},
2419 { .reg
= D40_DREG_LCICR2
, .val
= 0xFFFFFFFF},
2420 { .reg
= D40_DREG_LCICR3
, .val
= 0xFFFFFFFF},
2421 { .reg
= D40_DREG_LCTIS0
, .val
= 0xFFFFFFFF},
2422 { .reg
= D40_DREG_LCTIS1
, .val
= 0xFFFFFFFF},
2423 { .reg
= D40_DREG_LCTIS2
, .val
= 0xFFFFFFFF},
2424 { .reg
= D40_DREG_LCTIS3
, .val
= 0xFFFFFFFF}
2427 u32 prmseo
[2] = {0, 0};
2428 u32 activeo
[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2432 for (i
= 0; i
< ARRAY_SIZE(dma_init_reg
); i
++)
2433 writel(dma_init_reg
[i
].val
,
2434 base
->virtbase
+ dma_init_reg
[i
].reg
);
2436 /* Configure all our dma channels to default settings */
2437 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2439 activeo
[i
% 2] = activeo
[i
% 2] << 2;
2441 if (base
->phy_res
[base
->num_phy_chans
- i
- 1].allocated_src
2443 activeo
[i
% 2] |= 3;
2447 /* Enable interrupt # */
2448 pcmis
= (pcmis
<< 1) | 1;
2450 /* Clear interrupt # */
2451 pcicr
= (pcicr
<< 1) | 1;
2453 /* Set channel to physical mode */
2454 prmseo
[i
% 2] = prmseo
[i
% 2] << 2;
2459 writel(prmseo
[1], base
->virtbase
+ D40_DREG_PRMSE
);
2460 writel(prmseo
[0], base
->virtbase
+ D40_DREG_PRMSO
);
2461 writel(activeo
[1], base
->virtbase
+ D40_DREG_ACTIVE
);
2462 writel(activeo
[0], base
->virtbase
+ D40_DREG_ACTIVO
);
2464 /* Write which interrupt to enable */
2465 writel(pcmis
, base
->virtbase
+ D40_DREG_PCMIS
);
2467 /* Write which interrupt to clear */
2468 writel(pcicr
, base
->virtbase
+ D40_DREG_PCICR
);
2472 static int __init
d40_probe(struct platform_device
*pdev
)
2476 struct d40_base
*base
;
2477 struct resource
*res
= NULL
;
2478 int num_reserved_chans
;
2481 base
= d40_hw_detect_init(pdev
);
2486 num_reserved_chans
= d40_phy_res_init(base
);
2488 platform_set_drvdata(pdev
, base
);
2490 spin_lock_init(&base
->interrupt_lock
);
2491 spin_lock_init(&base
->execmd_lock
);
2493 /* Get IO for logical channel parameter address */
2494 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "lcpa");
2498 "[%s] No \"lcpa\" memory resource\n",
2502 base
->lcpa_size
= resource_size(res
);
2503 base
->phy_lcpa
= res
->start
;
2505 if (request_mem_region(res
->start
, resource_size(res
),
2506 D40_NAME
" I/O lcpa") == NULL
) {
2509 "[%s] Failed to request LCPA region 0x%x-0x%x\n",
2510 __func__
, res
->start
, res
->end
);
2514 /* We make use of ESRAM memory for this. */
2515 val
= readl(base
->virtbase
+ D40_DREG_LCPA
);
2516 if (res
->start
!= val
&& val
!= 0) {
2517 dev_warn(&pdev
->dev
,
2518 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2519 __func__
, val
, res
->start
);
2521 writel(res
->start
, base
->virtbase
+ D40_DREG_LCPA
);
2523 base
->lcpa_base
= ioremap(res
->start
, resource_size(res
));
2524 if (!base
->lcpa_base
) {
2527 "[%s] Failed to ioremap LCPA region\n",
2531 /* Get IO for logical channel link address */
2532 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "lcla");
2536 "[%s] No \"lcla\" resource defined\n",
2541 base
->lcla_pool
.base_size
= resource_size(res
);
2542 base
->lcla_pool
.phy
= res
->start
;
2544 if (request_mem_region(res
->start
, resource_size(res
),
2545 D40_NAME
" I/O lcla") == NULL
) {
2548 "[%s] Failed to request LCLA region 0x%x-0x%x\n",
2549 __func__
, res
->start
, res
->end
);
2552 val
= readl(base
->virtbase
+ D40_DREG_LCLA
);
2553 if (res
->start
!= val
&& val
!= 0) {
2554 dev_warn(&pdev
->dev
,
2555 "[%s] Mismatch LCLA dma 0x%x, def 0x%x\n",
2556 __func__
, val
, res
->start
);
2558 writel(res
->start
, base
->virtbase
+ D40_DREG_LCLA
);
2560 base
->lcla_pool
.base
= ioremap(res
->start
, resource_size(res
));
2561 if (!base
->lcla_pool
.base
) {
2564 "[%s] Failed to ioremap LCLA 0x%x-0x%x\n",
2565 __func__
, res
->start
, res
->end
);
2569 spin_lock_init(&base
->lcla_pool
.lock
);
2571 base
->lcla_pool
.num_blocks
= base
->num_phy_chans
;
2573 base
->irq
= platform_get_irq(pdev
, 0);
2575 ret
= request_irq(base
->irq
, d40_handle_interrupt
, 0, D40_NAME
, base
);
2578 dev_err(&pdev
->dev
, "[%s] No IRQ defined\n", __func__
);
2582 err
= d40_dmaengine_init(base
, num_reserved_chans
);
2588 dev_info(base
->dev
, "initialized\n");
2593 if (base
->desc_slab
)
2594 kmem_cache_destroy(base
->desc_slab
);
2596 iounmap(base
->virtbase
);
2597 if (base
->lcla_pool
.phy
)
2598 release_mem_region(base
->lcla_pool
.phy
,
2599 base
->lcla_pool
.base_size
);
2601 release_mem_region(base
->phy_lcpa
,
2603 if (base
->phy_start
)
2604 release_mem_region(base
->phy_start
,
2607 clk_disable(base
->clk
);
2611 kfree(base
->lcla_pool
.alloc_map
);
2612 kfree(base
->lookup_log_chans
);
2613 kfree(base
->lookup_phy_chans
);
2614 kfree(base
->phy_res
);
2618 dev_err(&pdev
->dev
, "[%s] probe failed\n", __func__
);
2622 static struct platform_driver d40_driver
= {
2624 .owner
= THIS_MODULE
,
2629 int __init
stedma40_init(void)
2631 return platform_driver_probe(&d40_driver
, d40_probe
);
2633 arch_initcall(stedma40_init
);