2 * driver/dma/ste_dma40.c
4 * Copyright (C) ST-Ericsson 2007-2010
5 * License terms: GNU General Public License (GPL) version 2
6 * Author: Per Friden <per.friden@stericsson.com>
7 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
18 #include <plat/ste_dma40.h>
20 #include "ste_dma40_ll.h"
22 #define D40_NAME "dma40"
24 #define D40_PHY_CHAN -1
26 /* For masking out/in 2 bit channel positions */
27 #define D40_CHAN_POS(chan) (2 * (chan / 2))
28 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
30 /* Maximum iterations taken before giving up suspending a channel */
31 #define D40_SUSPEND_MAX_IT 500
33 /* Hardware requirement on LCLA alignment */
34 #define LCLA_ALIGNMENT 0x40000
35 /* Attempts before giving up to trying to get pages that are aligned */
36 #define MAX_LCLA_ALLOC_ATTEMPTS 256
38 /* Bit markings for allocation map */
39 #define D40_ALLOC_FREE (1 << 31)
40 #define D40_ALLOC_PHY (1 << 30)
41 #define D40_ALLOC_LOG_FREE 0
43 /* Hardware designer of the block */
44 #define D40_PERIPHID2_DESIGNER 0x8
47 * enum 40_command - The different commands and/or statuses.
49 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
50 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
51 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
52 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57 D40_DMA_SUSPEND_REQ
= 2,
62 * struct d40_lli_pool - Structure for keeping LLIs in memory
64 * @base: Pointer to memory area when the pre_alloc_lli's are not large
65 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
66 * pre_alloc_lli is used.
67 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
68 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
69 * one buffer to one buffer.
74 /* Space for dst and src, plus an extra for padding */
75 u8 pre_alloc_lli
[3 * sizeof(struct d40_phy_lli
)];
79 * struct d40_desc - A descriptor is one DMA job.
81 * @lli_phy: LLI settings for physical channel. Both src and dst=
82 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
84 * @lli_log: Same as above but for logical channels.
85 * @lli_pool: The pool with two entries pre-allocated.
86 * @lli_len: Number of llis of current descriptor.
87 * @lli_count: Number of transfered llis.
88 * @lli_tx_len: Max number of LLIs per transfer, there can be
89 * many transfer for one descriptor.
90 * @txd: DMA engine struct. Used for among other things for communication
93 * @dir: The transfer direction of this job.
94 * @is_in_client_list: true if the client owns this descriptor.
96 * This descriptor is used for both logical and physical transfers.
101 struct d40_phy_lli_bidir lli_phy
;
103 struct d40_log_lli_bidir lli_log
;
105 struct d40_lli_pool lli_pool
;
110 struct dma_async_tx_descriptor txd
;
111 struct list_head node
;
113 enum dma_data_direction dir
;
114 bool is_in_client_list
;
118 * struct d40_lcla_pool - LCLA pool settings and data.
120 * @base: The virtual address of LCLA. 18 bit aligned.
121 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
122 * This pointer is only there for clean-up on error.
123 * @pages: The number of pages needed for all physical channels.
124 * Only used later for clean-up on error
125 * @lock: Lock to protect the content in this struct.
126 * @alloc_map: Bitmap mapping between physical channel and LCLA entries.
127 * @num_blocks: The number of entries of alloc_map. Equals to the
128 * number of physical channels.
130 struct d40_lcla_pool
{
132 void *base_unaligned
;
140 * struct d40_phy_res - struct for handling eventlines mapped to physical
143 * @lock: A lock protection this entity.
144 * @num: The physical channel number of this entity.
145 * @allocated_src: Bit mapped to show which src event line's are mapped to
146 * this physical channel. Can also be free or physically allocated.
147 * @allocated_dst: Same as for src but is dst.
148 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
149 * event line number. Both allocated_src and allocated_dst can not be
150 * allocated to a physical channel, since the interrupt handler has then
151 * no way of figure out which one the interrupt belongs to.
163 * struct d40_chan - Struct that describes a channel.
165 * @lock: A spinlock to protect this struct.
166 * @log_num: The logical number, if any of this channel.
167 * @completed: Starts with 1, after first interrupt it is set to dma engine's
169 * @pending_tx: The number of pending transfers. Used between interrupt handler
171 * @busy: Set to true when transfer is ongoing on this channel.
172 * @phy_chan: Pointer to physical channel which this instance runs on. If this
173 * point is NULL, then the channel is not allocated.
174 * @chan: DMA engine handle.
175 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
176 * transfer and call client callback.
177 * @client: Cliented owned descriptor list.
178 * @active: Active descriptor.
179 * @queue: Queued jobs.
180 * @dma_cfg: The client configuration of this dma channel.
181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
188 * This struct can either "be" a logical or a physical channel.
193 /* ID of the most recent completed transfer */
197 struct d40_phy_res
*phy_chan
;
198 struct dma_chan chan
;
199 struct tasklet_struct tasklet
;
200 struct list_head client
;
201 struct list_head active
;
202 struct list_head queue
;
203 struct stedma40_chan_cfg dma_cfg
;
204 struct d40_base
*base
;
205 /* Default register configurations */
208 struct d40_def_lcsp log_def
;
209 struct d40_lcla_elem lcla
;
210 struct d40_log_lli_full
*lcpa
;
214 * struct d40_base - The big global struct, one for each probe'd instance.
216 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
217 * @execmd_lock: Lock for execute command usage since several channels share
218 * the same physical register.
219 * @dev: The device structure.
220 * @virtbase: The virtual base address of the DMA's register.
221 * @clk: Pointer to the DMA clock structure.
222 * @phy_start: Physical memory start of the DMA registers.
223 * @phy_size: Size of the DMA register map.
224 * @irq: The IRQ number.
225 * @num_phy_chans: The number of physical channels. Read from HW. This
226 * is the number of available channels for this driver, not counting "Secure
227 * mode" allocated physical channels.
228 * @num_log_chans: The number of logical channels. Calculated from
230 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
231 * @dma_slave: dma_device channels that can do only do slave transfers.
232 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
233 * @phy_chans: Room for all possible physical channels in system.
234 * @log_chans: Room for all possible logical channels in system.
235 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
236 * to log_chans entries.
237 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
238 * to phy_chans entries.
239 * @plat_data: Pointer to provided platform_data which is the driver
241 * @phy_res: Vector containing all physical channels.
242 * @lcla_pool: lcla pool settings and data.
243 * @lcpa_base: The virtual mapped address of LCPA.
244 * @phy_lcpa: The physical address of the LCPA.
245 * @lcpa_size: The size of the LCPA area.
246 * @desc_slab: cache for descriptors.
249 spinlock_t interrupt_lock
;
250 spinlock_t execmd_lock
;
252 void __iomem
*virtbase
;
254 phys_addr_t phy_start
;
255 resource_size_t phy_size
;
259 struct dma_device dma_both
;
260 struct dma_device dma_slave
;
261 struct dma_device dma_memcpy
;
262 struct d40_chan
*phy_chans
;
263 struct d40_chan
*log_chans
;
264 struct d40_chan
**lookup_log_chans
;
265 struct d40_chan
**lookup_phy_chans
;
266 struct stedma40_platform_data
*plat_data
;
267 /* Physical half channels */
268 struct d40_phy_res
*phy_res
;
269 struct d40_lcla_pool lcla_pool
;
272 resource_size_t lcpa_size
;
273 struct kmem_cache
*desc_slab
;
277 * struct d40_interrupt_lookup - lookup table for interrupt handler
279 * @src: Interrupt mask register.
280 * @clr: Interrupt clear register.
281 * @is_error: true if this is an error interrupt.
282 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
283 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
285 struct d40_interrupt_lookup
{
293 * struct d40_reg_val - simple lookup struct
295 * @reg: The register.
296 * @val: The value that belongs to the register in reg.
303 static int d40_pool_lli_alloc(struct d40_desc
*d40d
,
304 int lli_len
, bool is_log
)
310 align
= sizeof(struct d40_log_lli
);
312 align
= sizeof(struct d40_phy_lli
);
315 base
= d40d
->lli_pool
.pre_alloc_lli
;
316 d40d
->lli_pool
.size
= sizeof(d40d
->lli_pool
.pre_alloc_lli
);
317 d40d
->lli_pool
.base
= NULL
;
319 d40d
->lli_pool
.size
= ALIGN(lli_len
* 2 * align
, align
);
321 base
= kmalloc(d40d
->lli_pool
.size
+ align
, GFP_NOWAIT
);
322 d40d
->lli_pool
.base
= base
;
324 if (d40d
->lli_pool
.base
== NULL
)
329 d40d
->lli_log
.src
= PTR_ALIGN((struct d40_log_lli
*) base
,
331 d40d
->lli_log
.dst
= PTR_ALIGN(d40d
->lli_log
.src
+ lli_len
,
334 d40d
->lli_phy
.src
= PTR_ALIGN((struct d40_phy_lli
*)base
,
336 d40d
->lli_phy
.dst
= PTR_ALIGN(d40d
->lli_phy
.src
+ lli_len
,
339 d40d
->lli_phy
.src_addr
= virt_to_phys(d40d
->lli_phy
.src
);
340 d40d
->lli_phy
.dst_addr
= virt_to_phys(d40d
->lli_phy
.dst
);
346 static void d40_pool_lli_free(struct d40_desc
*d40d
)
348 kfree(d40d
->lli_pool
.base
);
349 d40d
->lli_pool
.base
= NULL
;
350 d40d
->lli_pool
.size
= 0;
351 d40d
->lli_log
.src
= NULL
;
352 d40d
->lli_log
.dst
= NULL
;
353 d40d
->lli_phy
.src
= NULL
;
354 d40d
->lli_phy
.dst
= NULL
;
355 d40d
->lli_phy
.src_addr
= 0;
356 d40d
->lli_phy
.dst_addr
= 0;
359 static dma_cookie_t
d40_assign_cookie(struct d40_chan
*d40c
,
360 struct d40_desc
*desc
)
362 dma_cookie_t cookie
= d40c
->chan
.cookie
;
367 d40c
->chan
.cookie
= cookie
;
368 desc
->txd
.cookie
= cookie
;
373 static void d40_desc_remove(struct d40_desc
*d40d
)
375 list_del(&d40d
->node
);
378 static struct d40_desc
*d40_desc_get(struct d40_chan
*d40c
)
383 if (!list_empty(&d40c
->client
)) {
384 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
)
385 if (async_tx_test_ack(&d
->txd
)) {
386 d40_pool_lli_free(d
);
391 d
= kmem_cache_alloc(d40c
->base
->desc_slab
, GFP_NOWAIT
);
393 memset(d
, 0, sizeof(struct d40_desc
));
394 INIT_LIST_HEAD(&d
->node
);
400 static void d40_desc_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
402 kmem_cache_free(d40c
->base
->desc_slab
, d40d
);
405 static void d40_desc_submit(struct d40_chan
*d40c
, struct d40_desc
*desc
)
407 list_add_tail(&desc
->node
, &d40c
->active
);
410 static struct d40_desc
*d40_first_active_get(struct d40_chan
*d40c
)
414 if (list_empty(&d40c
->active
))
417 d
= list_first_entry(&d40c
->active
,
423 static void d40_desc_queue(struct d40_chan
*d40c
, struct d40_desc
*desc
)
425 list_add_tail(&desc
->node
, &d40c
->queue
);
428 static struct d40_desc
*d40_first_queued(struct d40_chan
*d40c
)
432 if (list_empty(&d40c
->queue
))
435 d
= list_first_entry(&d40c
->queue
,
441 /* Support functions for logical channels */
443 static int d40_lcla_id_get(struct d40_chan
*d40c
)
447 struct d40_log_lli
*lcla_lidx_base
=
448 d40c
->base
->lcla_pool
.base
+ d40c
->phy_chan
->num
* 1024;
450 int lli_per_log
= d40c
->base
->plat_data
->llis_per_log
;
453 if (d40c
->lcla
.src_id
>= 0 && d40c
->lcla
.dst_id
>= 0)
456 if (d40c
->base
->lcla_pool
.num_blocks
> 32)
459 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
461 for (i
= 0; i
< d40c
->base
->lcla_pool
.num_blocks
; i
++) {
462 if (!(d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] &
464 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] |=
470 if (src_id
>= d40c
->base
->lcla_pool
.num_blocks
)
473 for (; i
< d40c
->base
->lcla_pool
.num_blocks
; i
++) {
474 if (!(d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] &
476 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] |=
483 if (dst_id
== src_id
)
486 d40c
->lcla
.src_id
= src_id
;
487 d40c
->lcla
.dst_id
= dst_id
;
488 d40c
->lcla
.dst
= lcla_lidx_base
+ dst_id
* lli_per_log
+ 1;
489 d40c
->lcla
.src
= lcla_lidx_base
+ src_id
* lli_per_log
+ 1;
491 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
494 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
499 static int d40_channel_execute_command(struct d40_chan
*d40c
,
500 enum d40_command command
)
503 void __iomem
*active_reg
;
508 spin_lock_irqsave(&d40c
->base
->execmd_lock
, flags
);
510 if (d40c
->phy_chan
->num
% 2 == 0)
511 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
513 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
515 if (command
== D40_DMA_SUSPEND_REQ
) {
516 status
= (readl(active_reg
) &
517 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
518 D40_CHAN_POS(d40c
->phy_chan
->num
);
520 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
524 wmask
= 0xffffffff & ~(D40_CHAN_POS_MASK(d40c
->phy_chan
->num
));
525 writel(wmask
| (command
<< D40_CHAN_POS(d40c
->phy_chan
->num
)),
528 if (command
== D40_DMA_SUSPEND_REQ
) {
530 for (i
= 0 ; i
< D40_SUSPEND_MAX_IT
; i
++) {
531 status
= (readl(active_reg
) &
532 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
533 D40_CHAN_POS(d40c
->phy_chan
->num
);
537 * Reduce the number of bus accesses while
538 * waiting for the DMA to suspend.
542 if (status
== D40_DMA_STOP
||
543 status
== D40_DMA_SUSPENDED
)
547 if (i
== D40_SUSPEND_MAX_IT
) {
548 dev_err(&d40c
->chan
.dev
->device
,
549 "[%s]: unable to suspend the chl %d (log: %d) status %x\n",
550 __func__
, d40c
->phy_chan
->num
, d40c
->log_num
,
558 spin_unlock_irqrestore(&d40c
->base
->execmd_lock
, flags
);
562 static void d40_term_all(struct d40_chan
*d40c
)
564 struct d40_desc
*d40d
;
567 /* Release active descriptors */
568 while ((d40d
= d40_first_active_get(d40c
))) {
569 d40_desc_remove(d40d
);
571 /* Return desc to free-list */
572 d40_desc_free(d40c
, d40d
);
575 /* Release queued descriptors waiting for transfer */
576 while ((d40d
= d40_first_queued(d40c
))) {
577 d40_desc_remove(d40d
);
579 /* Return desc to free-list */
580 d40_desc_free(d40c
, d40d
);
583 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
585 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] &=
586 (~(0x1 << d40c
->lcla
.dst_id
));
587 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
] &=
588 (~(0x1 << d40c
->lcla
.src_id
));
590 d40c
->lcla
.src_id
= -1;
591 d40c
->lcla
.dst_id
= -1;
593 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
595 d40c
->pending_tx
= 0;
599 static void d40_config_set_event(struct d40_chan
*d40c
, bool do_enable
)
604 /* Notice, that disable requires the physical channel to be stopped */
606 val
= D40_ACTIVATE_EVENTLINE
;
608 val
= D40_DEACTIVATE_EVENTLINE
;
610 spin_lock_irqsave(&d40c
->phy_chan
->lock
, flags
);
612 /* Enable event line connected to device (or memcpy) */
613 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
614 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
)) {
615 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
617 writel((val
<< D40_EVENTLINE_POS(event
)) |
618 ~D40_EVENTLINE_MASK(event
),
619 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
620 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
623 if (d40c
->dma_cfg
.dir
!= STEDMA40_PERIPH_TO_MEM
) {
624 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
626 writel((val
<< D40_EVENTLINE_POS(event
)) |
627 ~D40_EVENTLINE_MASK(event
),
628 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
629 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
633 spin_unlock_irqrestore(&d40c
->phy_chan
->lock
, flags
);
636 static u32
d40_chan_has_events(struct d40_chan
*d40c
)
640 /* If SSLNK or SDLNK is zero all events are disabled */
641 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
642 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
643 val
= readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
644 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
647 if (d40c
->dma_cfg
.dir
!= STEDMA40_PERIPH_TO_MEM
)
648 val
= readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
649 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
654 static void d40_config_enable_lidx(struct d40_chan
*d40c
)
656 /* Set LIDX for lcla */
657 writel((d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
) &
658 D40_SREG_ELEM_LOG_LIDX_MASK
,
659 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
660 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+ D40_CHAN_REG_SDELT
);
662 writel((d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
) &
663 D40_SREG_ELEM_LOG_LIDX_MASK
,
664 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
665 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+ D40_CHAN_REG_SSELT
);
668 static int d40_config_write(struct d40_chan
*d40c
)
674 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
678 /* Odd addresses are even addresses + 4 */
679 addr_base
= (d40c
->phy_chan
->num
% 2) * 4;
680 /* Setup channel mode to logical or physical */
681 var
= ((u32
)(d40c
->log_num
!= D40_PHY_CHAN
) + 1) <<
682 D40_CHAN_POS(d40c
->phy_chan
->num
);
683 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMSE
+ addr_base
);
685 /* Setup operational mode option register */
686 var
= ((d40c
->dma_cfg
.channel_type
>> STEDMA40_INFO_CH_MODE_OPT_POS
) &
687 0x3) << D40_CHAN_POS(d40c
->phy_chan
->num
);
689 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMOE
+ addr_base
);
691 if (d40c
->log_num
!= D40_PHY_CHAN
) {
692 /* Set default config for CFG reg */
693 writel(d40c
->src_def_cfg
,
694 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
695 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
697 writel(d40c
->dst_def_cfg
,
698 d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
699 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
702 d40_config_enable_lidx(d40c
);
707 static void d40_desc_load(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
709 if (d40d
->lli_phy
.dst
&& d40d
->lli_phy
.src
) {
710 d40_phy_lli_write(d40c
->base
->virtbase
,
714 } else if (d40d
->lli_log
.dst
&& d40d
->lli_log
.src
) {
715 struct d40_log_lli
*src
= d40d
->lli_log
.src
;
716 struct d40_log_lli
*dst
= d40d
->lli_log
.dst
;
719 src
+= d40d
->lli_count
;
720 dst
+= d40d
->lli_count
;
721 s
= d40_log_lli_write(d40c
->lcpa
,
722 d40c
->lcla
.src
, d40c
->lcla
.dst
,
724 d40c
->base
->plat_data
->llis_per_log
);
726 /* If s equals to zero, the job is not linked */
728 (void) dma_map_single(d40c
->base
->dev
, d40c
->lcla
.src
,
729 s
* sizeof(struct d40_log_lli
),
731 (void) dma_map_single(d40c
->base
->dev
, d40c
->lcla
.dst
,
732 s
* sizeof(struct d40_log_lli
),
736 d40d
->lli_count
+= d40d
->lli_tx_len
;
739 static dma_cookie_t
d40_tx_submit(struct dma_async_tx_descriptor
*tx
)
741 struct d40_chan
*d40c
= container_of(tx
->chan
,
744 struct d40_desc
*d40d
= container_of(tx
, struct d40_desc
, txd
);
747 spin_lock_irqsave(&d40c
->lock
, flags
);
749 tx
->cookie
= d40_assign_cookie(d40c
, d40d
);
751 d40_desc_queue(d40c
, d40d
);
753 spin_unlock_irqrestore(&d40c
->lock
, flags
);
758 static int d40_start(struct d40_chan
*d40c
)
760 if (d40c
->log_num
!= D40_PHY_CHAN
)
761 d40_config_set_event(d40c
, true);
763 return d40_channel_execute_command(d40c
, D40_DMA_RUN
);
766 static struct d40_desc
*d40_queue_start(struct d40_chan
*d40c
)
768 struct d40_desc
*d40d
;
771 /* Start queued jobs, if any */
772 d40d
= d40_first_queued(d40c
);
777 /* Remove from queue */
778 d40_desc_remove(d40d
);
780 /* Add to active queue */
781 d40_desc_submit(d40c
, d40d
);
783 /* Initiate DMA job */
784 d40_desc_load(d40c
, d40d
);
787 err
= d40_start(d40c
);
796 /* called from interrupt context */
797 static void dma_tc_handle(struct d40_chan
*d40c
)
799 struct d40_desc
*d40d
;
804 /* Get first active entry from list */
805 d40d
= d40_first_active_get(d40c
);
810 if (d40d
->lli_count
< d40d
->lli_len
) {
812 d40_desc_load(d40c
, d40d
);
814 (void) d40_start(d40c
);
818 if (d40_queue_start(d40c
) == NULL
)
822 tasklet_schedule(&d40c
->tasklet
);
826 static void dma_tasklet(unsigned long data
)
828 struct d40_chan
*d40c
= (struct d40_chan
*) data
;
829 struct d40_desc
*d40d_fin
;
831 dma_async_tx_callback callback
;
832 void *callback_param
;
834 spin_lock_irqsave(&d40c
->lock
, flags
);
836 /* Get first active entry from list */
837 d40d_fin
= d40_first_active_get(d40c
);
839 if (d40d_fin
== NULL
)
842 d40c
->completed
= d40d_fin
->txd
.cookie
;
845 * If terminating a channel pending_tx is set to zero.
846 * This prevents any finished active jobs to return to the client.
848 if (d40c
->pending_tx
== 0) {
849 spin_unlock_irqrestore(&d40c
->lock
, flags
);
853 /* Callback to client */
854 callback
= d40d_fin
->txd
.callback
;
855 callback_param
= d40d_fin
->txd
.callback_param
;
857 if (async_tx_test_ack(&d40d_fin
->txd
)) {
858 d40_pool_lli_free(d40d_fin
);
859 d40_desc_remove(d40d_fin
);
860 /* Return desc to free-list */
861 d40_desc_free(d40c
, d40d_fin
);
863 if (!d40d_fin
->is_in_client_list
) {
864 d40_desc_remove(d40d_fin
);
865 list_add_tail(&d40d_fin
->node
, &d40c
->client
);
866 d40d_fin
->is_in_client_list
= true;
872 if (d40c
->pending_tx
)
873 tasklet_schedule(&d40c
->tasklet
);
875 spin_unlock_irqrestore(&d40c
->lock
, flags
);
878 callback(callback_param
);
883 /* Rescue manouver if receiving double interrupts */
884 if (d40c
->pending_tx
> 0)
886 spin_unlock_irqrestore(&d40c
->lock
, flags
);
889 static irqreturn_t
d40_handle_interrupt(int irq
, void *data
)
891 static const struct d40_interrupt_lookup il
[] = {
892 {D40_DREG_LCTIS0
, D40_DREG_LCICR0
, false, 0},
893 {D40_DREG_LCTIS1
, D40_DREG_LCICR1
, false, 32},
894 {D40_DREG_LCTIS2
, D40_DREG_LCICR2
, false, 64},
895 {D40_DREG_LCTIS3
, D40_DREG_LCICR3
, false, 96},
896 {D40_DREG_LCEIS0
, D40_DREG_LCICR0
, true, 0},
897 {D40_DREG_LCEIS1
, D40_DREG_LCICR1
, true, 32},
898 {D40_DREG_LCEIS2
, D40_DREG_LCICR2
, true, 64},
899 {D40_DREG_LCEIS3
, D40_DREG_LCICR3
, true, 96},
900 {D40_DREG_PCTIS
, D40_DREG_PCICR
, false, D40_PHY_CHAN
},
901 {D40_DREG_PCEIS
, D40_DREG_PCICR
, true, D40_PHY_CHAN
},
905 u32 regs
[ARRAY_SIZE(il
)];
910 struct d40_chan
*d40c
;
912 struct d40_base
*base
= data
;
914 spin_lock_irqsave(&base
->interrupt_lock
, flags
);
916 /* Read interrupt status of both logical and physical channels */
917 for (i
= 0; i
< ARRAY_SIZE(il
); i
++)
918 regs
[i
] = readl(base
->virtbase
+ il
[i
].src
);
922 chan
= find_next_bit((unsigned long *)regs
,
923 BITS_PER_LONG
* ARRAY_SIZE(il
), chan
+ 1);
925 /* No more set bits found? */
926 if (chan
== BITS_PER_LONG
* ARRAY_SIZE(il
))
929 row
= chan
/ BITS_PER_LONG
;
930 idx
= chan
& (BITS_PER_LONG
- 1);
933 tmp
= readl(base
->virtbase
+ il
[row
].clr
);
935 writel(tmp
, base
->virtbase
+ il
[row
].clr
);
937 if (il
[row
].offset
== D40_PHY_CHAN
)
938 d40c
= base
->lookup_phy_chans
[idx
];
940 d40c
= base
->lookup_log_chans
[il
[row
].offset
+ idx
];
941 spin_lock(&d40c
->lock
);
943 if (!il
[row
].is_error
)
947 "[%s] IRQ chan: %ld offset %d idx %d\n",
948 __func__
, chan
, il
[row
].offset
, idx
);
950 spin_unlock(&d40c
->lock
);
953 spin_unlock_irqrestore(&base
->interrupt_lock
, flags
);
959 static int d40_validate_conf(struct d40_chan
*d40c
,
960 struct stedma40_chan_cfg
*conf
)
963 u32 dst_event_group
= D40_TYPE_TO_GROUP(conf
->dst_dev_type
);
964 u32 src_event_group
= D40_TYPE_TO_GROUP(conf
->src_dev_type
);
965 bool is_log
= (conf
->channel_type
& STEDMA40_CHANNEL_IN_OPER_MODE
)
966 == STEDMA40_CHANNEL_IN_LOG_MODE
;
968 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
&&
969 dst_event_group
== STEDMA40_DEV_DST_MEMORY
) {
970 dev_err(&d40c
->chan
.dev
->device
, "[%s] Invalid dst\n",
975 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
&&
976 src_event_group
== STEDMA40_DEV_SRC_MEMORY
) {
977 dev_err(&d40c
->chan
.dev
->device
, "[%s] Invalid src\n",
982 if (src_event_group
== STEDMA40_DEV_SRC_MEMORY
&&
983 dst_event_group
== STEDMA40_DEV_DST_MEMORY
&& is_log
) {
984 dev_err(&d40c
->chan
.dev
->device
,
985 "[%s] No event line\n", __func__
);
989 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
&&
990 (src_event_group
!= dst_event_group
)) {
991 dev_err(&d40c
->chan
.dev
->device
,
992 "[%s] Invalid event group\n", __func__
);
996 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
) {
998 * DMAC HW supports it. Will be added to this driver,
999 * in case any dma client requires it.
1001 dev_err(&d40c
->chan
.dev
->device
,
1002 "[%s] periph to periph not supported\n",
1010 static bool d40_alloc_mask_set(struct d40_phy_res
*phy
, bool is_src
,
1011 int log_event_line
, bool is_log
)
1013 unsigned long flags
;
1014 spin_lock_irqsave(&phy
->lock
, flags
);
1016 /* Physical interrupts are masked per physical full channel */
1017 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1018 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1019 phy
->allocated_dst
= D40_ALLOC_PHY
;
1020 phy
->allocated_src
= D40_ALLOC_PHY
;
1026 /* Logical channel */
1028 if (phy
->allocated_src
== D40_ALLOC_PHY
)
1031 if (phy
->allocated_src
== D40_ALLOC_FREE
)
1032 phy
->allocated_src
= D40_ALLOC_LOG_FREE
;
1034 if (!(phy
->allocated_src
& (1 << log_event_line
))) {
1035 phy
->allocated_src
|= 1 << log_event_line
;
1040 if (phy
->allocated_dst
== D40_ALLOC_PHY
)
1043 if (phy
->allocated_dst
== D40_ALLOC_FREE
)
1044 phy
->allocated_dst
= D40_ALLOC_LOG_FREE
;
1046 if (!(phy
->allocated_dst
& (1 << log_event_line
))) {
1047 phy
->allocated_dst
|= 1 << log_event_line
;
1054 spin_unlock_irqrestore(&phy
->lock
, flags
);
1057 spin_unlock_irqrestore(&phy
->lock
, flags
);
1061 static bool d40_alloc_mask_free(struct d40_phy_res
*phy
, bool is_src
,
1064 unsigned long flags
;
1065 bool is_free
= false;
1067 spin_lock_irqsave(&phy
->lock
, flags
);
1068 if (!log_event_line
) {
1069 /* Physical interrupts are masked per physical full channel */
1070 phy
->allocated_dst
= D40_ALLOC_FREE
;
1071 phy
->allocated_src
= D40_ALLOC_FREE
;
1076 /* Logical channel */
1078 phy
->allocated_src
&= ~(1 << log_event_line
);
1079 if (phy
->allocated_src
== D40_ALLOC_LOG_FREE
)
1080 phy
->allocated_src
= D40_ALLOC_FREE
;
1082 phy
->allocated_dst
&= ~(1 << log_event_line
);
1083 if (phy
->allocated_dst
== D40_ALLOC_LOG_FREE
)
1084 phy
->allocated_dst
= D40_ALLOC_FREE
;
1087 is_free
= ((phy
->allocated_src
| phy
->allocated_dst
) ==
1091 spin_unlock_irqrestore(&phy
->lock
, flags
);
1096 static int d40_allocate_channel(struct d40_chan
*d40c
)
1101 struct d40_phy_res
*phys
;
1106 bool is_log
= (d40c
->dma_cfg
.channel_type
&
1107 STEDMA40_CHANNEL_IN_OPER_MODE
)
1108 == STEDMA40_CHANNEL_IN_LOG_MODE
;
1111 phys
= d40c
->base
->phy_res
;
1113 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1114 dev_type
= d40c
->dma_cfg
.src_dev_type
;
1115 log_num
= 2 * dev_type
;
1117 } else if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1118 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1119 /* dst event lines are used for logical memcpy */
1120 dev_type
= d40c
->dma_cfg
.dst_dev_type
;
1121 log_num
= 2 * dev_type
+ 1;
1126 event_group
= D40_TYPE_TO_GROUP(dev_type
);
1127 event_line
= D40_TYPE_TO_EVENT(dev_type
);
1130 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1131 /* Find physical half channel */
1132 for (i
= 0; i
< d40c
->base
->num_phy_chans
; i
++) {
1134 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1139 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1140 int phy_num
= j
+ event_group
* 2;
1141 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1142 if (d40_alloc_mask_set(&phys
[i
],
1151 d40c
->phy_chan
= &phys
[i
];
1152 d40c
->log_num
= D40_PHY_CHAN
;
1158 /* Find logical channel */
1159 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1160 int phy_num
= j
+ event_group
* 2;
1162 * Spread logical channels across all available physical rather
1163 * than pack every logical channel at the first available phy
1167 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1168 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1169 event_line
, is_log
))
1173 for (i
= phy_num
+ 1; i
>= phy_num
; i
--) {
1174 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1175 event_line
, is_log
))
1183 d40c
->phy_chan
= &phys
[i
];
1184 d40c
->log_num
= log_num
;
1188 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = d40c
;
1190 d40c
->base
->lookup_phy_chans
[d40c
->phy_chan
->num
] = d40c
;
1196 static int d40_config_memcpy(struct d40_chan
*d40c
)
1198 dma_cap_mask_t cap
= d40c
->chan
.device
->cap_mask
;
1200 if (dma_has_cap(DMA_MEMCPY
, cap
) && !dma_has_cap(DMA_SLAVE
, cap
)) {
1201 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_log
;
1202 d40c
->dma_cfg
.src_dev_type
= STEDMA40_DEV_SRC_MEMORY
;
1203 d40c
->dma_cfg
.dst_dev_type
= d40c
->base
->plat_data
->
1204 memcpy
[d40c
->chan
.chan_id
];
1206 } else if (dma_has_cap(DMA_MEMCPY
, cap
) &&
1207 dma_has_cap(DMA_SLAVE
, cap
)) {
1208 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_phy
;
1210 dev_err(&d40c
->chan
.dev
->device
, "[%s] No memcpy\n",
1219 static int d40_free_dma(struct d40_chan
*d40c
)
1224 struct d40_phy_res
*phy
= d40c
->phy_chan
;
1227 struct d40_desc
*_d
;
1230 /* Terminate all queued and active transfers */
1233 /* Release client owned descriptors */
1234 if (!list_empty(&d40c
->client
))
1235 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
) {
1236 d40_pool_lli_free(d
);
1238 /* Return desc to free-list */
1239 d40_desc_free(d40c
, d
);
1243 dev_err(&d40c
->chan
.dev
->device
, "[%s] phy == null\n",
1248 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1249 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1250 dev_err(&d40c
->chan
.dev
->device
, "[%s] channel already free\n",
1255 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1256 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1257 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1259 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1260 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1263 dev_err(&d40c
->chan
.dev
->device
,
1264 "[%s] Unknown direction\n", __func__
);
1268 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1270 dev_err(&d40c
->chan
.dev
->device
, "[%s] suspend failed\n",
1275 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1276 /* Release logical channel, deactivate the event line */
1278 d40_config_set_event(d40c
, false);
1279 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = NULL
;
1282 * Check if there are more logical allocation
1283 * on this phy channel.
1285 if (!d40_alloc_mask_free(phy
, is_src
, event
)) {
1286 /* Resume the other logical channels if any */
1287 if (d40_chan_has_events(d40c
)) {
1288 res
= d40_channel_execute_command(d40c
,
1291 dev_err(&d40c
->chan
.dev
->device
,
1292 "[%s] Executing RUN command\n",
1300 (void) d40_alloc_mask_free(phy
, is_src
, 0);
1303 /* Release physical channel */
1304 res
= d40_channel_execute_command(d40c
, D40_DMA_STOP
);
1306 dev_err(&d40c
->chan
.dev
->device
,
1307 "[%s] Failed to stop channel\n", __func__
);
1310 d40c
->phy_chan
= NULL
;
1311 /* Invalidate channel type */
1312 d40c
->dma_cfg
.channel_type
= 0;
1313 d40c
->base
->lookup_phy_chans
[phy
->num
] = NULL
;
1318 static int d40_pause(struct dma_chan
*chan
)
1320 struct d40_chan
*d40c
=
1321 container_of(chan
, struct d40_chan
, chan
);
1323 unsigned long flags
;
1325 spin_lock_irqsave(&d40c
->lock
, flags
);
1327 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1329 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1330 d40_config_set_event(d40c
, false);
1331 /* Resume the other logical channels if any */
1332 if (d40_chan_has_events(d40c
))
1333 res
= d40_channel_execute_command(d40c
,
1338 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1342 static bool d40_is_paused(struct d40_chan
*d40c
)
1344 bool is_paused
= false;
1345 unsigned long flags
;
1346 void __iomem
*active_reg
;
1350 spin_lock_irqsave(&d40c
->lock
, flags
);
1352 if (d40c
->log_num
== D40_PHY_CHAN
) {
1353 if (d40c
->phy_chan
->num
% 2 == 0)
1354 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
1356 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
1358 status
= (readl(active_reg
) &
1359 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
1360 D40_CHAN_POS(d40c
->phy_chan
->num
);
1361 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
1367 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1368 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
)
1369 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1370 else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
1371 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1373 dev_err(&d40c
->chan
.dev
->device
,
1374 "[%s] Unknown direction\n", __func__
);
1377 status
= d40_chan_has_events(d40c
);
1378 status
= (status
& D40_EVENTLINE_MASK(event
)) >>
1379 D40_EVENTLINE_POS(event
);
1381 if (status
!= D40_DMA_RUN
)
1384 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1390 static bool d40_tx_is_linked(struct d40_chan
*d40c
)
1394 if (d40c
->log_num
!= D40_PHY_CHAN
)
1395 is_link
= readl(&d40c
->lcpa
->lcsp3
) & D40_MEM_LCSP3_DLOS_MASK
;
1397 is_link
= readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
1398 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
1399 D40_CHAN_REG_SDLNK
) &
1400 D40_SREG_LNK_PHYS_LNK_MASK
;
1404 static u32
d40_residue(struct d40_chan
*d40c
)
1408 if (d40c
->log_num
!= D40_PHY_CHAN
)
1409 num_elt
= (readl(&d40c
->lcpa
->lcsp2
) & D40_MEM_LCSP2_ECNT_MASK
)
1410 >> D40_MEM_LCSP2_ECNT_POS
;
1412 num_elt
= (readl(d40c
->base
->virtbase
+ D40_DREG_PCBASE
+
1413 d40c
->phy_chan
->num
* D40_DREG_PCDELTA
+
1414 D40_CHAN_REG_SDELT
) &
1415 D40_SREG_ELEM_PHY_ECNT_MASK
) >>
1416 D40_SREG_ELEM_PHY_ECNT_POS
;
1417 return num_elt
* (1 << d40c
->dma_cfg
.dst_info
.data_width
);
1420 static int d40_resume(struct dma_chan
*chan
)
1422 struct d40_chan
*d40c
=
1423 container_of(chan
, struct d40_chan
, chan
);
1425 unsigned long flags
;
1427 spin_lock_irqsave(&d40c
->lock
, flags
);
1429 /* If bytes left to transfer or linked tx resume job */
1430 if (d40_residue(d40c
) || d40_tx_is_linked(d40c
)) {
1431 if (d40c
->log_num
!= D40_PHY_CHAN
)
1432 d40_config_set_event(d40c
, true);
1433 res
= d40_channel_execute_command(d40c
, D40_DMA_RUN
);
1436 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1440 static u32
stedma40_residue(struct dma_chan
*chan
)
1442 struct d40_chan
*d40c
=
1443 container_of(chan
, struct d40_chan
, chan
);
1445 unsigned long flags
;
1447 spin_lock_irqsave(&d40c
->lock
, flags
);
1448 bytes_left
= d40_residue(d40c
);
1449 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1454 /* Public DMA functions in addition to the DMA engine framework */
1456 int stedma40_set_psize(struct dma_chan
*chan
,
1460 struct d40_chan
*d40c
=
1461 container_of(chan
, struct d40_chan
, chan
);
1462 unsigned long flags
;
1464 spin_lock_irqsave(&d40c
->lock
, flags
);
1466 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1467 d40c
->log_def
.lcsp1
&= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK
;
1468 d40c
->log_def
.lcsp3
&= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK
;
1469 d40c
->log_def
.lcsp1
|= src_psize
<<
1470 D40_MEM_LCSP1_SCFG_PSIZE_POS
;
1471 d40c
->log_def
.lcsp3
|= dst_psize
<<
1472 D40_MEM_LCSP1_SCFG_PSIZE_POS
;
1476 if (src_psize
== STEDMA40_PSIZE_PHY_1
)
1477 d40c
->src_def_cfg
&= ~(1 << D40_SREG_CFG_PHY_PEN_POS
);
1479 d40c
->src_def_cfg
|= 1 << D40_SREG_CFG_PHY_PEN_POS
;
1480 d40c
->src_def_cfg
&= ~(STEDMA40_PSIZE_PHY_16
<<
1481 D40_SREG_CFG_PSIZE_POS
);
1482 d40c
->src_def_cfg
|= src_psize
<< D40_SREG_CFG_PSIZE_POS
;
1485 if (dst_psize
== STEDMA40_PSIZE_PHY_1
)
1486 d40c
->dst_def_cfg
&= ~(1 << D40_SREG_CFG_PHY_PEN_POS
);
1488 d40c
->dst_def_cfg
|= 1 << D40_SREG_CFG_PHY_PEN_POS
;
1489 d40c
->dst_def_cfg
&= ~(STEDMA40_PSIZE_PHY_16
<<
1490 D40_SREG_CFG_PSIZE_POS
);
1491 d40c
->dst_def_cfg
|= dst_psize
<< D40_SREG_CFG_PSIZE_POS
;
1494 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1497 EXPORT_SYMBOL(stedma40_set_psize
);
1499 struct dma_async_tx_descriptor
*stedma40_memcpy_sg(struct dma_chan
*chan
,
1500 struct scatterlist
*sgl_dst
,
1501 struct scatterlist
*sgl_src
,
1502 unsigned int sgl_len
,
1503 unsigned long dma_flags
)
1506 struct d40_desc
*d40d
;
1507 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1509 unsigned long flags
;
1511 if (d40c
->phy_chan
== NULL
) {
1512 dev_err(&d40c
->chan
.dev
->device
,
1513 "[%s] Unallocated channel.\n", __func__
);
1514 return ERR_PTR(-EINVAL
);
1517 spin_lock_irqsave(&d40c
->lock
, flags
);
1518 d40d
= d40_desc_get(d40c
);
1523 d40d
->lli_len
= sgl_len
;
1524 d40d
->lli_tx_len
= d40d
->lli_len
;
1525 d40d
->txd
.flags
= dma_flags
;
1527 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1528 if (d40d
->lli_len
> d40c
->base
->plat_data
->llis_per_log
)
1529 d40d
->lli_tx_len
= d40c
->base
->plat_data
->llis_per_log
;
1533 * Check if there is space available in lcla. If not,
1534 * split list into 1-length and run only in lcpa
1537 if (d40_lcla_id_get(d40c
) != 0)
1538 d40d
->lli_tx_len
= 1;
1540 if (d40_pool_lli_alloc(d40d
, sgl_len
, true) < 0) {
1541 dev_err(&d40c
->chan
.dev
->device
,
1542 "[%s] Out of memory\n", __func__
);
1546 (void) d40_log_sg_to_lli(d40c
->lcla
.src_id
,
1550 d40c
->log_def
.lcsp1
,
1551 d40c
->dma_cfg
.src_info
.data_width
,
1552 dma_flags
& DMA_PREP_INTERRUPT
,
1554 d40c
->base
->plat_data
->llis_per_log
);
1556 (void) d40_log_sg_to_lli(d40c
->lcla
.dst_id
,
1560 d40c
->log_def
.lcsp3
,
1561 d40c
->dma_cfg
.dst_info
.data_width
,
1562 dma_flags
& DMA_PREP_INTERRUPT
,
1564 d40c
->base
->plat_data
->llis_per_log
);
1568 if (d40_pool_lli_alloc(d40d
, sgl_len
, false) < 0) {
1569 dev_err(&d40c
->chan
.dev
->device
,
1570 "[%s] Out of memory\n", __func__
);
1574 res
= d40_phy_sg_to_lli(sgl_src
,
1578 d40d
->lli_phy
.src_addr
,
1580 d40c
->dma_cfg
.src_info
.data_width
,
1581 d40c
->dma_cfg
.src_info
.psize
,
1587 res
= d40_phy_sg_to_lli(sgl_dst
,
1591 d40d
->lli_phy
.dst_addr
,
1593 d40c
->dma_cfg
.dst_info
.data_width
,
1594 d40c
->dma_cfg
.dst_info
.psize
,
1600 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
1601 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1604 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1606 d40d
->txd
.tx_submit
= d40_tx_submit
;
1608 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1612 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1615 EXPORT_SYMBOL(stedma40_memcpy_sg
);
1617 bool stedma40_filter(struct dma_chan
*chan
, void *data
)
1619 struct stedma40_chan_cfg
*info
= data
;
1620 struct d40_chan
*d40c
=
1621 container_of(chan
, struct d40_chan
, chan
);
1625 err
= d40_validate_conf(d40c
, info
);
1627 d40c
->dma_cfg
= *info
;
1629 err
= d40_config_memcpy(d40c
);
1633 EXPORT_SYMBOL(stedma40_filter
);
1635 /* DMA ENGINE functions */
1636 static int d40_alloc_chan_resources(struct dma_chan
*chan
)
1639 unsigned long flags
;
1640 struct d40_chan
*d40c
=
1641 container_of(chan
, struct d40_chan
, chan
);
1643 spin_lock_irqsave(&d40c
->lock
, flags
);
1645 d40c
->completed
= chan
->cookie
= 1;
1648 * If no dma configuration is set (channel_type == 0)
1649 * use default configuration (memcpy)
1651 if (d40c
->dma_cfg
.channel_type
== 0) {
1652 err
= d40_config_memcpy(d40c
);
1654 dev_err(&d40c
->chan
.dev
->device
,
1655 "[%s] Failed to configure memcpy channel\n",
1660 is_free_phy
= (d40c
->phy_chan
== NULL
);
1662 err
= d40_allocate_channel(d40c
);
1664 dev_err(&d40c
->chan
.dev
->device
,
1665 "[%s] Failed to allocate channel\n", __func__
);
1669 /* Fill in basic CFG register values */
1670 d40_phy_cfg(&d40c
->dma_cfg
, &d40c
->src_def_cfg
,
1671 &d40c
->dst_def_cfg
, d40c
->log_num
!= D40_PHY_CHAN
);
1673 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1674 d40_log_cfg(&d40c
->dma_cfg
,
1675 &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
1677 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
1678 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1679 d40c
->dma_cfg
.src_dev_type
* D40_LCPA_CHAN_SIZE
;
1681 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1682 d40c
->dma_cfg
.dst_dev_type
*
1683 D40_LCPA_CHAN_SIZE
+ D40_LCPA_CHAN_DST_DELTA
;
1687 * Only write channel configuration to the DMA if the physical
1688 * resource is free. In case of multiple logical channels
1689 * on the same physical resource, only the first write is necessary.
1692 err
= d40_config_write(d40c
);
1694 dev_err(&d40c
->chan
.dev
->device
,
1695 "[%s] Failed to configure channel\n",
1700 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1704 static void d40_free_chan_resources(struct dma_chan
*chan
)
1706 struct d40_chan
*d40c
=
1707 container_of(chan
, struct d40_chan
, chan
);
1709 unsigned long flags
;
1711 if (d40c
->phy_chan
== NULL
) {
1712 dev_err(&d40c
->chan
.dev
->device
,
1713 "[%s] Cannot free unallocated channel\n", __func__
);
1718 spin_lock_irqsave(&d40c
->lock
, flags
);
1720 err
= d40_free_dma(d40c
);
1723 dev_err(&d40c
->chan
.dev
->device
,
1724 "[%s] Failed to free channel\n", __func__
);
1725 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1728 static struct dma_async_tx_descriptor
*d40_prep_memcpy(struct dma_chan
*chan
,
1732 unsigned long dma_flags
)
1734 struct d40_desc
*d40d
;
1735 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1737 unsigned long flags
;
1740 if (d40c
->phy_chan
== NULL
) {
1741 dev_err(&d40c
->chan
.dev
->device
,
1742 "[%s] Channel is not allocated.\n", __func__
);
1743 return ERR_PTR(-EINVAL
);
1746 spin_lock_irqsave(&d40c
->lock
, flags
);
1747 d40d
= d40_desc_get(d40c
);
1750 dev_err(&d40c
->chan
.dev
->device
,
1751 "[%s] Descriptor is NULL\n", __func__
);
1755 d40d
->txd
.flags
= dma_flags
;
1757 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1759 d40d
->txd
.tx_submit
= d40_tx_submit
;
1761 if (d40c
->log_num
!= D40_PHY_CHAN
) {
1763 if (d40_pool_lli_alloc(d40d
, 1, true) < 0) {
1764 dev_err(&d40c
->chan
.dev
->device
,
1765 "[%s] Out of memory\n", __func__
);
1769 d40d
->lli_tx_len
= 1;
1771 d40_log_fill_lli(d40d
->lli_log
.src
,
1775 d40c
->log_def
.lcsp1
,
1776 d40c
->dma_cfg
.src_info
.data_width
,
1779 d40_log_fill_lli(d40d
->lli_log
.dst
,
1783 d40c
->log_def
.lcsp3
,
1784 d40c
->dma_cfg
.dst_info
.data_width
,
1789 if (d40_pool_lli_alloc(d40d
, 1, false) < 0) {
1790 dev_err(&d40c
->chan
.dev
->device
,
1791 "[%s] Out of memory\n", __func__
);
1795 err
= d40_phy_fill_lli(d40d
->lli_phy
.src
,
1798 d40c
->dma_cfg
.src_info
.psize
,
1802 d40c
->dma_cfg
.src_info
.data_width
,
1807 err
= d40_phy_fill_lli(d40d
->lli_phy
.dst
,
1810 d40c
->dma_cfg
.dst_info
.psize
,
1814 d40c
->dma_cfg
.dst_info
.data_width
,
1820 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
1821 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1824 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1828 dev_err(&d40c
->chan
.dev
->device
,
1829 "[%s] Failed filling in PHY LLI\n", __func__
);
1830 d40_pool_lli_free(d40d
);
1832 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1836 static int d40_prep_slave_sg_log(struct d40_desc
*d40d
,
1837 struct d40_chan
*d40c
,
1838 struct scatterlist
*sgl
,
1839 unsigned int sg_len
,
1840 enum dma_data_direction direction
,
1841 unsigned long dma_flags
)
1843 dma_addr_t dev_addr
= 0;
1846 if (d40_pool_lli_alloc(d40d
, sg_len
, true) < 0) {
1847 dev_err(&d40c
->chan
.dev
->device
,
1848 "[%s] Out of memory\n", __func__
);
1852 d40d
->lli_len
= sg_len
;
1853 if (d40d
->lli_len
<= d40c
->base
->plat_data
->llis_per_log
)
1854 d40d
->lli_tx_len
= d40d
->lli_len
;
1856 d40d
->lli_tx_len
= d40c
->base
->plat_data
->llis_per_log
;
1860 * Check if there is space available in lcla.
1861 * If not, split list into 1-length and run only
1864 if (d40_lcla_id_get(d40c
) != 0)
1865 d40d
->lli_tx_len
= 1;
1867 if (direction
== DMA_FROM_DEVICE
)
1868 dev_addr
= d40c
->base
->plat_data
->dev_rx
[d40c
->dma_cfg
.src_dev_type
];
1869 else if (direction
== DMA_TO_DEVICE
)
1870 dev_addr
= d40c
->base
->plat_data
->dev_tx
[d40c
->dma_cfg
.dst_dev_type
];
1874 total_size
= d40_log_sg_to_dev(&d40c
->lcla
,
1878 d40c
->dma_cfg
.src_info
.data_width
,
1879 d40c
->dma_cfg
.dst_info
.data_width
,
1881 dma_flags
& DMA_PREP_INTERRUPT
,
1882 dev_addr
, d40d
->lli_tx_len
,
1883 d40c
->base
->plat_data
->llis_per_log
);
1891 static int d40_prep_slave_sg_phy(struct d40_desc
*d40d
,
1892 struct d40_chan
*d40c
,
1893 struct scatterlist
*sgl
,
1894 unsigned int sgl_len
,
1895 enum dma_data_direction direction
,
1896 unsigned long dma_flags
)
1898 dma_addr_t src_dev_addr
;
1899 dma_addr_t dst_dev_addr
;
1902 if (d40_pool_lli_alloc(d40d
, sgl_len
, false) < 0) {
1903 dev_err(&d40c
->chan
.dev
->device
,
1904 "[%s] Out of memory\n", __func__
);
1908 d40d
->lli_len
= sgl_len
;
1909 d40d
->lli_tx_len
= sgl_len
;
1911 if (direction
== DMA_FROM_DEVICE
) {
1913 src_dev_addr
= d40c
->base
->plat_data
->dev_rx
[d40c
->dma_cfg
.src_dev_type
];
1914 } else if (direction
== DMA_TO_DEVICE
) {
1915 dst_dev_addr
= d40c
->base
->plat_data
->dev_tx
[d40c
->dma_cfg
.dst_dev_type
];
1920 res
= d40_phy_sg_to_lli(sgl
,
1924 d40d
->lli_phy
.src_addr
,
1926 d40c
->dma_cfg
.src_info
.data_width
,
1927 d40c
->dma_cfg
.src_info
.psize
,
1932 res
= d40_phy_sg_to_lli(sgl
,
1936 d40d
->lli_phy
.dst_addr
,
1938 d40c
->dma_cfg
.dst_info
.data_width
,
1939 d40c
->dma_cfg
.dst_info
.psize
,
1944 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
1945 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1949 static struct dma_async_tx_descriptor
*d40_prep_slave_sg(struct dma_chan
*chan
,
1950 struct scatterlist
*sgl
,
1951 unsigned int sg_len
,
1952 enum dma_data_direction direction
,
1953 unsigned long dma_flags
)
1955 struct d40_desc
*d40d
;
1956 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1958 unsigned long flags
;
1961 if (d40c
->phy_chan
== NULL
) {
1962 dev_err(&d40c
->chan
.dev
->device
,
1963 "[%s] Cannot prepare unallocated channel\n", __func__
);
1964 return ERR_PTR(-EINVAL
);
1967 if (d40c
->dma_cfg
.pre_transfer
)
1968 d40c
->dma_cfg
.pre_transfer(chan
,
1969 d40c
->dma_cfg
.pre_transfer_data
,
1972 spin_lock_irqsave(&d40c
->lock
, flags
);
1973 d40d
= d40_desc_get(d40c
);
1974 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1979 if (d40c
->log_num
!= D40_PHY_CHAN
)
1980 err
= d40_prep_slave_sg_log(d40d
, d40c
, sgl
, sg_len
,
1981 direction
, dma_flags
);
1983 err
= d40_prep_slave_sg_phy(d40d
, d40c
, sgl
, sg_len
,
1984 direction
, dma_flags
);
1986 dev_err(&d40c
->chan
.dev
->device
,
1987 "[%s] Failed to prepare %s slave sg job: %d\n",
1989 d40c
->log_num
!= D40_PHY_CHAN
? "log" : "phy", err
);
1993 d40d
->txd
.flags
= dma_flags
;
1995 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1997 d40d
->txd
.tx_submit
= d40_tx_submit
;
2002 static enum dma_status
d40_tx_status(struct dma_chan
*chan
,
2003 dma_cookie_t cookie
,
2004 struct dma_tx_state
*txstate
)
2006 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2007 dma_cookie_t last_used
;
2008 dma_cookie_t last_complete
;
2011 if (d40c
->phy_chan
== NULL
) {
2012 dev_err(&d40c
->chan
.dev
->device
,
2013 "[%s] Cannot read status of unallocated channel\n",
2018 last_complete
= d40c
->completed
;
2019 last_used
= chan
->cookie
;
2021 if (d40_is_paused(d40c
))
2024 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
2026 dma_set_tx_state(txstate
, last_complete
, last_used
,
2027 stedma40_residue(chan
));
2032 static void d40_issue_pending(struct dma_chan
*chan
)
2034 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2035 unsigned long flags
;
2037 if (d40c
->phy_chan
== NULL
) {
2038 dev_err(&d40c
->chan
.dev
->device
,
2039 "[%s] Channel is not allocated!\n", __func__
);
2043 spin_lock_irqsave(&d40c
->lock
, flags
);
2045 /* Busy means that pending jobs are already being processed */
2047 (void) d40_queue_start(d40c
);
2049 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2052 static int d40_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
2055 unsigned long flags
;
2056 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2058 if (d40c
->phy_chan
== NULL
) {
2059 dev_err(&d40c
->chan
.dev
->device
,
2060 "[%s] Channel is not allocated!\n", __func__
);
2065 case DMA_TERMINATE_ALL
:
2066 spin_lock_irqsave(&d40c
->lock
, flags
);
2068 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2071 return d40_pause(chan
);
2073 return d40_resume(chan
);
2076 /* Other commands are unimplemented */
2080 /* Initialization functions */
2082 static void __init
d40_chan_init(struct d40_base
*base
, struct dma_device
*dma
,
2083 struct d40_chan
*chans
, int offset
,
2087 struct d40_chan
*d40c
;
2089 INIT_LIST_HEAD(&dma
->channels
);
2091 for (i
= offset
; i
< offset
+ num_chans
; i
++) {
2094 d40c
->chan
.device
= dma
;
2096 /* Invalidate lcla element */
2097 d40c
->lcla
.src_id
= -1;
2098 d40c
->lcla
.dst_id
= -1;
2100 spin_lock_init(&d40c
->lock
);
2102 d40c
->log_num
= D40_PHY_CHAN
;
2104 INIT_LIST_HEAD(&d40c
->active
);
2105 INIT_LIST_HEAD(&d40c
->queue
);
2106 INIT_LIST_HEAD(&d40c
->client
);
2108 tasklet_init(&d40c
->tasklet
, dma_tasklet
,
2109 (unsigned long) d40c
);
2111 list_add_tail(&d40c
->chan
.device_node
,
2116 static int __init
d40_dmaengine_init(struct d40_base
*base
,
2117 int num_reserved_chans
)
2121 d40_chan_init(base
, &base
->dma_slave
, base
->log_chans
,
2122 0, base
->num_log_chans
);
2124 dma_cap_zero(base
->dma_slave
.cap_mask
);
2125 dma_cap_set(DMA_SLAVE
, base
->dma_slave
.cap_mask
);
2127 base
->dma_slave
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2128 base
->dma_slave
.device_free_chan_resources
= d40_free_chan_resources
;
2129 base
->dma_slave
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2130 base
->dma_slave
.device_prep_slave_sg
= d40_prep_slave_sg
;
2131 base
->dma_slave
.device_tx_status
= d40_tx_status
;
2132 base
->dma_slave
.device_issue_pending
= d40_issue_pending
;
2133 base
->dma_slave
.device_control
= d40_control
;
2134 base
->dma_slave
.dev
= base
->dev
;
2136 err
= dma_async_device_register(&base
->dma_slave
);
2140 "[%s] Failed to register slave channels\n",
2145 d40_chan_init(base
, &base
->dma_memcpy
, base
->log_chans
,
2146 base
->num_log_chans
, base
->plat_data
->memcpy_len
);
2148 dma_cap_zero(base
->dma_memcpy
.cap_mask
);
2149 dma_cap_set(DMA_MEMCPY
, base
->dma_memcpy
.cap_mask
);
2151 base
->dma_memcpy
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2152 base
->dma_memcpy
.device_free_chan_resources
= d40_free_chan_resources
;
2153 base
->dma_memcpy
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2154 base
->dma_memcpy
.device_prep_slave_sg
= d40_prep_slave_sg
;
2155 base
->dma_memcpy
.device_tx_status
= d40_tx_status
;
2156 base
->dma_memcpy
.device_issue_pending
= d40_issue_pending
;
2157 base
->dma_memcpy
.device_control
= d40_control
;
2158 base
->dma_memcpy
.dev
= base
->dev
;
2160 * This controller can only access address at even
2161 * 32bit boundaries, i.e. 2^2
2163 base
->dma_memcpy
.copy_align
= 2;
2165 err
= dma_async_device_register(&base
->dma_memcpy
);
2169 "[%s] Failed to regsiter memcpy only channels\n",
2174 d40_chan_init(base
, &base
->dma_both
, base
->phy_chans
,
2175 0, num_reserved_chans
);
2177 dma_cap_zero(base
->dma_both
.cap_mask
);
2178 dma_cap_set(DMA_SLAVE
, base
->dma_both
.cap_mask
);
2179 dma_cap_set(DMA_MEMCPY
, base
->dma_both
.cap_mask
);
2181 base
->dma_both
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2182 base
->dma_both
.device_free_chan_resources
= d40_free_chan_resources
;
2183 base
->dma_both
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2184 base
->dma_both
.device_prep_slave_sg
= d40_prep_slave_sg
;
2185 base
->dma_both
.device_tx_status
= d40_tx_status
;
2186 base
->dma_both
.device_issue_pending
= d40_issue_pending
;
2187 base
->dma_both
.device_control
= d40_control
;
2188 base
->dma_both
.dev
= base
->dev
;
2189 base
->dma_both
.copy_align
= 2;
2190 err
= dma_async_device_register(&base
->dma_both
);
2194 "[%s] Failed to register logical and physical capable channels\n",
2200 dma_async_device_unregister(&base
->dma_memcpy
);
2202 dma_async_device_unregister(&base
->dma_slave
);
2207 /* Initialization functions. */
2209 static int __init
d40_phy_res_init(struct d40_base
*base
)
2212 int num_phy_chans_avail
= 0;
2214 int odd_even_bit
= -2;
2216 val
[0] = readl(base
->virtbase
+ D40_DREG_PRSME
);
2217 val
[1] = readl(base
->virtbase
+ D40_DREG_PRSMO
);
2219 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2220 base
->phy_res
[i
].num
= i
;
2221 odd_even_bit
+= 2 * ((i
% 2) == 0);
2222 if (((val
[i
% 2] >> odd_even_bit
) & 3) == 1) {
2223 /* Mark security only channels as occupied */
2224 base
->phy_res
[i
].allocated_src
= D40_ALLOC_PHY
;
2225 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_PHY
;
2227 base
->phy_res
[i
].allocated_src
= D40_ALLOC_FREE
;
2228 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_FREE
;
2229 num_phy_chans_avail
++;
2231 spin_lock_init(&base
->phy_res
[i
].lock
);
2233 dev_info(base
->dev
, "%d of %d physical DMA channels available\n",
2234 num_phy_chans_avail
, base
->num_phy_chans
);
2236 /* Verify settings extended vs standard */
2237 val
[0] = readl(base
->virtbase
+ D40_DREG_PRTYP
);
2239 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2241 if (base
->phy_res
[i
].allocated_src
== D40_ALLOC_FREE
&&
2242 (val
[0] & 0x3) != 1)
2244 "[%s] INFO: channel %d is misconfigured (%d)\n",
2245 __func__
, i
, val
[0] & 0x3);
2247 val
[0] = val
[0] >> 2;
2250 return num_phy_chans_avail
;
2253 static struct d40_base
* __init
d40_hw_detect_init(struct platform_device
*pdev
)
2255 static const struct d40_reg_val dma_id_regs
[] = {
2257 { .reg
= D40_DREG_PERIPHID0
, .val
= 0x0040},
2258 { .reg
= D40_DREG_PERIPHID1
, .val
= 0x0000},
2260 * D40_DREG_PERIPHID2 Depends on HW revision:
2261 * MOP500/HREF ED has 0x0008,
2263 * HREF V1 has 0x0028
2265 { .reg
= D40_DREG_PERIPHID3
, .val
= 0x0000},
2268 { .reg
= D40_DREG_CELLID0
, .val
= 0x000d},
2269 { .reg
= D40_DREG_CELLID1
, .val
= 0x00f0},
2270 { .reg
= D40_DREG_CELLID2
, .val
= 0x0005},
2271 { .reg
= D40_DREG_CELLID3
, .val
= 0x00b1}
2273 struct stedma40_platform_data
*plat_data
;
2274 struct clk
*clk
= NULL
;
2275 void __iomem
*virtbase
= NULL
;
2276 struct resource
*res
= NULL
;
2277 struct d40_base
*base
= NULL
;
2278 int num_log_chans
= 0;
2282 clk
= clk_get(&pdev
->dev
, NULL
);
2285 dev_err(&pdev
->dev
, "[%s] No matching clock found\n",
2292 /* Get IO for DMAC base address */
2293 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "base");
2297 if (request_mem_region(res
->start
, resource_size(res
),
2298 D40_NAME
" I/O base") == NULL
)
2301 virtbase
= ioremap(res
->start
, resource_size(res
));
2305 /* HW version check */
2306 for (i
= 0; i
< ARRAY_SIZE(dma_id_regs
); i
++) {
2307 if (dma_id_regs
[i
].val
!=
2308 readl(virtbase
+ dma_id_regs
[i
].reg
)) {
2310 "[%s] Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2314 readl(virtbase
+ dma_id_regs
[i
].reg
));
2319 i
= readl(virtbase
+ D40_DREG_PERIPHID2
);
2321 if ((i
& 0xf) != D40_PERIPHID2_DESIGNER
) {
2323 "[%s] Unknown designer! Got %x wanted %x\n",
2324 __func__
, i
& 0xf, D40_PERIPHID2_DESIGNER
);
2328 /* The number of physical channels on this HW */
2329 num_phy_chans
= 4 * (readl(virtbase
+ D40_DREG_ICFG
) & 0x7) + 4;
2331 dev_info(&pdev
->dev
, "hardware revision: %d @ 0x%x\n",
2332 (i
>> 4) & 0xf, res
->start
);
2334 plat_data
= pdev
->dev
.platform_data
;
2336 /* Count the number of logical channels in use */
2337 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2338 if (plat_data
->dev_rx
[i
] != 0)
2341 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2342 if (plat_data
->dev_tx
[i
] != 0)
2345 base
= kzalloc(ALIGN(sizeof(struct d40_base
), 4) +
2346 (num_phy_chans
+ num_log_chans
+ plat_data
->memcpy_len
) *
2347 sizeof(struct d40_chan
), GFP_KERNEL
);
2350 dev_err(&pdev
->dev
, "[%s] Out of memory\n", __func__
);
2355 base
->num_phy_chans
= num_phy_chans
;
2356 base
->num_log_chans
= num_log_chans
;
2357 base
->phy_start
= res
->start
;
2358 base
->phy_size
= resource_size(res
);
2359 base
->virtbase
= virtbase
;
2360 base
->plat_data
= plat_data
;
2361 base
->dev
= &pdev
->dev
;
2362 base
->phy_chans
= ((void *)base
) + ALIGN(sizeof(struct d40_base
), 4);
2363 base
->log_chans
= &base
->phy_chans
[num_phy_chans
];
2365 base
->phy_res
= kzalloc(num_phy_chans
* sizeof(struct d40_phy_res
),
2370 base
->lookup_phy_chans
= kzalloc(num_phy_chans
*
2371 sizeof(struct d40_chan
*),
2373 if (!base
->lookup_phy_chans
)
2376 if (num_log_chans
+ plat_data
->memcpy_len
) {
2378 * The max number of logical channels are event lines for all
2379 * src devices and dst devices
2381 base
->lookup_log_chans
= kzalloc(plat_data
->dev_len
* 2 *
2382 sizeof(struct d40_chan
*),
2384 if (!base
->lookup_log_chans
)
2387 base
->lcla_pool
.alloc_map
= kzalloc(num_phy_chans
* sizeof(u32
),
2389 if (!base
->lcla_pool
.alloc_map
)
2392 base
->desc_slab
= kmem_cache_create(D40_NAME
, sizeof(struct d40_desc
),
2393 0, SLAB_HWCACHE_ALIGN
,
2395 if (base
->desc_slab
== NULL
)
2408 release_mem_region(res
->start
,
2409 resource_size(res
));
2414 kfree(base
->lcla_pool
.alloc_map
);
2415 kfree(base
->lookup_log_chans
);
2416 kfree(base
->lookup_phy_chans
);
2417 kfree(base
->phy_res
);
2424 static void __init
d40_hw_init(struct d40_base
*base
)
2427 static const struct d40_reg_val dma_init_reg
[] = {
2428 /* Clock every part of the DMA block from start */
2429 { .reg
= D40_DREG_GCC
, .val
= 0x0000ff01},
2431 /* Interrupts on all logical channels */
2432 { .reg
= D40_DREG_LCMIS0
, .val
= 0xFFFFFFFF},
2433 { .reg
= D40_DREG_LCMIS1
, .val
= 0xFFFFFFFF},
2434 { .reg
= D40_DREG_LCMIS2
, .val
= 0xFFFFFFFF},
2435 { .reg
= D40_DREG_LCMIS3
, .val
= 0xFFFFFFFF},
2436 { .reg
= D40_DREG_LCICR0
, .val
= 0xFFFFFFFF},
2437 { .reg
= D40_DREG_LCICR1
, .val
= 0xFFFFFFFF},
2438 { .reg
= D40_DREG_LCICR2
, .val
= 0xFFFFFFFF},
2439 { .reg
= D40_DREG_LCICR3
, .val
= 0xFFFFFFFF},
2440 { .reg
= D40_DREG_LCTIS0
, .val
= 0xFFFFFFFF},
2441 { .reg
= D40_DREG_LCTIS1
, .val
= 0xFFFFFFFF},
2442 { .reg
= D40_DREG_LCTIS2
, .val
= 0xFFFFFFFF},
2443 { .reg
= D40_DREG_LCTIS3
, .val
= 0xFFFFFFFF}
2446 u32 prmseo
[2] = {0, 0};
2447 u32 activeo
[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2451 for (i
= 0; i
< ARRAY_SIZE(dma_init_reg
); i
++)
2452 writel(dma_init_reg
[i
].val
,
2453 base
->virtbase
+ dma_init_reg
[i
].reg
);
2455 /* Configure all our dma channels to default settings */
2456 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2458 activeo
[i
% 2] = activeo
[i
% 2] << 2;
2460 if (base
->phy_res
[base
->num_phy_chans
- i
- 1].allocated_src
2462 activeo
[i
% 2] |= 3;
2466 /* Enable interrupt # */
2467 pcmis
= (pcmis
<< 1) | 1;
2469 /* Clear interrupt # */
2470 pcicr
= (pcicr
<< 1) | 1;
2472 /* Set channel to physical mode */
2473 prmseo
[i
% 2] = prmseo
[i
% 2] << 2;
2478 writel(prmseo
[1], base
->virtbase
+ D40_DREG_PRMSE
);
2479 writel(prmseo
[0], base
->virtbase
+ D40_DREG_PRMSO
);
2480 writel(activeo
[1], base
->virtbase
+ D40_DREG_ACTIVE
);
2481 writel(activeo
[0], base
->virtbase
+ D40_DREG_ACTIVO
);
2483 /* Write which interrupt to enable */
2484 writel(pcmis
, base
->virtbase
+ D40_DREG_PCMIS
);
2486 /* Write which interrupt to clear */
2487 writel(pcicr
, base
->virtbase
+ D40_DREG_PCICR
);
2491 static int __init
d40_lcla_allocate(struct d40_base
*base
)
2493 unsigned long *page_list
;
2498 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2499 * To full fill this hardware requirement without wasting 256 kb
2500 * we allocate pages until we get an aligned one.
2502 page_list
= kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS
,
2510 /* Calculating how many pages that are required */
2511 base
->lcla_pool
.pages
= SZ_1K
* base
->num_phy_chans
/ PAGE_SIZE
;
2513 for (i
= 0; i
< MAX_LCLA_ALLOC_ATTEMPTS
; i
++) {
2514 page_list
[i
] = __get_free_pages(GFP_KERNEL
,
2515 base
->lcla_pool
.pages
);
2516 if (!page_list
[i
]) {
2519 "[%s] Failed to allocate %d pages.\n",
2520 __func__
, base
->lcla_pool
.pages
);
2522 for (j
= 0; j
< i
; j
++)
2523 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2527 if ((virt_to_phys((void *)page_list
[i
]) &
2528 (LCLA_ALIGNMENT
- 1)) == 0)
2532 for (j
= 0; j
< i
; j
++)
2533 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2535 if (i
< MAX_LCLA_ALLOC_ATTEMPTS
) {
2536 base
->lcla_pool
.base
= (void *)page_list
[i
];
2538 /* After many attempts, no succees with finding the correct
2539 * alignment try with allocating a big buffer */
2541 "[%s] Failed to get %d pages @ 18 bit align.\n",
2542 __func__
, base
->lcla_pool
.pages
);
2543 base
->lcla_pool
.base_unaligned
= kmalloc(SZ_1K
*
2544 base
->num_phy_chans
+
2547 if (!base
->lcla_pool
.base_unaligned
) {
2552 base
->lcla_pool
.base
= PTR_ALIGN(base
->lcla_pool
.base_unaligned
,
2556 writel(virt_to_phys(base
->lcla_pool
.base
),
2557 base
->virtbase
+ D40_DREG_LCLA
);
2563 static int __init
d40_probe(struct platform_device
*pdev
)
2567 struct d40_base
*base
;
2568 struct resource
*res
= NULL
;
2569 int num_reserved_chans
;
2572 base
= d40_hw_detect_init(pdev
);
2577 num_reserved_chans
= d40_phy_res_init(base
);
2579 platform_set_drvdata(pdev
, base
);
2581 spin_lock_init(&base
->interrupt_lock
);
2582 spin_lock_init(&base
->execmd_lock
);
2584 /* Get IO for logical channel parameter address */
2585 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "lcpa");
2589 "[%s] No \"lcpa\" memory resource\n",
2593 base
->lcpa_size
= resource_size(res
);
2594 base
->phy_lcpa
= res
->start
;
2596 if (request_mem_region(res
->start
, resource_size(res
),
2597 D40_NAME
" I/O lcpa") == NULL
) {
2600 "[%s] Failed to request LCPA region 0x%x-0x%x\n",
2601 __func__
, res
->start
, res
->end
);
2605 /* We make use of ESRAM memory for this. */
2606 val
= readl(base
->virtbase
+ D40_DREG_LCPA
);
2607 if (res
->start
!= val
&& val
!= 0) {
2608 dev_warn(&pdev
->dev
,
2609 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2610 __func__
, val
, res
->start
);
2612 writel(res
->start
, base
->virtbase
+ D40_DREG_LCPA
);
2614 base
->lcpa_base
= ioremap(res
->start
, resource_size(res
));
2615 if (!base
->lcpa_base
) {
2618 "[%s] Failed to ioremap LCPA region\n",
2623 ret
= d40_lcla_allocate(base
);
2625 dev_err(&pdev
->dev
, "[%s] Failed to allocate LCLA area\n",
2630 spin_lock_init(&base
->lcla_pool
.lock
);
2632 base
->lcla_pool
.num_blocks
= base
->num_phy_chans
;
2634 base
->irq
= platform_get_irq(pdev
, 0);
2636 ret
= request_irq(base
->irq
, d40_handle_interrupt
, 0, D40_NAME
, base
);
2639 dev_err(&pdev
->dev
, "[%s] No IRQ defined\n", __func__
);
2643 err
= d40_dmaengine_init(base
, num_reserved_chans
);
2649 dev_info(base
->dev
, "initialized\n");
2654 if (base
->desc_slab
)
2655 kmem_cache_destroy(base
->desc_slab
);
2657 iounmap(base
->virtbase
);
2658 if (!base
->lcla_pool
.base_unaligned
&& base
->lcla_pool
.base
)
2659 free_pages((unsigned long)base
->lcla_pool
.base
,
2660 base
->lcla_pool
.pages
);
2661 if (base
->lcla_pool
.base_unaligned
)
2662 kfree(base
->lcla_pool
.base_unaligned
);
2664 release_mem_region(base
->phy_lcpa
,
2666 if (base
->phy_start
)
2667 release_mem_region(base
->phy_start
,
2670 clk_disable(base
->clk
);
2674 kfree(base
->lcla_pool
.alloc_map
);
2675 kfree(base
->lookup_log_chans
);
2676 kfree(base
->lookup_phy_chans
);
2677 kfree(base
->phy_res
);
2681 dev_err(&pdev
->dev
, "[%s] probe failed\n", __func__
);
2685 static struct platform_driver d40_driver
= {
2687 .owner
= THIS_MODULE
,
2692 int __init
stedma40_init(void)
2694 return platform_driver_probe(&d40_driver
, d40_probe
);
2696 arch_initcall(stedma40_init
);