2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
9 #include <linux/kernel.h>
10 #include <linux/slab.h>
11 #include <linux/dmaengine.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
17 #include <plat/ste_dma40.h>
19 #include "ste_dma40_ll.h"
21 #define D40_NAME "dma40"
23 #define D40_PHY_CHAN -1
25 /* For masking out/in 2 bit channel positions */
26 #define D40_CHAN_POS(chan) (2 * (chan / 2))
27 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
29 /* Maximum iterations taken before giving up suspending a channel */
30 #define D40_SUSPEND_MAX_IT 500
32 /* Hardware requirement on LCLA alignment */
33 #define LCLA_ALIGNMENT 0x40000
35 /* Max number of links per event group */
36 #define D40_LCLA_LINK_PER_EVENT_GRP 128
37 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
39 /* Attempts before giving up to trying to get pages that are aligned */
40 #define MAX_LCLA_ALLOC_ATTEMPTS 256
42 /* Bit markings for allocation map */
43 #define D40_ALLOC_FREE (1 << 31)
44 #define D40_ALLOC_PHY (1 << 30)
45 #define D40_ALLOC_LOG_FREE 0
47 /* Hardware designer of the block */
48 #define D40_HW_DESIGNER 0x8
51 * enum 40_command - The different commands and/or statuses.
53 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
61 D40_DMA_SUSPEND_REQ
= 2,
66 * struct d40_lli_pool - Structure for keeping LLIs in memory
68 * @base: Pointer to memory area when the pre_alloc_lli's are not large
69 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70 * pre_alloc_lli is used.
71 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
72 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
73 * one buffer to one buffer.
78 /* Space for dst and src, plus an extra for padding */
79 u8 pre_alloc_lli
[3 * sizeof(struct d40_phy_lli
)];
83 * struct d40_desc - A descriptor is one DMA job.
85 * @lli_phy: LLI settings for physical channel. Both src and dst=
86 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
88 * @lli_log: Same as above but for logical channels.
89 * @lli_pool: The pool with two entries pre-allocated.
90 * @lli_len: Number of llis of current descriptor.
91 * @lli_current: Number of transfered llis.
92 * @lcla_alloc: Number of LCLA entries allocated.
93 * @txd: DMA engine struct. Used for among other things for communication
96 * @is_in_client_list: true if the client owns this descriptor.
99 * This descriptor is used for both logical and physical transfers.
103 struct d40_phy_lli_bidir lli_phy
;
105 struct d40_log_lli_bidir lli_log
;
107 struct d40_lli_pool lli_pool
;
112 struct dma_async_tx_descriptor txd
;
113 struct list_head node
;
115 bool is_in_client_list
;
119 * struct d40_lcla_pool - LCLA pool settings and data.
121 * @base: The virtual address of LCLA. 18 bit aligned.
122 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
123 * This pointer is only there for clean-up on error.
124 * @pages: The number of pages needed for all physical channels.
125 * Only used later for clean-up on error
126 * @lock: Lock to protect the content in this struct.
127 * @alloc_map: big map over which LCLA entry is own by which job.
129 struct d40_lcla_pool
{
132 void *base_unaligned
;
135 struct d40_desc
**alloc_map
;
139 * struct d40_phy_res - struct for handling eventlines mapped to physical
142 * @lock: A lock protection this entity.
143 * @num: The physical channel number of this entity.
144 * @allocated_src: Bit mapped to show which src event line's are mapped to
145 * this physical channel. Can also be free or physically allocated.
146 * @allocated_dst: Same as for src but is dst.
147 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
160 * struct d40_chan - Struct that describes a channel.
162 * @lock: A spinlock to protect this struct.
163 * @log_num: The logical number, if any of this channel.
164 * @completed: Starts with 1, after first interrupt it is set to dma engine's
166 * @pending_tx: The number of pending transfers. Used between interrupt handler
168 * @busy: Set to true when transfer is ongoing on this channel.
169 * @phy_chan: Pointer to physical channel which this instance runs on. If this
170 * point is NULL, then the channel is not allocated.
171 * @chan: DMA engine handle.
172 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
173 * transfer and call client callback.
174 * @client: Cliented owned descriptor list.
175 * @active: Active descriptor.
176 * @queue: Queued jobs.
177 * @dma_cfg: The client configuration of this dma channel.
178 * @configured: whether the dma_cfg configuration is valid
179 * @base: Pointer to the device instance struct.
180 * @src_def_cfg: Default cfg register setting for src.
181 * @dst_def_cfg: Default cfg register setting for dst.
182 * @log_def: Default logical channel settings.
183 * @lcla: Space for one dst src pair for logical channel transfers.
184 * @lcpa: Pointer to dst and src lcpa settings.
186 * This struct can either "be" a logical or a physical channel.
191 /* ID of the most recent completed transfer */
195 struct d40_phy_res
*phy_chan
;
196 struct dma_chan chan
;
197 struct tasklet_struct tasklet
;
198 struct list_head client
;
199 struct list_head active
;
200 struct list_head queue
;
201 struct stedma40_chan_cfg dma_cfg
;
203 struct d40_base
*base
;
204 /* Default register configurations */
207 struct d40_def_lcsp log_def
;
208 struct d40_log_lli_full
*lcpa
;
209 /* Runtime reconfiguration */
210 dma_addr_t runtime_addr
;
211 enum dma_data_direction runtime_direction
;
215 * struct d40_base - The big global struct, one for each probe'd instance.
217 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
218 * @execmd_lock: Lock for execute command usage since several channels share
219 * the same physical register.
220 * @dev: The device structure.
221 * @virtbase: The virtual base address of the DMA's register.
222 * @rev: silicon revision detected.
223 * @clk: Pointer to the DMA clock structure.
224 * @phy_start: Physical memory start of the DMA registers.
225 * @phy_size: Size of the DMA register map.
226 * @irq: The IRQ number.
227 * @num_phy_chans: The number of physical channels. Read from HW. This
228 * is the number of available channels for this driver, not counting "Secure
229 * mode" allocated physical channels.
230 * @num_log_chans: The number of logical channels. Calculated from
232 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
233 * @dma_slave: dma_device channels that can do only do slave transfers.
234 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
235 * @log_chans: Room for all possible logical channels in system.
236 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
237 * to log_chans entries.
238 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
239 * to phy_chans entries.
240 * @plat_data: Pointer to provided platform_data which is the driver
242 * @phy_res: Vector containing all physical channels.
243 * @lcla_pool: lcla pool settings and data.
244 * @lcpa_base: The virtual mapped address of LCPA.
245 * @phy_lcpa: The physical address of the LCPA.
246 * @lcpa_size: The size of the LCPA area.
247 * @desc_slab: cache for descriptors.
250 spinlock_t interrupt_lock
;
251 spinlock_t execmd_lock
;
253 void __iomem
*virtbase
;
256 phys_addr_t phy_start
;
257 resource_size_t phy_size
;
261 struct dma_device dma_both
;
262 struct dma_device dma_slave
;
263 struct dma_device dma_memcpy
;
264 struct d40_chan
*phy_chans
;
265 struct d40_chan
*log_chans
;
266 struct d40_chan
**lookup_log_chans
;
267 struct d40_chan
**lookup_phy_chans
;
268 struct stedma40_platform_data
*plat_data
;
269 /* Physical half channels */
270 struct d40_phy_res
*phy_res
;
271 struct d40_lcla_pool lcla_pool
;
274 resource_size_t lcpa_size
;
275 struct kmem_cache
*desc_slab
;
279 * struct d40_interrupt_lookup - lookup table for interrupt handler
281 * @src: Interrupt mask register.
282 * @clr: Interrupt clear register.
283 * @is_error: true if this is an error interrupt.
284 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
285 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
287 struct d40_interrupt_lookup
{
295 * struct d40_reg_val - simple lookup struct
297 * @reg: The register.
298 * @val: The value that belongs to the register in reg.
305 static struct device
*chan2dev(struct d40_chan
*d40c
)
307 return &d40c
->chan
.dev
->device
;
310 static bool chan_is_physical(struct d40_chan
*chan
)
312 return chan
->log_num
== D40_PHY_CHAN
;
315 static bool chan_is_logical(struct d40_chan
*chan
)
317 return !chan_is_physical(chan
);
320 static void __iomem
*chan_base(struct d40_chan
*chan
)
322 return chan
->base
->virtbase
+ D40_DREG_PCBASE
+
323 chan
->phy_chan
->num
* D40_DREG_PCDELTA
;
326 #define d40_err(dev, format, arg...) \
327 dev_err(dev, "[%s] " format, __func__, ## arg)
329 #define chan_err(d40c, format, arg...) \
330 d40_err(chan2dev(d40c), format, ## arg)
332 static int d40_pool_lli_alloc(struct d40_desc
*d40d
,
333 int lli_len
, bool is_log
)
339 align
= sizeof(struct d40_log_lli
);
341 align
= sizeof(struct d40_phy_lli
);
344 base
= d40d
->lli_pool
.pre_alloc_lli
;
345 d40d
->lli_pool
.size
= sizeof(d40d
->lli_pool
.pre_alloc_lli
);
346 d40d
->lli_pool
.base
= NULL
;
348 d40d
->lli_pool
.size
= lli_len
* 2 * align
;
350 base
= kmalloc(d40d
->lli_pool
.size
+ align
, GFP_NOWAIT
);
351 d40d
->lli_pool
.base
= base
;
353 if (d40d
->lli_pool
.base
== NULL
)
358 d40d
->lli_log
.src
= PTR_ALIGN((struct d40_log_lli
*) base
,
360 d40d
->lli_log
.dst
= d40d
->lli_log
.src
+ lli_len
;
362 d40d
->lli_phy
.src
= PTR_ALIGN((struct d40_phy_lli
*)base
,
364 d40d
->lli_phy
.dst
= d40d
->lli_phy
.src
+ lli_len
;
370 static void d40_pool_lli_free(struct d40_desc
*d40d
)
372 kfree(d40d
->lli_pool
.base
);
373 d40d
->lli_pool
.base
= NULL
;
374 d40d
->lli_pool
.size
= 0;
375 d40d
->lli_log
.src
= NULL
;
376 d40d
->lli_log
.dst
= NULL
;
377 d40d
->lli_phy
.src
= NULL
;
378 d40d
->lli_phy
.dst
= NULL
;
381 static int d40_lcla_alloc_one(struct d40_chan
*d40c
,
382 struct d40_desc
*d40d
)
389 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
391 p
= d40c
->phy_chan
->num
* D40_LCLA_LINK_PER_EVENT_GRP
;
394 * Allocate both src and dst at the same time, therefore the half
395 * start on 1 since 0 can't be used since zero is used as end marker.
397 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
398 if (!d40c
->base
->lcla_pool
.alloc_map
[p
+ i
]) {
399 d40c
->base
->lcla_pool
.alloc_map
[p
+ i
] = d40d
;
406 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
411 static int d40_lcla_free_all(struct d40_chan
*d40c
,
412 struct d40_desc
*d40d
)
418 if (chan_is_physical(d40c
))
421 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
423 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
424 if (d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
425 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] == d40d
) {
426 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
427 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] = NULL
;
429 if (d40d
->lcla_alloc
== 0) {
436 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
442 static void d40_desc_remove(struct d40_desc
*d40d
)
444 list_del(&d40d
->node
);
447 static struct d40_desc
*d40_desc_get(struct d40_chan
*d40c
)
449 struct d40_desc
*desc
= NULL
;
451 if (!list_empty(&d40c
->client
)) {
455 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
)
456 if (async_tx_test_ack(&d
->txd
)) {
457 d40_pool_lli_free(d
);
460 memset(desc
, 0, sizeof(*desc
));
466 desc
= kmem_cache_zalloc(d40c
->base
->desc_slab
, GFP_NOWAIT
);
469 INIT_LIST_HEAD(&desc
->node
);
474 static void d40_desc_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
477 d40_lcla_free_all(d40c
, d40d
);
478 kmem_cache_free(d40c
->base
->desc_slab
, d40d
);
481 static void d40_desc_submit(struct d40_chan
*d40c
, struct d40_desc
*desc
)
483 list_add_tail(&desc
->node
, &d40c
->active
);
486 static void d40_desc_load(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
488 int curr_lcla
= -EINVAL
, next_lcla
;
490 if (chan_is_physical(d40c
)) {
491 d40_phy_lli_write(d40c
->base
->virtbase
,
495 d40d
->lli_current
= d40d
->lli_len
;
498 if ((d40d
->lli_len
- d40d
->lli_current
) > 1)
499 curr_lcla
= d40_lcla_alloc_one(d40c
, d40d
);
501 d40_log_lli_lcpa_write(d40c
->lcpa
,
502 &d40d
->lli_log
.dst
[d40d
->lli_current
],
503 &d40d
->lli_log
.src
[d40d
->lli_current
],
507 for (; d40d
->lli_current
< d40d
->lli_len
; d40d
->lli_current
++) {
508 unsigned int lcla_offset
= d40c
->phy_chan
->num
* 1024 +
510 struct d40_lcla_pool
*pool
= &d40c
->base
->lcla_pool
;
511 struct d40_log_lli
*lcla
= pool
->base
+ lcla_offset
;
513 if (d40d
->lli_current
+ 1 < d40d
->lli_len
)
514 next_lcla
= d40_lcla_alloc_one(d40c
, d40d
);
518 d40_log_lli_lcla_write(lcla
,
519 &d40d
->lli_log
.dst
[d40d
->lli_current
],
520 &d40d
->lli_log
.src
[d40d
->lli_current
],
523 dma_sync_single_range_for_device(d40c
->base
->dev
,
524 pool
->dma_addr
, lcla_offset
,
525 2 * sizeof(struct d40_log_lli
),
528 curr_lcla
= next_lcla
;
530 if (curr_lcla
== -EINVAL
) {
539 static struct d40_desc
*d40_first_active_get(struct d40_chan
*d40c
)
543 if (list_empty(&d40c
->active
))
546 d
= list_first_entry(&d40c
->active
,
552 static void d40_desc_queue(struct d40_chan
*d40c
, struct d40_desc
*desc
)
554 list_add_tail(&desc
->node
, &d40c
->queue
);
557 static struct d40_desc
*d40_first_queued(struct d40_chan
*d40c
)
561 if (list_empty(&d40c
->queue
))
564 d
= list_first_entry(&d40c
->queue
,
570 static int d40_psize_2_burst_size(bool is_log
, int psize
)
573 if (psize
== STEDMA40_PSIZE_LOG_1
)
576 if (psize
== STEDMA40_PSIZE_PHY_1
)
584 * The dma only supports transmitting packages up to
585 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
586 * dma elements required to send the entire sg list
588 static int d40_size_2_dmalen(int size
, u32 data_width1
, u32 data_width2
)
591 u32 max_w
= max(data_width1
, data_width2
);
592 u32 min_w
= min(data_width1
, data_width2
);
593 u32 seg_max
= ALIGN(STEDMA40_MAX_SEG_SIZE
<< min_w
, 1 << max_w
);
595 if (seg_max
> STEDMA40_MAX_SEG_SIZE
)
596 seg_max
-= (1 << max_w
);
598 if (!IS_ALIGNED(size
, 1 << max_w
))
604 dmalen
= size
/ seg_max
;
605 if (dmalen
* seg_max
< size
)
611 static int d40_sg_2_dmalen(struct scatterlist
*sgl
, int sg_len
,
612 u32 data_width1
, u32 data_width2
)
614 struct scatterlist
*sg
;
619 for_each_sg(sgl
, sg
, sg_len
, i
) {
620 ret
= d40_size_2_dmalen(sg_dma_len(sg
),
621 data_width1
, data_width2
);
629 /* Support functions for logical channels */
631 static int d40_channel_execute_command(struct d40_chan
*d40c
,
632 enum d40_command command
)
636 void __iomem
*active_reg
;
641 spin_lock_irqsave(&d40c
->base
->execmd_lock
, flags
);
643 if (d40c
->phy_chan
->num
% 2 == 0)
644 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
646 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
648 if (command
== D40_DMA_SUSPEND_REQ
) {
649 status
= (readl(active_reg
) &
650 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
651 D40_CHAN_POS(d40c
->phy_chan
->num
);
653 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
657 wmask
= 0xffffffff & ~(D40_CHAN_POS_MASK(d40c
->phy_chan
->num
));
658 writel(wmask
| (command
<< D40_CHAN_POS(d40c
->phy_chan
->num
)),
661 if (command
== D40_DMA_SUSPEND_REQ
) {
663 for (i
= 0 ; i
< D40_SUSPEND_MAX_IT
; i
++) {
664 status
= (readl(active_reg
) &
665 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
666 D40_CHAN_POS(d40c
->phy_chan
->num
);
670 * Reduce the number of bus accesses while
671 * waiting for the DMA to suspend.
675 if (status
== D40_DMA_STOP
||
676 status
== D40_DMA_SUSPENDED
)
680 if (i
== D40_SUSPEND_MAX_IT
) {
682 "unable to suspend the chl %d (log: %d) status %x\n",
683 d40c
->phy_chan
->num
, d40c
->log_num
,
691 spin_unlock_irqrestore(&d40c
->base
->execmd_lock
, flags
);
695 static void d40_term_all(struct d40_chan
*d40c
)
697 struct d40_desc
*d40d
;
699 /* Release active descriptors */
700 while ((d40d
= d40_first_active_get(d40c
))) {
701 d40_desc_remove(d40d
);
702 d40_desc_free(d40c
, d40d
);
705 /* Release queued descriptors waiting for transfer */
706 while ((d40d
= d40_first_queued(d40c
))) {
707 d40_desc_remove(d40d
);
708 d40_desc_free(d40c
, d40d
);
712 d40c
->pending_tx
= 0;
716 static void __d40_config_set_event(struct d40_chan
*d40c
, bool enable
,
719 void __iomem
*addr
= chan_base(d40c
) + reg
;
723 writel((D40_DEACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
))
724 | ~D40_EVENTLINE_MASK(event
), addr
);
729 * The hardware sometimes doesn't register the enable when src and dst
730 * event lines are active on the same logical channel. Retry to ensure
731 * it does. Usually only one retry is sufficient.
735 writel((D40_ACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
))
736 | ~D40_EVENTLINE_MASK(event
), addr
);
738 if (readl(addr
) & D40_EVENTLINE_MASK(event
))
743 dev_dbg(chan2dev(d40c
),
744 "[%s] workaround enable S%cLNK (%d tries)\n",
745 __func__
, reg
== D40_CHAN_REG_SSLNK
? 'S' : 'D',
751 static void d40_config_set_event(struct d40_chan
*d40c
, bool do_enable
)
755 spin_lock_irqsave(&d40c
->phy_chan
->lock
, flags
);
757 /* Enable event line connected to device (or memcpy) */
758 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
759 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
)) {
760 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
762 __d40_config_set_event(d40c
, do_enable
, event
,
766 if (d40c
->dma_cfg
.dir
!= STEDMA40_PERIPH_TO_MEM
) {
767 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
769 __d40_config_set_event(d40c
, do_enable
, event
,
773 spin_unlock_irqrestore(&d40c
->phy_chan
->lock
, flags
);
776 static u32
d40_chan_has_events(struct d40_chan
*d40c
)
778 void __iomem
*chanbase
= chan_base(d40c
);
781 val
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
782 val
|= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
787 static u32
d40_get_prmo(struct d40_chan
*d40c
)
789 static const unsigned int phy_map
[] = {
790 [STEDMA40_PCHAN_BASIC_MODE
]
791 = D40_DREG_PRMO_PCHAN_BASIC
,
792 [STEDMA40_PCHAN_MODULO_MODE
]
793 = D40_DREG_PRMO_PCHAN_MODULO
,
794 [STEDMA40_PCHAN_DOUBLE_DST_MODE
]
795 = D40_DREG_PRMO_PCHAN_DOUBLE_DST
,
797 static const unsigned int log_map
[] = {
798 [STEDMA40_LCHAN_SRC_PHY_DST_LOG
]
799 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG
,
800 [STEDMA40_LCHAN_SRC_LOG_DST_PHY
]
801 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY
,
802 [STEDMA40_LCHAN_SRC_LOG_DST_LOG
]
803 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG
,
806 if (chan_is_physical(d40c
))
807 return phy_map
[d40c
->dma_cfg
.mode_opt
];
809 return log_map
[d40c
->dma_cfg
.mode_opt
];
812 static void d40_config_write(struct d40_chan
*d40c
)
817 /* Odd addresses are even addresses + 4 */
818 addr_base
= (d40c
->phy_chan
->num
% 2) * 4;
819 /* Setup channel mode to logical or physical */
820 var
= ((u32
)(chan_is_logical(d40c
)) + 1) <<
821 D40_CHAN_POS(d40c
->phy_chan
->num
);
822 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMSE
+ addr_base
);
824 /* Setup operational mode option register */
825 var
= d40_get_prmo(d40c
) << D40_CHAN_POS(d40c
->phy_chan
->num
);
827 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMOE
+ addr_base
);
829 if (chan_is_logical(d40c
)) {
830 int lidx
= (d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
)
831 & D40_SREG_ELEM_LOG_LIDX_MASK
;
832 void __iomem
*chanbase
= chan_base(d40c
);
834 /* Set default config for CFG reg */
835 writel(d40c
->src_def_cfg
, chanbase
+ D40_CHAN_REG_SSCFG
);
836 writel(d40c
->dst_def_cfg
, chanbase
+ D40_CHAN_REG_SDCFG
);
838 /* Set LIDX for lcla */
839 writel(lidx
, chanbase
+ D40_CHAN_REG_SSELT
);
840 writel(lidx
, chanbase
+ D40_CHAN_REG_SDELT
);
844 static u32
d40_residue(struct d40_chan
*d40c
)
848 if (chan_is_logical(d40c
))
849 num_elt
= (readl(&d40c
->lcpa
->lcsp2
) & D40_MEM_LCSP2_ECNT_MASK
)
850 >> D40_MEM_LCSP2_ECNT_POS
;
852 u32 val
= readl(chan_base(d40c
) + D40_CHAN_REG_SDELT
);
853 num_elt
= (val
& D40_SREG_ELEM_PHY_ECNT_MASK
)
854 >> D40_SREG_ELEM_PHY_ECNT_POS
;
857 return num_elt
* (1 << d40c
->dma_cfg
.dst_info
.data_width
);
860 static bool d40_tx_is_linked(struct d40_chan
*d40c
)
864 if (chan_is_logical(d40c
))
865 is_link
= readl(&d40c
->lcpa
->lcsp3
) & D40_MEM_LCSP3_DLOS_MASK
;
867 is_link
= readl(chan_base(d40c
) + D40_CHAN_REG_SDLNK
)
868 & D40_SREG_LNK_PHYS_LNK_MASK
;
873 static int d40_pause(struct dma_chan
*chan
)
875 struct d40_chan
*d40c
=
876 container_of(chan
, struct d40_chan
, chan
);
883 spin_lock_irqsave(&d40c
->lock
, flags
);
885 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
887 if (chan_is_logical(d40c
)) {
888 d40_config_set_event(d40c
, false);
889 /* Resume the other logical channels if any */
890 if (d40_chan_has_events(d40c
))
891 res
= d40_channel_execute_command(d40c
,
896 spin_unlock_irqrestore(&d40c
->lock
, flags
);
900 static int d40_resume(struct dma_chan
*chan
)
902 struct d40_chan
*d40c
=
903 container_of(chan
, struct d40_chan
, chan
);
910 spin_lock_irqsave(&d40c
->lock
, flags
);
912 if (d40c
->base
->rev
== 0)
913 if (chan_is_logical(d40c
)) {
914 res
= d40_channel_execute_command(d40c
,
915 D40_DMA_SUSPEND_REQ
);
919 /* If bytes left to transfer or linked tx resume job */
920 if (d40_residue(d40c
) || d40_tx_is_linked(d40c
)) {
922 if (chan_is_logical(d40c
))
923 d40_config_set_event(d40c
, true);
925 res
= d40_channel_execute_command(d40c
, D40_DMA_RUN
);
929 spin_unlock_irqrestore(&d40c
->lock
, flags
);
933 static dma_cookie_t
d40_tx_submit(struct dma_async_tx_descriptor
*tx
)
935 struct d40_chan
*d40c
= container_of(tx
->chan
,
938 struct d40_desc
*d40d
= container_of(tx
, struct d40_desc
, txd
);
941 spin_lock_irqsave(&d40c
->lock
, flags
);
945 if (d40c
->chan
.cookie
< 0)
946 d40c
->chan
.cookie
= 1;
948 d40d
->txd
.cookie
= d40c
->chan
.cookie
;
950 d40_desc_queue(d40c
, d40d
);
952 spin_unlock_irqrestore(&d40c
->lock
, flags
);
957 static int d40_start(struct d40_chan
*d40c
)
959 if (d40c
->base
->rev
== 0) {
962 if (chan_is_logical(d40c
)) {
963 err
= d40_channel_execute_command(d40c
,
964 D40_DMA_SUSPEND_REQ
);
970 if (chan_is_logical(d40c
))
971 d40_config_set_event(d40c
, true);
973 return d40_channel_execute_command(d40c
, D40_DMA_RUN
);
976 static struct d40_desc
*d40_queue_start(struct d40_chan
*d40c
)
978 struct d40_desc
*d40d
;
981 /* Start queued jobs, if any */
982 d40d
= d40_first_queued(d40c
);
987 /* Remove from queue */
988 d40_desc_remove(d40d
);
990 /* Add to active queue */
991 d40_desc_submit(d40c
, d40d
);
993 /* Initiate DMA job */
994 d40_desc_load(d40c
, d40d
);
997 err
= d40_start(d40c
);
1006 /* called from interrupt context */
1007 static void dma_tc_handle(struct d40_chan
*d40c
)
1009 struct d40_desc
*d40d
;
1011 /* Get first active entry from list */
1012 d40d
= d40_first_active_get(d40c
);
1017 d40_lcla_free_all(d40c
, d40d
);
1019 if (d40d
->lli_current
< d40d
->lli_len
) {
1020 d40_desc_load(d40c
, d40d
);
1022 (void) d40_start(d40c
);
1026 if (d40_queue_start(d40c
) == NULL
)
1030 tasklet_schedule(&d40c
->tasklet
);
1034 static void dma_tasklet(unsigned long data
)
1036 struct d40_chan
*d40c
= (struct d40_chan
*) data
;
1037 struct d40_desc
*d40d
;
1038 unsigned long flags
;
1039 dma_async_tx_callback callback
;
1040 void *callback_param
;
1042 spin_lock_irqsave(&d40c
->lock
, flags
);
1044 /* Get first active entry from list */
1045 d40d
= d40_first_active_get(d40c
);
1050 d40c
->completed
= d40d
->txd
.cookie
;
1053 * If terminating a channel pending_tx is set to zero.
1054 * This prevents any finished active jobs to return to the client.
1056 if (d40c
->pending_tx
== 0) {
1057 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1061 /* Callback to client */
1062 callback
= d40d
->txd
.callback
;
1063 callback_param
= d40d
->txd
.callback_param
;
1065 if (async_tx_test_ack(&d40d
->txd
)) {
1066 d40_pool_lli_free(d40d
);
1067 d40_desc_remove(d40d
);
1068 d40_desc_free(d40c
, d40d
);
1070 if (!d40d
->is_in_client_list
) {
1071 d40_desc_remove(d40d
);
1072 d40_lcla_free_all(d40c
, d40d
);
1073 list_add_tail(&d40d
->node
, &d40c
->client
);
1074 d40d
->is_in_client_list
= true;
1080 if (d40c
->pending_tx
)
1081 tasklet_schedule(&d40c
->tasklet
);
1083 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1085 if (callback
&& (d40d
->txd
.flags
& DMA_PREP_INTERRUPT
))
1086 callback(callback_param
);
1091 /* Rescue manouver if receiving double interrupts */
1092 if (d40c
->pending_tx
> 0)
1094 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1097 static irqreturn_t
d40_handle_interrupt(int irq
, void *data
)
1099 static const struct d40_interrupt_lookup il
[] = {
1100 {D40_DREG_LCTIS0
, D40_DREG_LCICR0
, false, 0},
1101 {D40_DREG_LCTIS1
, D40_DREG_LCICR1
, false, 32},
1102 {D40_DREG_LCTIS2
, D40_DREG_LCICR2
, false, 64},
1103 {D40_DREG_LCTIS3
, D40_DREG_LCICR3
, false, 96},
1104 {D40_DREG_LCEIS0
, D40_DREG_LCICR0
, true, 0},
1105 {D40_DREG_LCEIS1
, D40_DREG_LCICR1
, true, 32},
1106 {D40_DREG_LCEIS2
, D40_DREG_LCICR2
, true, 64},
1107 {D40_DREG_LCEIS3
, D40_DREG_LCICR3
, true, 96},
1108 {D40_DREG_PCTIS
, D40_DREG_PCICR
, false, D40_PHY_CHAN
},
1109 {D40_DREG_PCEIS
, D40_DREG_PCICR
, true, D40_PHY_CHAN
},
1113 u32 regs
[ARRAY_SIZE(il
)];
1117 struct d40_chan
*d40c
;
1118 unsigned long flags
;
1119 struct d40_base
*base
= data
;
1121 spin_lock_irqsave(&base
->interrupt_lock
, flags
);
1123 /* Read interrupt status of both logical and physical channels */
1124 for (i
= 0; i
< ARRAY_SIZE(il
); i
++)
1125 regs
[i
] = readl(base
->virtbase
+ il
[i
].src
);
1129 chan
= find_next_bit((unsigned long *)regs
,
1130 BITS_PER_LONG
* ARRAY_SIZE(il
), chan
+ 1);
1132 /* No more set bits found? */
1133 if (chan
== BITS_PER_LONG
* ARRAY_SIZE(il
))
1136 row
= chan
/ BITS_PER_LONG
;
1137 idx
= chan
& (BITS_PER_LONG
- 1);
1140 writel(1 << idx
, base
->virtbase
+ il
[row
].clr
);
1142 if (il
[row
].offset
== D40_PHY_CHAN
)
1143 d40c
= base
->lookup_phy_chans
[idx
];
1145 d40c
= base
->lookup_log_chans
[il
[row
].offset
+ idx
];
1146 spin_lock(&d40c
->lock
);
1148 if (!il
[row
].is_error
)
1149 dma_tc_handle(d40c
);
1151 d40_err(base
->dev
, "IRQ chan: %ld offset %d idx %d\n",
1152 chan
, il
[row
].offset
, idx
);
1154 spin_unlock(&d40c
->lock
);
1157 spin_unlock_irqrestore(&base
->interrupt_lock
, flags
);
1162 static int d40_validate_conf(struct d40_chan
*d40c
,
1163 struct stedma40_chan_cfg
*conf
)
1166 u32 dst_event_group
= D40_TYPE_TO_GROUP(conf
->dst_dev_type
);
1167 u32 src_event_group
= D40_TYPE_TO_GROUP(conf
->src_dev_type
);
1168 bool is_log
= conf
->mode
== STEDMA40_MODE_LOGICAL
;
1171 chan_err(d40c
, "Invalid direction.\n");
1175 if (conf
->dst_dev_type
!= STEDMA40_DEV_DST_MEMORY
&&
1176 d40c
->base
->plat_data
->dev_tx
[conf
->dst_dev_type
] == 0 &&
1177 d40c
->runtime_addr
== 0) {
1179 chan_err(d40c
, "Invalid TX channel address (%d)\n",
1180 conf
->dst_dev_type
);
1184 if (conf
->src_dev_type
!= STEDMA40_DEV_SRC_MEMORY
&&
1185 d40c
->base
->plat_data
->dev_rx
[conf
->src_dev_type
] == 0 &&
1186 d40c
->runtime_addr
== 0) {
1187 chan_err(d40c
, "Invalid RX channel address (%d)\n",
1188 conf
->src_dev_type
);
1192 if (conf
->dir
== STEDMA40_MEM_TO_PERIPH
&&
1193 dst_event_group
== STEDMA40_DEV_DST_MEMORY
) {
1194 chan_err(d40c
, "Invalid dst\n");
1198 if (conf
->dir
== STEDMA40_PERIPH_TO_MEM
&&
1199 src_event_group
== STEDMA40_DEV_SRC_MEMORY
) {
1200 chan_err(d40c
, "Invalid src\n");
1204 if (src_event_group
== STEDMA40_DEV_SRC_MEMORY
&&
1205 dst_event_group
== STEDMA40_DEV_DST_MEMORY
&& is_log
) {
1206 chan_err(d40c
, "No event line\n");
1210 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
&&
1211 (src_event_group
!= dst_event_group
)) {
1212 chan_err(d40c
, "Invalid event group\n");
1216 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
) {
1218 * DMAC HW supports it. Will be added to this driver,
1219 * in case any dma client requires it.
1221 chan_err(d40c
, "periph to periph not supported\n");
1225 if (d40_psize_2_burst_size(is_log
, conf
->src_info
.psize
) *
1226 (1 << conf
->src_info
.data_width
) !=
1227 d40_psize_2_burst_size(is_log
, conf
->dst_info
.psize
) *
1228 (1 << conf
->dst_info
.data_width
)) {
1230 * The DMAC hardware only supports
1231 * src (burst x width) == dst (burst x width)
1234 chan_err(d40c
, "src (burst x width) != dst (burst x width)\n");
1241 static bool d40_alloc_mask_set(struct d40_phy_res
*phy
, bool is_src
,
1242 int log_event_line
, bool is_log
)
1244 unsigned long flags
;
1245 spin_lock_irqsave(&phy
->lock
, flags
);
1247 /* Physical interrupts are masked per physical full channel */
1248 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1249 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1250 phy
->allocated_dst
= D40_ALLOC_PHY
;
1251 phy
->allocated_src
= D40_ALLOC_PHY
;
1257 /* Logical channel */
1259 if (phy
->allocated_src
== D40_ALLOC_PHY
)
1262 if (phy
->allocated_src
== D40_ALLOC_FREE
)
1263 phy
->allocated_src
= D40_ALLOC_LOG_FREE
;
1265 if (!(phy
->allocated_src
& (1 << log_event_line
))) {
1266 phy
->allocated_src
|= 1 << log_event_line
;
1271 if (phy
->allocated_dst
== D40_ALLOC_PHY
)
1274 if (phy
->allocated_dst
== D40_ALLOC_FREE
)
1275 phy
->allocated_dst
= D40_ALLOC_LOG_FREE
;
1277 if (!(phy
->allocated_dst
& (1 << log_event_line
))) {
1278 phy
->allocated_dst
|= 1 << log_event_line
;
1285 spin_unlock_irqrestore(&phy
->lock
, flags
);
1288 spin_unlock_irqrestore(&phy
->lock
, flags
);
1292 static bool d40_alloc_mask_free(struct d40_phy_res
*phy
, bool is_src
,
1295 unsigned long flags
;
1296 bool is_free
= false;
1298 spin_lock_irqsave(&phy
->lock
, flags
);
1299 if (!log_event_line
) {
1300 phy
->allocated_dst
= D40_ALLOC_FREE
;
1301 phy
->allocated_src
= D40_ALLOC_FREE
;
1306 /* Logical channel */
1308 phy
->allocated_src
&= ~(1 << log_event_line
);
1309 if (phy
->allocated_src
== D40_ALLOC_LOG_FREE
)
1310 phy
->allocated_src
= D40_ALLOC_FREE
;
1312 phy
->allocated_dst
&= ~(1 << log_event_line
);
1313 if (phy
->allocated_dst
== D40_ALLOC_LOG_FREE
)
1314 phy
->allocated_dst
= D40_ALLOC_FREE
;
1317 is_free
= ((phy
->allocated_src
| phy
->allocated_dst
) ==
1321 spin_unlock_irqrestore(&phy
->lock
, flags
);
1326 static int d40_allocate_channel(struct d40_chan
*d40c
)
1331 struct d40_phy_res
*phys
;
1336 bool is_log
= d40c
->dma_cfg
.mode
== STEDMA40_MODE_LOGICAL
;
1338 phys
= d40c
->base
->phy_res
;
1340 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1341 dev_type
= d40c
->dma_cfg
.src_dev_type
;
1342 log_num
= 2 * dev_type
;
1344 } else if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1345 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1346 /* dst event lines are used for logical memcpy */
1347 dev_type
= d40c
->dma_cfg
.dst_dev_type
;
1348 log_num
= 2 * dev_type
+ 1;
1353 event_group
= D40_TYPE_TO_GROUP(dev_type
);
1354 event_line
= D40_TYPE_TO_EVENT(dev_type
);
1357 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1358 /* Find physical half channel */
1359 for (i
= 0; i
< d40c
->base
->num_phy_chans
; i
++) {
1361 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1366 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1367 int phy_num
= j
+ event_group
* 2;
1368 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1369 if (d40_alloc_mask_set(&phys
[i
],
1378 d40c
->phy_chan
= &phys
[i
];
1379 d40c
->log_num
= D40_PHY_CHAN
;
1385 /* Find logical channel */
1386 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1387 int phy_num
= j
+ event_group
* 2;
1389 * Spread logical channels across all available physical rather
1390 * than pack every logical channel at the first available phy
1394 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1395 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1396 event_line
, is_log
))
1400 for (i
= phy_num
+ 1; i
>= phy_num
; i
--) {
1401 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1402 event_line
, is_log
))
1410 d40c
->phy_chan
= &phys
[i
];
1411 d40c
->log_num
= log_num
;
1415 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = d40c
;
1417 d40c
->base
->lookup_phy_chans
[d40c
->phy_chan
->num
] = d40c
;
1423 static int d40_config_memcpy(struct d40_chan
*d40c
)
1425 dma_cap_mask_t cap
= d40c
->chan
.device
->cap_mask
;
1427 if (dma_has_cap(DMA_MEMCPY
, cap
) && !dma_has_cap(DMA_SLAVE
, cap
)) {
1428 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_log
;
1429 d40c
->dma_cfg
.src_dev_type
= STEDMA40_DEV_SRC_MEMORY
;
1430 d40c
->dma_cfg
.dst_dev_type
= d40c
->base
->plat_data
->
1431 memcpy
[d40c
->chan
.chan_id
];
1433 } else if (dma_has_cap(DMA_MEMCPY
, cap
) &&
1434 dma_has_cap(DMA_SLAVE
, cap
)) {
1435 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_phy
;
1437 chan_err(d40c
, "No memcpy\n");
1445 static int d40_free_dma(struct d40_chan
*d40c
)
1450 struct d40_phy_res
*phy
= d40c
->phy_chan
;
1453 struct d40_desc
*_d
;
1456 /* Terminate all queued and active transfers */
1459 /* Release client owned descriptors */
1460 if (!list_empty(&d40c
->client
))
1461 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
) {
1462 d40_pool_lli_free(d
);
1464 d40_desc_free(d40c
, d
);
1468 chan_err(d40c
, "phy == null\n");
1472 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1473 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1474 chan_err(d40c
, "channel already free\n");
1478 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1479 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1480 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1482 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1483 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1486 chan_err(d40c
, "Unknown direction\n");
1490 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1492 chan_err(d40c
, "suspend failed\n");
1496 if (chan_is_logical(d40c
)) {
1497 /* Release logical channel, deactivate the event line */
1499 d40_config_set_event(d40c
, false);
1500 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = NULL
;
1503 * Check if there are more logical allocation
1504 * on this phy channel.
1506 if (!d40_alloc_mask_free(phy
, is_src
, event
)) {
1507 /* Resume the other logical channels if any */
1508 if (d40_chan_has_events(d40c
)) {
1509 res
= d40_channel_execute_command(d40c
,
1513 "Executing RUN command\n");
1520 (void) d40_alloc_mask_free(phy
, is_src
, 0);
1523 /* Release physical channel */
1524 res
= d40_channel_execute_command(d40c
, D40_DMA_STOP
);
1526 chan_err(d40c
, "Failed to stop channel\n");
1529 d40c
->phy_chan
= NULL
;
1530 d40c
->configured
= false;
1531 d40c
->base
->lookup_phy_chans
[phy
->num
] = NULL
;
1536 static bool d40_is_paused(struct d40_chan
*d40c
)
1538 void __iomem
*chanbase
= chan_base(d40c
);
1539 bool is_paused
= false;
1540 unsigned long flags
;
1541 void __iomem
*active_reg
;
1545 spin_lock_irqsave(&d40c
->lock
, flags
);
1547 if (chan_is_physical(d40c
)) {
1548 if (d40c
->phy_chan
->num
% 2 == 0)
1549 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
1551 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
1553 status
= (readl(active_reg
) &
1554 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
1555 D40_CHAN_POS(d40c
->phy_chan
->num
);
1556 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
1562 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1563 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1564 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1565 status
= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
1566 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1567 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1568 status
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
1570 chan_err(d40c
, "Unknown direction\n");
1574 status
= (status
& D40_EVENTLINE_MASK(event
)) >>
1575 D40_EVENTLINE_POS(event
);
1577 if (status
!= D40_DMA_RUN
)
1580 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1586 static u32
stedma40_residue(struct dma_chan
*chan
)
1588 struct d40_chan
*d40c
=
1589 container_of(chan
, struct d40_chan
, chan
);
1591 unsigned long flags
;
1593 spin_lock_irqsave(&d40c
->lock
, flags
);
1594 bytes_left
= d40_residue(d40c
);
1595 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1600 struct dma_async_tx_descriptor
*stedma40_memcpy_sg(struct dma_chan
*chan
,
1601 struct scatterlist
*sgl_dst
,
1602 struct scatterlist
*sgl_src
,
1603 unsigned int sgl_len
,
1604 unsigned long dma_flags
)
1607 struct d40_desc
*d40d
;
1608 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1610 unsigned long flags
;
1612 if (d40c
->phy_chan
== NULL
) {
1613 chan_err(d40c
, "Unallocated channel.\n");
1614 return ERR_PTR(-EINVAL
);
1617 spin_lock_irqsave(&d40c
->lock
, flags
);
1618 d40d
= d40_desc_get(d40c
);
1623 d40d
->lli_len
= d40_sg_2_dmalen(sgl_dst
, sgl_len
,
1624 d40c
->dma_cfg
.src_info
.data_width
,
1625 d40c
->dma_cfg
.dst_info
.data_width
);
1626 if (d40d
->lli_len
< 0) {
1627 chan_err(d40c
, "Unaligned size\n");
1631 d40d
->lli_current
= 0;
1632 d40d
->txd
.flags
= dma_flags
;
1634 if (chan_is_logical(d40c
)) {
1636 if (d40_pool_lli_alloc(d40d
, d40d
->lli_len
, true) < 0) {
1637 chan_err(d40c
, "Out of memory\n");
1641 (void) d40_log_sg_to_lli(sgl_src
,
1644 d40c
->log_def
.lcsp1
,
1645 d40c
->dma_cfg
.src_info
.data_width
,
1646 d40c
->dma_cfg
.dst_info
.data_width
);
1648 (void) d40_log_sg_to_lli(sgl_dst
,
1651 d40c
->log_def
.lcsp3
,
1652 d40c
->dma_cfg
.dst_info
.data_width
,
1653 d40c
->dma_cfg
.src_info
.data_width
);
1655 if (d40_pool_lli_alloc(d40d
, d40d
->lli_len
, false) < 0) {
1656 chan_err(d40c
, "Out of memory\n");
1660 res
= d40_phy_sg_to_lli(sgl_src
,
1664 virt_to_phys(d40d
->lli_phy
.src
),
1666 d40c
->dma_cfg
.src_info
.data_width
,
1667 d40c
->dma_cfg
.dst_info
.data_width
,
1668 d40c
->dma_cfg
.src_info
.psize
);
1673 res
= d40_phy_sg_to_lli(sgl_dst
,
1677 virt_to_phys(d40d
->lli_phy
.dst
),
1679 d40c
->dma_cfg
.dst_info
.data_width
,
1680 d40c
->dma_cfg
.src_info
.data_width
,
1681 d40c
->dma_cfg
.dst_info
.psize
);
1686 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
1687 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1690 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1692 d40d
->txd
.tx_submit
= d40_tx_submit
;
1694 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1699 d40_desc_free(d40c
, d40d
);
1700 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1703 EXPORT_SYMBOL(stedma40_memcpy_sg
);
1705 bool stedma40_filter(struct dma_chan
*chan
, void *data
)
1707 struct stedma40_chan_cfg
*info
= data
;
1708 struct d40_chan
*d40c
=
1709 container_of(chan
, struct d40_chan
, chan
);
1713 err
= d40_validate_conf(d40c
, info
);
1715 d40c
->dma_cfg
= *info
;
1717 err
= d40_config_memcpy(d40c
);
1720 d40c
->configured
= true;
1724 EXPORT_SYMBOL(stedma40_filter
);
1726 static void __d40_set_prio_rt(struct d40_chan
*d40c
, int dev_type
, bool src
)
1728 bool realtime
= d40c
->dma_cfg
.realtime
;
1729 bool highprio
= d40c
->dma_cfg
.high_priority
;
1730 u32 prioreg
= highprio
? D40_DREG_PSEG1
: D40_DREG_PCEG1
;
1731 u32 rtreg
= realtime
? D40_DREG_RSEG1
: D40_DREG_RCEG1
;
1732 u32 event
= D40_TYPE_TO_EVENT(dev_type
);
1733 u32 group
= D40_TYPE_TO_GROUP(dev_type
);
1734 u32 bit
= 1 << event
;
1736 /* Destination event lines are stored in the upper halfword */
1740 writel(bit
, d40c
->base
->virtbase
+ prioreg
+ group
* 4);
1741 writel(bit
, d40c
->base
->virtbase
+ rtreg
+ group
* 4);
1744 static void d40_set_prio_realtime(struct d40_chan
*d40c
)
1746 if (d40c
->base
->rev
< 3)
1749 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
1750 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
1751 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.src_dev_type
, true);
1753 if ((d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
) ||
1754 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
1755 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.dst_dev_type
, false);
1758 /* DMA ENGINE functions */
1759 static int d40_alloc_chan_resources(struct dma_chan
*chan
)
1762 unsigned long flags
;
1763 struct d40_chan
*d40c
=
1764 container_of(chan
, struct d40_chan
, chan
);
1766 spin_lock_irqsave(&d40c
->lock
, flags
);
1768 d40c
->completed
= chan
->cookie
= 1;
1770 /* If no dma configuration is set use default configuration (memcpy) */
1771 if (!d40c
->configured
) {
1772 err
= d40_config_memcpy(d40c
);
1774 chan_err(d40c
, "Failed to configure memcpy channel\n");
1778 is_free_phy
= (d40c
->phy_chan
== NULL
);
1780 err
= d40_allocate_channel(d40c
);
1782 chan_err(d40c
, "Failed to allocate channel\n");
1786 /* Fill in basic CFG register values */
1787 d40_phy_cfg(&d40c
->dma_cfg
, &d40c
->src_def_cfg
,
1788 &d40c
->dst_def_cfg
, chan_is_logical(d40c
));
1790 d40_set_prio_realtime(d40c
);
1792 if (chan_is_logical(d40c
)) {
1793 d40_log_cfg(&d40c
->dma_cfg
,
1794 &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
1796 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
1797 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1798 d40c
->dma_cfg
.src_dev_type
* D40_LCPA_CHAN_SIZE
;
1800 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1801 d40c
->dma_cfg
.dst_dev_type
*
1802 D40_LCPA_CHAN_SIZE
+ D40_LCPA_CHAN_DST_DELTA
;
1806 * Only write channel configuration to the DMA if the physical
1807 * resource is free. In case of multiple logical channels
1808 * on the same physical resource, only the first write is necessary.
1811 d40_config_write(d40c
);
1813 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1817 static void d40_free_chan_resources(struct dma_chan
*chan
)
1819 struct d40_chan
*d40c
=
1820 container_of(chan
, struct d40_chan
, chan
);
1822 unsigned long flags
;
1824 if (d40c
->phy_chan
== NULL
) {
1825 chan_err(d40c
, "Cannot free unallocated channel\n");
1830 spin_lock_irqsave(&d40c
->lock
, flags
);
1832 err
= d40_free_dma(d40c
);
1835 chan_err(d40c
, "Failed to free channel\n");
1836 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1839 static struct dma_async_tx_descriptor
*d40_prep_memcpy(struct dma_chan
*chan
,
1843 unsigned long dma_flags
)
1845 struct d40_desc
*d40d
;
1846 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1848 unsigned long flags
;
1850 if (d40c
->phy_chan
== NULL
) {
1851 chan_err(d40c
, "Channel is not allocated.\n");
1852 return ERR_PTR(-EINVAL
);
1855 spin_lock_irqsave(&d40c
->lock
, flags
);
1856 d40d
= d40_desc_get(d40c
);
1859 chan_err(d40c
, "Descriptor is NULL\n");
1863 d40d
->txd
.flags
= dma_flags
;
1864 d40d
->lli_len
= d40_size_2_dmalen(size
,
1865 d40c
->dma_cfg
.src_info
.data_width
,
1866 d40c
->dma_cfg
.dst_info
.data_width
);
1867 if (d40d
->lli_len
< 0) {
1868 chan_err(d40c
, "Unaligned size\n");
1873 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1875 d40d
->txd
.tx_submit
= d40_tx_submit
;
1877 if (chan_is_logical(d40c
)) {
1879 if (d40_pool_lli_alloc(d40d
, d40d
->lli_len
, true) < 0) {
1880 chan_err(d40c
, "Out of memory\n");
1883 d40d
->lli_current
= 0;
1885 if (d40_log_buf_to_lli(d40d
->lli_log
.src
,
1888 d40c
->log_def
.lcsp1
,
1889 d40c
->dma_cfg
.src_info
.data_width
,
1890 d40c
->dma_cfg
.dst_info
.data_width
,
1894 if (d40_log_buf_to_lli(d40d
->lli_log
.dst
,
1897 d40c
->log_def
.lcsp3
,
1898 d40c
->dma_cfg
.dst_info
.data_width
,
1899 d40c
->dma_cfg
.src_info
.data_width
,
1905 if (d40_pool_lli_alloc(d40d
, d40d
->lli_len
, false) < 0) {
1906 chan_err(d40c
, "Out of memory\n");
1910 if (d40_phy_buf_to_lli(d40d
->lli_phy
.src
,
1913 d40c
->dma_cfg
.src_info
.psize
,
1917 d40c
->dma_cfg
.src_info
.data_width
,
1918 d40c
->dma_cfg
.dst_info
.data_width
,
1922 if (d40_phy_buf_to_lli(d40d
->lli_phy
.dst
,
1925 d40c
->dma_cfg
.dst_info
.psize
,
1929 d40c
->dma_cfg
.dst_info
.data_width
,
1930 d40c
->dma_cfg
.src_info
.data_width
,
1934 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
1935 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1938 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1943 d40_desc_free(d40c
, d40d
);
1944 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1948 static struct dma_async_tx_descriptor
*
1949 d40_prep_sg(struct dma_chan
*chan
,
1950 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
1951 struct scatterlist
*src_sg
, unsigned int src_nents
,
1952 unsigned long dma_flags
)
1954 if (dst_nents
!= src_nents
)
1957 return stedma40_memcpy_sg(chan
, dst_sg
, src_sg
, dst_nents
, dma_flags
);
1960 static int d40_prep_slave_sg_log(struct d40_desc
*d40d
,
1961 struct d40_chan
*d40c
,
1962 struct scatterlist
*sgl
,
1963 unsigned int sg_len
,
1964 enum dma_data_direction direction
,
1965 unsigned long dma_flags
)
1967 dma_addr_t dev_addr
= 0;
1970 d40d
->lli_len
= d40_sg_2_dmalen(sgl
, sg_len
,
1971 d40c
->dma_cfg
.src_info
.data_width
,
1972 d40c
->dma_cfg
.dst_info
.data_width
);
1973 if (d40d
->lli_len
< 0) {
1974 chan_err(d40c
, "Unaligned size\n");
1978 if (d40_pool_lli_alloc(d40d
, d40d
->lli_len
, true) < 0) {
1979 chan_err(d40c
, "Out of memory\n");
1983 d40d
->lli_current
= 0;
1985 if (direction
== DMA_FROM_DEVICE
)
1986 if (d40c
->runtime_addr
)
1987 dev_addr
= d40c
->runtime_addr
;
1989 dev_addr
= d40c
->base
->plat_data
->dev_rx
[d40c
->dma_cfg
.src_dev_type
];
1990 else if (direction
== DMA_TO_DEVICE
)
1991 if (d40c
->runtime_addr
)
1992 dev_addr
= d40c
->runtime_addr
;
1994 dev_addr
= d40c
->base
->plat_data
->dev_tx
[d40c
->dma_cfg
.dst_dev_type
];
1999 total_size
= d40_log_sg_to_dev(sgl
, sg_len
,
2002 d40c
->dma_cfg
.src_info
.data_width
,
2003 d40c
->dma_cfg
.dst_info
.data_width
,
2013 static int d40_prep_slave_sg_phy(struct d40_desc
*d40d
,
2014 struct d40_chan
*d40c
,
2015 struct scatterlist
*sgl
,
2016 unsigned int sgl_len
,
2017 enum dma_data_direction direction
,
2018 unsigned long dma_flags
)
2020 dma_addr_t src_dev_addr
;
2021 dma_addr_t dst_dev_addr
;
2024 d40d
->lli_len
= d40_sg_2_dmalen(sgl
, sgl_len
,
2025 d40c
->dma_cfg
.src_info
.data_width
,
2026 d40c
->dma_cfg
.dst_info
.data_width
);
2027 if (d40d
->lli_len
< 0) {
2028 chan_err(d40c
, "Unaligned size\n");
2032 if (d40_pool_lli_alloc(d40d
, d40d
->lli_len
, false) < 0) {
2033 chan_err(d40c
, "Out of memory\n");
2037 d40d
->lli_current
= 0;
2039 if (direction
== DMA_FROM_DEVICE
) {
2041 if (d40c
->runtime_addr
)
2042 src_dev_addr
= d40c
->runtime_addr
;
2044 src_dev_addr
= d40c
->base
->plat_data
->dev_rx
[d40c
->dma_cfg
.src_dev_type
];
2045 } else if (direction
== DMA_TO_DEVICE
) {
2046 if (d40c
->runtime_addr
)
2047 dst_dev_addr
= d40c
->runtime_addr
;
2049 dst_dev_addr
= d40c
->base
->plat_data
->dev_tx
[d40c
->dma_cfg
.dst_dev_type
];
2054 res
= d40_phy_sg_to_lli(sgl
,
2058 virt_to_phys(d40d
->lli_phy
.src
),
2060 d40c
->dma_cfg
.src_info
.data_width
,
2061 d40c
->dma_cfg
.dst_info
.data_width
,
2062 d40c
->dma_cfg
.src_info
.psize
);
2066 res
= d40_phy_sg_to_lli(sgl
,
2070 virt_to_phys(d40d
->lli_phy
.dst
),
2072 d40c
->dma_cfg
.dst_info
.data_width
,
2073 d40c
->dma_cfg
.src_info
.data_width
,
2074 d40c
->dma_cfg
.dst_info
.psize
);
2078 (void) dma_map_single(d40c
->base
->dev
, d40d
->lli_phy
.src
,
2079 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
2083 static struct dma_async_tx_descriptor
*d40_prep_slave_sg(struct dma_chan
*chan
,
2084 struct scatterlist
*sgl
,
2085 unsigned int sg_len
,
2086 enum dma_data_direction direction
,
2087 unsigned long dma_flags
)
2089 struct d40_desc
*d40d
;
2090 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
2092 unsigned long flags
;
2095 if (d40c
->phy_chan
== NULL
) {
2096 chan_err(d40c
, "Cannot prepare unallocated channel\n");
2097 return ERR_PTR(-EINVAL
);
2100 spin_lock_irqsave(&d40c
->lock
, flags
);
2101 d40d
= d40_desc_get(d40c
);
2106 if (chan_is_logical(d40c
))
2107 err
= d40_prep_slave_sg_log(d40d
, d40c
, sgl
, sg_len
,
2108 direction
, dma_flags
);
2110 err
= d40_prep_slave_sg_phy(d40d
, d40c
, sgl
, sg_len
,
2111 direction
, dma_flags
);
2113 chan_err(d40c
, "Failed to prepare %s slave sg job: %d\n",
2114 chan_is_logical(d40c
) ? "log" : "phy", err
);
2118 d40d
->txd
.flags
= dma_flags
;
2120 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
2122 d40d
->txd
.tx_submit
= d40_tx_submit
;
2124 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2129 d40_desc_free(d40c
, d40d
);
2130 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2134 static enum dma_status
d40_tx_status(struct dma_chan
*chan
,
2135 dma_cookie_t cookie
,
2136 struct dma_tx_state
*txstate
)
2138 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2139 dma_cookie_t last_used
;
2140 dma_cookie_t last_complete
;
2143 if (d40c
->phy_chan
== NULL
) {
2144 chan_err(d40c
, "Cannot read status of unallocated channel\n");
2148 last_complete
= d40c
->completed
;
2149 last_used
= chan
->cookie
;
2151 if (d40_is_paused(d40c
))
2154 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
2156 dma_set_tx_state(txstate
, last_complete
, last_used
,
2157 stedma40_residue(chan
));
2162 static void d40_issue_pending(struct dma_chan
*chan
)
2164 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2165 unsigned long flags
;
2167 if (d40c
->phy_chan
== NULL
) {
2168 chan_err(d40c
, "Channel is not allocated!\n");
2172 spin_lock_irqsave(&d40c
->lock
, flags
);
2174 /* Busy means that pending jobs are already being processed */
2176 (void) d40_queue_start(d40c
);
2178 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2181 /* Runtime reconfiguration extension */
2182 static void d40_set_runtime_config(struct dma_chan
*chan
,
2183 struct dma_slave_config
*config
)
2185 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2186 struct stedma40_chan_cfg
*cfg
= &d40c
->dma_cfg
;
2187 enum dma_slave_buswidth config_addr_width
;
2188 dma_addr_t config_addr
;
2189 u32 config_maxburst
;
2190 enum stedma40_periph_data_width addr_width
;
2193 if (config
->direction
== DMA_FROM_DEVICE
) {
2194 dma_addr_t dev_addr_rx
=
2195 d40c
->base
->plat_data
->dev_rx
[cfg
->src_dev_type
];
2197 config_addr
= config
->src_addr
;
2199 dev_dbg(d40c
->base
->dev
,
2200 "channel has a pre-wired RX address %08x "
2201 "overriding with %08x\n",
2202 dev_addr_rx
, config_addr
);
2203 if (cfg
->dir
!= STEDMA40_PERIPH_TO_MEM
)
2204 dev_dbg(d40c
->base
->dev
,
2205 "channel was not configured for peripheral "
2206 "to memory transfer (%d) overriding\n",
2208 cfg
->dir
= STEDMA40_PERIPH_TO_MEM
;
2210 config_addr_width
= config
->src_addr_width
;
2211 config_maxburst
= config
->src_maxburst
;
2213 } else if (config
->direction
== DMA_TO_DEVICE
) {
2214 dma_addr_t dev_addr_tx
=
2215 d40c
->base
->plat_data
->dev_tx
[cfg
->dst_dev_type
];
2217 config_addr
= config
->dst_addr
;
2219 dev_dbg(d40c
->base
->dev
,
2220 "channel has a pre-wired TX address %08x "
2221 "overriding with %08x\n",
2222 dev_addr_tx
, config_addr
);
2223 if (cfg
->dir
!= STEDMA40_MEM_TO_PERIPH
)
2224 dev_dbg(d40c
->base
->dev
,
2225 "channel was not configured for memory "
2226 "to peripheral transfer (%d) overriding\n",
2228 cfg
->dir
= STEDMA40_MEM_TO_PERIPH
;
2230 config_addr_width
= config
->dst_addr_width
;
2231 config_maxburst
= config
->dst_maxburst
;
2234 dev_err(d40c
->base
->dev
,
2235 "unrecognized channel direction %d\n",
2240 switch (config_addr_width
) {
2241 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
2242 addr_width
= STEDMA40_BYTE_WIDTH
;
2244 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
2245 addr_width
= STEDMA40_HALFWORD_WIDTH
;
2247 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
2248 addr_width
= STEDMA40_WORD_WIDTH
;
2250 case DMA_SLAVE_BUSWIDTH_8_BYTES
:
2251 addr_width
= STEDMA40_DOUBLEWORD_WIDTH
;
2254 dev_err(d40c
->base
->dev
,
2255 "illegal peripheral address width "
2257 config
->src_addr_width
);
2261 if (chan_is_logical(d40c
)) {
2262 if (config_maxburst
>= 16)
2263 psize
= STEDMA40_PSIZE_LOG_16
;
2264 else if (config_maxburst
>= 8)
2265 psize
= STEDMA40_PSIZE_LOG_8
;
2266 else if (config_maxburst
>= 4)
2267 psize
= STEDMA40_PSIZE_LOG_4
;
2269 psize
= STEDMA40_PSIZE_LOG_1
;
2271 if (config_maxburst
>= 16)
2272 psize
= STEDMA40_PSIZE_PHY_16
;
2273 else if (config_maxburst
>= 8)
2274 psize
= STEDMA40_PSIZE_PHY_8
;
2275 else if (config_maxburst
>= 4)
2276 psize
= STEDMA40_PSIZE_PHY_4
;
2277 else if (config_maxburst
>= 2)
2278 psize
= STEDMA40_PSIZE_PHY_2
;
2280 psize
= STEDMA40_PSIZE_PHY_1
;
2283 /* Set up all the endpoint configs */
2284 cfg
->src_info
.data_width
= addr_width
;
2285 cfg
->src_info
.psize
= psize
;
2286 cfg
->src_info
.big_endian
= false;
2287 cfg
->src_info
.flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2288 cfg
->dst_info
.data_width
= addr_width
;
2289 cfg
->dst_info
.psize
= psize
;
2290 cfg
->dst_info
.big_endian
= false;
2291 cfg
->dst_info
.flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2293 /* Fill in register values */
2294 if (chan_is_logical(d40c
))
2295 d40_log_cfg(cfg
, &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
2297 d40_phy_cfg(cfg
, &d40c
->src_def_cfg
,
2298 &d40c
->dst_def_cfg
, false);
2300 /* These settings will take precedence later */
2301 d40c
->runtime_addr
= config_addr
;
2302 d40c
->runtime_direction
= config
->direction
;
2303 dev_dbg(d40c
->base
->dev
,
2304 "configured channel %s for %s, data width %d, "
2305 "maxburst %d bytes, LE, no flow control\n",
2306 dma_chan_name(chan
),
2307 (config
->direction
== DMA_FROM_DEVICE
) ? "RX" : "TX",
2312 static int d40_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
2315 unsigned long flags
;
2316 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2318 if (d40c
->phy_chan
== NULL
) {
2319 chan_err(d40c
, "Channel is not allocated!\n");
2324 case DMA_TERMINATE_ALL
:
2325 spin_lock_irqsave(&d40c
->lock
, flags
);
2327 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2330 return d40_pause(chan
);
2332 return d40_resume(chan
);
2333 case DMA_SLAVE_CONFIG
:
2334 d40_set_runtime_config(chan
,
2335 (struct dma_slave_config
*) arg
);
2341 /* Other commands are unimplemented */
2345 /* Initialization functions */
2347 static void __init
d40_chan_init(struct d40_base
*base
, struct dma_device
*dma
,
2348 struct d40_chan
*chans
, int offset
,
2352 struct d40_chan
*d40c
;
2354 INIT_LIST_HEAD(&dma
->channels
);
2356 for (i
= offset
; i
< offset
+ num_chans
; i
++) {
2359 d40c
->chan
.device
= dma
;
2361 spin_lock_init(&d40c
->lock
);
2363 d40c
->log_num
= D40_PHY_CHAN
;
2365 INIT_LIST_HEAD(&d40c
->active
);
2366 INIT_LIST_HEAD(&d40c
->queue
);
2367 INIT_LIST_HEAD(&d40c
->client
);
2369 tasklet_init(&d40c
->tasklet
, dma_tasklet
,
2370 (unsigned long) d40c
);
2372 list_add_tail(&d40c
->chan
.device_node
,
2377 static int __init
d40_dmaengine_init(struct d40_base
*base
,
2378 int num_reserved_chans
)
2382 d40_chan_init(base
, &base
->dma_slave
, base
->log_chans
,
2383 0, base
->num_log_chans
);
2385 dma_cap_zero(base
->dma_slave
.cap_mask
);
2386 dma_cap_set(DMA_SLAVE
, base
->dma_slave
.cap_mask
);
2388 base
->dma_slave
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2389 base
->dma_slave
.device_free_chan_resources
= d40_free_chan_resources
;
2390 base
->dma_slave
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2391 base
->dma_slave
.device_prep_dma_sg
= d40_prep_sg
;
2392 base
->dma_slave
.device_prep_slave_sg
= d40_prep_slave_sg
;
2393 base
->dma_slave
.device_tx_status
= d40_tx_status
;
2394 base
->dma_slave
.device_issue_pending
= d40_issue_pending
;
2395 base
->dma_slave
.device_control
= d40_control
;
2396 base
->dma_slave
.dev
= base
->dev
;
2398 err
= dma_async_device_register(&base
->dma_slave
);
2401 d40_err(base
->dev
, "Failed to register slave channels\n");
2405 d40_chan_init(base
, &base
->dma_memcpy
, base
->log_chans
,
2406 base
->num_log_chans
, base
->plat_data
->memcpy_len
);
2408 dma_cap_zero(base
->dma_memcpy
.cap_mask
);
2409 dma_cap_set(DMA_MEMCPY
, base
->dma_memcpy
.cap_mask
);
2410 dma_cap_set(DMA_SG
, base
->dma_slave
.cap_mask
);
2412 base
->dma_memcpy
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2413 base
->dma_memcpy
.device_free_chan_resources
= d40_free_chan_resources
;
2414 base
->dma_memcpy
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2415 base
->dma_slave
.device_prep_dma_sg
= d40_prep_sg
;
2416 base
->dma_memcpy
.device_prep_slave_sg
= d40_prep_slave_sg
;
2417 base
->dma_memcpy
.device_tx_status
= d40_tx_status
;
2418 base
->dma_memcpy
.device_issue_pending
= d40_issue_pending
;
2419 base
->dma_memcpy
.device_control
= d40_control
;
2420 base
->dma_memcpy
.dev
= base
->dev
;
2422 * This controller can only access address at even
2423 * 32bit boundaries, i.e. 2^2
2425 base
->dma_memcpy
.copy_align
= 2;
2427 err
= dma_async_device_register(&base
->dma_memcpy
);
2431 "Failed to regsiter memcpy only channels\n");
2435 d40_chan_init(base
, &base
->dma_both
, base
->phy_chans
,
2436 0, num_reserved_chans
);
2438 dma_cap_zero(base
->dma_both
.cap_mask
);
2439 dma_cap_set(DMA_SLAVE
, base
->dma_both
.cap_mask
);
2440 dma_cap_set(DMA_MEMCPY
, base
->dma_both
.cap_mask
);
2441 dma_cap_set(DMA_SG
, base
->dma_slave
.cap_mask
);
2443 base
->dma_both
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2444 base
->dma_both
.device_free_chan_resources
= d40_free_chan_resources
;
2445 base
->dma_both
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2446 base
->dma_slave
.device_prep_dma_sg
= d40_prep_sg
;
2447 base
->dma_both
.device_prep_slave_sg
= d40_prep_slave_sg
;
2448 base
->dma_both
.device_tx_status
= d40_tx_status
;
2449 base
->dma_both
.device_issue_pending
= d40_issue_pending
;
2450 base
->dma_both
.device_control
= d40_control
;
2451 base
->dma_both
.dev
= base
->dev
;
2452 base
->dma_both
.copy_align
= 2;
2453 err
= dma_async_device_register(&base
->dma_both
);
2457 "Failed to register logical and physical capable channels\n");
2462 dma_async_device_unregister(&base
->dma_memcpy
);
2464 dma_async_device_unregister(&base
->dma_slave
);
2469 /* Initialization functions. */
2471 static int __init
d40_phy_res_init(struct d40_base
*base
)
2474 int num_phy_chans_avail
= 0;
2476 int odd_even_bit
= -2;
2478 val
[0] = readl(base
->virtbase
+ D40_DREG_PRSME
);
2479 val
[1] = readl(base
->virtbase
+ D40_DREG_PRSMO
);
2481 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2482 base
->phy_res
[i
].num
= i
;
2483 odd_even_bit
+= 2 * ((i
% 2) == 0);
2484 if (((val
[i
% 2] >> odd_even_bit
) & 3) == 1) {
2485 /* Mark security only channels as occupied */
2486 base
->phy_res
[i
].allocated_src
= D40_ALLOC_PHY
;
2487 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_PHY
;
2489 base
->phy_res
[i
].allocated_src
= D40_ALLOC_FREE
;
2490 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_FREE
;
2491 num_phy_chans_avail
++;
2493 spin_lock_init(&base
->phy_res
[i
].lock
);
2496 /* Mark disabled channels as occupied */
2497 for (i
= 0; base
->plat_data
->disabled_channels
[i
] != -1; i
++) {
2498 int chan
= base
->plat_data
->disabled_channels
[i
];
2500 base
->phy_res
[chan
].allocated_src
= D40_ALLOC_PHY
;
2501 base
->phy_res
[chan
].allocated_dst
= D40_ALLOC_PHY
;
2502 num_phy_chans_avail
--;
2505 dev_info(base
->dev
, "%d of %d physical DMA channels available\n",
2506 num_phy_chans_avail
, base
->num_phy_chans
);
2508 /* Verify settings extended vs standard */
2509 val
[0] = readl(base
->virtbase
+ D40_DREG_PRTYP
);
2511 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2513 if (base
->phy_res
[i
].allocated_src
== D40_ALLOC_FREE
&&
2514 (val
[0] & 0x3) != 1)
2516 "[%s] INFO: channel %d is misconfigured (%d)\n",
2517 __func__
, i
, val
[0] & 0x3);
2519 val
[0] = val
[0] >> 2;
2522 return num_phy_chans_avail
;
2525 static struct d40_base
* __init
d40_hw_detect_init(struct platform_device
*pdev
)
2527 static const struct d40_reg_val dma_id_regs
[] = {
2529 { .reg
= D40_DREG_PERIPHID0
, .val
= 0x0040},
2530 { .reg
= D40_DREG_PERIPHID1
, .val
= 0x0000},
2532 * D40_DREG_PERIPHID2 Depends on HW revision:
2533 * DB8500ed has 0x0008,
2535 * DB8500v1 has 0x0028
2536 * DB8500v2 has 0x0038
2538 { .reg
= D40_DREG_PERIPHID3
, .val
= 0x0000},
2541 { .reg
= D40_DREG_CELLID0
, .val
= 0x000d},
2542 { .reg
= D40_DREG_CELLID1
, .val
= 0x00f0},
2543 { .reg
= D40_DREG_CELLID2
, .val
= 0x0005},
2544 { .reg
= D40_DREG_CELLID3
, .val
= 0x00b1}
2546 struct stedma40_platform_data
*plat_data
;
2547 struct clk
*clk
= NULL
;
2548 void __iomem
*virtbase
= NULL
;
2549 struct resource
*res
= NULL
;
2550 struct d40_base
*base
= NULL
;
2551 int num_log_chans
= 0;
2557 clk
= clk_get(&pdev
->dev
, NULL
);
2560 d40_err(&pdev
->dev
, "No matching clock found\n");
2566 /* Get IO for DMAC base address */
2567 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "base");
2571 if (request_mem_region(res
->start
, resource_size(res
),
2572 D40_NAME
" I/O base") == NULL
)
2575 virtbase
= ioremap(res
->start
, resource_size(res
));
2579 /* HW version check */
2580 for (i
= 0; i
< ARRAY_SIZE(dma_id_regs
); i
++) {
2581 if (dma_id_regs
[i
].val
!=
2582 readl(virtbase
+ dma_id_regs
[i
].reg
)) {
2584 "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2587 readl(virtbase
+ dma_id_regs
[i
].reg
));
2592 /* Get silicon revision and designer */
2593 val
= readl(virtbase
+ D40_DREG_PERIPHID2
);
2595 if ((val
& D40_DREG_PERIPHID2_DESIGNER_MASK
) !=
2597 d40_err(&pdev
->dev
, "Unknown designer! Got %x wanted %x\n",
2598 val
& D40_DREG_PERIPHID2_DESIGNER_MASK
,
2603 rev
= (val
& D40_DREG_PERIPHID2_REV_MASK
) >>
2604 D40_DREG_PERIPHID2_REV_POS
;
2606 /* The number of physical channels on this HW */
2607 num_phy_chans
= 4 * (readl(virtbase
+ D40_DREG_ICFG
) & 0x7) + 4;
2609 dev_info(&pdev
->dev
, "hardware revision: %d @ 0x%x\n",
2612 plat_data
= pdev
->dev
.platform_data
;
2614 /* Count the number of logical channels in use */
2615 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2616 if (plat_data
->dev_rx
[i
] != 0)
2619 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2620 if (plat_data
->dev_tx
[i
] != 0)
2623 base
= kzalloc(ALIGN(sizeof(struct d40_base
), 4) +
2624 (num_phy_chans
+ num_log_chans
+ plat_data
->memcpy_len
) *
2625 sizeof(struct d40_chan
), GFP_KERNEL
);
2628 d40_err(&pdev
->dev
, "Out of memory\n");
2634 base
->num_phy_chans
= num_phy_chans
;
2635 base
->num_log_chans
= num_log_chans
;
2636 base
->phy_start
= res
->start
;
2637 base
->phy_size
= resource_size(res
);
2638 base
->virtbase
= virtbase
;
2639 base
->plat_data
= plat_data
;
2640 base
->dev
= &pdev
->dev
;
2641 base
->phy_chans
= ((void *)base
) + ALIGN(sizeof(struct d40_base
), 4);
2642 base
->log_chans
= &base
->phy_chans
[num_phy_chans
];
2644 base
->phy_res
= kzalloc(num_phy_chans
* sizeof(struct d40_phy_res
),
2649 base
->lookup_phy_chans
= kzalloc(num_phy_chans
*
2650 sizeof(struct d40_chan
*),
2652 if (!base
->lookup_phy_chans
)
2655 if (num_log_chans
+ plat_data
->memcpy_len
) {
2657 * The max number of logical channels are event lines for all
2658 * src devices and dst devices
2660 base
->lookup_log_chans
= kzalloc(plat_data
->dev_len
* 2 *
2661 sizeof(struct d40_chan
*),
2663 if (!base
->lookup_log_chans
)
2667 base
->lcla_pool
.alloc_map
= kzalloc(num_phy_chans
*
2668 sizeof(struct d40_desc
*) *
2669 D40_LCLA_LINK_PER_EVENT_GRP
,
2671 if (!base
->lcla_pool
.alloc_map
)
2674 base
->desc_slab
= kmem_cache_create(D40_NAME
, sizeof(struct d40_desc
),
2675 0, SLAB_HWCACHE_ALIGN
,
2677 if (base
->desc_slab
== NULL
)
2690 release_mem_region(res
->start
,
2691 resource_size(res
));
2696 kfree(base
->lcla_pool
.alloc_map
);
2697 kfree(base
->lookup_log_chans
);
2698 kfree(base
->lookup_phy_chans
);
2699 kfree(base
->phy_res
);
2706 static void __init
d40_hw_init(struct d40_base
*base
)
2709 static const struct d40_reg_val dma_init_reg
[] = {
2710 /* Clock every part of the DMA block from start */
2711 { .reg
= D40_DREG_GCC
, .val
= 0x0000ff01},
2713 /* Interrupts on all logical channels */
2714 { .reg
= D40_DREG_LCMIS0
, .val
= 0xFFFFFFFF},
2715 { .reg
= D40_DREG_LCMIS1
, .val
= 0xFFFFFFFF},
2716 { .reg
= D40_DREG_LCMIS2
, .val
= 0xFFFFFFFF},
2717 { .reg
= D40_DREG_LCMIS3
, .val
= 0xFFFFFFFF},
2718 { .reg
= D40_DREG_LCICR0
, .val
= 0xFFFFFFFF},
2719 { .reg
= D40_DREG_LCICR1
, .val
= 0xFFFFFFFF},
2720 { .reg
= D40_DREG_LCICR2
, .val
= 0xFFFFFFFF},
2721 { .reg
= D40_DREG_LCICR3
, .val
= 0xFFFFFFFF},
2722 { .reg
= D40_DREG_LCTIS0
, .val
= 0xFFFFFFFF},
2723 { .reg
= D40_DREG_LCTIS1
, .val
= 0xFFFFFFFF},
2724 { .reg
= D40_DREG_LCTIS2
, .val
= 0xFFFFFFFF},
2725 { .reg
= D40_DREG_LCTIS3
, .val
= 0xFFFFFFFF}
2728 u32 prmseo
[2] = {0, 0};
2729 u32 activeo
[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2733 for (i
= 0; i
< ARRAY_SIZE(dma_init_reg
); i
++)
2734 writel(dma_init_reg
[i
].val
,
2735 base
->virtbase
+ dma_init_reg
[i
].reg
);
2737 /* Configure all our dma channels to default settings */
2738 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2740 activeo
[i
% 2] = activeo
[i
% 2] << 2;
2742 if (base
->phy_res
[base
->num_phy_chans
- i
- 1].allocated_src
2744 activeo
[i
% 2] |= 3;
2748 /* Enable interrupt # */
2749 pcmis
= (pcmis
<< 1) | 1;
2751 /* Clear interrupt # */
2752 pcicr
= (pcicr
<< 1) | 1;
2754 /* Set channel to physical mode */
2755 prmseo
[i
% 2] = prmseo
[i
% 2] << 2;
2760 writel(prmseo
[1], base
->virtbase
+ D40_DREG_PRMSE
);
2761 writel(prmseo
[0], base
->virtbase
+ D40_DREG_PRMSO
);
2762 writel(activeo
[1], base
->virtbase
+ D40_DREG_ACTIVE
);
2763 writel(activeo
[0], base
->virtbase
+ D40_DREG_ACTIVO
);
2765 /* Write which interrupt to enable */
2766 writel(pcmis
, base
->virtbase
+ D40_DREG_PCMIS
);
2768 /* Write which interrupt to clear */
2769 writel(pcicr
, base
->virtbase
+ D40_DREG_PCICR
);
2773 static int __init
d40_lcla_allocate(struct d40_base
*base
)
2775 struct d40_lcla_pool
*pool
= &base
->lcla_pool
;
2776 unsigned long *page_list
;
2781 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2782 * To full fill this hardware requirement without wasting 256 kb
2783 * we allocate pages until we get an aligned one.
2785 page_list
= kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS
,
2793 /* Calculating how many pages that are required */
2794 base
->lcla_pool
.pages
= SZ_1K
* base
->num_phy_chans
/ PAGE_SIZE
;
2796 for (i
= 0; i
< MAX_LCLA_ALLOC_ATTEMPTS
; i
++) {
2797 page_list
[i
] = __get_free_pages(GFP_KERNEL
,
2798 base
->lcla_pool
.pages
);
2799 if (!page_list
[i
]) {
2801 d40_err(base
->dev
, "Failed to allocate %d pages.\n",
2802 base
->lcla_pool
.pages
);
2804 for (j
= 0; j
< i
; j
++)
2805 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2809 if ((virt_to_phys((void *)page_list
[i
]) &
2810 (LCLA_ALIGNMENT
- 1)) == 0)
2814 for (j
= 0; j
< i
; j
++)
2815 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2817 if (i
< MAX_LCLA_ALLOC_ATTEMPTS
) {
2818 base
->lcla_pool
.base
= (void *)page_list
[i
];
2821 * After many attempts and no succees with finding the correct
2822 * alignment, try with allocating a big buffer.
2825 "[%s] Failed to get %d pages @ 18 bit align.\n",
2826 __func__
, base
->lcla_pool
.pages
);
2827 base
->lcla_pool
.base_unaligned
= kmalloc(SZ_1K
*
2828 base
->num_phy_chans
+
2831 if (!base
->lcla_pool
.base_unaligned
) {
2836 base
->lcla_pool
.base
= PTR_ALIGN(base
->lcla_pool
.base_unaligned
,
2840 pool
->dma_addr
= dma_map_single(base
->dev
, pool
->base
,
2841 SZ_1K
* base
->num_phy_chans
,
2843 if (dma_mapping_error(base
->dev
, pool
->dma_addr
)) {
2849 writel(virt_to_phys(base
->lcla_pool
.base
),
2850 base
->virtbase
+ D40_DREG_LCLA
);
2856 static int __init
d40_probe(struct platform_device
*pdev
)
2860 struct d40_base
*base
;
2861 struct resource
*res
= NULL
;
2862 int num_reserved_chans
;
2865 base
= d40_hw_detect_init(pdev
);
2870 num_reserved_chans
= d40_phy_res_init(base
);
2872 platform_set_drvdata(pdev
, base
);
2874 spin_lock_init(&base
->interrupt_lock
);
2875 spin_lock_init(&base
->execmd_lock
);
2877 /* Get IO for logical channel parameter address */
2878 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "lcpa");
2881 d40_err(&pdev
->dev
, "No \"lcpa\" memory resource\n");
2884 base
->lcpa_size
= resource_size(res
);
2885 base
->phy_lcpa
= res
->start
;
2887 if (request_mem_region(res
->start
, resource_size(res
),
2888 D40_NAME
" I/O lcpa") == NULL
) {
2891 "Failed to request LCPA region 0x%x-0x%x\n",
2892 res
->start
, res
->end
);
2896 /* We make use of ESRAM memory for this. */
2897 val
= readl(base
->virtbase
+ D40_DREG_LCPA
);
2898 if (res
->start
!= val
&& val
!= 0) {
2899 dev_warn(&pdev
->dev
,
2900 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2901 __func__
, val
, res
->start
);
2903 writel(res
->start
, base
->virtbase
+ D40_DREG_LCPA
);
2905 base
->lcpa_base
= ioremap(res
->start
, resource_size(res
));
2906 if (!base
->lcpa_base
) {
2908 d40_err(&pdev
->dev
, "Failed to ioremap LCPA region\n");
2912 ret
= d40_lcla_allocate(base
);
2914 d40_err(&pdev
->dev
, "Failed to allocate LCLA area\n");
2918 spin_lock_init(&base
->lcla_pool
.lock
);
2920 base
->irq
= platform_get_irq(pdev
, 0);
2922 ret
= request_irq(base
->irq
, d40_handle_interrupt
, 0, D40_NAME
, base
);
2924 d40_err(&pdev
->dev
, "No IRQ defined\n");
2928 err
= d40_dmaengine_init(base
, num_reserved_chans
);
2934 dev_info(base
->dev
, "initialized\n");
2939 if (base
->desc_slab
)
2940 kmem_cache_destroy(base
->desc_slab
);
2942 iounmap(base
->virtbase
);
2944 if (base
->lcla_pool
.dma_addr
)
2945 dma_unmap_single(base
->dev
, base
->lcla_pool
.dma_addr
,
2946 SZ_1K
* base
->num_phy_chans
,
2949 if (!base
->lcla_pool
.base_unaligned
&& base
->lcla_pool
.base
)
2950 free_pages((unsigned long)base
->lcla_pool
.base
,
2951 base
->lcla_pool
.pages
);
2953 kfree(base
->lcla_pool
.base_unaligned
);
2956 release_mem_region(base
->phy_lcpa
,
2958 if (base
->phy_start
)
2959 release_mem_region(base
->phy_start
,
2962 clk_disable(base
->clk
);
2966 kfree(base
->lcla_pool
.alloc_map
);
2967 kfree(base
->lookup_log_chans
);
2968 kfree(base
->lookup_phy_chans
);
2969 kfree(base
->phy_res
);
2973 d40_err(&pdev
->dev
, "probe failed\n");
2977 static struct platform_driver d40_driver
= {
2979 .owner
= THIS_MODULE
,
2984 static int __init
stedma40_init(void)
2986 return platform_driver_probe(&d40_driver
, d40_probe
);
2988 arch_initcall(stedma40_init
);