2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
9 #include <linux/dma-mapping.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/export.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/err.h>
20 #include <linux/amba/bus.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/platform_data/dma-ste-dma40.h>
24 #include "dmaengine.h"
25 #include "ste_dma40_ll.h"
27 #define D40_NAME "dma40"
29 #define D40_PHY_CHAN -1
31 /* For masking out/in 2 bit channel positions */
32 #define D40_CHAN_POS(chan) (2 * (chan / 2))
33 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
35 /* Maximum iterations taken before giving up suspending a channel */
36 #define D40_SUSPEND_MAX_IT 500
39 #define DMA40_AUTOSUSPEND_DELAY 100
41 /* Hardware requirement on LCLA alignment */
42 #define LCLA_ALIGNMENT 0x40000
44 /* Max number of links per event group */
45 #define D40_LCLA_LINK_PER_EVENT_GRP 128
46 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
48 /* Attempts before giving up to trying to get pages that are aligned */
49 #define MAX_LCLA_ALLOC_ATTEMPTS 256
51 /* Bit markings for allocation map */
52 #define D40_ALLOC_FREE (1 << 31)
53 #define D40_ALLOC_PHY (1 << 30)
54 #define D40_ALLOC_LOG_FREE 0
57 * enum 40_command - The different commands and/or statuses.
59 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
60 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
61 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
62 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
67 D40_DMA_SUSPEND_REQ
= 2,
72 * enum d40_events - The different Event Enables for the event lines.
74 * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
75 * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
76 * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
77 * @D40_ROUND_EVENTLINE: Status check for event line.
81 D40_DEACTIVATE_EVENTLINE
= 0,
82 D40_ACTIVATE_EVENTLINE
= 1,
83 D40_SUSPEND_REQ_EVENTLINE
= 2,
84 D40_ROUND_EVENTLINE
= 3
88 * These are the registers that has to be saved and later restored
89 * when the DMA hw is powered off.
90 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
92 static u32 d40_backup_regs
[] = {
101 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
103 /* TODO: Check if all these registers have to be saved/restored on dma40 v3 */
104 static u32 d40_backup_regs_v3
[] = {
123 #define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3)
125 static u32 d40_backup_regs_chan
[] = {
137 * struct d40_lli_pool - Structure for keeping LLIs in memory
139 * @base: Pointer to memory area when the pre_alloc_lli's are not large
140 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
141 * pre_alloc_lli is used.
142 * @dma_addr: DMA address, if mapped
143 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
144 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
145 * one buffer to one buffer.
147 struct d40_lli_pool
{
151 /* Space for dst and src, plus an extra for padding */
152 u8 pre_alloc_lli
[3 * sizeof(struct d40_phy_lli
)];
156 * struct d40_desc - A descriptor is one DMA job.
158 * @lli_phy: LLI settings for physical channel. Both src and dst=
159 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
160 * lli_len equals one.
161 * @lli_log: Same as above but for logical channels.
162 * @lli_pool: The pool with two entries pre-allocated.
163 * @lli_len: Number of llis of current descriptor.
164 * @lli_current: Number of transferred llis.
165 * @lcla_alloc: Number of LCLA entries allocated.
166 * @txd: DMA engine struct. Used for among other things for communication
169 * @is_in_client_list: true if the client owns this descriptor.
170 * @cyclic: true if this is a cyclic job
172 * This descriptor is used for both logical and physical transfers.
176 struct d40_phy_lli_bidir lli_phy
;
178 struct d40_log_lli_bidir lli_log
;
180 struct d40_lli_pool lli_pool
;
185 struct dma_async_tx_descriptor txd
;
186 struct list_head node
;
188 bool is_in_client_list
;
193 * struct d40_lcla_pool - LCLA pool settings and data.
195 * @base: The virtual address of LCLA. 18 bit aligned.
196 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
197 * This pointer is only there for clean-up on error.
198 * @pages: The number of pages needed for all physical channels.
199 * Only used later for clean-up on error
200 * @lock: Lock to protect the content in this struct.
201 * @alloc_map: big map over which LCLA entry is own by which job.
203 struct d40_lcla_pool
{
206 void *base_unaligned
;
209 struct d40_desc
**alloc_map
;
213 * struct d40_phy_res - struct for handling eventlines mapped to physical
216 * @lock: A lock protection this entity.
217 * @reserved: True if used by secure world or otherwise.
218 * @num: The physical channel number of this entity.
219 * @allocated_src: Bit mapped to show which src event line's are mapped to
220 * this physical channel. Can also be free or physically allocated.
221 * @allocated_dst: Same as for src but is dst.
222 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
236 * struct d40_chan - Struct that describes a channel.
238 * @lock: A spinlock to protect this struct.
239 * @log_num: The logical number, if any of this channel.
240 * @pending_tx: The number of pending transfers. Used between interrupt handler
242 * @busy: Set to true when transfer is ongoing on this channel.
243 * @phy_chan: Pointer to physical channel which this instance runs on. If this
244 * point is NULL, then the channel is not allocated.
245 * @chan: DMA engine handle.
246 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
247 * transfer and call client callback.
248 * @client: Cliented owned descriptor list.
249 * @pending_queue: Submitted jobs, to be issued by issue_pending()
250 * @active: Active descriptor.
251 * @queue: Queued jobs.
252 * @prepare_queue: Prepared jobs.
253 * @dma_cfg: The client configuration of this dma channel.
254 * @configured: whether the dma_cfg configuration is valid
255 * @base: Pointer to the device instance struct.
256 * @src_def_cfg: Default cfg register setting for src.
257 * @dst_def_cfg: Default cfg register setting for dst.
258 * @log_def: Default logical channel settings.
259 * @lcpa: Pointer to dst and src lcpa settings.
260 * @runtime_addr: runtime configured address.
261 * @runtime_direction: runtime configured direction.
263 * This struct can either "be" a logical or a physical channel.
270 struct d40_phy_res
*phy_chan
;
271 struct dma_chan chan
;
272 struct tasklet_struct tasklet
;
273 struct list_head client
;
274 struct list_head pending_queue
;
275 struct list_head active
;
276 struct list_head queue
;
277 struct list_head prepare_queue
;
278 struct stedma40_chan_cfg dma_cfg
;
280 struct d40_base
*base
;
281 /* Default register configurations */
284 struct d40_def_lcsp log_def
;
285 struct d40_log_lli_full
*lcpa
;
286 /* Runtime reconfiguration */
287 dma_addr_t runtime_addr
;
288 enum dma_transfer_direction runtime_direction
;
292 * struct d40_base - The big global struct, one for each probe'd instance.
294 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
295 * @execmd_lock: Lock for execute command usage since several channels share
296 * the same physical register.
297 * @dev: The device structure.
298 * @virtbase: The virtual base address of the DMA's register.
299 * @rev: silicon revision detected.
300 * @clk: Pointer to the DMA clock structure.
301 * @phy_start: Physical memory start of the DMA registers.
302 * @phy_size: Size of the DMA register map.
303 * @irq: The IRQ number.
304 * @num_phy_chans: The number of physical channels. Read from HW. This
305 * is the number of available channels for this driver, not counting "Secure
306 * mode" allocated physical channels.
307 * @num_log_chans: The number of logical channels. Calculated from
309 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
310 * @dma_slave: dma_device channels that can do only do slave transfers.
311 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
312 * @phy_chans: Room for all possible physical channels in system.
313 * @log_chans: Room for all possible logical channels in system.
314 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
315 * to log_chans entries.
316 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
317 * to phy_chans entries.
318 * @plat_data: Pointer to provided platform_data which is the driver
320 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
321 * @phy_res: Vector containing all physical channels.
322 * @lcla_pool: lcla pool settings and data.
323 * @lcpa_base: The virtual mapped address of LCPA.
324 * @phy_lcpa: The physical address of the LCPA.
325 * @lcpa_size: The size of the LCPA area.
326 * @desc_slab: cache for descriptors.
327 * @reg_val_backup: Here the values of some hardware registers are stored
328 * before the DMA is powered off. They are restored when the power is back on.
329 * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and
331 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
332 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
333 * @initialized: true if the dma has been initialized
336 spinlock_t interrupt_lock
;
337 spinlock_t execmd_lock
;
339 void __iomem
*virtbase
;
342 phys_addr_t phy_start
;
343 resource_size_t phy_size
;
347 struct device_dma_parameters dma_parms
;
348 struct dma_device dma_both
;
349 struct dma_device dma_slave
;
350 struct dma_device dma_memcpy
;
351 struct d40_chan
*phy_chans
;
352 struct d40_chan
*log_chans
;
353 struct d40_chan
**lookup_log_chans
;
354 struct d40_chan
**lookup_phy_chans
;
355 struct stedma40_platform_data
*plat_data
;
356 struct regulator
*lcpa_regulator
;
357 /* Physical half channels */
358 struct d40_phy_res
*phy_res
;
359 struct d40_lcla_pool lcla_pool
;
362 resource_size_t lcpa_size
;
363 struct kmem_cache
*desc_slab
;
364 u32 reg_val_backup
[BACKUP_REGS_SZ
];
365 u32 reg_val_backup_v3
[BACKUP_REGS_SZ_V3
];
366 u32
*reg_val_backup_chan
;
367 u16 gcc_pwr_off_mask
;
372 * struct d40_interrupt_lookup - lookup table for interrupt handler
374 * @src: Interrupt mask register.
375 * @clr: Interrupt clear register.
376 * @is_error: true if this is an error interrupt.
377 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
378 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
380 struct d40_interrupt_lookup
{
388 * struct d40_reg_val - simple lookup struct
390 * @reg: The register.
391 * @val: The value that belongs to the register in reg.
398 static struct device
*chan2dev(struct d40_chan
*d40c
)
400 return &d40c
->chan
.dev
->device
;
403 static bool chan_is_physical(struct d40_chan
*chan
)
405 return chan
->log_num
== D40_PHY_CHAN
;
408 static bool chan_is_logical(struct d40_chan
*chan
)
410 return !chan_is_physical(chan
);
413 static void __iomem
*chan_base(struct d40_chan
*chan
)
415 return chan
->base
->virtbase
+ D40_DREG_PCBASE
+
416 chan
->phy_chan
->num
* D40_DREG_PCDELTA
;
419 #define d40_err(dev, format, arg...) \
420 dev_err(dev, "[%s] " format, __func__, ## arg)
422 #define chan_err(d40c, format, arg...) \
423 d40_err(chan2dev(d40c), format, ## arg)
425 static int d40_pool_lli_alloc(struct d40_chan
*d40c
, struct d40_desc
*d40d
,
428 bool is_log
= chan_is_logical(d40c
);
433 align
= sizeof(struct d40_log_lli
);
435 align
= sizeof(struct d40_phy_lli
);
438 base
= d40d
->lli_pool
.pre_alloc_lli
;
439 d40d
->lli_pool
.size
= sizeof(d40d
->lli_pool
.pre_alloc_lli
);
440 d40d
->lli_pool
.base
= NULL
;
442 d40d
->lli_pool
.size
= lli_len
* 2 * align
;
444 base
= kmalloc(d40d
->lli_pool
.size
+ align
, GFP_NOWAIT
);
445 d40d
->lli_pool
.base
= base
;
447 if (d40d
->lli_pool
.base
== NULL
)
452 d40d
->lli_log
.src
= PTR_ALIGN(base
, align
);
453 d40d
->lli_log
.dst
= d40d
->lli_log
.src
+ lli_len
;
455 d40d
->lli_pool
.dma_addr
= 0;
457 d40d
->lli_phy
.src
= PTR_ALIGN(base
, align
);
458 d40d
->lli_phy
.dst
= d40d
->lli_phy
.src
+ lli_len
;
460 d40d
->lli_pool
.dma_addr
= dma_map_single(d40c
->base
->dev
,
465 if (dma_mapping_error(d40c
->base
->dev
,
466 d40d
->lli_pool
.dma_addr
)) {
467 kfree(d40d
->lli_pool
.base
);
468 d40d
->lli_pool
.base
= NULL
;
469 d40d
->lli_pool
.dma_addr
= 0;
477 static void d40_pool_lli_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
479 if (d40d
->lli_pool
.dma_addr
)
480 dma_unmap_single(d40c
->base
->dev
, d40d
->lli_pool
.dma_addr
,
481 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
483 kfree(d40d
->lli_pool
.base
);
484 d40d
->lli_pool
.base
= NULL
;
485 d40d
->lli_pool
.size
= 0;
486 d40d
->lli_log
.src
= NULL
;
487 d40d
->lli_log
.dst
= NULL
;
488 d40d
->lli_phy
.src
= NULL
;
489 d40d
->lli_phy
.dst
= NULL
;
492 static int d40_lcla_alloc_one(struct d40_chan
*d40c
,
493 struct d40_desc
*d40d
)
500 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
502 p
= d40c
->phy_chan
->num
* D40_LCLA_LINK_PER_EVENT_GRP
;
505 * Allocate both src and dst at the same time, therefore the half
506 * start on 1 since 0 can't be used since zero is used as end marker.
508 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
509 if (!d40c
->base
->lcla_pool
.alloc_map
[p
+ i
]) {
510 d40c
->base
->lcla_pool
.alloc_map
[p
+ i
] = d40d
;
517 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
522 static int d40_lcla_free_all(struct d40_chan
*d40c
,
523 struct d40_desc
*d40d
)
529 if (chan_is_physical(d40c
))
532 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
534 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
535 if (d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
536 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] == d40d
) {
537 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
538 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] = NULL
;
540 if (d40d
->lcla_alloc
== 0) {
547 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
553 static void d40_desc_remove(struct d40_desc
*d40d
)
555 list_del(&d40d
->node
);
558 static struct d40_desc
*d40_desc_get(struct d40_chan
*d40c
)
560 struct d40_desc
*desc
= NULL
;
562 if (!list_empty(&d40c
->client
)) {
566 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
) {
567 if (async_tx_test_ack(&d
->txd
)) {
570 memset(desc
, 0, sizeof(*desc
));
577 desc
= kmem_cache_zalloc(d40c
->base
->desc_slab
, GFP_NOWAIT
);
580 INIT_LIST_HEAD(&desc
->node
);
585 static void d40_desc_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
588 d40_pool_lli_free(d40c
, d40d
);
589 d40_lcla_free_all(d40c
, d40d
);
590 kmem_cache_free(d40c
->base
->desc_slab
, d40d
);
593 static void d40_desc_submit(struct d40_chan
*d40c
, struct d40_desc
*desc
)
595 list_add_tail(&desc
->node
, &d40c
->active
);
598 static void d40_phy_lli_load(struct d40_chan
*chan
, struct d40_desc
*desc
)
600 struct d40_phy_lli
*lli_dst
= desc
->lli_phy
.dst
;
601 struct d40_phy_lli
*lli_src
= desc
->lli_phy
.src
;
602 void __iomem
*base
= chan_base(chan
);
604 writel(lli_src
->reg_cfg
, base
+ D40_CHAN_REG_SSCFG
);
605 writel(lli_src
->reg_elt
, base
+ D40_CHAN_REG_SSELT
);
606 writel(lli_src
->reg_ptr
, base
+ D40_CHAN_REG_SSPTR
);
607 writel(lli_src
->reg_lnk
, base
+ D40_CHAN_REG_SSLNK
);
609 writel(lli_dst
->reg_cfg
, base
+ D40_CHAN_REG_SDCFG
);
610 writel(lli_dst
->reg_elt
, base
+ D40_CHAN_REG_SDELT
);
611 writel(lli_dst
->reg_ptr
, base
+ D40_CHAN_REG_SDPTR
);
612 writel(lli_dst
->reg_lnk
, base
+ D40_CHAN_REG_SDLNK
);
615 static void d40_log_lli_to_lcxa(struct d40_chan
*chan
, struct d40_desc
*desc
)
617 struct d40_lcla_pool
*pool
= &chan
->base
->lcla_pool
;
618 struct d40_log_lli_bidir
*lli
= &desc
->lli_log
;
619 int lli_current
= desc
->lli_current
;
620 int lli_len
= desc
->lli_len
;
621 bool cyclic
= desc
->cyclic
;
622 int curr_lcla
= -EINVAL
;
624 bool use_esram_lcla
= chan
->base
->plat_data
->use_esram_lcla
;
628 * We may have partially running cyclic transfers, in case we did't get
629 * enough LCLA entries.
631 linkback
= cyclic
&& lli_current
== 0;
634 * For linkback, we need one LCLA even with only one link, because we
635 * can't link back to the one in LCPA space
637 if (linkback
|| (lli_len
- lli_current
> 1)) {
638 curr_lcla
= d40_lcla_alloc_one(chan
, desc
);
639 first_lcla
= curr_lcla
;
643 * For linkback, we normally load the LCPA in the loop since we need to
644 * link it to the second LCLA and not the first. However, if we
645 * couldn't even get a first LCLA, then we have to run in LCPA and
648 if (!linkback
|| curr_lcla
== -EINVAL
) {
649 unsigned int flags
= 0;
651 if (curr_lcla
== -EINVAL
)
652 flags
|= LLI_TERM_INT
;
654 d40_log_lli_lcpa_write(chan
->lcpa
,
655 &lli
->dst
[lli_current
],
656 &lli
->src
[lli_current
],
665 for (; lli_current
< lli_len
; lli_current
++) {
666 unsigned int lcla_offset
= chan
->phy_chan
->num
* 1024 +
668 struct d40_log_lli
*lcla
= pool
->base
+ lcla_offset
;
669 unsigned int flags
= 0;
672 if (lli_current
+ 1 < lli_len
)
673 next_lcla
= d40_lcla_alloc_one(chan
, desc
);
675 next_lcla
= linkback
? first_lcla
: -EINVAL
;
677 if (cyclic
|| next_lcla
== -EINVAL
)
678 flags
|= LLI_TERM_INT
;
680 if (linkback
&& curr_lcla
== first_lcla
) {
681 /* First link goes in both LCPA and LCLA */
682 d40_log_lli_lcpa_write(chan
->lcpa
,
683 &lli
->dst
[lli_current
],
684 &lli
->src
[lli_current
],
689 * One unused LCLA in the cyclic case if the very first
692 d40_log_lli_lcla_write(lcla
,
693 &lli
->dst
[lli_current
],
694 &lli
->src
[lli_current
],
698 * Cache maintenance is not needed if lcla is
701 if (!use_esram_lcla
) {
702 dma_sync_single_range_for_device(chan
->base
->dev
,
703 pool
->dma_addr
, lcla_offset
,
704 2 * sizeof(struct d40_log_lli
),
707 curr_lcla
= next_lcla
;
709 if (curr_lcla
== -EINVAL
|| curr_lcla
== first_lcla
) {
716 desc
->lli_current
= lli_current
;
719 static void d40_desc_load(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
721 if (chan_is_physical(d40c
)) {
722 d40_phy_lli_load(d40c
, d40d
);
723 d40d
->lli_current
= d40d
->lli_len
;
725 d40_log_lli_to_lcxa(d40c
, d40d
);
728 static struct d40_desc
*d40_first_active_get(struct d40_chan
*d40c
)
732 if (list_empty(&d40c
->active
))
735 d
= list_first_entry(&d40c
->active
,
741 /* remove desc from current queue and add it to the pending_queue */
742 static void d40_desc_queue(struct d40_chan
*d40c
, struct d40_desc
*desc
)
744 d40_desc_remove(desc
);
745 desc
->is_in_client_list
= false;
746 list_add_tail(&desc
->node
, &d40c
->pending_queue
);
749 static struct d40_desc
*d40_first_pending(struct d40_chan
*d40c
)
753 if (list_empty(&d40c
->pending_queue
))
756 d
= list_first_entry(&d40c
->pending_queue
,
762 static struct d40_desc
*d40_first_queued(struct d40_chan
*d40c
)
766 if (list_empty(&d40c
->queue
))
769 d
= list_first_entry(&d40c
->queue
,
775 static int d40_psize_2_burst_size(bool is_log
, int psize
)
778 if (psize
== STEDMA40_PSIZE_LOG_1
)
781 if (psize
== STEDMA40_PSIZE_PHY_1
)
789 * The dma only supports transmitting packages up to
790 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
791 * dma elements required to send the entire sg list
793 static int d40_size_2_dmalen(int size
, u32 data_width1
, u32 data_width2
)
796 u32 max_w
= max(data_width1
, data_width2
);
797 u32 min_w
= min(data_width1
, data_width2
);
798 u32 seg_max
= ALIGN(STEDMA40_MAX_SEG_SIZE
<< min_w
, 1 << max_w
);
800 if (seg_max
> STEDMA40_MAX_SEG_SIZE
)
801 seg_max
-= (1 << max_w
);
803 if (!IS_ALIGNED(size
, 1 << max_w
))
809 dmalen
= size
/ seg_max
;
810 if (dmalen
* seg_max
< size
)
816 static int d40_sg_2_dmalen(struct scatterlist
*sgl
, int sg_len
,
817 u32 data_width1
, u32 data_width2
)
819 struct scatterlist
*sg
;
824 for_each_sg(sgl
, sg
, sg_len
, i
) {
825 ret
= d40_size_2_dmalen(sg_dma_len(sg
),
826 data_width1
, data_width2
);
836 static void dma40_backup(void __iomem
*baseaddr
, u32
*backup
,
837 u32
*regaddr
, int num
, bool save
)
841 for (i
= 0; i
< num
; i
++) {
842 void __iomem
*addr
= baseaddr
+ regaddr
[i
];
845 backup
[i
] = readl_relaxed(addr
);
847 writel_relaxed(backup
[i
], addr
);
851 static void d40_save_restore_registers(struct d40_base
*base
, bool save
)
855 /* Save/Restore channel specific registers */
856 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
860 if (base
->phy_res
[i
].reserved
)
863 addr
= base
->virtbase
+ D40_DREG_PCBASE
+ i
* D40_DREG_PCDELTA
;
864 idx
= i
* ARRAY_SIZE(d40_backup_regs_chan
);
866 dma40_backup(addr
, &base
->reg_val_backup_chan
[idx
],
867 d40_backup_regs_chan
,
868 ARRAY_SIZE(d40_backup_regs_chan
),
872 /* Save/Restore global registers */
873 dma40_backup(base
->virtbase
, base
->reg_val_backup
,
874 d40_backup_regs
, ARRAY_SIZE(d40_backup_regs
),
877 /* Save/Restore registers only existing on dma40 v3 and later */
879 dma40_backup(base
->virtbase
, base
->reg_val_backup_v3
,
881 ARRAY_SIZE(d40_backup_regs_v3
),
885 static void d40_save_restore_registers(struct d40_base
*base
, bool save
)
890 static int __d40_execute_command_phy(struct d40_chan
*d40c
,
891 enum d40_command command
)
895 void __iomem
*active_reg
;
900 if (command
== D40_DMA_STOP
) {
901 ret
= __d40_execute_command_phy(d40c
, D40_DMA_SUSPEND_REQ
);
906 spin_lock_irqsave(&d40c
->base
->execmd_lock
, flags
);
908 if (d40c
->phy_chan
->num
% 2 == 0)
909 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
911 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
913 if (command
== D40_DMA_SUSPEND_REQ
) {
914 status
= (readl(active_reg
) &
915 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
916 D40_CHAN_POS(d40c
->phy_chan
->num
);
918 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
922 wmask
= 0xffffffff & ~(D40_CHAN_POS_MASK(d40c
->phy_chan
->num
));
923 writel(wmask
| (command
<< D40_CHAN_POS(d40c
->phy_chan
->num
)),
926 if (command
== D40_DMA_SUSPEND_REQ
) {
928 for (i
= 0 ; i
< D40_SUSPEND_MAX_IT
; i
++) {
929 status
= (readl(active_reg
) &
930 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
931 D40_CHAN_POS(d40c
->phy_chan
->num
);
935 * Reduce the number of bus accesses while
936 * waiting for the DMA to suspend.
940 if (status
== D40_DMA_STOP
||
941 status
== D40_DMA_SUSPENDED
)
945 if (i
== D40_SUSPEND_MAX_IT
) {
947 "unable to suspend the chl %d (log: %d) status %x\n",
948 d40c
->phy_chan
->num
, d40c
->log_num
,
956 spin_unlock_irqrestore(&d40c
->base
->execmd_lock
, flags
);
960 static void d40_term_all(struct d40_chan
*d40c
)
962 struct d40_desc
*d40d
;
965 /* Release active descriptors */
966 while ((d40d
= d40_first_active_get(d40c
))) {
967 d40_desc_remove(d40d
);
968 d40_desc_free(d40c
, d40d
);
971 /* Release queued descriptors waiting for transfer */
972 while ((d40d
= d40_first_queued(d40c
))) {
973 d40_desc_remove(d40d
);
974 d40_desc_free(d40c
, d40d
);
977 /* Release pending descriptors */
978 while ((d40d
= d40_first_pending(d40c
))) {
979 d40_desc_remove(d40d
);
980 d40_desc_free(d40c
, d40d
);
983 /* Release client owned descriptors */
984 if (!list_empty(&d40c
->client
))
985 list_for_each_entry_safe(d40d
, _d
, &d40c
->client
, node
) {
986 d40_desc_remove(d40d
);
987 d40_desc_free(d40c
, d40d
);
990 /* Release descriptors in prepare queue */
991 if (!list_empty(&d40c
->prepare_queue
))
992 list_for_each_entry_safe(d40d
, _d
,
993 &d40c
->prepare_queue
, node
) {
994 d40_desc_remove(d40d
);
995 d40_desc_free(d40c
, d40d
);
998 d40c
->pending_tx
= 0;
1001 static void __d40_config_set_event(struct d40_chan
*d40c
,
1002 enum d40_events event_type
, u32 event
,
1005 void __iomem
*addr
= chan_base(d40c
) + reg
;
1009 switch (event_type
) {
1011 case D40_DEACTIVATE_EVENTLINE
:
1013 writel((D40_DEACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
))
1014 | ~D40_EVENTLINE_MASK(event
), addr
);
1017 case D40_SUSPEND_REQ_EVENTLINE
:
1018 status
= (readl(addr
) & D40_EVENTLINE_MASK(event
)) >>
1019 D40_EVENTLINE_POS(event
);
1021 if (status
== D40_DEACTIVATE_EVENTLINE
||
1022 status
== D40_SUSPEND_REQ_EVENTLINE
)
1025 writel((D40_SUSPEND_REQ_EVENTLINE
<< D40_EVENTLINE_POS(event
))
1026 | ~D40_EVENTLINE_MASK(event
), addr
);
1028 for (tries
= 0 ; tries
< D40_SUSPEND_MAX_IT
; tries
++) {
1030 status
= (readl(addr
) & D40_EVENTLINE_MASK(event
)) >>
1031 D40_EVENTLINE_POS(event
);
1035 * Reduce the number of bus accesses while
1036 * waiting for the DMA to suspend.
1040 if (status
== D40_DEACTIVATE_EVENTLINE
)
1044 if (tries
== D40_SUSPEND_MAX_IT
) {
1046 "unable to stop the event_line chl %d (log: %d)"
1047 "status %x\n", d40c
->phy_chan
->num
,
1048 d40c
->log_num
, status
);
1052 case D40_ACTIVATE_EVENTLINE
:
1054 * The hardware sometimes doesn't register the enable when src and dst
1055 * event lines are active on the same logical channel. Retry to ensure
1056 * it does. Usually only one retry is sufficient.
1060 writel((D40_ACTIVATE_EVENTLINE
<<
1061 D40_EVENTLINE_POS(event
)) |
1062 ~D40_EVENTLINE_MASK(event
), addr
);
1064 if (readl(addr
) & D40_EVENTLINE_MASK(event
))
1069 dev_dbg(chan2dev(d40c
),
1070 "[%s] workaround enable S%cLNK (%d tries)\n",
1071 __func__
, reg
== D40_CHAN_REG_SSLNK
? 'S' : 'D',
1077 case D40_ROUND_EVENTLINE
:
1084 static void d40_config_set_event(struct d40_chan
*d40c
,
1085 enum d40_events event_type
)
1087 /* Enable event line connected to device (or memcpy) */
1088 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
1089 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
)) {
1090 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1092 __d40_config_set_event(d40c
, event_type
, event
,
1093 D40_CHAN_REG_SSLNK
);
1096 if (d40c
->dma_cfg
.dir
!= STEDMA40_PERIPH_TO_MEM
) {
1097 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1099 __d40_config_set_event(d40c
, event_type
, event
,
1100 D40_CHAN_REG_SDLNK
);
1104 static u32
d40_chan_has_events(struct d40_chan
*d40c
)
1106 void __iomem
*chanbase
= chan_base(d40c
);
1109 val
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
1110 val
|= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
1116 __d40_execute_command_log(struct d40_chan
*d40c
, enum d40_command command
)
1118 unsigned long flags
;
1121 void __iomem
*active_reg
;
1123 if (d40c
->phy_chan
->num
% 2 == 0)
1124 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
1126 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
1129 spin_lock_irqsave(&d40c
->phy_chan
->lock
, flags
);
1133 case D40_DMA_SUSPEND_REQ
:
1135 active_status
= (readl(active_reg
) &
1136 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
1137 D40_CHAN_POS(d40c
->phy_chan
->num
);
1139 if (active_status
== D40_DMA_RUN
)
1140 d40_config_set_event(d40c
, D40_SUSPEND_REQ_EVENTLINE
);
1142 d40_config_set_event(d40c
, D40_DEACTIVATE_EVENTLINE
);
1144 if (!d40_chan_has_events(d40c
) && (command
== D40_DMA_STOP
))
1145 ret
= __d40_execute_command_phy(d40c
, command
);
1151 d40_config_set_event(d40c
, D40_ACTIVATE_EVENTLINE
);
1152 ret
= __d40_execute_command_phy(d40c
, command
);
1155 case D40_DMA_SUSPENDED
:
1160 spin_unlock_irqrestore(&d40c
->phy_chan
->lock
, flags
);
1164 static int d40_channel_execute_command(struct d40_chan
*d40c
,
1165 enum d40_command command
)
1167 if (chan_is_logical(d40c
))
1168 return __d40_execute_command_log(d40c
, command
);
1170 return __d40_execute_command_phy(d40c
, command
);
1173 static u32
d40_get_prmo(struct d40_chan
*d40c
)
1175 static const unsigned int phy_map
[] = {
1176 [STEDMA40_PCHAN_BASIC_MODE
]
1177 = D40_DREG_PRMO_PCHAN_BASIC
,
1178 [STEDMA40_PCHAN_MODULO_MODE
]
1179 = D40_DREG_PRMO_PCHAN_MODULO
,
1180 [STEDMA40_PCHAN_DOUBLE_DST_MODE
]
1181 = D40_DREG_PRMO_PCHAN_DOUBLE_DST
,
1183 static const unsigned int log_map
[] = {
1184 [STEDMA40_LCHAN_SRC_PHY_DST_LOG
]
1185 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG
,
1186 [STEDMA40_LCHAN_SRC_LOG_DST_PHY
]
1187 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY
,
1188 [STEDMA40_LCHAN_SRC_LOG_DST_LOG
]
1189 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG
,
1192 if (chan_is_physical(d40c
))
1193 return phy_map
[d40c
->dma_cfg
.mode_opt
];
1195 return log_map
[d40c
->dma_cfg
.mode_opt
];
1198 static void d40_config_write(struct d40_chan
*d40c
)
1203 /* Odd addresses are even addresses + 4 */
1204 addr_base
= (d40c
->phy_chan
->num
% 2) * 4;
1205 /* Setup channel mode to logical or physical */
1206 var
= ((u32
)(chan_is_logical(d40c
)) + 1) <<
1207 D40_CHAN_POS(d40c
->phy_chan
->num
);
1208 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMSE
+ addr_base
);
1210 /* Setup operational mode option register */
1211 var
= d40_get_prmo(d40c
) << D40_CHAN_POS(d40c
->phy_chan
->num
);
1213 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMOE
+ addr_base
);
1215 if (chan_is_logical(d40c
)) {
1216 int lidx
= (d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
)
1217 & D40_SREG_ELEM_LOG_LIDX_MASK
;
1218 void __iomem
*chanbase
= chan_base(d40c
);
1220 /* Set default config for CFG reg */
1221 writel(d40c
->src_def_cfg
, chanbase
+ D40_CHAN_REG_SSCFG
);
1222 writel(d40c
->dst_def_cfg
, chanbase
+ D40_CHAN_REG_SDCFG
);
1224 /* Set LIDX for lcla */
1225 writel(lidx
, chanbase
+ D40_CHAN_REG_SSELT
);
1226 writel(lidx
, chanbase
+ D40_CHAN_REG_SDELT
);
1228 /* Clear LNK which will be used by d40_chan_has_events() */
1229 writel(0, chanbase
+ D40_CHAN_REG_SSLNK
);
1230 writel(0, chanbase
+ D40_CHAN_REG_SDLNK
);
1234 static u32
d40_residue(struct d40_chan
*d40c
)
1238 if (chan_is_logical(d40c
))
1239 num_elt
= (readl(&d40c
->lcpa
->lcsp2
) & D40_MEM_LCSP2_ECNT_MASK
)
1240 >> D40_MEM_LCSP2_ECNT_POS
;
1242 u32 val
= readl(chan_base(d40c
) + D40_CHAN_REG_SDELT
);
1243 num_elt
= (val
& D40_SREG_ELEM_PHY_ECNT_MASK
)
1244 >> D40_SREG_ELEM_PHY_ECNT_POS
;
1247 return num_elt
* (1 << d40c
->dma_cfg
.dst_info
.data_width
);
1250 static bool d40_tx_is_linked(struct d40_chan
*d40c
)
1254 if (chan_is_logical(d40c
))
1255 is_link
= readl(&d40c
->lcpa
->lcsp3
) & D40_MEM_LCSP3_DLOS_MASK
;
1257 is_link
= readl(chan_base(d40c
) + D40_CHAN_REG_SDLNK
)
1258 & D40_SREG_LNK_PHYS_LNK_MASK
;
1263 static int d40_pause(struct d40_chan
*d40c
)
1266 unsigned long flags
;
1271 pm_runtime_get_sync(d40c
->base
->dev
);
1272 spin_lock_irqsave(&d40c
->lock
, flags
);
1274 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1276 pm_runtime_mark_last_busy(d40c
->base
->dev
);
1277 pm_runtime_put_autosuspend(d40c
->base
->dev
);
1278 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1282 static int d40_resume(struct d40_chan
*d40c
)
1285 unsigned long flags
;
1290 spin_lock_irqsave(&d40c
->lock
, flags
);
1291 pm_runtime_get_sync(d40c
->base
->dev
);
1293 /* If bytes left to transfer or linked tx resume job */
1294 if (d40_residue(d40c
) || d40_tx_is_linked(d40c
))
1295 res
= d40_channel_execute_command(d40c
, D40_DMA_RUN
);
1297 pm_runtime_mark_last_busy(d40c
->base
->dev
);
1298 pm_runtime_put_autosuspend(d40c
->base
->dev
);
1299 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1303 static dma_cookie_t
d40_tx_submit(struct dma_async_tx_descriptor
*tx
)
1305 struct d40_chan
*d40c
= container_of(tx
->chan
,
1308 struct d40_desc
*d40d
= container_of(tx
, struct d40_desc
, txd
);
1309 unsigned long flags
;
1310 dma_cookie_t cookie
;
1312 spin_lock_irqsave(&d40c
->lock
, flags
);
1313 cookie
= dma_cookie_assign(tx
);
1314 d40_desc_queue(d40c
, d40d
);
1315 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1320 static int d40_start(struct d40_chan
*d40c
)
1322 return d40_channel_execute_command(d40c
, D40_DMA_RUN
);
1325 static struct d40_desc
*d40_queue_start(struct d40_chan
*d40c
)
1327 struct d40_desc
*d40d
;
1330 /* Start queued jobs, if any */
1331 d40d
= d40_first_queued(d40c
);
1336 pm_runtime_get_sync(d40c
->base
->dev
);
1339 /* Remove from queue */
1340 d40_desc_remove(d40d
);
1342 /* Add to active queue */
1343 d40_desc_submit(d40c
, d40d
);
1345 /* Initiate DMA job */
1346 d40_desc_load(d40c
, d40d
);
1349 err
= d40_start(d40c
);
1358 /* called from interrupt context */
1359 static void dma_tc_handle(struct d40_chan
*d40c
)
1361 struct d40_desc
*d40d
;
1363 /* Get first active entry from list */
1364 d40d
= d40_first_active_get(d40c
);
1371 * If this was a paritially loaded list, we need to reloaded
1372 * it, and only when the list is completed. We need to check
1373 * for done because the interrupt will hit for every link, and
1374 * not just the last one.
1376 if (d40d
->lli_current
< d40d
->lli_len
1377 && !d40_tx_is_linked(d40c
)
1378 && !d40_residue(d40c
)) {
1379 d40_lcla_free_all(d40c
, d40d
);
1380 d40_desc_load(d40c
, d40d
);
1381 (void) d40_start(d40c
);
1383 if (d40d
->lli_current
== d40d
->lli_len
)
1384 d40d
->lli_current
= 0;
1387 d40_lcla_free_all(d40c
, d40d
);
1389 if (d40d
->lli_current
< d40d
->lli_len
) {
1390 d40_desc_load(d40c
, d40d
);
1392 (void) d40_start(d40c
);
1396 if (d40_queue_start(d40c
) == NULL
)
1398 pm_runtime_mark_last_busy(d40c
->base
->dev
);
1399 pm_runtime_put_autosuspend(d40c
->base
->dev
);
1403 tasklet_schedule(&d40c
->tasklet
);
1407 static void dma_tasklet(unsigned long data
)
1409 struct d40_chan
*d40c
= (struct d40_chan
*) data
;
1410 struct d40_desc
*d40d
;
1411 unsigned long flags
;
1412 dma_async_tx_callback callback
;
1413 void *callback_param
;
1415 spin_lock_irqsave(&d40c
->lock
, flags
);
1417 /* Get first active entry from list */
1418 d40d
= d40_first_active_get(d40c
);
1423 dma_cookie_complete(&d40d
->txd
);
1426 * If terminating a channel pending_tx is set to zero.
1427 * This prevents any finished active jobs to return to the client.
1429 if (d40c
->pending_tx
== 0) {
1430 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1434 /* Callback to client */
1435 callback
= d40d
->txd
.callback
;
1436 callback_param
= d40d
->txd
.callback_param
;
1438 if (!d40d
->cyclic
) {
1439 if (async_tx_test_ack(&d40d
->txd
)) {
1440 d40_desc_remove(d40d
);
1441 d40_desc_free(d40c
, d40d
);
1443 if (!d40d
->is_in_client_list
) {
1444 d40_desc_remove(d40d
);
1445 d40_lcla_free_all(d40c
, d40d
);
1446 list_add_tail(&d40d
->node
, &d40c
->client
);
1447 d40d
->is_in_client_list
= true;
1454 if (d40c
->pending_tx
)
1455 tasklet_schedule(&d40c
->tasklet
);
1457 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1459 if (callback
&& (d40d
->txd
.flags
& DMA_PREP_INTERRUPT
))
1460 callback(callback_param
);
1465 /* Rescue manouver if receiving double interrupts */
1466 if (d40c
->pending_tx
> 0)
1468 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1471 static irqreturn_t
d40_handle_interrupt(int irq
, void *data
)
1473 static const struct d40_interrupt_lookup il
[] = {
1474 {D40_DREG_LCTIS0
, D40_DREG_LCICR0
, false, 0},
1475 {D40_DREG_LCTIS1
, D40_DREG_LCICR1
, false, 32},
1476 {D40_DREG_LCTIS2
, D40_DREG_LCICR2
, false, 64},
1477 {D40_DREG_LCTIS3
, D40_DREG_LCICR3
, false, 96},
1478 {D40_DREG_LCEIS0
, D40_DREG_LCICR0
, true, 0},
1479 {D40_DREG_LCEIS1
, D40_DREG_LCICR1
, true, 32},
1480 {D40_DREG_LCEIS2
, D40_DREG_LCICR2
, true, 64},
1481 {D40_DREG_LCEIS3
, D40_DREG_LCICR3
, true, 96},
1482 {D40_DREG_PCTIS
, D40_DREG_PCICR
, false, D40_PHY_CHAN
},
1483 {D40_DREG_PCEIS
, D40_DREG_PCICR
, true, D40_PHY_CHAN
},
1487 u32 regs
[ARRAY_SIZE(il
)];
1491 struct d40_chan
*d40c
;
1492 unsigned long flags
;
1493 struct d40_base
*base
= data
;
1495 spin_lock_irqsave(&base
->interrupt_lock
, flags
);
1497 /* Read interrupt status of both logical and physical channels */
1498 for (i
= 0; i
< ARRAY_SIZE(il
); i
++)
1499 regs
[i
] = readl(base
->virtbase
+ il
[i
].src
);
1503 chan
= find_next_bit((unsigned long *)regs
,
1504 BITS_PER_LONG
* ARRAY_SIZE(il
), chan
+ 1);
1506 /* No more set bits found? */
1507 if (chan
== BITS_PER_LONG
* ARRAY_SIZE(il
))
1510 row
= chan
/ BITS_PER_LONG
;
1511 idx
= chan
& (BITS_PER_LONG
- 1);
1514 writel(1 << idx
, base
->virtbase
+ il
[row
].clr
);
1516 if (il
[row
].offset
== D40_PHY_CHAN
)
1517 d40c
= base
->lookup_phy_chans
[idx
];
1519 d40c
= base
->lookup_log_chans
[il
[row
].offset
+ idx
];
1520 spin_lock(&d40c
->lock
);
1522 if (!il
[row
].is_error
)
1523 dma_tc_handle(d40c
);
1525 d40_err(base
->dev
, "IRQ chan: %ld offset %d idx %d\n",
1526 chan
, il
[row
].offset
, idx
);
1528 spin_unlock(&d40c
->lock
);
1531 spin_unlock_irqrestore(&base
->interrupt_lock
, flags
);
1536 static int d40_validate_conf(struct d40_chan
*d40c
,
1537 struct stedma40_chan_cfg
*conf
)
1540 u32 dst_event_group
= D40_TYPE_TO_GROUP(conf
->dst_dev_type
);
1541 u32 src_event_group
= D40_TYPE_TO_GROUP(conf
->src_dev_type
);
1542 bool is_log
= conf
->mode
== STEDMA40_MODE_LOGICAL
;
1545 chan_err(d40c
, "Invalid direction.\n");
1549 if (conf
->dst_dev_type
!= STEDMA40_DEV_DST_MEMORY
&&
1550 d40c
->base
->plat_data
->dev_tx
[conf
->dst_dev_type
] == 0 &&
1551 d40c
->runtime_addr
== 0) {
1553 chan_err(d40c
, "Invalid TX channel address (%d)\n",
1554 conf
->dst_dev_type
);
1558 if (conf
->src_dev_type
!= STEDMA40_DEV_SRC_MEMORY
&&
1559 d40c
->base
->plat_data
->dev_rx
[conf
->src_dev_type
] == 0 &&
1560 d40c
->runtime_addr
== 0) {
1561 chan_err(d40c
, "Invalid RX channel address (%d)\n",
1562 conf
->src_dev_type
);
1566 if (conf
->dir
== STEDMA40_MEM_TO_PERIPH
&&
1567 dst_event_group
== STEDMA40_DEV_DST_MEMORY
) {
1568 chan_err(d40c
, "Invalid dst\n");
1572 if (conf
->dir
== STEDMA40_PERIPH_TO_MEM
&&
1573 src_event_group
== STEDMA40_DEV_SRC_MEMORY
) {
1574 chan_err(d40c
, "Invalid src\n");
1578 if (src_event_group
== STEDMA40_DEV_SRC_MEMORY
&&
1579 dst_event_group
== STEDMA40_DEV_DST_MEMORY
&& is_log
) {
1580 chan_err(d40c
, "No event line\n");
1584 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
&&
1585 (src_event_group
!= dst_event_group
)) {
1586 chan_err(d40c
, "Invalid event group\n");
1590 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
) {
1592 * DMAC HW supports it. Will be added to this driver,
1593 * in case any dma client requires it.
1595 chan_err(d40c
, "periph to periph not supported\n");
1599 if (d40_psize_2_burst_size(is_log
, conf
->src_info
.psize
) *
1600 (1 << conf
->src_info
.data_width
) !=
1601 d40_psize_2_burst_size(is_log
, conf
->dst_info
.psize
) *
1602 (1 << conf
->dst_info
.data_width
)) {
1604 * The DMAC hardware only supports
1605 * src (burst x width) == dst (burst x width)
1608 chan_err(d40c
, "src (burst x width) != dst (burst x width)\n");
1615 static bool d40_alloc_mask_set(struct d40_phy_res
*phy
,
1616 bool is_src
, int log_event_line
, bool is_log
,
1619 unsigned long flags
;
1620 spin_lock_irqsave(&phy
->lock
, flags
);
1622 *first_user
= ((phy
->allocated_src
| phy
->allocated_dst
)
1626 /* Physical interrupts are masked per physical full channel */
1627 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1628 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1629 phy
->allocated_dst
= D40_ALLOC_PHY
;
1630 phy
->allocated_src
= D40_ALLOC_PHY
;
1636 /* Logical channel */
1638 if (phy
->allocated_src
== D40_ALLOC_PHY
)
1641 if (phy
->allocated_src
== D40_ALLOC_FREE
)
1642 phy
->allocated_src
= D40_ALLOC_LOG_FREE
;
1644 if (!(phy
->allocated_src
& (1 << log_event_line
))) {
1645 phy
->allocated_src
|= 1 << log_event_line
;
1650 if (phy
->allocated_dst
== D40_ALLOC_PHY
)
1653 if (phy
->allocated_dst
== D40_ALLOC_FREE
)
1654 phy
->allocated_dst
= D40_ALLOC_LOG_FREE
;
1656 if (!(phy
->allocated_dst
& (1 << log_event_line
))) {
1657 phy
->allocated_dst
|= 1 << log_event_line
;
1664 spin_unlock_irqrestore(&phy
->lock
, flags
);
1667 spin_unlock_irqrestore(&phy
->lock
, flags
);
1671 static bool d40_alloc_mask_free(struct d40_phy_res
*phy
, bool is_src
,
1674 unsigned long flags
;
1675 bool is_free
= false;
1677 spin_lock_irqsave(&phy
->lock
, flags
);
1678 if (!log_event_line
) {
1679 phy
->allocated_dst
= D40_ALLOC_FREE
;
1680 phy
->allocated_src
= D40_ALLOC_FREE
;
1685 /* Logical channel */
1687 phy
->allocated_src
&= ~(1 << log_event_line
);
1688 if (phy
->allocated_src
== D40_ALLOC_LOG_FREE
)
1689 phy
->allocated_src
= D40_ALLOC_FREE
;
1691 phy
->allocated_dst
&= ~(1 << log_event_line
);
1692 if (phy
->allocated_dst
== D40_ALLOC_LOG_FREE
)
1693 phy
->allocated_dst
= D40_ALLOC_FREE
;
1696 is_free
= ((phy
->allocated_src
| phy
->allocated_dst
) ==
1700 spin_unlock_irqrestore(&phy
->lock
, flags
);
1705 static int d40_allocate_channel(struct d40_chan
*d40c
, bool *first_phy_user
)
1710 struct d40_phy_res
*phys
;
1716 bool is_log
= d40c
->dma_cfg
.mode
== STEDMA40_MODE_LOGICAL
;
1718 phys
= d40c
->base
->phy_res
;
1719 num_phy_chans
= d40c
->base
->num_phy_chans
;
1721 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1722 dev_type
= d40c
->dma_cfg
.src_dev_type
;
1723 log_num
= 2 * dev_type
;
1725 } else if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1726 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1727 /* dst event lines are used for logical memcpy */
1728 dev_type
= d40c
->dma_cfg
.dst_dev_type
;
1729 log_num
= 2 * dev_type
+ 1;
1734 event_group
= D40_TYPE_TO_GROUP(dev_type
);
1735 event_line
= D40_TYPE_TO_EVENT(dev_type
);
1738 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1739 /* Find physical half channel */
1740 if (d40c
->dma_cfg
.use_fixed_channel
) {
1741 i
= d40c
->dma_cfg
.phy_channel
;
1742 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1747 for (i
= 0; i
< num_phy_chans
; i
++) {
1748 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1755 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1756 int phy_num
= j
+ event_group
* 2;
1757 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1758 if (d40_alloc_mask_set(&phys
[i
],
1768 d40c
->phy_chan
= &phys
[i
];
1769 d40c
->log_num
= D40_PHY_CHAN
;
1775 /* Find logical channel */
1776 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1777 int phy_num
= j
+ event_group
* 2;
1779 if (d40c
->dma_cfg
.use_fixed_channel
) {
1780 i
= d40c
->dma_cfg
.phy_channel
;
1782 if ((i
!= phy_num
) && (i
!= phy_num
+ 1)) {
1783 dev_err(chan2dev(d40c
),
1784 "invalid fixed phy channel %d\n", i
);
1788 if (d40_alloc_mask_set(&phys
[i
], is_src
, event_line
,
1789 is_log
, first_phy_user
))
1792 dev_err(chan2dev(d40c
),
1793 "could not allocate fixed phy channel %d\n", i
);
1798 * Spread logical channels across all available physical rather
1799 * than pack every logical channel at the first available phy
1803 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1804 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1810 for (i
= phy_num
+ 1; i
>= phy_num
; i
--) {
1811 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1821 d40c
->phy_chan
= &phys
[i
];
1822 d40c
->log_num
= log_num
;
1826 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = d40c
;
1828 d40c
->base
->lookup_phy_chans
[d40c
->phy_chan
->num
] = d40c
;
1834 static int d40_config_memcpy(struct d40_chan
*d40c
)
1836 dma_cap_mask_t cap
= d40c
->chan
.device
->cap_mask
;
1838 if (dma_has_cap(DMA_MEMCPY
, cap
) && !dma_has_cap(DMA_SLAVE
, cap
)) {
1839 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_log
;
1840 d40c
->dma_cfg
.src_dev_type
= STEDMA40_DEV_SRC_MEMORY
;
1841 d40c
->dma_cfg
.dst_dev_type
= d40c
->base
->plat_data
->
1842 memcpy
[d40c
->chan
.chan_id
];
1844 } else if (dma_has_cap(DMA_MEMCPY
, cap
) &&
1845 dma_has_cap(DMA_SLAVE
, cap
)) {
1846 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_phy
;
1848 chan_err(d40c
, "No memcpy\n");
1855 static int d40_free_dma(struct d40_chan
*d40c
)
1860 struct d40_phy_res
*phy
= d40c
->phy_chan
;
1863 /* Terminate all queued and active transfers */
1867 chan_err(d40c
, "phy == null\n");
1871 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1872 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1873 chan_err(d40c
, "channel already free\n");
1877 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1878 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1879 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1881 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1882 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1885 chan_err(d40c
, "Unknown direction\n");
1889 pm_runtime_get_sync(d40c
->base
->dev
);
1890 res
= d40_channel_execute_command(d40c
, D40_DMA_STOP
);
1892 chan_err(d40c
, "stop failed\n");
1896 d40_alloc_mask_free(phy
, is_src
, chan_is_logical(d40c
) ? event
: 0);
1898 if (chan_is_logical(d40c
))
1899 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = NULL
;
1901 d40c
->base
->lookup_phy_chans
[phy
->num
] = NULL
;
1904 pm_runtime_mark_last_busy(d40c
->base
->dev
);
1905 pm_runtime_put_autosuspend(d40c
->base
->dev
);
1909 d40c
->phy_chan
= NULL
;
1910 d40c
->configured
= false;
1913 pm_runtime_mark_last_busy(d40c
->base
->dev
);
1914 pm_runtime_put_autosuspend(d40c
->base
->dev
);
1918 static bool d40_is_paused(struct d40_chan
*d40c
)
1920 void __iomem
*chanbase
= chan_base(d40c
);
1921 bool is_paused
= false;
1922 unsigned long flags
;
1923 void __iomem
*active_reg
;
1927 spin_lock_irqsave(&d40c
->lock
, flags
);
1929 if (chan_is_physical(d40c
)) {
1930 if (d40c
->phy_chan
->num
% 2 == 0)
1931 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
1933 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
1935 status
= (readl(active_reg
) &
1936 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
1937 D40_CHAN_POS(d40c
->phy_chan
->num
);
1938 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
1944 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1945 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1946 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1947 status
= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
1948 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1949 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1950 status
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
1952 chan_err(d40c
, "Unknown direction\n");
1956 status
= (status
& D40_EVENTLINE_MASK(event
)) >>
1957 D40_EVENTLINE_POS(event
);
1959 if (status
!= D40_DMA_RUN
)
1962 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1968 static u32
stedma40_residue(struct dma_chan
*chan
)
1970 struct d40_chan
*d40c
=
1971 container_of(chan
, struct d40_chan
, chan
);
1973 unsigned long flags
;
1975 spin_lock_irqsave(&d40c
->lock
, flags
);
1976 bytes_left
= d40_residue(d40c
);
1977 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1983 d40_prep_sg_log(struct d40_chan
*chan
, struct d40_desc
*desc
,
1984 struct scatterlist
*sg_src
, struct scatterlist
*sg_dst
,
1985 unsigned int sg_len
, dma_addr_t src_dev_addr
,
1986 dma_addr_t dst_dev_addr
)
1988 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
1989 struct stedma40_half_channel_info
*src_info
= &cfg
->src_info
;
1990 struct stedma40_half_channel_info
*dst_info
= &cfg
->dst_info
;
1993 ret
= d40_log_sg_to_lli(sg_src
, sg_len
,
1996 chan
->log_def
.lcsp1
,
1997 src_info
->data_width
,
1998 dst_info
->data_width
);
2000 ret
= d40_log_sg_to_lli(sg_dst
, sg_len
,
2003 chan
->log_def
.lcsp3
,
2004 dst_info
->data_width
,
2005 src_info
->data_width
);
2007 return ret
< 0 ? ret
: 0;
2011 d40_prep_sg_phy(struct d40_chan
*chan
, struct d40_desc
*desc
,
2012 struct scatterlist
*sg_src
, struct scatterlist
*sg_dst
,
2013 unsigned int sg_len
, dma_addr_t src_dev_addr
,
2014 dma_addr_t dst_dev_addr
)
2016 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
2017 struct stedma40_half_channel_info
*src_info
= &cfg
->src_info
;
2018 struct stedma40_half_channel_info
*dst_info
= &cfg
->dst_info
;
2019 unsigned long flags
= 0;
2023 flags
|= LLI_CYCLIC
| LLI_TERM_INT
;
2025 ret
= d40_phy_sg_to_lli(sg_src
, sg_len
, src_dev_addr
,
2027 virt_to_phys(desc
->lli_phy
.src
),
2029 src_info
, dst_info
, flags
);
2031 ret
= d40_phy_sg_to_lli(sg_dst
, sg_len
, dst_dev_addr
,
2033 virt_to_phys(desc
->lli_phy
.dst
),
2035 dst_info
, src_info
, flags
);
2037 dma_sync_single_for_device(chan
->base
->dev
, desc
->lli_pool
.dma_addr
,
2038 desc
->lli_pool
.size
, DMA_TO_DEVICE
);
2040 return ret
< 0 ? ret
: 0;
2044 static struct d40_desc
*
2045 d40_prep_desc(struct d40_chan
*chan
, struct scatterlist
*sg
,
2046 unsigned int sg_len
, unsigned long dma_flags
)
2048 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
2049 struct d40_desc
*desc
;
2052 desc
= d40_desc_get(chan
);
2056 desc
->lli_len
= d40_sg_2_dmalen(sg
, sg_len
, cfg
->src_info
.data_width
,
2057 cfg
->dst_info
.data_width
);
2058 if (desc
->lli_len
< 0) {
2059 chan_err(chan
, "Unaligned size\n");
2063 ret
= d40_pool_lli_alloc(chan
, desc
, desc
->lli_len
);
2065 chan_err(chan
, "Could not allocate lli\n");
2070 desc
->lli_current
= 0;
2071 desc
->txd
.flags
= dma_flags
;
2072 desc
->txd
.tx_submit
= d40_tx_submit
;
2074 dma_async_tx_descriptor_init(&desc
->txd
, &chan
->chan
);
2079 d40_desc_free(chan
, desc
);
2084 d40_get_dev_addr(struct d40_chan
*chan
, enum dma_transfer_direction direction
)
2086 struct stedma40_platform_data
*plat
= chan
->base
->plat_data
;
2087 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
2088 dma_addr_t addr
= 0;
2090 if (chan
->runtime_addr
)
2091 return chan
->runtime_addr
;
2093 if (direction
== DMA_DEV_TO_MEM
)
2094 addr
= plat
->dev_rx
[cfg
->src_dev_type
];
2095 else if (direction
== DMA_MEM_TO_DEV
)
2096 addr
= plat
->dev_tx
[cfg
->dst_dev_type
];
2101 static struct dma_async_tx_descriptor
*
2102 d40_prep_sg(struct dma_chan
*dchan
, struct scatterlist
*sg_src
,
2103 struct scatterlist
*sg_dst
, unsigned int sg_len
,
2104 enum dma_transfer_direction direction
, unsigned long dma_flags
)
2106 struct d40_chan
*chan
= container_of(dchan
, struct d40_chan
, chan
);
2107 dma_addr_t src_dev_addr
= 0;
2108 dma_addr_t dst_dev_addr
= 0;
2109 struct d40_desc
*desc
;
2110 unsigned long flags
;
2113 if (!chan
->phy_chan
) {
2114 chan_err(chan
, "Cannot prepare unallocated channel\n");
2119 spin_lock_irqsave(&chan
->lock
, flags
);
2121 desc
= d40_prep_desc(chan
, sg_src
, sg_len
, dma_flags
);
2125 if (sg_next(&sg_src
[sg_len
- 1]) == sg_src
)
2126 desc
->cyclic
= true;
2128 if (direction
!= DMA_TRANS_NONE
) {
2129 dma_addr_t dev_addr
= d40_get_dev_addr(chan
, direction
);
2131 if (direction
== DMA_DEV_TO_MEM
)
2132 src_dev_addr
= dev_addr
;
2133 else if (direction
== DMA_MEM_TO_DEV
)
2134 dst_dev_addr
= dev_addr
;
2137 if (chan_is_logical(chan
))
2138 ret
= d40_prep_sg_log(chan
, desc
, sg_src
, sg_dst
,
2139 sg_len
, src_dev_addr
, dst_dev_addr
);
2141 ret
= d40_prep_sg_phy(chan
, desc
, sg_src
, sg_dst
,
2142 sg_len
, src_dev_addr
, dst_dev_addr
);
2145 chan_err(chan
, "Failed to prepare %s sg job: %d\n",
2146 chan_is_logical(chan
) ? "log" : "phy", ret
);
2151 * add descriptor to the prepare queue in order to be able
2152 * to free them later in terminate_all
2154 list_add_tail(&desc
->node
, &chan
->prepare_queue
);
2156 spin_unlock_irqrestore(&chan
->lock
, flags
);
2162 d40_desc_free(chan
, desc
);
2163 spin_unlock_irqrestore(&chan
->lock
, flags
);
2167 bool stedma40_filter(struct dma_chan
*chan
, void *data
)
2169 struct stedma40_chan_cfg
*info
= data
;
2170 struct d40_chan
*d40c
=
2171 container_of(chan
, struct d40_chan
, chan
);
2175 err
= d40_validate_conf(d40c
, info
);
2177 d40c
->dma_cfg
= *info
;
2179 err
= d40_config_memcpy(d40c
);
2182 d40c
->configured
= true;
2186 EXPORT_SYMBOL(stedma40_filter
);
2188 static void __d40_set_prio_rt(struct d40_chan
*d40c
, int dev_type
, bool src
)
2190 bool realtime
= d40c
->dma_cfg
.realtime
;
2191 bool highprio
= d40c
->dma_cfg
.high_priority
;
2192 u32 rtreg
= realtime
? D40_DREG_RSEG1
: D40_DREG_RCEG1
;
2193 u32 event
= D40_TYPE_TO_EVENT(dev_type
);
2194 u32 group
= D40_TYPE_TO_GROUP(dev_type
);
2195 u32 bit
= 1 << event
;
2199 * Due to a hardware bug, in some cases a logical channel triggered by
2200 * a high priority destination event line can generate extra packet
2203 * The workaround is to not set the high priority level for the
2204 * destination event lines that trigger logical channels.
2206 if (!src
&& chan_is_logical(d40c
))
2209 prioreg
= highprio
? D40_DREG_PSEG1
: D40_DREG_PCEG1
;
2211 /* Destination event lines are stored in the upper halfword */
2215 writel(bit
, d40c
->base
->virtbase
+ prioreg
+ group
* 4);
2216 writel(bit
, d40c
->base
->virtbase
+ rtreg
+ group
* 4);
2219 static void d40_set_prio_realtime(struct d40_chan
*d40c
)
2221 if (d40c
->base
->rev
< 3)
2224 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
2225 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
2226 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.src_dev_type
, true);
2228 if ((d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
) ||
2229 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
2230 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.dst_dev_type
, false);
2233 /* DMA ENGINE functions */
2234 static int d40_alloc_chan_resources(struct dma_chan
*chan
)
2237 unsigned long flags
;
2238 struct d40_chan
*d40c
=
2239 container_of(chan
, struct d40_chan
, chan
);
2241 spin_lock_irqsave(&d40c
->lock
, flags
);
2243 dma_cookie_init(chan
);
2245 /* If no dma configuration is set use default configuration (memcpy) */
2246 if (!d40c
->configured
) {
2247 err
= d40_config_memcpy(d40c
);
2249 chan_err(d40c
, "Failed to configure memcpy channel\n");
2254 err
= d40_allocate_channel(d40c
, &is_free_phy
);
2256 chan_err(d40c
, "Failed to allocate channel\n");
2257 d40c
->configured
= false;
2261 pm_runtime_get_sync(d40c
->base
->dev
);
2262 /* Fill in basic CFG register values */
2263 d40_phy_cfg(&d40c
->dma_cfg
, &d40c
->src_def_cfg
,
2264 &d40c
->dst_def_cfg
, chan_is_logical(d40c
));
2266 d40_set_prio_realtime(d40c
);
2268 if (chan_is_logical(d40c
)) {
2269 d40_log_cfg(&d40c
->dma_cfg
,
2270 &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
2272 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
2273 d40c
->lcpa
= d40c
->base
->lcpa_base
+
2274 d40c
->dma_cfg
.src_dev_type
* D40_LCPA_CHAN_SIZE
;
2276 d40c
->lcpa
= d40c
->base
->lcpa_base
+
2277 d40c
->dma_cfg
.dst_dev_type
*
2278 D40_LCPA_CHAN_SIZE
+ D40_LCPA_CHAN_DST_DELTA
;
2281 dev_dbg(chan2dev(d40c
), "allocated %s channel (phy %d%s)\n",
2282 chan_is_logical(d40c
) ? "logical" : "physical",
2283 d40c
->phy_chan
->num
,
2284 d40c
->dma_cfg
.use_fixed_channel
? ", fixed" : "");
2288 * Only write channel configuration to the DMA if the physical
2289 * resource is free. In case of multiple logical channels
2290 * on the same physical resource, only the first write is necessary.
2293 d40_config_write(d40c
);
2295 pm_runtime_mark_last_busy(d40c
->base
->dev
);
2296 pm_runtime_put_autosuspend(d40c
->base
->dev
);
2297 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2301 static void d40_free_chan_resources(struct dma_chan
*chan
)
2303 struct d40_chan
*d40c
=
2304 container_of(chan
, struct d40_chan
, chan
);
2306 unsigned long flags
;
2308 if (d40c
->phy_chan
== NULL
) {
2309 chan_err(d40c
, "Cannot free unallocated channel\n");
2314 spin_lock_irqsave(&d40c
->lock
, flags
);
2316 err
= d40_free_dma(d40c
);
2319 chan_err(d40c
, "Failed to free channel\n");
2320 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2323 static struct dma_async_tx_descriptor
*d40_prep_memcpy(struct dma_chan
*chan
,
2327 unsigned long dma_flags
)
2329 struct scatterlist dst_sg
;
2330 struct scatterlist src_sg
;
2332 sg_init_table(&dst_sg
, 1);
2333 sg_init_table(&src_sg
, 1);
2335 sg_dma_address(&dst_sg
) = dst
;
2336 sg_dma_address(&src_sg
) = src
;
2338 sg_dma_len(&dst_sg
) = size
;
2339 sg_dma_len(&src_sg
) = size
;
2341 return d40_prep_sg(chan
, &src_sg
, &dst_sg
, 1, DMA_NONE
, dma_flags
);
2344 static struct dma_async_tx_descriptor
*
2345 d40_prep_memcpy_sg(struct dma_chan
*chan
,
2346 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
2347 struct scatterlist
*src_sg
, unsigned int src_nents
,
2348 unsigned long dma_flags
)
2350 if (dst_nents
!= src_nents
)
2353 return d40_prep_sg(chan
, src_sg
, dst_sg
, src_nents
, DMA_NONE
, dma_flags
);
2356 static struct dma_async_tx_descriptor
*d40_prep_slave_sg(struct dma_chan
*chan
,
2357 struct scatterlist
*sgl
,
2358 unsigned int sg_len
,
2359 enum dma_transfer_direction direction
,
2360 unsigned long dma_flags
,
2363 if (direction
!= DMA_DEV_TO_MEM
&& direction
!= DMA_MEM_TO_DEV
)
2366 return d40_prep_sg(chan
, sgl
, sgl
, sg_len
, direction
, dma_flags
);
2369 static struct dma_async_tx_descriptor
*
2370 dma40_prep_dma_cyclic(struct dma_chan
*chan
, dma_addr_t dma_addr
,
2371 size_t buf_len
, size_t period_len
,
2372 enum dma_transfer_direction direction
, unsigned long flags
,
2375 unsigned int periods
= buf_len
/ period_len
;
2376 struct dma_async_tx_descriptor
*txd
;
2377 struct scatterlist
*sg
;
2380 sg
= kcalloc(periods
+ 1, sizeof(struct scatterlist
), GFP_NOWAIT
);
2381 for (i
= 0; i
< periods
; i
++) {
2382 sg_dma_address(&sg
[i
]) = dma_addr
;
2383 sg_dma_len(&sg
[i
]) = period_len
;
2384 dma_addr
+= period_len
;
2387 sg
[periods
].offset
= 0;
2388 sg_dma_len(&sg
[periods
]) = 0;
2389 sg
[periods
].page_link
=
2390 ((unsigned long)sg
| 0x01) & ~0x02;
2392 txd
= d40_prep_sg(chan
, sg
, sg
, periods
, direction
,
2393 DMA_PREP_INTERRUPT
);
2400 static enum dma_status
d40_tx_status(struct dma_chan
*chan
,
2401 dma_cookie_t cookie
,
2402 struct dma_tx_state
*txstate
)
2404 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2405 enum dma_status ret
;
2407 if (d40c
->phy_chan
== NULL
) {
2408 chan_err(d40c
, "Cannot read status of unallocated channel\n");
2412 ret
= dma_cookie_status(chan
, cookie
, txstate
);
2413 if (ret
!= DMA_SUCCESS
)
2414 dma_set_residue(txstate
, stedma40_residue(chan
));
2416 if (d40_is_paused(d40c
))
2422 static void d40_issue_pending(struct dma_chan
*chan
)
2424 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2425 unsigned long flags
;
2427 if (d40c
->phy_chan
== NULL
) {
2428 chan_err(d40c
, "Channel is not allocated!\n");
2432 spin_lock_irqsave(&d40c
->lock
, flags
);
2434 list_splice_tail_init(&d40c
->pending_queue
, &d40c
->queue
);
2436 /* Busy means that queued jobs are already being processed */
2438 (void) d40_queue_start(d40c
);
2440 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2443 static void d40_terminate_all(struct dma_chan
*chan
)
2445 unsigned long flags
;
2446 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2449 spin_lock_irqsave(&d40c
->lock
, flags
);
2451 pm_runtime_get_sync(d40c
->base
->dev
);
2452 ret
= d40_channel_execute_command(d40c
, D40_DMA_STOP
);
2454 chan_err(d40c
, "Failed to stop channel\n");
2457 pm_runtime_mark_last_busy(d40c
->base
->dev
);
2458 pm_runtime_put_autosuspend(d40c
->base
->dev
);
2460 pm_runtime_mark_last_busy(d40c
->base
->dev
);
2461 pm_runtime_put_autosuspend(d40c
->base
->dev
);
2465 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2469 dma40_config_to_halfchannel(struct d40_chan
*d40c
,
2470 struct stedma40_half_channel_info
*info
,
2471 enum dma_slave_buswidth width
,
2474 enum stedma40_periph_data_width addr_width
;
2478 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
2479 addr_width
= STEDMA40_BYTE_WIDTH
;
2481 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
2482 addr_width
= STEDMA40_HALFWORD_WIDTH
;
2484 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
2485 addr_width
= STEDMA40_WORD_WIDTH
;
2487 case DMA_SLAVE_BUSWIDTH_8_BYTES
:
2488 addr_width
= STEDMA40_DOUBLEWORD_WIDTH
;
2491 dev_err(d40c
->base
->dev
,
2492 "illegal peripheral address width "
2498 if (chan_is_logical(d40c
)) {
2500 psize
= STEDMA40_PSIZE_LOG_16
;
2501 else if (maxburst
>= 8)
2502 psize
= STEDMA40_PSIZE_LOG_8
;
2503 else if (maxburst
>= 4)
2504 psize
= STEDMA40_PSIZE_LOG_4
;
2506 psize
= STEDMA40_PSIZE_LOG_1
;
2509 psize
= STEDMA40_PSIZE_PHY_16
;
2510 else if (maxburst
>= 8)
2511 psize
= STEDMA40_PSIZE_PHY_8
;
2512 else if (maxburst
>= 4)
2513 psize
= STEDMA40_PSIZE_PHY_4
;
2515 psize
= STEDMA40_PSIZE_PHY_1
;
2518 info
->data_width
= addr_width
;
2519 info
->psize
= psize
;
2520 info
->flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2525 /* Runtime reconfiguration extension */
2526 static int d40_set_runtime_config(struct dma_chan
*chan
,
2527 struct dma_slave_config
*config
)
2529 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2530 struct stedma40_chan_cfg
*cfg
= &d40c
->dma_cfg
;
2531 enum dma_slave_buswidth src_addr_width
, dst_addr_width
;
2532 dma_addr_t config_addr
;
2533 u32 src_maxburst
, dst_maxburst
;
2536 src_addr_width
= config
->src_addr_width
;
2537 src_maxburst
= config
->src_maxburst
;
2538 dst_addr_width
= config
->dst_addr_width
;
2539 dst_maxburst
= config
->dst_maxburst
;
2541 if (config
->direction
== DMA_DEV_TO_MEM
) {
2542 dma_addr_t dev_addr_rx
=
2543 d40c
->base
->plat_data
->dev_rx
[cfg
->src_dev_type
];
2545 config_addr
= config
->src_addr
;
2547 dev_dbg(d40c
->base
->dev
,
2548 "channel has a pre-wired RX address %08x "
2549 "overriding with %08x\n",
2550 dev_addr_rx
, config_addr
);
2551 if (cfg
->dir
!= STEDMA40_PERIPH_TO_MEM
)
2552 dev_dbg(d40c
->base
->dev
,
2553 "channel was not configured for peripheral "
2554 "to memory transfer (%d) overriding\n",
2556 cfg
->dir
= STEDMA40_PERIPH_TO_MEM
;
2558 /* Configure the memory side */
2559 if (dst_addr_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
)
2560 dst_addr_width
= src_addr_width
;
2561 if (dst_maxburst
== 0)
2562 dst_maxburst
= src_maxburst
;
2564 } else if (config
->direction
== DMA_MEM_TO_DEV
) {
2565 dma_addr_t dev_addr_tx
=
2566 d40c
->base
->plat_data
->dev_tx
[cfg
->dst_dev_type
];
2568 config_addr
= config
->dst_addr
;
2570 dev_dbg(d40c
->base
->dev
,
2571 "channel has a pre-wired TX address %08x "
2572 "overriding with %08x\n",
2573 dev_addr_tx
, config_addr
);
2574 if (cfg
->dir
!= STEDMA40_MEM_TO_PERIPH
)
2575 dev_dbg(d40c
->base
->dev
,
2576 "channel was not configured for memory "
2577 "to peripheral transfer (%d) overriding\n",
2579 cfg
->dir
= STEDMA40_MEM_TO_PERIPH
;
2581 /* Configure the memory side */
2582 if (src_addr_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
)
2583 src_addr_width
= dst_addr_width
;
2584 if (src_maxburst
== 0)
2585 src_maxburst
= dst_maxburst
;
2587 dev_err(d40c
->base
->dev
,
2588 "unrecognized channel direction %d\n",
2593 if (src_maxburst
* src_addr_width
!= dst_maxburst
* dst_addr_width
) {
2594 dev_err(d40c
->base
->dev
,
2595 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2603 if (src_maxburst
> 16) {
2605 dst_maxburst
= src_maxburst
* src_addr_width
/ dst_addr_width
;
2606 } else if (dst_maxburst
> 16) {
2608 src_maxburst
= dst_maxburst
* dst_addr_width
/ src_addr_width
;
2611 ret
= dma40_config_to_halfchannel(d40c
, &cfg
->src_info
,
2617 ret
= dma40_config_to_halfchannel(d40c
, &cfg
->dst_info
,
2623 /* Fill in register values */
2624 if (chan_is_logical(d40c
))
2625 d40_log_cfg(cfg
, &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
2627 d40_phy_cfg(cfg
, &d40c
->src_def_cfg
,
2628 &d40c
->dst_def_cfg
, false);
2630 /* These settings will take precedence later */
2631 d40c
->runtime_addr
= config_addr
;
2632 d40c
->runtime_direction
= config
->direction
;
2633 dev_dbg(d40c
->base
->dev
,
2634 "configured channel %s for %s, data width %d/%d, "
2635 "maxburst %d/%d elements, LE, no flow control\n",
2636 dma_chan_name(chan
),
2637 (config
->direction
== DMA_DEV_TO_MEM
) ? "RX" : "TX",
2638 src_addr_width
, dst_addr_width
,
2639 src_maxburst
, dst_maxburst
);
2644 static int d40_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
2647 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2649 if (d40c
->phy_chan
== NULL
) {
2650 chan_err(d40c
, "Channel is not allocated!\n");
2655 case DMA_TERMINATE_ALL
:
2656 d40_terminate_all(chan
);
2659 return d40_pause(d40c
);
2661 return d40_resume(d40c
);
2662 case DMA_SLAVE_CONFIG
:
2663 return d40_set_runtime_config(chan
,
2664 (struct dma_slave_config
*) arg
);
2669 /* Other commands are unimplemented */
2673 /* Initialization functions */
2675 static void __init
d40_chan_init(struct d40_base
*base
, struct dma_device
*dma
,
2676 struct d40_chan
*chans
, int offset
,
2680 struct d40_chan
*d40c
;
2682 INIT_LIST_HEAD(&dma
->channels
);
2684 for (i
= offset
; i
< offset
+ num_chans
; i
++) {
2687 d40c
->chan
.device
= dma
;
2689 spin_lock_init(&d40c
->lock
);
2691 d40c
->log_num
= D40_PHY_CHAN
;
2693 INIT_LIST_HEAD(&d40c
->active
);
2694 INIT_LIST_HEAD(&d40c
->queue
);
2695 INIT_LIST_HEAD(&d40c
->pending_queue
);
2696 INIT_LIST_HEAD(&d40c
->client
);
2697 INIT_LIST_HEAD(&d40c
->prepare_queue
);
2699 tasklet_init(&d40c
->tasklet
, dma_tasklet
,
2700 (unsigned long) d40c
);
2702 list_add_tail(&d40c
->chan
.device_node
,
2707 static void d40_ops_init(struct d40_base
*base
, struct dma_device
*dev
)
2709 if (dma_has_cap(DMA_SLAVE
, dev
->cap_mask
))
2710 dev
->device_prep_slave_sg
= d40_prep_slave_sg
;
2712 if (dma_has_cap(DMA_MEMCPY
, dev
->cap_mask
)) {
2713 dev
->device_prep_dma_memcpy
= d40_prep_memcpy
;
2716 * This controller can only access address at even
2717 * 32bit boundaries, i.e. 2^2
2719 dev
->copy_align
= 2;
2722 if (dma_has_cap(DMA_SG
, dev
->cap_mask
))
2723 dev
->device_prep_dma_sg
= d40_prep_memcpy_sg
;
2725 if (dma_has_cap(DMA_CYCLIC
, dev
->cap_mask
))
2726 dev
->device_prep_dma_cyclic
= dma40_prep_dma_cyclic
;
2728 dev
->device_alloc_chan_resources
= d40_alloc_chan_resources
;
2729 dev
->device_free_chan_resources
= d40_free_chan_resources
;
2730 dev
->device_issue_pending
= d40_issue_pending
;
2731 dev
->device_tx_status
= d40_tx_status
;
2732 dev
->device_control
= d40_control
;
2733 dev
->dev
= base
->dev
;
2736 static int __init
d40_dmaengine_init(struct d40_base
*base
,
2737 int num_reserved_chans
)
2741 d40_chan_init(base
, &base
->dma_slave
, base
->log_chans
,
2742 0, base
->num_log_chans
);
2744 dma_cap_zero(base
->dma_slave
.cap_mask
);
2745 dma_cap_set(DMA_SLAVE
, base
->dma_slave
.cap_mask
);
2746 dma_cap_set(DMA_CYCLIC
, base
->dma_slave
.cap_mask
);
2748 d40_ops_init(base
, &base
->dma_slave
);
2750 err
= dma_async_device_register(&base
->dma_slave
);
2753 d40_err(base
->dev
, "Failed to register slave channels\n");
2757 d40_chan_init(base
, &base
->dma_memcpy
, base
->log_chans
,
2758 base
->num_log_chans
, base
->plat_data
->memcpy_len
);
2760 dma_cap_zero(base
->dma_memcpy
.cap_mask
);
2761 dma_cap_set(DMA_MEMCPY
, base
->dma_memcpy
.cap_mask
);
2762 dma_cap_set(DMA_SG
, base
->dma_memcpy
.cap_mask
);
2764 d40_ops_init(base
, &base
->dma_memcpy
);
2766 err
= dma_async_device_register(&base
->dma_memcpy
);
2770 "Failed to regsiter memcpy only channels\n");
2774 d40_chan_init(base
, &base
->dma_both
, base
->phy_chans
,
2775 0, num_reserved_chans
);
2777 dma_cap_zero(base
->dma_both
.cap_mask
);
2778 dma_cap_set(DMA_SLAVE
, base
->dma_both
.cap_mask
);
2779 dma_cap_set(DMA_MEMCPY
, base
->dma_both
.cap_mask
);
2780 dma_cap_set(DMA_SG
, base
->dma_both
.cap_mask
);
2781 dma_cap_set(DMA_CYCLIC
, base
->dma_slave
.cap_mask
);
2783 d40_ops_init(base
, &base
->dma_both
);
2784 err
= dma_async_device_register(&base
->dma_both
);
2788 "Failed to register logical and physical capable channels\n");
2793 dma_async_device_unregister(&base
->dma_memcpy
);
2795 dma_async_device_unregister(&base
->dma_slave
);
2800 /* Suspend resume functionality */
2802 static int dma40_pm_suspend(struct device
*dev
)
2804 struct platform_device
*pdev
= to_platform_device(dev
);
2805 struct d40_base
*base
= platform_get_drvdata(pdev
);
2808 if (base
->lcpa_regulator
)
2809 ret
= regulator_disable(base
->lcpa_regulator
);
2813 static int dma40_runtime_suspend(struct device
*dev
)
2815 struct platform_device
*pdev
= to_platform_device(dev
);
2816 struct d40_base
*base
= platform_get_drvdata(pdev
);
2818 d40_save_restore_registers(base
, true);
2820 /* Don't disable/enable clocks for v1 due to HW bugs */
2822 writel_relaxed(base
->gcc_pwr_off_mask
,
2823 base
->virtbase
+ D40_DREG_GCC
);
2828 static int dma40_runtime_resume(struct device
*dev
)
2830 struct platform_device
*pdev
= to_platform_device(dev
);
2831 struct d40_base
*base
= platform_get_drvdata(pdev
);
2833 if (base
->initialized
)
2834 d40_save_restore_registers(base
, false);
2836 writel_relaxed(D40_DREG_GCC_ENABLE_ALL
,
2837 base
->virtbase
+ D40_DREG_GCC
);
2841 static int dma40_resume(struct device
*dev
)
2843 struct platform_device
*pdev
= to_platform_device(dev
);
2844 struct d40_base
*base
= platform_get_drvdata(pdev
);
2847 if (base
->lcpa_regulator
)
2848 ret
= regulator_enable(base
->lcpa_regulator
);
2853 static const struct dev_pm_ops dma40_pm_ops
= {
2854 .suspend
= dma40_pm_suspend
,
2855 .runtime_suspend
= dma40_runtime_suspend
,
2856 .runtime_resume
= dma40_runtime_resume
,
2857 .resume
= dma40_resume
,
2859 #define DMA40_PM_OPS (&dma40_pm_ops)
2861 #define DMA40_PM_OPS NULL
2864 /* Initialization functions. */
2866 static int __init
d40_phy_res_init(struct d40_base
*base
)
2869 int num_phy_chans_avail
= 0;
2871 int odd_even_bit
= -2;
2872 int gcc
= D40_DREG_GCC_ENA
;
2874 val
[0] = readl(base
->virtbase
+ D40_DREG_PRSME
);
2875 val
[1] = readl(base
->virtbase
+ D40_DREG_PRSMO
);
2877 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2878 base
->phy_res
[i
].num
= i
;
2879 odd_even_bit
+= 2 * ((i
% 2) == 0);
2880 if (((val
[i
% 2] >> odd_even_bit
) & 3) == 1) {
2881 /* Mark security only channels as occupied */
2882 base
->phy_res
[i
].allocated_src
= D40_ALLOC_PHY
;
2883 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_PHY
;
2884 base
->phy_res
[i
].reserved
= true;
2885 gcc
|= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i
),
2887 gcc
|= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i
),
2892 base
->phy_res
[i
].allocated_src
= D40_ALLOC_FREE
;
2893 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_FREE
;
2894 base
->phy_res
[i
].reserved
= false;
2895 num_phy_chans_avail
++;
2897 spin_lock_init(&base
->phy_res
[i
].lock
);
2900 /* Mark disabled channels as occupied */
2901 for (i
= 0; base
->plat_data
->disabled_channels
[i
] != -1; i
++) {
2902 int chan
= base
->plat_data
->disabled_channels
[i
];
2904 base
->phy_res
[chan
].allocated_src
= D40_ALLOC_PHY
;
2905 base
->phy_res
[chan
].allocated_dst
= D40_ALLOC_PHY
;
2906 base
->phy_res
[chan
].reserved
= true;
2907 gcc
|= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan
),
2909 gcc
|= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan
),
2911 num_phy_chans_avail
--;
2914 dev_info(base
->dev
, "%d of %d physical DMA channels available\n",
2915 num_phy_chans_avail
, base
->num_phy_chans
);
2917 /* Verify settings extended vs standard */
2918 val
[0] = readl(base
->virtbase
+ D40_DREG_PRTYP
);
2920 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2922 if (base
->phy_res
[i
].allocated_src
== D40_ALLOC_FREE
&&
2923 (val
[0] & 0x3) != 1)
2925 "[%s] INFO: channel %d is misconfigured (%d)\n",
2926 __func__
, i
, val
[0] & 0x3);
2928 val
[0] = val
[0] >> 2;
2932 * To keep things simple, Enable all clocks initially.
2933 * The clocks will get managed later post channel allocation.
2934 * The clocks for the event lines on which reserved channels exists
2935 * are not managed here.
2937 writel(D40_DREG_GCC_ENABLE_ALL
, base
->virtbase
+ D40_DREG_GCC
);
2938 base
->gcc_pwr_off_mask
= gcc
;
2940 return num_phy_chans_avail
;
2943 static struct d40_base
* __init
d40_hw_detect_init(struct platform_device
*pdev
)
2945 struct stedma40_platform_data
*plat_data
;
2946 struct clk
*clk
= NULL
;
2947 void __iomem
*virtbase
= NULL
;
2948 struct resource
*res
= NULL
;
2949 struct d40_base
*base
= NULL
;
2950 int num_log_chans
= 0;
2952 int clk_ret
= -EINVAL
;
2958 clk
= clk_get(&pdev
->dev
, NULL
);
2960 d40_err(&pdev
->dev
, "No matching clock found\n");
2964 clk_ret
= clk_prepare_enable(clk
);
2966 d40_err(&pdev
->dev
, "Failed to prepare/enable clock\n");
2970 /* Get IO for DMAC base address */
2971 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "base");
2975 if (request_mem_region(res
->start
, resource_size(res
),
2976 D40_NAME
" I/O base") == NULL
)
2979 virtbase
= ioremap(res
->start
, resource_size(res
));
2983 /* This is just a regular AMBA PrimeCell ID actually */
2984 for (pid
= 0, i
= 0; i
< 4; i
++)
2985 pid
|= (readl(virtbase
+ resource_size(res
) - 0x20 + 4 * i
)
2987 for (cid
= 0, i
= 0; i
< 4; i
++)
2988 cid
|= (readl(virtbase
+ resource_size(res
) - 0x10 + 4 * i
)
2991 if (cid
!= AMBA_CID
) {
2992 d40_err(&pdev
->dev
, "Unknown hardware! No PrimeCell ID\n");
2995 if (AMBA_MANF_BITS(pid
) != AMBA_VENDOR_ST
) {
2996 d40_err(&pdev
->dev
, "Unknown designer! Got %x wanted %x\n",
2997 AMBA_MANF_BITS(pid
),
3003 * DB8500ed has revision 0
3005 * DB8500v1 has revision 2
3006 * DB8500v2 has revision 3
3007 * AP9540v1 has revision 4
3008 * DB8540v1 has revision 4
3010 rev
= AMBA_REV_BITS(pid
);
3012 plat_data
= pdev
->dev
.platform_data
;
3014 /* The number of physical channels on this HW */
3015 if (plat_data
->num_of_phy_chans
)
3016 num_phy_chans
= plat_data
->num_of_phy_chans
;
3018 num_phy_chans
= 4 * (readl(virtbase
+ D40_DREG_ICFG
) & 0x7) + 4;
3020 dev_info(&pdev
->dev
, "hardware revision: %d @ 0x%x with %d physical channels\n",
3021 rev
, res
->start
, num_phy_chans
);
3024 d40_err(&pdev
->dev
, "hardware revision: %d is not supported",
3029 /* Count the number of logical channels in use */
3030 for (i
= 0; i
< plat_data
->dev_len
; i
++)
3031 if (plat_data
->dev_rx
[i
] != 0)
3034 for (i
= 0; i
< plat_data
->dev_len
; i
++)
3035 if (plat_data
->dev_tx
[i
] != 0)
3038 base
= kzalloc(ALIGN(sizeof(struct d40_base
), 4) +
3039 (num_phy_chans
+ num_log_chans
+ plat_data
->memcpy_len
) *
3040 sizeof(struct d40_chan
), GFP_KERNEL
);
3043 d40_err(&pdev
->dev
, "Out of memory\n");
3049 base
->num_phy_chans
= num_phy_chans
;
3050 base
->num_log_chans
= num_log_chans
;
3051 base
->phy_start
= res
->start
;
3052 base
->phy_size
= resource_size(res
);
3053 base
->virtbase
= virtbase
;
3054 base
->plat_data
= plat_data
;
3055 base
->dev
= &pdev
->dev
;
3056 base
->phy_chans
= ((void *)base
) + ALIGN(sizeof(struct d40_base
), 4);
3057 base
->log_chans
= &base
->phy_chans
[num_phy_chans
];
3059 base
->phy_res
= kzalloc(num_phy_chans
* sizeof(struct d40_phy_res
),
3064 base
->lookup_phy_chans
= kzalloc(num_phy_chans
*
3065 sizeof(struct d40_chan
*),
3067 if (!base
->lookup_phy_chans
)
3070 if (num_log_chans
+ plat_data
->memcpy_len
) {
3072 * The max number of logical channels are event lines for all
3073 * src devices and dst devices
3075 base
->lookup_log_chans
= kzalloc(plat_data
->dev_len
* 2 *
3076 sizeof(struct d40_chan
*),
3078 if (!base
->lookup_log_chans
)
3082 base
->reg_val_backup_chan
= kmalloc(base
->num_phy_chans
*
3083 sizeof(d40_backup_regs_chan
),
3085 if (!base
->reg_val_backup_chan
)
3088 base
->lcla_pool
.alloc_map
=
3089 kzalloc(num_phy_chans
* sizeof(struct d40_desc
*)
3090 * D40_LCLA_LINK_PER_EVENT_GRP
, GFP_KERNEL
);
3091 if (!base
->lcla_pool
.alloc_map
)
3094 base
->desc_slab
= kmem_cache_create(D40_NAME
, sizeof(struct d40_desc
),
3095 0, SLAB_HWCACHE_ALIGN
,
3097 if (base
->desc_slab
== NULL
)
3104 clk_disable_unprepare(clk
);
3110 release_mem_region(res
->start
,
3111 resource_size(res
));
3116 kfree(base
->lcla_pool
.alloc_map
);
3117 kfree(base
->reg_val_backup_chan
);
3118 kfree(base
->lookup_log_chans
);
3119 kfree(base
->lookup_phy_chans
);
3120 kfree(base
->phy_res
);
3127 static void __init
d40_hw_init(struct d40_base
*base
)
3130 static struct d40_reg_val dma_init_reg
[] = {
3131 /* Clock every part of the DMA block from start */
3132 { .reg
= D40_DREG_GCC
, .val
= D40_DREG_GCC_ENABLE_ALL
},
3134 /* Interrupts on all logical channels */
3135 { .reg
= D40_DREG_LCMIS0
, .val
= 0xFFFFFFFF},
3136 { .reg
= D40_DREG_LCMIS1
, .val
= 0xFFFFFFFF},
3137 { .reg
= D40_DREG_LCMIS2
, .val
= 0xFFFFFFFF},
3138 { .reg
= D40_DREG_LCMIS3
, .val
= 0xFFFFFFFF},
3139 { .reg
= D40_DREG_LCICR0
, .val
= 0xFFFFFFFF},
3140 { .reg
= D40_DREG_LCICR1
, .val
= 0xFFFFFFFF},
3141 { .reg
= D40_DREG_LCICR2
, .val
= 0xFFFFFFFF},
3142 { .reg
= D40_DREG_LCICR3
, .val
= 0xFFFFFFFF},
3143 { .reg
= D40_DREG_LCTIS0
, .val
= 0xFFFFFFFF},
3144 { .reg
= D40_DREG_LCTIS1
, .val
= 0xFFFFFFFF},
3145 { .reg
= D40_DREG_LCTIS2
, .val
= 0xFFFFFFFF},
3146 { .reg
= D40_DREG_LCTIS3
, .val
= 0xFFFFFFFF}
3149 u32 prmseo
[2] = {0, 0};
3150 u32 activeo
[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3154 for (i
= 0; i
< ARRAY_SIZE(dma_init_reg
); i
++)
3155 writel(dma_init_reg
[i
].val
,
3156 base
->virtbase
+ dma_init_reg
[i
].reg
);
3158 /* Configure all our dma channels to default settings */
3159 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
3161 activeo
[i
% 2] = activeo
[i
% 2] << 2;
3163 if (base
->phy_res
[base
->num_phy_chans
- i
- 1].allocated_src
3165 activeo
[i
% 2] |= 3;
3169 /* Enable interrupt # */
3170 pcmis
= (pcmis
<< 1) | 1;
3172 /* Clear interrupt # */
3173 pcicr
= (pcicr
<< 1) | 1;
3175 /* Set channel to physical mode */
3176 prmseo
[i
% 2] = prmseo
[i
% 2] << 2;
3181 writel(prmseo
[1], base
->virtbase
+ D40_DREG_PRMSE
);
3182 writel(prmseo
[0], base
->virtbase
+ D40_DREG_PRMSO
);
3183 writel(activeo
[1], base
->virtbase
+ D40_DREG_ACTIVE
);
3184 writel(activeo
[0], base
->virtbase
+ D40_DREG_ACTIVO
);
3186 /* Write which interrupt to enable */
3187 writel(pcmis
, base
->virtbase
+ D40_DREG_PCMIS
);
3189 /* Write which interrupt to clear */
3190 writel(pcicr
, base
->virtbase
+ D40_DREG_PCICR
);
3194 static int __init
d40_lcla_allocate(struct d40_base
*base
)
3196 struct d40_lcla_pool
*pool
= &base
->lcla_pool
;
3197 unsigned long *page_list
;
3202 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3203 * To full fill this hardware requirement without wasting 256 kb
3204 * we allocate pages until we get an aligned one.
3206 page_list
= kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS
,
3214 /* Calculating how many pages that are required */
3215 base
->lcla_pool
.pages
= SZ_1K
* base
->num_phy_chans
/ PAGE_SIZE
;
3217 for (i
= 0; i
< MAX_LCLA_ALLOC_ATTEMPTS
; i
++) {
3218 page_list
[i
] = __get_free_pages(GFP_KERNEL
,
3219 base
->lcla_pool
.pages
);
3220 if (!page_list
[i
]) {
3222 d40_err(base
->dev
, "Failed to allocate %d pages.\n",
3223 base
->lcla_pool
.pages
);
3225 for (j
= 0; j
< i
; j
++)
3226 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
3230 if ((virt_to_phys((void *)page_list
[i
]) &
3231 (LCLA_ALIGNMENT
- 1)) == 0)
3235 for (j
= 0; j
< i
; j
++)
3236 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
3238 if (i
< MAX_LCLA_ALLOC_ATTEMPTS
) {
3239 base
->lcla_pool
.base
= (void *)page_list
[i
];
3242 * After many attempts and no succees with finding the correct
3243 * alignment, try with allocating a big buffer.
3246 "[%s] Failed to get %d pages @ 18 bit align.\n",
3247 __func__
, base
->lcla_pool
.pages
);
3248 base
->lcla_pool
.base_unaligned
= kmalloc(SZ_1K
*
3249 base
->num_phy_chans
+
3252 if (!base
->lcla_pool
.base_unaligned
) {
3257 base
->lcla_pool
.base
= PTR_ALIGN(base
->lcla_pool
.base_unaligned
,
3261 pool
->dma_addr
= dma_map_single(base
->dev
, pool
->base
,
3262 SZ_1K
* base
->num_phy_chans
,
3264 if (dma_mapping_error(base
->dev
, pool
->dma_addr
)) {
3270 writel(virt_to_phys(base
->lcla_pool
.base
),
3271 base
->virtbase
+ D40_DREG_LCLA
);
3277 static int __init
d40_probe(struct platform_device
*pdev
)
3281 struct d40_base
*base
;
3282 struct resource
*res
= NULL
;
3283 int num_reserved_chans
;
3286 base
= d40_hw_detect_init(pdev
);
3291 num_reserved_chans
= d40_phy_res_init(base
);
3293 platform_set_drvdata(pdev
, base
);
3295 spin_lock_init(&base
->interrupt_lock
);
3296 spin_lock_init(&base
->execmd_lock
);
3298 /* Get IO for logical channel parameter address */
3299 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "lcpa");
3302 d40_err(&pdev
->dev
, "No \"lcpa\" memory resource\n");
3305 base
->lcpa_size
= resource_size(res
);
3306 base
->phy_lcpa
= res
->start
;
3308 if (request_mem_region(res
->start
, resource_size(res
),
3309 D40_NAME
" I/O lcpa") == NULL
) {
3312 "Failed to request LCPA region 0x%x-0x%x\n",
3313 res
->start
, res
->end
);
3317 /* We make use of ESRAM memory for this. */
3318 val
= readl(base
->virtbase
+ D40_DREG_LCPA
);
3319 if (res
->start
!= val
&& val
!= 0) {
3320 dev_warn(&pdev
->dev
,
3321 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
3322 __func__
, val
, res
->start
);
3324 writel(res
->start
, base
->virtbase
+ D40_DREG_LCPA
);
3326 base
->lcpa_base
= ioremap(res
->start
, resource_size(res
));
3327 if (!base
->lcpa_base
) {
3329 d40_err(&pdev
->dev
, "Failed to ioremap LCPA region\n");
3332 /* If lcla has to be located in ESRAM we don't need to allocate */
3333 if (base
->plat_data
->use_esram_lcla
) {
3334 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
3339 "No \"lcla_esram\" memory resource\n");
3342 base
->lcla_pool
.base
= ioremap(res
->start
,
3343 resource_size(res
));
3344 if (!base
->lcla_pool
.base
) {
3346 d40_err(&pdev
->dev
, "Failed to ioremap LCLA region\n");
3349 writel(res
->start
, base
->virtbase
+ D40_DREG_LCLA
);
3352 ret
= d40_lcla_allocate(base
);
3354 d40_err(&pdev
->dev
, "Failed to allocate LCLA area\n");
3359 spin_lock_init(&base
->lcla_pool
.lock
);
3361 base
->irq
= platform_get_irq(pdev
, 0);
3363 ret
= request_irq(base
->irq
, d40_handle_interrupt
, 0, D40_NAME
, base
);
3365 d40_err(&pdev
->dev
, "No IRQ defined\n");
3369 pm_runtime_irq_safe(base
->dev
);
3370 pm_runtime_set_autosuspend_delay(base
->dev
, DMA40_AUTOSUSPEND_DELAY
);
3371 pm_runtime_use_autosuspend(base
->dev
);
3372 pm_runtime_enable(base
->dev
);
3373 pm_runtime_resume(base
->dev
);
3375 if (base
->plat_data
->use_esram_lcla
) {
3377 base
->lcpa_regulator
= regulator_get(base
->dev
, "lcla_esram");
3378 if (IS_ERR(base
->lcpa_regulator
)) {
3379 d40_err(&pdev
->dev
, "Failed to get lcpa_regulator\n");
3380 base
->lcpa_regulator
= NULL
;
3384 ret
= regulator_enable(base
->lcpa_regulator
);
3387 "Failed to enable lcpa_regulator\n");
3388 regulator_put(base
->lcpa_regulator
);
3389 base
->lcpa_regulator
= NULL
;
3394 base
->initialized
= true;
3395 err
= d40_dmaengine_init(base
, num_reserved_chans
);
3399 base
->dev
->dma_parms
= &base
->dma_parms
;
3400 err
= dma_set_max_seg_size(base
->dev
, STEDMA40_MAX_SEG_SIZE
);
3402 d40_err(&pdev
->dev
, "Failed to set dma max seg size\n");
3408 dev_info(base
->dev
, "initialized\n");
3413 if (base
->desc_slab
)
3414 kmem_cache_destroy(base
->desc_slab
);
3416 iounmap(base
->virtbase
);
3418 if (base
->lcla_pool
.base
&& base
->plat_data
->use_esram_lcla
) {
3419 iounmap(base
->lcla_pool
.base
);
3420 base
->lcla_pool
.base
= NULL
;
3423 if (base
->lcla_pool
.dma_addr
)
3424 dma_unmap_single(base
->dev
, base
->lcla_pool
.dma_addr
,
3425 SZ_1K
* base
->num_phy_chans
,
3428 if (!base
->lcla_pool
.base_unaligned
&& base
->lcla_pool
.base
)
3429 free_pages((unsigned long)base
->lcla_pool
.base
,
3430 base
->lcla_pool
.pages
);
3432 kfree(base
->lcla_pool
.base_unaligned
);
3435 release_mem_region(base
->phy_lcpa
,
3437 if (base
->phy_start
)
3438 release_mem_region(base
->phy_start
,
3441 clk_disable(base
->clk
);
3445 if (base
->lcpa_regulator
) {
3446 regulator_disable(base
->lcpa_regulator
);
3447 regulator_put(base
->lcpa_regulator
);
3450 kfree(base
->lcla_pool
.alloc_map
);
3451 kfree(base
->lookup_log_chans
);
3452 kfree(base
->lookup_phy_chans
);
3453 kfree(base
->phy_res
);
3457 d40_err(&pdev
->dev
, "probe failed\n");
3461 static struct platform_driver d40_driver
= {
3463 .owner
= THIS_MODULE
,
3469 static int __init
stedma40_init(void)
3471 return platform_driver_probe(&d40_driver
, d40_probe
);
3473 subsys_initcall(stedma40_init
);