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dma40: use helpers for channel type check
[deliverable/linux.git] / drivers / dma / ste_dma40.c
1 /*
2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/slab.h>
11 #include <linux/dmaengine.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16
17 #include <plat/ste_dma40.h>
18
19 #include "ste_dma40_ll.h"
20
21 #define D40_NAME "dma40"
22
23 #define D40_PHY_CHAN -1
24
25 /* For masking out/in 2 bit channel positions */
26 #define D40_CHAN_POS(chan) (2 * (chan / 2))
27 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
28
29 /* Maximum iterations taken before giving up suspending a channel */
30 #define D40_SUSPEND_MAX_IT 500
31
32 /* Hardware requirement on LCLA alignment */
33 #define LCLA_ALIGNMENT 0x40000
34
35 /* Max number of links per event group */
36 #define D40_LCLA_LINK_PER_EVENT_GRP 128
37 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
38
39 /* Attempts before giving up to trying to get pages that are aligned */
40 #define MAX_LCLA_ALLOC_ATTEMPTS 256
41
42 /* Bit markings for allocation map */
43 #define D40_ALLOC_FREE (1 << 31)
44 #define D40_ALLOC_PHY (1 << 30)
45 #define D40_ALLOC_LOG_FREE 0
46
47 /* Hardware designer of the block */
48 #define D40_HW_DESIGNER 0x8
49
50 /**
51 * enum 40_command - The different commands and/or statuses.
52 *
53 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57 */
58 enum d40_command {
59 D40_DMA_STOP = 0,
60 D40_DMA_RUN = 1,
61 D40_DMA_SUSPEND_REQ = 2,
62 D40_DMA_SUSPENDED = 3
63 };
64
65 /**
66 * struct d40_lli_pool - Structure for keeping LLIs in memory
67 *
68 * @base: Pointer to memory area when the pre_alloc_lli's are not large
69 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70 * pre_alloc_lli is used.
71 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
72 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
73 * one buffer to one buffer.
74 */
75 struct d40_lli_pool {
76 void *base;
77 int size;
78 /* Space for dst and src, plus an extra for padding */
79 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
80 };
81
82 /**
83 * struct d40_desc - A descriptor is one DMA job.
84 *
85 * @lli_phy: LLI settings for physical channel. Both src and dst=
86 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
87 * lli_len equals one.
88 * @lli_log: Same as above but for logical channels.
89 * @lli_pool: The pool with two entries pre-allocated.
90 * @lli_len: Number of llis of current descriptor.
91 * @lli_current: Number of transfered llis.
92 * @lcla_alloc: Number of LCLA entries allocated.
93 * @txd: DMA engine struct. Used for among other things for communication
94 * during a transfer.
95 * @node: List entry.
96 * @is_in_client_list: true if the client owns this descriptor.
97 * the previous one.
98 *
99 * This descriptor is used for both logical and physical transfers.
100 */
101 struct d40_desc {
102 /* LLI physical */
103 struct d40_phy_lli_bidir lli_phy;
104 /* LLI logical */
105 struct d40_log_lli_bidir lli_log;
106
107 struct d40_lli_pool lli_pool;
108 int lli_len;
109 int lli_current;
110 int lcla_alloc;
111
112 struct dma_async_tx_descriptor txd;
113 struct list_head node;
114
115 bool is_in_client_list;
116 };
117
118 /**
119 * struct d40_lcla_pool - LCLA pool settings and data.
120 *
121 * @base: The virtual address of LCLA. 18 bit aligned.
122 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
123 * This pointer is only there for clean-up on error.
124 * @pages: The number of pages needed for all physical channels.
125 * Only used later for clean-up on error
126 * @lock: Lock to protect the content in this struct.
127 * @alloc_map: big map over which LCLA entry is own by which job.
128 */
129 struct d40_lcla_pool {
130 void *base;
131 void *base_unaligned;
132 int pages;
133 spinlock_t lock;
134 struct d40_desc **alloc_map;
135 };
136
137 /**
138 * struct d40_phy_res - struct for handling eventlines mapped to physical
139 * channels.
140 *
141 * @lock: A lock protection this entity.
142 * @num: The physical channel number of this entity.
143 * @allocated_src: Bit mapped to show which src event line's are mapped to
144 * this physical channel. Can also be free or physically allocated.
145 * @allocated_dst: Same as for src but is dst.
146 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
147 * event line number.
148 */
149 struct d40_phy_res {
150 spinlock_t lock;
151 int num;
152 u32 allocated_src;
153 u32 allocated_dst;
154 };
155
156 struct d40_base;
157
158 /**
159 * struct d40_chan - Struct that describes a channel.
160 *
161 * @lock: A spinlock to protect this struct.
162 * @log_num: The logical number, if any of this channel.
163 * @completed: Starts with 1, after first interrupt it is set to dma engine's
164 * current cookie.
165 * @pending_tx: The number of pending transfers. Used between interrupt handler
166 * and tasklet.
167 * @busy: Set to true when transfer is ongoing on this channel.
168 * @phy_chan: Pointer to physical channel which this instance runs on. If this
169 * point is NULL, then the channel is not allocated.
170 * @chan: DMA engine handle.
171 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
172 * transfer and call client callback.
173 * @client: Cliented owned descriptor list.
174 * @active: Active descriptor.
175 * @queue: Queued jobs.
176 * @dma_cfg: The client configuration of this dma channel.
177 * @configured: whether the dma_cfg configuration is valid
178 * @base: Pointer to the device instance struct.
179 * @src_def_cfg: Default cfg register setting for src.
180 * @dst_def_cfg: Default cfg register setting for dst.
181 * @log_def: Default logical channel settings.
182 * @lcla: Space for one dst src pair for logical channel transfers.
183 * @lcpa: Pointer to dst and src lcpa settings.
184 *
185 * This struct can either "be" a logical or a physical channel.
186 */
187 struct d40_chan {
188 spinlock_t lock;
189 int log_num;
190 /* ID of the most recent completed transfer */
191 int completed;
192 int pending_tx;
193 bool busy;
194 struct d40_phy_res *phy_chan;
195 struct dma_chan chan;
196 struct tasklet_struct tasklet;
197 struct list_head client;
198 struct list_head active;
199 struct list_head queue;
200 struct stedma40_chan_cfg dma_cfg;
201 bool configured;
202 struct d40_base *base;
203 /* Default register configurations */
204 u32 src_def_cfg;
205 u32 dst_def_cfg;
206 struct d40_def_lcsp log_def;
207 struct d40_log_lli_full *lcpa;
208 /* Runtime reconfiguration */
209 dma_addr_t runtime_addr;
210 enum dma_data_direction runtime_direction;
211 };
212
213 /**
214 * struct d40_base - The big global struct, one for each probe'd instance.
215 *
216 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
217 * @execmd_lock: Lock for execute command usage since several channels share
218 * the same physical register.
219 * @dev: The device structure.
220 * @virtbase: The virtual base address of the DMA's register.
221 * @rev: silicon revision detected.
222 * @clk: Pointer to the DMA clock structure.
223 * @phy_start: Physical memory start of the DMA registers.
224 * @phy_size: Size of the DMA register map.
225 * @irq: The IRQ number.
226 * @num_phy_chans: The number of physical channels. Read from HW. This
227 * is the number of available channels for this driver, not counting "Secure
228 * mode" allocated physical channels.
229 * @num_log_chans: The number of logical channels. Calculated from
230 * num_phy_chans.
231 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
232 * @dma_slave: dma_device channels that can do only do slave transfers.
233 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
234 * @log_chans: Room for all possible logical channels in system.
235 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
236 * to log_chans entries.
237 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
238 * to phy_chans entries.
239 * @plat_data: Pointer to provided platform_data which is the driver
240 * configuration.
241 * @phy_res: Vector containing all physical channels.
242 * @lcla_pool: lcla pool settings and data.
243 * @lcpa_base: The virtual mapped address of LCPA.
244 * @phy_lcpa: The physical address of the LCPA.
245 * @lcpa_size: The size of the LCPA area.
246 * @desc_slab: cache for descriptors.
247 */
248 struct d40_base {
249 spinlock_t interrupt_lock;
250 spinlock_t execmd_lock;
251 struct device *dev;
252 void __iomem *virtbase;
253 u8 rev:4;
254 struct clk *clk;
255 phys_addr_t phy_start;
256 resource_size_t phy_size;
257 int irq;
258 int num_phy_chans;
259 int num_log_chans;
260 struct dma_device dma_both;
261 struct dma_device dma_slave;
262 struct dma_device dma_memcpy;
263 struct d40_chan *phy_chans;
264 struct d40_chan *log_chans;
265 struct d40_chan **lookup_log_chans;
266 struct d40_chan **lookup_phy_chans;
267 struct stedma40_platform_data *plat_data;
268 /* Physical half channels */
269 struct d40_phy_res *phy_res;
270 struct d40_lcla_pool lcla_pool;
271 void *lcpa_base;
272 dma_addr_t phy_lcpa;
273 resource_size_t lcpa_size;
274 struct kmem_cache *desc_slab;
275 };
276
277 /**
278 * struct d40_interrupt_lookup - lookup table for interrupt handler
279 *
280 * @src: Interrupt mask register.
281 * @clr: Interrupt clear register.
282 * @is_error: true if this is an error interrupt.
283 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
284 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
285 */
286 struct d40_interrupt_lookup {
287 u32 src;
288 u32 clr;
289 bool is_error;
290 int offset;
291 };
292
293 /**
294 * struct d40_reg_val - simple lookup struct
295 *
296 * @reg: The register.
297 * @val: The value that belongs to the register in reg.
298 */
299 struct d40_reg_val {
300 unsigned int reg;
301 unsigned int val;
302 };
303
304 static struct device *chan2dev(struct d40_chan *d40c)
305 {
306 return &d40c->chan.dev->device;
307 }
308
309 static bool chan_is_physical(struct d40_chan *chan)
310 {
311 return chan->log_num == D40_PHY_CHAN;
312 }
313
314 static bool chan_is_logical(struct d40_chan *chan)
315 {
316 return !chan_is_physical(chan);
317 }
318
319 static void __iomem *chan_base(struct d40_chan *chan)
320 {
321 return chan->base->virtbase + D40_DREG_PCBASE +
322 chan->phy_chan->num * D40_DREG_PCDELTA;
323 }
324
325 static int d40_pool_lli_alloc(struct d40_desc *d40d,
326 int lli_len, bool is_log)
327 {
328 u32 align;
329 void *base;
330
331 if (is_log)
332 align = sizeof(struct d40_log_lli);
333 else
334 align = sizeof(struct d40_phy_lli);
335
336 if (lli_len == 1) {
337 base = d40d->lli_pool.pre_alloc_lli;
338 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
339 d40d->lli_pool.base = NULL;
340 } else {
341 d40d->lli_pool.size = ALIGN(lli_len * 2 * align, align);
342
343 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
344 d40d->lli_pool.base = base;
345
346 if (d40d->lli_pool.base == NULL)
347 return -ENOMEM;
348 }
349
350 if (is_log) {
351 d40d->lli_log.src = PTR_ALIGN((struct d40_log_lli *) base,
352 align);
353 d40d->lli_log.dst = PTR_ALIGN(d40d->lli_log.src + lli_len,
354 align);
355 } else {
356 d40d->lli_phy.src = PTR_ALIGN((struct d40_phy_lli *)base,
357 align);
358 d40d->lli_phy.dst = PTR_ALIGN(d40d->lli_phy.src + lli_len,
359 align);
360 }
361
362 return 0;
363 }
364
365 static void d40_pool_lli_free(struct d40_desc *d40d)
366 {
367 kfree(d40d->lli_pool.base);
368 d40d->lli_pool.base = NULL;
369 d40d->lli_pool.size = 0;
370 d40d->lli_log.src = NULL;
371 d40d->lli_log.dst = NULL;
372 d40d->lli_phy.src = NULL;
373 d40d->lli_phy.dst = NULL;
374 }
375
376 static int d40_lcla_alloc_one(struct d40_chan *d40c,
377 struct d40_desc *d40d)
378 {
379 unsigned long flags;
380 int i;
381 int ret = -EINVAL;
382 int p;
383
384 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
385
386 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
387
388 /*
389 * Allocate both src and dst at the same time, therefore the half
390 * start on 1 since 0 can't be used since zero is used as end marker.
391 */
392 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
393 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
394 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
395 d40d->lcla_alloc++;
396 ret = i;
397 break;
398 }
399 }
400
401 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
402
403 return ret;
404 }
405
406 static int d40_lcla_free_all(struct d40_chan *d40c,
407 struct d40_desc *d40d)
408 {
409 unsigned long flags;
410 int i;
411 int ret = -EINVAL;
412
413 if (chan_is_physical(d40c))
414 return 0;
415
416 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
417
418 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
419 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
420 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
421 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
422 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
423 d40d->lcla_alloc--;
424 if (d40d->lcla_alloc == 0) {
425 ret = 0;
426 break;
427 }
428 }
429 }
430
431 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
432
433 return ret;
434
435 }
436
437 static void d40_desc_remove(struct d40_desc *d40d)
438 {
439 list_del(&d40d->node);
440 }
441
442 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
443 {
444 struct d40_desc *desc = NULL;
445
446 if (!list_empty(&d40c->client)) {
447 struct d40_desc *d;
448 struct d40_desc *_d;
449
450 list_for_each_entry_safe(d, _d, &d40c->client, node)
451 if (async_tx_test_ack(&d->txd)) {
452 d40_pool_lli_free(d);
453 d40_desc_remove(d);
454 desc = d;
455 memset(desc, 0, sizeof(*desc));
456 break;
457 }
458 }
459
460 if (!desc)
461 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
462
463 if (desc)
464 INIT_LIST_HEAD(&desc->node);
465
466 return desc;
467 }
468
469 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
470 {
471
472 d40_lcla_free_all(d40c, d40d);
473 kmem_cache_free(d40c->base->desc_slab, d40d);
474 }
475
476 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
477 {
478 list_add_tail(&desc->node, &d40c->active);
479 }
480
481 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
482 {
483 int curr_lcla = -EINVAL, next_lcla;
484
485 if (chan_is_physical(d40c)) {
486 d40_phy_lli_write(d40c->base->virtbase,
487 d40c->phy_chan->num,
488 d40d->lli_phy.dst,
489 d40d->lli_phy.src);
490 d40d->lli_current = d40d->lli_len;
491 } else {
492
493 if ((d40d->lli_len - d40d->lli_current) > 1)
494 curr_lcla = d40_lcla_alloc_one(d40c, d40d);
495
496 d40_log_lli_lcpa_write(d40c->lcpa,
497 &d40d->lli_log.dst[d40d->lli_current],
498 &d40d->lli_log.src[d40d->lli_current],
499 curr_lcla);
500
501 d40d->lli_current++;
502 for (; d40d->lli_current < d40d->lli_len; d40d->lli_current++) {
503 struct d40_log_lli *lcla;
504
505 if (d40d->lli_current + 1 < d40d->lli_len)
506 next_lcla = d40_lcla_alloc_one(d40c, d40d);
507 else
508 next_lcla = -EINVAL;
509
510 lcla = d40c->base->lcla_pool.base +
511 d40c->phy_chan->num * 1024 +
512 8 * curr_lcla * 2;
513
514 d40_log_lli_lcla_write(lcla,
515 &d40d->lli_log.dst[d40d->lli_current],
516 &d40d->lli_log.src[d40d->lli_current],
517 next_lcla);
518
519 (void) dma_map_single(d40c->base->dev, lcla,
520 2 * sizeof(struct d40_log_lli),
521 DMA_TO_DEVICE);
522
523 curr_lcla = next_lcla;
524
525 if (curr_lcla == -EINVAL) {
526 d40d->lli_current++;
527 break;
528 }
529
530 }
531 }
532 }
533
534 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
535 {
536 struct d40_desc *d;
537
538 if (list_empty(&d40c->active))
539 return NULL;
540
541 d = list_first_entry(&d40c->active,
542 struct d40_desc,
543 node);
544 return d;
545 }
546
547 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
548 {
549 list_add_tail(&desc->node, &d40c->queue);
550 }
551
552 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
553 {
554 struct d40_desc *d;
555
556 if (list_empty(&d40c->queue))
557 return NULL;
558
559 d = list_first_entry(&d40c->queue,
560 struct d40_desc,
561 node);
562 return d;
563 }
564
565 static int d40_psize_2_burst_size(bool is_log, int psize)
566 {
567 if (is_log) {
568 if (psize == STEDMA40_PSIZE_LOG_1)
569 return 1;
570 } else {
571 if (psize == STEDMA40_PSIZE_PHY_1)
572 return 1;
573 }
574
575 return 2 << psize;
576 }
577
578 /*
579 * The dma only supports transmitting packages up to
580 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
581 * dma elements required to send the entire sg list
582 */
583 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
584 {
585 int dmalen;
586 u32 max_w = max(data_width1, data_width2);
587 u32 min_w = min(data_width1, data_width2);
588 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
589
590 if (seg_max > STEDMA40_MAX_SEG_SIZE)
591 seg_max -= (1 << max_w);
592
593 if (!IS_ALIGNED(size, 1 << max_w))
594 return -EINVAL;
595
596 if (size <= seg_max)
597 dmalen = 1;
598 else {
599 dmalen = size / seg_max;
600 if (dmalen * seg_max < size)
601 dmalen++;
602 }
603 return dmalen;
604 }
605
606 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
607 u32 data_width1, u32 data_width2)
608 {
609 struct scatterlist *sg;
610 int i;
611 int len = 0;
612 int ret;
613
614 for_each_sg(sgl, sg, sg_len, i) {
615 ret = d40_size_2_dmalen(sg_dma_len(sg),
616 data_width1, data_width2);
617 if (ret < 0)
618 return ret;
619 len += ret;
620 }
621 return len;
622 }
623
624 /* Support functions for logical channels */
625
626 static int d40_channel_execute_command(struct d40_chan *d40c,
627 enum d40_command command)
628 {
629 u32 status;
630 int i;
631 void __iomem *active_reg;
632 int ret = 0;
633 unsigned long flags;
634 u32 wmask;
635
636 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
637
638 if (d40c->phy_chan->num % 2 == 0)
639 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
640 else
641 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
642
643 if (command == D40_DMA_SUSPEND_REQ) {
644 status = (readl(active_reg) &
645 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
646 D40_CHAN_POS(d40c->phy_chan->num);
647
648 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
649 goto done;
650 }
651
652 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
653 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
654 active_reg);
655
656 if (command == D40_DMA_SUSPEND_REQ) {
657
658 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
659 status = (readl(active_reg) &
660 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
661 D40_CHAN_POS(d40c->phy_chan->num);
662
663 cpu_relax();
664 /*
665 * Reduce the number of bus accesses while
666 * waiting for the DMA to suspend.
667 */
668 udelay(3);
669
670 if (status == D40_DMA_STOP ||
671 status == D40_DMA_SUSPENDED)
672 break;
673 }
674
675 if (i == D40_SUSPEND_MAX_IT) {
676 dev_err(&d40c->chan.dev->device,
677 "[%s]: unable to suspend the chl %d (log: %d) status %x\n",
678 __func__, d40c->phy_chan->num, d40c->log_num,
679 status);
680 dump_stack();
681 ret = -EBUSY;
682 }
683
684 }
685 done:
686 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
687 return ret;
688 }
689
690 static void d40_term_all(struct d40_chan *d40c)
691 {
692 struct d40_desc *d40d;
693
694 /* Release active descriptors */
695 while ((d40d = d40_first_active_get(d40c))) {
696 d40_desc_remove(d40d);
697 d40_desc_free(d40c, d40d);
698 }
699
700 /* Release queued descriptors waiting for transfer */
701 while ((d40d = d40_first_queued(d40c))) {
702 d40_desc_remove(d40d);
703 d40_desc_free(d40c, d40d);
704 }
705
706
707 d40c->pending_tx = 0;
708 d40c->busy = false;
709 }
710
711 static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
712 u32 event, int reg)
713 {
714 void __iomem *addr = chan_base(d40c) + reg;
715 int tries;
716
717 if (!enable) {
718 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
719 | ~D40_EVENTLINE_MASK(event), addr);
720 return;
721 }
722
723 /*
724 * The hardware sometimes doesn't register the enable when src and dst
725 * event lines are active on the same logical channel. Retry to ensure
726 * it does. Usually only one retry is sufficient.
727 */
728 tries = 100;
729 while (--tries) {
730 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
731 | ~D40_EVENTLINE_MASK(event), addr);
732
733 if (readl(addr) & D40_EVENTLINE_MASK(event))
734 break;
735 }
736
737 if (tries != 99)
738 dev_dbg(chan2dev(d40c),
739 "[%s] workaround enable S%cLNK (%d tries)\n",
740 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
741 100 - tries);
742
743 WARN_ON(!tries);
744 }
745
746 static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
747 {
748 unsigned long flags;
749
750 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
751
752 /* Enable event line connected to device (or memcpy) */
753 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
754 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
755 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
756
757 __d40_config_set_event(d40c, do_enable, event,
758 D40_CHAN_REG_SSLNK);
759 }
760
761 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
762 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
763
764 __d40_config_set_event(d40c, do_enable, event,
765 D40_CHAN_REG_SDLNK);
766 }
767
768 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
769 }
770
771 static u32 d40_chan_has_events(struct d40_chan *d40c)
772 {
773 void __iomem *chanbase = chan_base(d40c);
774 u32 val;
775
776 val = readl(chanbase + D40_CHAN_REG_SSLNK);
777 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
778
779 return val;
780 }
781
782 static u32 d40_get_prmo(struct d40_chan *d40c)
783 {
784 static const unsigned int phy_map[] = {
785 [STEDMA40_PCHAN_BASIC_MODE]
786 = D40_DREG_PRMO_PCHAN_BASIC,
787 [STEDMA40_PCHAN_MODULO_MODE]
788 = D40_DREG_PRMO_PCHAN_MODULO,
789 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
790 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
791 };
792 static const unsigned int log_map[] = {
793 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
794 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
795 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
796 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
797 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
798 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
799 };
800
801 if (chan_is_physical(d40c))
802 return phy_map[d40c->dma_cfg.mode_opt];
803 else
804 return log_map[d40c->dma_cfg.mode_opt];
805 }
806
807 static void d40_config_write(struct d40_chan *d40c)
808 {
809 u32 addr_base;
810 u32 var;
811
812 /* Odd addresses are even addresses + 4 */
813 addr_base = (d40c->phy_chan->num % 2) * 4;
814 /* Setup channel mode to logical or physical */
815 var = ((u32)(chan_is_logical(d40c)) + 1) <<
816 D40_CHAN_POS(d40c->phy_chan->num);
817 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
818
819 /* Setup operational mode option register */
820 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
821
822 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
823
824 if (chan_is_logical(d40c)) {
825 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
826 & D40_SREG_ELEM_LOG_LIDX_MASK;
827 void __iomem *chanbase = chan_base(d40c);
828
829 /* Set default config for CFG reg */
830 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
831 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
832
833 /* Set LIDX for lcla */
834 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
835 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
836 }
837 }
838
839 static u32 d40_residue(struct d40_chan *d40c)
840 {
841 u32 num_elt;
842
843 if (chan_is_logical(d40c))
844 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
845 >> D40_MEM_LCSP2_ECNT_POS;
846 else {
847 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
848 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
849 >> D40_SREG_ELEM_PHY_ECNT_POS;
850 }
851
852 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
853 }
854
855 static bool d40_tx_is_linked(struct d40_chan *d40c)
856 {
857 bool is_link;
858
859 if (chan_is_logical(d40c))
860 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
861 else
862 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
863 & D40_SREG_LNK_PHYS_LNK_MASK;
864
865 return is_link;
866 }
867
868 static int d40_pause(struct dma_chan *chan)
869 {
870 struct d40_chan *d40c =
871 container_of(chan, struct d40_chan, chan);
872 int res = 0;
873 unsigned long flags;
874
875 if (!d40c->busy)
876 return 0;
877
878 spin_lock_irqsave(&d40c->lock, flags);
879
880 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
881 if (res == 0) {
882 if (chan_is_logical(d40c)) {
883 d40_config_set_event(d40c, false);
884 /* Resume the other logical channels if any */
885 if (d40_chan_has_events(d40c))
886 res = d40_channel_execute_command(d40c,
887 D40_DMA_RUN);
888 }
889 }
890
891 spin_unlock_irqrestore(&d40c->lock, flags);
892 return res;
893 }
894
895 static int d40_resume(struct dma_chan *chan)
896 {
897 struct d40_chan *d40c =
898 container_of(chan, struct d40_chan, chan);
899 int res = 0;
900 unsigned long flags;
901
902 if (!d40c->busy)
903 return 0;
904
905 spin_lock_irqsave(&d40c->lock, flags);
906
907 if (d40c->base->rev == 0)
908 if (chan_is_logical(d40c)) {
909 res = d40_channel_execute_command(d40c,
910 D40_DMA_SUSPEND_REQ);
911 goto no_suspend;
912 }
913
914 /* If bytes left to transfer or linked tx resume job */
915 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
916
917 if (chan_is_logical(d40c))
918 d40_config_set_event(d40c, true);
919
920 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
921 }
922
923 no_suspend:
924 spin_unlock_irqrestore(&d40c->lock, flags);
925 return res;
926 }
927
928 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
929 {
930 struct d40_chan *d40c = container_of(tx->chan,
931 struct d40_chan,
932 chan);
933 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
934 unsigned long flags;
935
936 spin_lock_irqsave(&d40c->lock, flags);
937
938 d40c->chan.cookie++;
939
940 if (d40c->chan.cookie < 0)
941 d40c->chan.cookie = 1;
942
943 d40d->txd.cookie = d40c->chan.cookie;
944
945 d40_desc_queue(d40c, d40d);
946
947 spin_unlock_irqrestore(&d40c->lock, flags);
948
949 return tx->cookie;
950 }
951
952 static int d40_start(struct d40_chan *d40c)
953 {
954 if (d40c->base->rev == 0) {
955 int err;
956
957 if (chan_is_logical(d40c)) {
958 err = d40_channel_execute_command(d40c,
959 D40_DMA_SUSPEND_REQ);
960 if (err)
961 return err;
962 }
963 }
964
965 if (chan_is_logical(d40c))
966 d40_config_set_event(d40c, true);
967
968 return d40_channel_execute_command(d40c, D40_DMA_RUN);
969 }
970
971 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
972 {
973 struct d40_desc *d40d;
974 int err;
975
976 /* Start queued jobs, if any */
977 d40d = d40_first_queued(d40c);
978
979 if (d40d != NULL) {
980 d40c->busy = true;
981
982 /* Remove from queue */
983 d40_desc_remove(d40d);
984
985 /* Add to active queue */
986 d40_desc_submit(d40c, d40d);
987
988 /* Initiate DMA job */
989 d40_desc_load(d40c, d40d);
990
991 /* Start dma job */
992 err = d40_start(d40c);
993
994 if (err)
995 return NULL;
996 }
997
998 return d40d;
999 }
1000
1001 /* called from interrupt context */
1002 static void dma_tc_handle(struct d40_chan *d40c)
1003 {
1004 struct d40_desc *d40d;
1005
1006 /* Get first active entry from list */
1007 d40d = d40_first_active_get(d40c);
1008
1009 if (d40d == NULL)
1010 return;
1011
1012 d40_lcla_free_all(d40c, d40d);
1013
1014 if (d40d->lli_current < d40d->lli_len) {
1015 d40_desc_load(d40c, d40d);
1016 /* Start dma job */
1017 (void) d40_start(d40c);
1018 return;
1019 }
1020
1021 if (d40_queue_start(d40c) == NULL)
1022 d40c->busy = false;
1023
1024 d40c->pending_tx++;
1025 tasklet_schedule(&d40c->tasklet);
1026
1027 }
1028
1029 static void dma_tasklet(unsigned long data)
1030 {
1031 struct d40_chan *d40c = (struct d40_chan *) data;
1032 struct d40_desc *d40d;
1033 unsigned long flags;
1034 dma_async_tx_callback callback;
1035 void *callback_param;
1036
1037 spin_lock_irqsave(&d40c->lock, flags);
1038
1039 /* Get first active entry from list */
1040 d40d = d40_first_active_get(d40c);
1041
1042 if (d40d == NULL)
1043 goto err;
1044
1045 d40c->completed = d40d->txd.cookie;
1046
1047 /*
1048 * If terminating a channel pending_tx is set to zero.
1049 * This prevents any finished active jobs to return to the client.
1050 */
1051 if (d40c->pending_tx == 0) {
1052 spin_unlock_irqrestore(&d40c->lock, flags);
1053 return;
1054 }
1055
1056 /* Callback to client */
1057 callback = d40d->txd.callback;
1058 callback_param = d40d->txd.callback_param;
1059
1060 if (async_tx_test_ack(&d40d->txd)) {
1061 d40_pool_lli_free(d40d);
1062 d40_desc_remove(d40d);
1063 d40_desc_free(d40c, d40d);
1064 } else {
1065 if (!d40d->is_in_client_list) {
1066 d40_desc_remove(d40d);
1067 d40_lcla_free_all(d40c, d40d);
1068 list_add_tail(&d40d->node, &d40c->client);
1069 d40d->is_in_client_list = true;
1070 }
1071 }
1072
1073 d40c->pending_tx--;
1074
1075 if (d40c->pending_tx)
1076 tasklet_schedule(&d40c->tasklet);
1077
1078 spin_unlock_irqrestore(&d40c->lock, flags);
1079
1080 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
1081 callback(callback_param);
1082
1083 return;
1084
1085 err:
1086 /* Rescue manouver if receiving double interrupts */
1087 if (d40c->pending_tx > 0)
1088 d40c->pending_tx--;
1089 spin_unlock_irqrestore(&d40c->lock, flags);
1090 }
1091
1092 static irqreturn_t d40_handle_interrupt(int irq, void *data)
1093 {
1094 static const struct d40_interrupt_lookup il[] = {
1095 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1096 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1097 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1098 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1099 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1100 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1101 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1102 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1103 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1104 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1105 };
1106
1107 int i;
1108 u32 regs[ARRAY_SIZE(il)];
1109 u32 idx;
1110 u32 row;
1111 long chan = -1;
1112 struct d40_chan *d40c;
1113 unsigned long flags;
1114 struct d40_base *base = data;
1115
1116 spin_lock_irqsave(&base->interrupt_lock, flags);
1117
1118 /* Read interrupt status of both logical and physical channels */
1119 for (i = 0; i < ARRAY_SIZE(il); i++)
1120 regs[i] = readl(base->virtbase + il[i].src);
1121
1122 for (;;) {
1123
1124 chan = find_next_bit((unsigned long *)regs,
1125 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1126
1127 /* No more set bits found? */
1128 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1129 break;
1130
1131 row = chan / BITS_PER_LONG;
1132 idx = chan & (BITS_PER_LONG - 1);
1133
1134 /* ACK interrupt */
1135 writel(1 << idx, base->virtbase + il[row].clr);
1136
1137 if (il[row].offset == D40_PHY_CHAN)
1138 d40c = base->lookup_phy_chans[idx];
1139 else
1140 d40c = base->lookup_log_chans[il[row].offset + idx];
1141 spin_lock(&d40c->lock);
1142
1143 if (!il[row].is_error)
1144 dma_tc_handle(d40c);
1145 else
1146 dev_err(base->dev,
1147 "[%s] IRQ chan: %ld offset %d idx %d\n",
1148 __func__, chan, il[row].offset, idx);
1149
1150 spin_unlock(&d40c->lock);
1151 }
1152
1153 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1154
1155 return IRQ_HANDLED;
1156 }
1157
1158 static int d40_validate_conf(struct d40_chan *d40c,
1159 struct stedma40_chan_cfg *conf)
1160 {
1161 int res = 0;
1162 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1163 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
1164 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1165
1166 if (!conf->dir) {
1167 dev_err(&d40c->chan.dev->device, "[%s] Invalid direction.\n",
1168 __func__);
1169 res = -EINVAL;
1170 }
1171
1172 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1173 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1174 d40c->runtime_addr == 0) {
1175
1176 dev_err(&d40c->chan.dev->device,
1177 "[%s] Invalid TX channel address (%d)\n",
1178 __func__, conf->dst_dev_type);
1179 res = -EINVAL;
1180 }
1181
1182 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1183 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1184 d40c->runtime_addr == 0) {
1185 dev_err(&d40c->chan.dev->device,
1186 "[%s] Invalid RX channel address (%d)\n",
1187 __func__, conf->src_dev_type);
1188 res = -EINVAL;
1189 }
1190
1191 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
1192 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
1193 dev_err(&d40c->chan.dev->device, "[%s] Invalid dst\n",
1194 __func__);
1195 res = -EINVAL;
1196 }
1197
1198 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
1199 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
1200 dev_err(&d40c->chan.dev->device, "[%s] Invalid src\n",
1201 __func__);
1202 res = -EINVAL;
1203 }
1204
1205 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1206 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
1207 dev_err(&d40c->chan.dev->device,
1208 "[%s] No event line\n", __func__);
1209 res = -EINVAL;
1210 }
1211
1212 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1213 (src_event_group != dst_event_group)) {
1214 dev_err(&d40c->chan.dev->device,
1215 "[%s] Invalid event group\n", __func__);
1216 res = -EINVAL;
1217 }
1218
1219 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1220 /*
1221 * DMAC HW supports it. Will be added to this driver,
1222 * in case any dma client requires it.
1223 */
1224 dev_err(&d40c->chan.dev->device,
1225 "[%s] periph to periph not supported\n",
1226 __func__);
1227 res = -EINVAL;
1228 }
1229
1230 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1231 (1 << conf->src_info.data_width) !=
1232 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1233 (1 << conf->dst_info.data_width)) {
1234 /*
1235 * The DMAC hardware only supports
1236 * src (burst x width) == dst (burst x width)
1237 */
1238
1239 dev_err(&d40c->chan.dev->device,
1240 "[%s] src (burst x width) != dst (burst x width)\n",
1241 __func__);
1242 res = -EINVAL;
1243 }
1244
1245 return res;
1246 }
1247
1248 static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
1249 int log_event_line, bool is_log)
1250 {
1251 unsigned long flags;
1252 spin_lock_irqsave(&phy->lock, flags);
1253 if (!is_log) {
1254 /* Physical interrupts are masked per physical full channel */
1255 if (phy->allocated_src == D40_ALLOC_FREE &&
1256 phy->allocated_dst == D40_ALLOC_FREE) {
1257 phy->allocated_dst = D40_ALLOC_PHY;
1258 phy->allocated_src = D40_ALLOC_PHY;
1259 goto found;
1260 } else
1261 goto not_found;
1262 }
1263
1264 /* Logical channel */
1265 if (is_src) {
1266 if (phy->allocated_src == D40_ALLOC_PHY)
1267 goto not_found;
1268
1269 if (phy->allocated_src == D40_ALLOC_FREE)
1270 phy->allocated_src = D40_ALLOC_LOG_FREE;
1271
1272 if (!(phy->allocated_src & (1 << log_event_line))) {
1273 phy->allocated_src |= 1 << log_event_line;
1274 goto found;
1275 } else
1276 goto not_found;
1277 } else {
1278 if (phy->allocated_dst == D40_ALLOC_PHY)
1279 goto not_found;
1280
1281 if (phy->allocated_dst == D40_ALLOC_FREE)
1282 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1283
1284 if (!(phy->allocated_dst & (1 << log_event_line))) {
1285 phy->allocated_dst |= 1 << log_event_line;
1286 goto found;
1287 } else
1288 goto not_found;
1289 }
1290
1291 not_found:
1292 spin_unlock_irqrestore(&phy->lock, flags);
1293 return false;
1294 found:
1295 spin_unlock_irqrestore(&phy->lock, flags);
1296 return true;
1297 }
1298
1299 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1300 int log_event_line)
1301 {
1302 unsigned long flags;
1303 bool is_free = false;
1304
1305 spin_lock_irqsave(&phy->lock, flags);
1306 if (!log_event_line) {
1307 phy->allocated_dst = D40_ALLOC_FREE;
1308 phy->allocated_src = D40_ALLOC_FREE;
1309 is_free = true;
1310 goto out;
1311 }
1312
1313 /* Logical channel */
1314 if (is_src) {
1315 phy->allocated_src &= ~(1 << log_event_line);
1316 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1317 phy->allocated_src = D40_ALLOC_FREE;
1318 } else {
1319 phy->allocated_dst &= ~(1 << log_event_line);
1320 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1321 phy->allocated_dst = D40_ALLOC_FREE;
1322 }
1323
1324 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1325 D40_ALLOC_FREE);
1326
1327 out:
1328 spin_unlock_irqrestore(&phy->lock, flags);
1329
1330 return is_free;
1331 }
1332
1333 static int d40_allocate_channel(struct d40_chan *d40c)
1334 {
1335 int dev_type;
1336 int event_group;
1337 int event_line;
1338 struct d40_phy_res *phys;
1339 int i;
1340 int j;
1341 int log_num;
1342 bool is_src;
1343 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1344
1345 phys = d40c->base->phy_res;
1346
1347 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1348 dev_type = d40c->dma_cfg.src_dev_type;
1349 log_num = 2 * dev_type;
1350 is_src = true;
1351 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1352 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1353 /* dst event lines are used for logical memcpy */
1354 dev_type = d40c->dma_cfg.dst_dev_type;
1355 log_num = 2 * dev_type + 1;
1356 is_src = false;
1357 } else
1358 return -EINVAL;
1359
1360 event_group = D40_TYPE_TO_GROUP(dev_type);
1361 event_line = D40_TYPE_TO_EVENT(dev_type);
1362
1363 if (!is_log) {
1364 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1365 /* Find physical half channel */
1366 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1367
1368 if (d40_alloc_mask_set(&phys[i], is_src,
1369 0, is_log))
1370 goto found_phy;
1371 }
1372 } else
1373 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1374 int phy_num = j + event_group * 2;
1375 for (i = phy_num; i < phy_num + 2; i++) {
1376 if (d40_alloc_mask_set(&phys[i],
1377 is_src,
1378 0,
1379 is_log))
1380 goto found_phy;
1381 }
1382 }
1383 return -EINVAL;
1384 found_phy:
1385 d40c->phy_chan = &phys[i];
1386 d40c->log_num = D40_PHY_CHAN;
1387 goto out;
1388 }
1389 if (dev_type == -1)
1390 return -EINVAL;
1391
1392 /* Find logical channel */
1393 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1394 int phy_num = j + event_group * 2;
1395 /*
1396 * Spread logical channels across all available physical rather
1397 * than pack every logical channel at the first available phy
1398 * channels.
1399 */
1400 if (is_src) {
1401 for (i = phy_num; i < phy_num + 2; i++) {
1402 if (d40_alloc_mask_set(&phys[i], is_src,
1403 event_line, is_log))
1404 goto found_log;
1405 }
1406 } else {
1407 for (i = phy_num + 1; i >= phy_num; i--) {
1408 if (d40_alloc_mask_set(&phys[i], is_src,
1409 event_line, is_log))
1410 goto found_log;
1411 }
1412 }
1413 }
1414 return -EINVAL;
1415
1416 found_log:
1417 d40c->phy_chan = &phys[i];
1418 d40c->log_num = log_num;
1419 out:
1420
1421 if (is_log)
1422 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1423 else
1424 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1425
1426 return 0;
1427
1428 }
1429
1430 static int d40_config_memcpy(struct d40_chan *d40c)
1431 {
1432 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1433
1434 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1435 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1436 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1437 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1438 memcpy[d40c->chan.chan_id];
1439
1440 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1441 dma_has_cap(DMA_SLAVE, cap)) {
1442 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1443 } else {
1444 dev_err(&d40c->chan.dev->device, "[%s] No memcpy\n",
1445 __func__);
1446 return -EINVAL;
1447 }
1448
1449 return 0;
1450 }
1451
1452
1453 static int d40_free_dma(struct d40_chan *d40c)
1454 {
1455
1456 int res = 0;
1457 u32 event;
1458 struct d40_phy_res *phy = d40c->phy_chan;
1459 bool is_src;
1460 struct d40_desc *d;
1461 struct d40_desc *_d;
1462
1463
1464 /* Terminate all queued and active transfers */
1465 d40_term_all(d40c);
1466
1467 /* Release client owned descriptors */
1468 if (!list_empty(&d40c->client))
1469 list_for_each_entry_safe(d, _d, &d40c->client, node) {
1470 d40_pool_lli_free(d);
1471 d40_desc_remove(d);
1472 d40_desc_free(d40c, d);
1473 }
1474
1475 if (phy == NULL) {
1476 dev_err(&d40c->chan.dev->device, "[%s] phy == null\n",
1477 __func__);
1478 return -EINVAL;
1479 }
1480
1481 if (phy->allocated_src == D40_ALLOC_FREE &&
1482 phy->allocated_dst == D40_ALLOC_FREE) {
1483 dev_err(&d40c->chan.dev->device, "[%s] channel already free\n",
1484 __func__);
1485 return -EINVAL;
1486 }
1487
1488 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1489 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1490 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1491 is_src = false;
1492 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1493 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1494 is_src = true;
1495 } else {
1496 dev_err(&d40c->chan.dev->device,
1497 "[%s] Unknown direction\n", __func__);
1498 return -EINVAL;
1499 }
1500
1501 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1502 if (res) {
1503 dev_err(&d40c->chan.dev->device, "[%s] suspend failed\n",
1504 __func__);
1505 return res;
1506 }
1507
1508 if (chan_is_logical(d40c)) {
1509 /* Release logical channel, deactivate the event line */
1510
1511 d40_config_set_event(d40c, false);
1512 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1513
1514 /*
1515 * Check if there are more logical allocation
1516 * on this phy channel.
1517 */
1518 if (!d40_alloc_mask_free(phy, is_src, event)) {
1519 /* Resume the other logical channels if any */
1520 if (d40_chan_has_events(d40c)) {
1521 res = d40_channel_execute_command(d40c,
1522 D40_DMA_RUN);
1523 if (res) {
1524 dev_err(&d40c->chan.dev->device,
1525 "[%s] Executing RUN command\n",
1526 __func__);
1527 return res;
1528 }
1529 }
1530 return 0;
1531 }
1532 } else {
1533 (void) d40_alloc_mask_free(phy, is_src, 0);
1534 }
1535
1536 /* Release physical channel */
1537 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1538 if (res) {
1539 dev_err(&d40c->chan.dev->device,
1540 "[%s] Failed to stop channel\n", __func__);
1541 return res;
1542 }
1543 d40c->phy_chan = NULL;
1544 d40c->configured = false;
1545 d40c->base->lookup_phy_chans[phy->num] = NULL;
1546
1547 return 0;
1548 }
1549
1550 static bool d40_is_paused(struct d40_chan *d40c)
1551 {
1552 void __iomem *chanbase = chan_base(d40c);
1553 bool is_paused = false;
1554 unsigned long flags;
1555 void __iomem *active_reg;
1556 u32 status;
1557 u32 event;
1558
1559 spin_lock_irqsave(&d40c->lock, flags);
1560
1561 if (chan_is_physical(d40c)) {
1562 if (d40c->phy_chan->num % 2 == 0)
1563 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1564 else
1565 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1566
1567 status = (readl(active_reg) &
1568 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1569 D40_CHAN_POS(d40c->phy_chan->num);
1570 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1571 is_paused = true;
1572
1573 goto _exit;
1574 }
1575
1576 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1577 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1578 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1579 status = readl(chanbase + D40_CHAN_REG_SDLNK);
1580 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1581 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1582 status = readl(chanbase + D40_CHAN_REG_SSLNK);
1583 } else {
1584 dev_err(&d40c->chan.dev->device,
1585 "[%s] Unknown direction\n", __func__);
1586 goto _exit;
1587 }
1588
1589 status = (status & D40_EVENTLINE_MASK(event)) >>
1590 D40_EVENTLINE_POS(event);
1591
1592 if (status != D40_DMA_RUN)
1593 is_paused = true;
1594 _exit:
1595 spin_unlock_irqrestore(&d40c->lock, flags);
1596 return is_paused;
1597
1598 }
1599
1600
1601 static u32 stedma40_residue(struct dma_chan *chan)
1602 {
1603 struct d40_chan *d40c =
1604 container_of(chan, struct d40_chan, chan);
1605 u32 bytes_left;
1606 unsigned long flags;
1607
1608 spin_lock_irqsave(&d40c->lock, flags);
1609 bytes_left = d40_residue(d40c);
1610 spin_unlock_irqrestore(&d40c->lock, flags);
1611
1612 return bytes_left;
1613 }
1614
1615 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
1616 struct scatterlist *sgl_dst,
1617 struct scatterlist *sgl_src,
1618 unsigned int sgl_len,
1619 unsigned long dma_flags)
1620 {
1621 int res;
1622 struct d40_desc *d40d;
1623 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1624 chan);
1625 unsigned long flags;
1626
1627 if (d40c->phy_chan == NULL) {
1628 dev_err(&d40c->chan.dev->device,
1629 "[%s] Unallocated channel.\n", __func__);
1630 return ERR_PTR(-EINVAL);
1631 }
1632
1633 spin_lock_irqsave(&d40c->lock, flags);
1634 d40d = d40_desc_get(d40c);
1635
1636 if (d40d == NULL)
1637 goto err;
1638
1639 d40d->lli_len = d40_sg_2_dmalen(sgl_dst, sgl_len,
1640 d40c->dma_cfg.src_info.data_width,
1641 d40c->dma_cfg.dst_info.data_width);
1642 if (d40d->lli_len < 0) {
1643 dev_err(&d40c->chan.dev->device,
1644 "[%s] Unaligned size\n", __func__);
1645 goto err;
1646 }
1647
1648 d40d->lli_current = 0;
1649 d40d->txd.flags = dma_flags;
1650
1651 if (chan_is_logical(d40c)) {
1652
1653 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
1654 dev_err(&d40c->chan.dev->device,
1655 "[%s] Out of memory\n", __func__);
1656 goto err;
1657 }
1658
1659 (void) d40_log_sg_to_lli(sgl_src,
1660 sgl_len,
1661 d40d->lli_log.src,
1662 d40c->log_def.lcsp1,
1663 d40c->dma_cfg.src_info.data_width,
1664 d40c->dma_cfg.dst_info.data_width);
1665
1666 (void) d40_log_sg_to_lli(sgl_dst,
1667 sgl_len,
1668 d40d->lli_log.dst,
1669 d40c->log_def.lcsp3,
1670 d40c->dma_cfg.dst_info.data_width,
1671 d40c->dma_cfg.src_info.data_width);
1672 } else {
1673 if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
1674 dev_err(&d40c->chan.dev->device,
1675 "[%s] Out of memory\n", __func__);
1676 goto err;
1677 }
1678
1679 res = d40_phy_sg_to_lli(sgl_src,
1680 sgl_len,
1681 0,
1682 d40d->lli_phy.src,
1683 virt_to_phys(d40d->lli_phy.src),
1684 d40c->src_def_cfg,
1685 d40c->dma_cfg.src_info.data_width,
1686 d40c->dma_cfg.dst_info.data_width,
1687 d40c->dma_cfg.src_info.psize);
1688
1689 if (res < 0)
1690 goto err;
1691
1692 res = d40_phy_sg_to_lli(sgl_dst,
1693 sgl_len,
1694 0,
1695 d40d->lli_phy.dst,
1696 virt_to_phys(d40d->lli_phy.dst),
1697 d40c->dst_def_cfg,
1698 d40c->dma_cfg.dst_info.data_width,
1699 d40c->dma_cfg.src_info.data_width,
1700 d40c->dma_cfg.dst_info.psize);
1701
1702 if (res < 0)
1703 goto err;
1704
1705 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1706 d40d->lli_pool.size, DMA_TO_DEVICE);
1707 }
1708
1709 dma_async_tx_descriptor_init(&d40d->txd, chan);
1710
1711 d40d->txd.tx_submit = d40_tx_submit;
1712
1713 spin_unlock_irqrestore(&d40c->lock, flags);
1714
1715 return &d40d->txd;
1716 err:
1717 if (d40d)
1718 d40_desc_free(d40c, d40d);
1719 spin_unlock_irqrestore(&d40c->lock, flags);
1720 return NULL;
1721 }
1722 EXPORT_SYMBOL(stedma40_memcpy_sg);
1723
1724 bool stedma40_filter(struct dma_chan *chan, void *data)
1725 {
1726 struct stedma40_chan_cfg *info = data;
1727 struct d40_chan *d40c =
1728 container_of(chan, struct d40_chan, chan);
1729 int err;
1730
1731 if (data) {
1732 err = d40_validate_conf(d40c, info);
1733 if (!err)
1734 d40c->dma_cfg = *info;
1735 } else
1736 err = d40_config_memcpy(d40c);
1737
1738 if (!err)
1739 d40c->configured = true;
1740
1741 return err == 0;
1742 }
1743 EXPORT_SYMBOL(stedma40_filter);
1744
1745 /* DMA ENGINE functions */
1746 static int d40_alloc_chan_resources(struct dma_chan *chan)
1747 {
1748 int err;
1749 unsigned long flags;
1750 struct d40_chan *d40c =
1751 container_of(chan, struct d40_chan, chan);
1752 bool is_free_phy;
1753 spin_lock_irqsave(&d40c->lock, flags);
1754
1755 d40c->completed = chan->cookie = 1;
1756
1757 /* If no dma configuration is set use default configuration (memcpy) */
1758 if (!d40c->configured) {
1759 err = d40_config_memcpy(d40c);
1760 if (err) {
1761 dev_err(&d40c->chan.dev->device,
1762 "[%s] Failed to configure memcpy channel\n",
1763 __func__);
1764 goto fail;
1765 }
1766 }
1767 is_free_phy = (d40c->phy_chan == NULL);
1768
1769 err = d40_allocate_channel(d40c);
1770 if (err) {
1771 dev_err(&d40c->chan.dev->device,
1772 "[%s] Failed to allocate channel\n", __func__);
1773 goto fail;
1774 }
1775
1776 /* Fill in basic CFG register values */
1777 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
1778 &d40c->dst_def_cfg, chan_is_logical(d40c));
1779
1780 if (chan_is_logical(d40c)) {
1781 d40_log_cfg(&d40c->dma_cfg,
1782 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1783
1784 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1785 d40c->lcpa = d40c->base->lcpa_base +
1786 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1787 else
1788 d40c->lcpa = d40c->base->lcpa_base +
1789 d40c->dma_cfg.dst_dev_type *
1790 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1791 }
1792
1793 /*
1794 * Only write channel configuration to the DMA if the physical
1795 * resource is free. In case of multiple logical channels
1796 * on the same physical resource, only the first write is necessary.
1797 */
1798 if (is_free_phy)
1799 d40_config_write(d40c);
1800 fail:
1801 spin_unlock_irqrestore(&d40c->lock, flags);
1802 return err;
1803 }
1804
1805 static void d40_free_chan_resources(struct dma_chan *chan)
1806 {
1807 struct d40_chan *d40c =
1808 container_of(chan, struct d40_chan, chan);
1809 int err;
1810 unsigned long flags;
1811
1812 if (d40c->phy_chan == NULL) {
1813 dev_err(&d40c->chan.dev->device,
1814 "[%s] Cannot free unallocated channel\n", __func__);
1815 return;
1816 }
1817
1818
1819 spin_lock_irqsave(&d40c->lock, flags);
1820
1821 err = d40_free_dma(d40c);
1822
1823 if (err)
1824 dev_err(&d40c->chan.dev->device,
1825 "[%s] Failed to free channel\n", __func__);
1826 spin_unlock_irqrestore(&d40c->lock, flags);
1827 }
1828
1829 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1830 dma_addr_t dst,
1831 dma_addr_t src,
1832 size_t size,
1833 unsigned long dma_flags)
1834 {
1835 struct d40_desc *d40d;
1836 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1837 chan);
1838 unsigned long flags;
1839
1840 if (d40c->phy_chan == NULL) {
1841 dev_err(&d40c->chan.dev->device,
1842 "[%s] Channel is not allocated.\n", __func__);
1843 return ERR_PTR(-EINVAL);
1844 }
1845
1846 spin_lock_irqsave(&d40c->lock, flags);
1847 d40d = d40_desc_get(d40c);
1848
1849 if (d40d == NULL) {
1850 dev_err(&d40c->chan.dev->device,
1851 "[%s] Descriptor is NULL\n", __func__);
1852 goto err;
1853 }
1854
1855 d40d->txd.flags = dma_flags;
1856 d40d->lli_len = d40_size_2_dmalen(size,
1857 d40c->dma_cfg.src_info.data_width,
1858 d40c->dma_cfg.dst_info.data_width);
1859 if (d40d->lli_len < 0) {
1860 dev_err(&d40c->chan.dev->device,
1861 "[%s] Unaligned size\n", __func__);
1862 goto err;
1863 }
1864
1865
1866 dma_async_tx_descriptor_init(&d40d->txd, chan);
1867
1868 d40d->txd.tx_submit = d40_tx_submit;
1869
1870 if (chan_is_logical(d40c)) {
1871
1872 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
1873 dev_err(&d40c->chan.dev->device,
1874 "[%s] Out of memory\n", __func__);
1875 goto err;
1876 }
1877 d40d->lli_current = 0;
1878
1879 if (d40_log_buf_to_lli(d40d->lli_log.src,
1880 src,
1881 size,
1882 d40c->log_def.lcsp1,
1883 d40c->dma_cfg.src_info.data_width,
1884 d40c->dma_cfg.dst_info.data_width,
1885 true) == NULL)
1886 goto err;
1887
1888 if (d40_log_buf_to_lli(d40d->lli_log.dst,
1889 dst,
1890 size,
1891 d40c->log_def.lcsp3,
1892 d40c->dma_cfg.dst_info.data_width,
1893 d40c->dma_cfg.src_info.data_width,
1894 true) == NULL)
1895 goto err;
1896
1897 } else {
1898
1899 if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
1900 dev_err(&d40c->chan.dev->device,
1901 "[%s] Out of memory\n", __func__);
1902 goto err;
1903 }
1904
1905 if (d40_phy_buf_to_lli(d40d->lli_phy.src,
1906 src,
1907 size,
1908 d40c->dma_cfg.src_info.psize,
1909 0,
1910 d40c->src_def_cfg,
1911 true,
1912 d40c->dma_cfg.src_info.data_width,
1913 d40c->dma_cfg.dst_info.data_width,
1914 false) == NULL)
1915 goto err;
1916
1917 if (d40_phy_buf_to_lli(d40d->lli_phy.dst,
1918 dst,
1919 size,
1920 d40c->dma_cfg.dst_info.psize,
1921 0,
1922 d40c->dst_def_cfg,
1923 true,
1924 d40c->dma_cfg.dst_info.data_width,
1925 d40c->dma_cfg.src_info.data_width,
1926 false) == NULL)
1927 goto err;
1928
1929 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1930 d40d->lli_pool.size, DMA_TO_DEVICE);
1931 }
1932
1933 spin_unlock_irqrestore(&d40c->lock, flags);
1934 return &d40d->txd;
1935
1936 err:
1937 if (d40d)
1938 d40_desc_free(d40c, d40d);
1939 spin_unlock_irqrestore(&d40c->lock, flags);
1940 return NULL;
1941 }
1942
1943 static struct dma_async_tx_descriptor *
1944 d40_prep_sg(struct dma_chan *chan,
1945 struct scatterlist *dst_sg, unsigned int dst_nents,
1946 struct scatterlist *src_sg, unsigned int src_nents,
1947 unsigned long dma_flags)
1948 {
1949 if (dst_nents != src_nents)
1950 return NULL;
1951
1952 return stedma40_memcpy_sg(chan, dst_sg, src_sg, dst_nents, dma_flags);
1953 }
1954
1955 static int d40_prep_slave_sg_log(struct d40_desc *d40d,
1956 struct d40_chan *d40c,
1957 struct scatterlist *sgl,
1958 unsigned int sg_len,
1959 enum dma_data_direction direction,
1960 unsigned long dma_flags)
1961 {
1962 dma_addr_t dev_addr = 0;
1963 int total_size;
1964
1965 d40d->lli_len = d40_sg_2_dmalen(sgl, sg_len,
1966 d40c->dma_cfg.src_info.data_width,
1967 d40c->dma_cfg.dst_info.data_width);
1968 if (d40d->lli_len < 0) {
1969 dev_err(&d40c->chan.dev->device,
1970 "[%s] Unaligned size\n", __func__);
1971 return -EINVAL;
1972 }
1973
1974 if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
1975 dev_err(&d40c->chan.dev->device,
1976 "[%s] Out of memory\n", __func__);
1977 return -ENOMEM;
1978 }
1979
1980 d40d->lli_current = 0;
1981
1982 if (direction == DMA_FROM_DEVICE)
1983 if (d40c->runtime_addr)
1984 dev_addr = d40c->runtime_addr;
1985 else
1986 dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1987 else if (direction == DMA_TO_DEVICE)
1988 if (d40c->runtime_addr)
1989 dev_addr = d40c->runtime_addr;
1990 else
1991 dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1992
1993 else
1994 return -EINVAL;
1995
1996 total_size = d40_log_sg_to_dev(sgl, sg_len,
1997 &d40d->lli_log,
1998 &d40c->log_def,
1999 d40c->dma_cfg.src_info.data_width,
2000 d40c->dma_cfg.dst_info.data_width,
2001 direction,
2002 dev_addr);
2003
2004 if (total_size < 0)
2005 return -EINVAL;
2006
2007 return 0;
2008 }
2009
2010 static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
2011 struct d40_chan *d40c,
2012 struct scatterlist *sgl,
2013 unsigned int sgl_len,
2014 enum dma_data_direction direction,
2015 unsigned long dma_flags)
2016 {
2017 dma_addr_t src_dev_addr;
2018 dma_addr_t dst_dev_addr;
2019 int res;
2020
2021 d40d->lli_len = d40_sg_2_dmalen(sgl, sgl_len,
2022 d40c->dma_cfg.src_info.data_width,
2023 d40c->dma_cfg.dst_info.data_width);
2024 if (d40d->lli_len < 0) {
2025 dev_err(&d40c->chan.dev->device,
2026 "[%s] Unaligned size\n", __func__);
2027 return -EINVAL;
2028 }
2029
2030 if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
2031 dev_err(&d40c->chan.dev->device,
2032 "[%s] Out of memory\n", __func__);
2033 return -ENOMEM;
2034 }
2035
2036 d40d->lli_current = 0;
2037
2038 if (direction == DMA_FROM_DEVICE) {
2039 dst_dev_addr = 0;
2040 if (d40c->runtime_addr)
2041 src_dev_addr = d40c->runtime_addr;
2042 else
2043 src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
2044 } else if (direction == DMA_TO_DEVICE) {
2045 if (d40c->runtime_addr)
2046 dst_dev_addr = d40c->runtime_addr;
2047 else
2048 dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
2049 src_dev_addr = 0;
2050 } else
2051 return -EINVAL;
2052
2053 res = d40_phy_sg_to_lli(sgl,
2054 sgl_len,
2055 src_dev_addr,
2056 d40d->lli_phy.src,
2057 virt_to_phys(d40d->lli_phy.src),
2058 d40c->src_def_cfg,
2059 d40c->dma_cfg.src_info.data_width,
2060 d40c->dma_cfg.dst_info.data_width,
2061 d40c->dma_cfg.src_info.psize);
2062 if (res < 0)
2063 return res;
2064
2065 res = d40_phy_sg_to_lli(sgl,
2066 sgl_len,
2067 dst_dev_addr,
2068 d40d->lli_phy.dst,
2069 virt_to_phys(d40d->lli_phy.dst),
2070 d40c->dst_def_cfg,
2071 d40c->dma_cfg.dst_info.data_width,
2072 d40c->dma_cfg.src_info.data_width,
2073 d40c->dma_cfg.dst_info.psize);
2074 if (res < 0)
2075 return res;
2076
2077 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
2078 d40d->lli_pool.size, DMA_TO_DEVICE);
2079 return 0;
2080 }
2081
2082 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2083 struct scatterlist *sgl,
2084 unsigned int sg_len,
2085 enum dma_data_direction direction,
2086 unsigned long dma_flags)
2087 {
2088 struct d40_desc *d40d;
2089 struct d40_chan *d40c = container_of(chan, struct d40_chan,
2090 chan);
2091 unsigned long flags;
2092 int err;
2093
2094 if (d40c->phy_chan == NULL) {
2095 dev_err(&d40c->chan.dev->device,
2096 "[%s] Cannot prepare unallocated channel\n", __func__);
2097 return ERR_PTR(-EINVAL);
2098 }
2099
2100 spin_lock_irqsave(&d40c->lock, flags);
2101 d40d = d40_desc_get(d40c);
2102
2103 if (d40d == NULL)
2104 goto err;
2105
2106 if (chan_is_logical(d40c))
2107 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
2108 direction, dma_flags);
2109 else
2110 err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
2111 direction, dma_flags);
2112 if (err) {
2113 dev_err(&d40c->chan.dev->device,
2114 "[%s] Failed to prepare %s slave sg job: %d\n",
2115 __func__,
2116 chan_is_logical(d40c) ? "log" : "phy", err);
2117 goto err;
2118 }
2119
2120 d40d->txd.flags = dma_flags;
2121
2122 dma_async_tx_descriptor_init(&d40d->txd, chan);
2123
2124 d40d->txd.tx_submit = d40_tx_submit;
2125
2126 spin_unlock_irqrestore(&d40c->lock, flags);
2127 return &d40d->txd;
2128
2129 err:
2130 if (d40d)
2131 d40_desc_free(d40c, d40d);
2132 spin_unlock_irqrestore(&d40c->lock, flags);
2133 return NULL;
2134 }
2135
2136 static enum dma_status d40_tx_status(struct dma_chan *chan,
2137 dma_cookie_t cookie,
2138 struct dma_tx_state *txstate)
2139 {
2140 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2141 dma_cookie_t last_used;
2142 dma_cookie_t last_complete;
2143 int ret;
2144
2145 if (d40c->phy_chan == NULL) {
2146 dev_err(&d40c->chan.dev->device,
2147 "[%s] Cannot read status of unallocated channel\n",
2148 __func__);
2149 return -EINVAL;
2150 }
2151
2152 last_complete = d40c->completed;
2153 last_used = chan->cookie;
2154
2155 if (d40_is_paused(d40c))
2156 ret = DMA_PAUSED;
2157 else
2158 ret = dma_async_is_complete(cookie, last_complete, last_used);
2159
2160 dma_set_tx_state(txstate, last_complete, last_used,
2161 stedma40_residue(chan));
2162
2163 return ret;
2164 }
2165
2166 static void d40_issue_pending(struct dma_chan *chan)
2167 {
2168 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2169 unsigned long flags;
2170
2171 if (d40c->phy_chan == NULL) {
2172 dev_err(&d40c->chan.dev->device,
2173 "[%s] Channel is not allocated!\n", __func__);
2174 return;
2175 }
2176
2177 spin_lock_irqsave(&d40c->lock, flags);
2178
2179 /* Busy means that pending jobs are already being processed */
2180 if (!d40c->busy)
2181 (void) d40_queue_start(d40c);
2182
2183 spin_unlock_irqrestore(&d40c->lock, flags);
2184 }
2185
2186 /* Runtime reconfiguration extension */
2187 static void d40_set_runtime_config(struct dma_chan *chan,
2188 struct dma_slave_config *config)
2189 {
2190 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2191 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2192 enum dma_slave_buswidth config_addr_width;
2193 dma_addr_t config_addr;
2194 u32 config_maxburst;
2195 enum stedma40_periph_data_width addr_width;
2196 int psize;
2197
2198 if (config->direction == DMA_FROM_DEVICE) {
2199 dma_addr_t dev_addr_rx =
2200 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2201
2202 config_addr = config->src_addr;
2203 if (dev_addr_rx)
2204 dev_dbg(d40c->base->dev,
2205 "channel has a pre-wired RX address %08x "
2206 "overriding with %08x\n",
2207 dev_addr_rx, config_addr);
2208 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2209 dev_dbg(d40c->base->dev,
2210 "channel was not configured for peripheral "
2211 "to memory transfer (%d) overriding\n",
2212 cfg->dir);
2213 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2214
2215 config_addr_width = config->src_addr_width;
2216 config_maxburst = config->src_maxburst;
2217
2218 } else if (config->direction == DMA_TO_DEVICE) {
2219 dma_addr_t dev_addr_tx =
2220 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2221
2222 config_addr = config->dst_addr;
2223 if (dev_addr_tx)
2224 dev_dbg(d40c->base->dev,
2225 "channel has a pre-wired TX address %08x "
2226 "overriding with %08x\n",
2227 dev_addr_tx, config_addr);
2228 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2229 dev_dbg(d40c->base->dev,
2230 "channel was not configured for memory "
2231 "to peripheral transfer (%d) overriding\n",
2232 cfg->dir);
2233 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2234
2235 config_addr_width = config->dst_addr_width;
2236 config_maxburst = config->dst_maxburst;
2237
2238 } else {
2239 dev_err(d40c->base->dev,
2240 "unrecognized channel direction %d\n",
2241 config->direction);
2242 return;
2243 }
2244
2245 switch (config_addr_width) {
2246 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2247 addr_width = STEDMA40_BYTE_WIDTH;
2248 break;
2249 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2250 addr_width = STEDMA40_HALFWORD_WIDTH;
2251 break;
2252 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2253 addr_width = STEDMA40_WORD_WIDTH;
2254 break;
2255 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2256 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2257 break;
2258 default:
2259 dev_err(d40c->base->dev,
2260 "illegal peripheral address width "
2261 "requested (%d)\n",
2262 config->src_addr_width);
2263 return;
2264 }
2265
2266 if (chan_is_logical(d40c)) {
2267 if (config_maxburst >= 16)
2268 psize = STEDMA40_PSIZE_LOG_16;
2269 else if (config_maxburst >= 8)
2270 psize = STEDMA40_PSIZE_LOG_8;
2271 else if (config_maxburst >= 4)
2272 psize = STEDMA40_PSIZE_LOG_4;
2273 else
2274 psize = STEDMA40_PSIZE_LOG_1;
2275 } else {
2276 if (config_maxburst >= 16)
2277 psize = STEDMA40_PSIZE_PHY_16;
2278 else if (config_maxburst >= 8)
2279 psize = STEDMA40_PSIZE_PHY_8;
2280 else if (config_maxburst >= 4)
2281 psize = STEDMA40_PSIZE_PHY_4;
2282 else if (config_maxburst >= 2)
2283 psize = STEDMA40_PSIZE_PHY_2;
2284 else
2285 psize = STEDMA40_PSIZE_PHY_1;
2286 }
2287
2288 /* Set up all the endpoint configs */
2289 cfg->src_info.data_width = addr_width;
2290 cfg->src_info.psize = psize;
2291 cfg->src_info.big_endian = false;
2292 cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2293 cfg->dst_info.data_width = addr_width;
2294 cfg->dst_info.psize = psize;
2295 cfg->dst_info.big_endian = false;
2296 cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2297
2298 /* Fill in register values */
2299 if (chan_is_logical(d40c))
2300 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2301 else
2302 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2303 &d40c->dst_def_cfg, false);
2304
2305 /* These settings will take precedence later */
2306 d40c->runtime_addr = config_addr;
2307 d40c->runtime_direction = config->direction;
2308 dev_dbg(d40c->base->dev,
2309 "configured channel %s for %s, data width %d, "
2310 "maxburst %d bytes, LE, no flow control\n",
2311 dma_chan_name(chan),
2312 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2313 config_addr_width,
2314 config_maxburst);
2315 }
2316
2317 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2318 unsigned long arg)
2319 {
2320 unsigned long flags;
2321 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2322
2323 if (d40c->phy_chan == NULL) {
2324 dev_err(&d40c->chan.dev->device,
2325 "[%s] Channel is not allocated!\n", __func__);
2326 return -EINVAL;
2327 }
2328
2329 switch (cmd) {
2330 case DMA_TERMINATE_ALL:
2331 spin_lock_irqsave(&d40c->lock, flags);
2332 d40_term_all(d40c);
2333 spin_unlock_irqrestore(&d40c->lock, flags);
2334 return 0;
2335 case DMA_PAUSE:
2336 return d40_pause(chan);
2337 case DMA_RESUME:
2338 return d40_resume(chan);
2339 case DMA_SLAVE_CONFIG:
2340 d40_set_runtime_config(chan,
2341 (struct dma_slave_config *) arg);
2342 return 0;
2343 default:
2344 break;
2345 }
2346
2347 /* Other commands are unimplemented */
2348 return -ENXIO;
2349 }
2350
2351 /* Initialization functions */
2352
2353 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2354 struct d40_chan *chans, int offset,
2355 int num_chans)
2356 {
2357 int i = 0;
2358 struct d40_chan *d40c;
2359
2360 INIT_LIST_HEAD(&dma->channels);
2361
2362 for (i = offset; i < offset + num_chans; i++) {
2363 d40c = &chans[i];
2364 d40c->base = base;
2365 d40c->chan.device = dma;
2366
2367 spin_lock_init(&d40c->lock);
2368
2369 d40c->log_num = D40_PHY_CHAN;
2370
2371 INIT_LIST_HEAD(&d40c->active);
2372 INIT_LIST_HEAD(&d40c->queue);
2373 INIT_LIST_HEAD(&d40c->client);
2374
2375 tasklet_init(&d40c->tasklet, dma_tasklet,
2376 (unsigned long) d40c);
2377
2378 list_add_tail(&d40c->chan.device_node,
2379 &dma->channels);
2380 }
2381 }
2382
2383 static int __init d40_dmaengine_init(struct d40_base *base,
2384 int num_reserved_chans)
2385 {
2386 int err ;
2387
2388 d40_chan_init(base, &base->dma_slave, base->log_chans,
2389 0, base->num_log_chans);
2390
2391 dma_cap_zero(base->dma_slave.cap_mask);
2392 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2393
2394 base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2395 base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2396 base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
2397 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
2398 base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2399 base->dma_slave.device_tx_status = d40_tx_status;
2400 base->dma_slave.device_issue_pending = d40_issue_pending;
2401 base->dma_slave.device_control = d40_control;
2402 base->dma_slave.dev = base->dev;
2403
2404 err = dma_async_device_register(&base->dma_slave);
2405
2406 if (err) {
2407 dev_err(base->dev,
2408 "[%s] Failed to register slave channels\n",
2409 __func__);
2410 goto failure1;
2411 }
2412
2413 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2414 base->num_log_chans, base->plat_data->memcpy_len);
2415
2416 dma_cap_zero(base->dma_memcpy.cap_mask);
2417 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2418 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
2419
2420 base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2421 base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2422 base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
2423 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
2424 base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2425 base->dma_memcpy.device_tx_status = d40_tx_status;
2426 base->dma_memcpy.device_issue_pending = d40_issue_pending;
2427 base->dma_memcpy.device_control = d40_control;
2428 base->dma_memcpy.dev = base->dev;
2429 /*
2430 * This controller can only access address at even
2431 * 32bit boundaries, i.e. 2^2
2432 */
2433 base->dma_memcpy.copy_align = 2;
2434
2435 err = dma_async_device_register(&base->dma_memcpy);
2436
2437 if (err) {
2438 dev_err(base->dev,
2439 "[%s] Failed to regsiter memcpy only channels\n",
2440 __func__);
2441 goto failure2;
2442 }
2443
2444 d40_chan_init(base, &base->dma_both, base->phy_chans,
2445 0, num_reserved_chans);
2446
2447 dma_cap_zero(base->dma_both.cap_mask);
2448 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2449 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2450 dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
2451
2452 base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2453 base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2454 base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
2455 base->dma_slave.device_prep_dma_sg = d40_prep_sg;
2456 base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2457 base->dma_both.device_tx_status = d40_tx_status;
2458 base->dma_both.device_issue_pending = d40_issue_pending;
2459 base->dma_both.device_control = d40_control;
2460 base->dma_both.dev = base->dev;
2461 base->dma_both.copy_align = 2;
2462 err = dma_async_device_register(&base->dma_both);
2463
2464 if (err) {
2465 dev_err(base->dev,
2466 "[%s] Failed to register logical and physical capable channels\n",
2467 __func__);
2468 goto failure3;
2469 }
2470 return 0;
2471 failure3:
2472 dma_async_device_unregister(&base->dma_memcpy);
2473 failure2:
2474 dma_async_device_unregister(&base->dma_slave);
2475 failure1:
2476 return err;
2477 }
2478
2479 /* Initialization functions. */
2480
2481 static int __init d40_phy_res_init(struct d40_base *base)
2482 {
2483 int i;
2484 int num_phy_chans_avail = 0;
2485 u32 val[2];
2486 int odd_even_bit = -2;
2487
2488 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2489 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2490
2491 for (i = 0; i < base->num_phy_chans; i++) {
2492 base->phy_res[i].num = i;
2493 odd_even_bit += 2 * ((i % 2) == 0);
2494 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2495 /* Mark security only channels as occupied */
2496 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2497 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2498 } else {
2499 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2500 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2501 num_phy_chans_avail++;
2502 }
2503 spin_lock_init(&base->phy_res[i].lock);
2504 }
2505
2506 /* Mark disabled channels as occupied */
2507 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
2508 int chan = base->plat_data->disabled_channels[i];
2509
2510 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2511 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
2512 num_phy_chans_avail--;
2513 }
2514
2515 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2516 num_phy_chans_avail, base->num_phy_chans);
2517
2518 /* Verify settings extended vs standard */
2519 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2520
2521 for (i = 0; i < base->num_phy_chans; i++) {
2522
2523 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2524 (val[0] & 0x3) != 1)
2525 dev_info(base->dev,
2526 "[%s] INFO: channel %d is misconfigured (%d)\n",
2527 __func__, i, val[0] & 0x3);
2528
2529 val[0] = val[0] >> 2;
2530 }
2531
2532 return num_phy_chans_avail;
2533 }
2534
2535 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2536 {
2537 static const struct d40_reg_val dma_id_regs[] = {
2538 /* Peripheral Id */
2539 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2540 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2541 /*
2542 * D40_DREG_PERIPHID2 Depends on HW revision:
2543 * MOP500/HREF ED has 0x0008,
2544 * ? has 0x0018,
2545 * HREF V1 has 0x0028
2546 */
2547 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2548
2549 /* PCell Id */
2550 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2551 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2552 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2553 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2554 };
2555 struct stedma40_platform_data *plat_data;
2556 struct clk *clk = NULL;
2557 void __iomem *virtbase = NULL;
2558 struct resource *res = NULL;
2559 struct d40_base *base = NULL;
2560 int num_log_chans = 0;
2561 int num_phy_chans;
2562 int i;
2563 u32 val;
2564 u32 rev;
2565
2566 clk = clk_get(&pdev->dev, NULL);
2567
2568 if (IS_ERR(clk)) {
2569 dev_err(&pdev->dev, "[%s] No matching clock found\n",
2570 __func__);
2571 goto failure;
2572 }
2573
2574 clk_enable(clk);
2575
2576 /* Get IO for DMAC base address */
2577 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2578 if (!res)
2579 goto failure;
2580
2581 if (request_mem_region(res->start, resource_size(res),
2582 D40_NAME " I/O base") == NULL)
2583 goto failure;
2584
2585 virtbase = ioremap(res->start, resource_size(res));
2586 if (!virtbase)
2587 goto failure;
2588
2589 /* HW version check */
2590 for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2591 if (dma_id_regs[i].val !=
2592 readl(virtbase + dma_id_regs[i].reg)) {
2593 dev_err(&pdev->dev,
2594 "[%s] Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2595 __func__,
2596 dma_id_regs[i].val,
2597 dma_id_regs[i].reg,
2598 readl(virtbase + dma_id_regs[i].reg));
2599 goto failure;
2600 }
2601 }
2602
2603 /* Get silicon revision and designer */
2604 val = readl(virtbase + D40_DREG_PERIPHID2);
2605
2606 if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
2607 D40_HW_DESIGNER) {
2608 dev_err(&pdev->dev,
2609 "[%s] Unknown designer! Got %x wanted %x\n",
2610 __func__, val & D40_DREG_PERIPHID2_DESIGNER_MASK,
2611 D40_HW_DESIGNER);
2612 goto failure;
2613 }
2614
2615 rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
2616 D40_DREG_PERIPHID2_REV_POS;
2617
2618 /* The number of physical channels on this HW */
2619 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2620
2621 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
2622 rev, res->start);
2623
2624 plat_data = pdev->dev.platform_data;
2625
2626 /* Count the number of logical channels in use */
2627 for (i = 0; i < plat_data->dev_len; i++)
2628 if (plat_data->dev_rx[i] != 0)
2629 num_log_chans++;
2630
2631 for (i = 0; i < plat_data->dev_len; i++)
2632 if (plat_data->dev_tx[i] != 0)
2633 num_log_chans++;
2634
2635 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2636 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2637 sizeof(struct d40_chan), GFP_KERNEL);
2638
2639 if (base == NULL) {
2640 dev_err(&pdev->dev, "[%s] Out of memory\n", __func__);
2641 goto failure;
2642 }
2643
2644 base->rev = rev;
2645 base->clk = clk;
2646 base->num_phy_chans = num_phy_chans;
2647 base->num_log_chans = num_log_chans;
2648 base->phy_start = res->start;
2649 base->phy_size = resource_size(res);
2650 base->virtbase = virtbase;
2651 base->plat_data = plat_data;
2652 base->dev = &pdev->dev;
2653 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2654 base->log_chans = &base->phy_chans[num_phy_chans];
2655
2656 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2657 GFP_KERNEL);
2658 if (!base->phy_res)
2659 goto failure;
2660
2661 base->lookup_phy_chans = kzalloc(num_phy_chans *
2662 sizeof(struct d40_chan *),
2663 GFP_KERNEL);
2664 if (!base->lookup_phy_chans)
2665 goto failure;
2666
2667 if (num_log_chans + plat_data->memcpy_len) {
2668 /*
2669 * The max number of logical channels are event lines for all
2670 * src devices and dst devices
2671 */
2672 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2673 sizeof(struct d40_chan *),
2674 GFP_KERNEL);
2675 if (!base->lookup_log_chans)
2676 goto failure;
2677 }
2678
2679 base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
2680 sizeof(struct d40_desc *) *
2681 D40_LCLA_LINK_PER_EVENT_GRP,
2682 GFP_KERNEL);
2683 if (!base->lcla_pool.alloc_map)
2684 goto failure;
2685
2686 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2687 0, SLAB_HWCACHE_ALIGN,
2688 NULL);
2689 if (base->desc_slab == NULL)
2690 goto failure;
2691
2692 return base;
2693
2694 failure:
2695 if (!IS_ERR(clk)) {
2696 clk_disable(clk);
2697 clk_put(clk);
2698 }
2699 if (virtbase)
2700 iounmap(virtbase);
2701 if (res)
2702 release_mem_region(res->start,
2703 resource_size(res));
2704 if (virtbase)
2705 iounmap(virtbase);
2706
2707 if (base) {
2708 kfree(base->lcla_pool.alloc_map);
2709 kfree(base->lookup_log_chans);
2710 kfree(base->lookup_phy_chans);
2711 kfree(base->phy_res);
2712 kfree(base);
2713 }
2714
2715 return NULL;
2716 }
2717
2718 static void __init d40_hw_init(struct d40_base *base)
2719 {
2720
2721 static const struct d40_reg_val dma_init_reg[] = {
2722 /* Clock every part of the DMA block from start */
2723 { .reg = D40_DREG_GCC, .val = 0x0000ff01},
2724
2725 /* Interrupts on all logical channels */
2726 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2727 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2728 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2729 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2730 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2731 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2732 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2733 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2734 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2735 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2736 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2737 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2738 };
2739 int i;
2740 u32 prmseo[2] = {0, 0};
2741 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2742 u32 pcmis = 0;
2743 u32 pcicr = 0;
2744
2745 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2746 writel(dma_init_reg[i].val,
2747 base->virtbase + dma_init_reg[i].reg);
2748
2749 /* Configure all our dma channels to default settings */
2750 for (i = 0; i < base->num_phy_chans; i++) {
2751
2752 activeo[i % 2] = activeo[i % 2] << 2;
2753
2754 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2755 == D40_ALLOC_PHY) {
2756 activeo[i % 2] |= 3;
2757 continue;
2758 }
2759
2760 /* Enable interrupt # */
2761 pcmis = (pcmis << 1) | 1;
2762
2763 /* Clear interrupt # */
2764 pcicr = (pcicr << 1) | 1;
2765
2766 /* Set channel to physical mode */
2767 prmseo[i % 2] = prmseo[i % 2] << 2;
2768 prmseo[i % 2] |= 1;
2769
2770 }
2771
2772 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2773 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2774 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2775 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2776
2777 /* Write which interrupt to enable */
2778 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2779
2780 /* Write which interrupt to clear */
2781 writel(pcicr, base->virtbase + D40_DREG_PCICR);
2782
2783 }
2784
2785 static int __init d40_lcla_allocate(struct d40_base *base)
2786 {
2787 unsigned long *page_list;
2788 int i, j;
2789 int ret = 0;
2790
2791 /*
2792 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2793 * To full fill this hardware requirement without wasting 256 kb
2794 * we allocate pages until we get an aligned one.
2795 */
2796 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2797 GFP_KERNEL);
2798
2799 if (!page_list) {
2800 ret = -ENOMEM;
2801 goto failure;
2802 }
2803
2804 /* Calculating how many pages that are required */
2805 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2806
2807 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2808 page_list[i] = __get_free_pages(GFP_KERNEL,
2809 base->lcla_pool.pages);
2810 if (!page_list[i]) {
2811
2812 dev_err(base->dev,
2813 "[%s] Failed to allocate %d pages.\n",
2814 __func__, base->lcla_pool.pages);
2815
2816 for (j = 0; j < i; j++)
2817 free_pages(page_list[j], base->lcla_pool.pages);
2818 goto failure;
2819 }
2820
2821 if ((virt_to_phys((void *)page_list[i]) &
2822 (LCLA_ALIGNMENT - 1)) == 0)
2823 break;
2824 }
2825
2826 for (j = 0; j < i; j++)
2827 free_pages(page_list[j], base->lcla_pool.pages);
2828
2829 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2830 base->lcla_pool.base = (void *)page_list[i];
2831 } else {
2832 /*
2833 * After many attempts and no succees with finding the correct
2834 * alignment, try with allocating a big buffer.
2835 */
2836 dev_warn(base->dev,
2837 "[%s] Failed to get %d pages @ 18 bit align.\n",
2838 __func__, base->lcla_pool.pages);
2839 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2840 base->num_phy_chans +
2841 LCLA_ALIGNMENT,
2842 GFP_KERNEL);
2843 if (!base->lcla_pool.base_unaligned) {
2844 ret = -ENOMEM;
2845 goto failure;
2846 }
2847
2848 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2849 LCLA_ALIGNMENT);
2850 }
2851
2852 writel(virt_to_phys(base->lcla_pool.base),
2853 base->virtbase + D40_DREG_LCLA);
2854 failure:
2855 kfree(page_list);
2856 return ret;
2857 }
2858
2859 static int __init d40_probe(struct platform_device *pdev)
2860 {
2861 int err;
2862 int ret = -ENOENT;
2863 struct d40_base *base;
2864 struct resource *res = NULL;
2865 int num_reserved_chans;
2866 u32 val;
2867
2868 base = d40_hw_detect_init(pdev);
2869
2870 if (!base)
2871 goto failure;
2872
2873 num_reserved_chans = d40_phy_res_init(base);
2874
2875 platform_set_drvdata(pdev, base);
2876
2877 spin_lock_init(&base->interrupt_lock);
2878 spin_lock_init(&base->execmd_lock);
2879
2880 /* Get IO for logical channel parameter address */
2881 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2882 if (!res) {
2883 ret = -ENOENT;
2884 dev_err(&pdev->dev,
2885 "[%s] No \"lcpa\" memory resource\n",
2886 __func__);
2887 goto failure;
2888 }
2889 base->lcpa_size = resource_size(res);
2890 base->phy_lcpa = res->start;
2891
2892 if (request_mem_region(res->start, resource_size(res),
2893 D40_NAME " I/O lcpa") == NULL) {
2894 ret = -EBUSY;
2895 dev_err(&pdev->dev,
2896 "[%s] Failed to request LCPA region 0x%x-0x%x\n",
2897 __func__, res->start, res->end);
2898 goto failure;
2899 }
2900
2901 /* We make use of ESRAM memory for this. */
2902 val = readl(base->virtbase + D40_DREG_LCPA);
2903 if (res->start != val && val != 0) {
2904 dev_warn(&pdev->dev,
2905 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2906 __func__, val, res->start);
2907 } else
2908 writel(res->start, base->virtbase + D40_DREG_LCPA);
2909
2910 base->lcpa_base = ioremap(res->start, resource_size(res));
2911 if (!base->lcpa_base) {
2912 ret = -ENOMEM;
2913 dev_err(&pdev->dev,
2914 "[%s] Failed to ioremap LCPA region\n",
2915 __func__);
2916 goto failure;
2917 }
2918
2919 ret = d40_lcla_allocate(base);
2920 if (ret) {
2921 dev_err(&pdev->dev, "[%s] Failed to allocate LCLA area\n",
2922 __func__);
2923 goto failure;
2924 }
2925
2926 spin_lock_init(&base->lcla_pool.lock);
2927
2928 base->irq = platform_get_irq(pdev, 0);
2929
2930 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
2931
2932 if (ret) {
2933 dev_err(&pdev->dev, "[%s] No IRQ defined\n", __func__);
2934 goto failure;
2935 }
2936
2937 err = d40_dmaengine_init(base, num_reserved_chans);
2938 if (err)
2939 goto failure;
2940
2941 d40_hw_init(base);
2942
2943 dev_info(base->dev, "initialized\n");
2944 return 0;
2945
2946 failure:
2947 if (base) {
2948 if (base->desc_slab)
2949 kmem_cache_destroy(base->desc_slab);
2950 if (base->virtbase)
2951 iounmap(base->virtbase);
2952 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2953 free_pages((unsigned long)base->lcla_pool.base,
2954 base->lcla_pool.pages);
2955
2956 kfree(base->lcla_pool.base_unaligned);
2957
2958 if (base->phy_lcpa)
2959 release_mem_region(base->phy_lcpa,
2960 base->lcpa_size);
2961 if (base->phy_start)
2962 release_mem_region(base->phy_start,
2963 base->phy_size);
2964 if (base->clk) {
2965 clk_disable(base->clk);
2966 clk_put(base->clk);
2967 }
2968
2969 kfree(base->lcla_pool.alloc_map);
2970 kfree(base->lookup_log_chans);
2971 kfree(base->lookup_phy_chans);
2972 kfree(base->phy_res);
2973 kfree(base);
2974 }
2975
2976 dev_err(&pdev->dev, "[%s] probe failed\n", __func__);
2977 return ret;
2978 }
2979
2980 static struct platform_driver d40_driver = {
2981 .driver = {
2982 .owner = THIS_MODULE,
2983 .name = D40_NAME,
2984 },
2985 };
2986
2987 static int __init stedma40_init(void)
2988 {
2989 return platform_driver_probe(&d40_driver, d40_probe);
2990 }
2991 arch_initcall(stedma40_init);
Linux kernel - Deliverables
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