2 * DMA driver for Nvidia's Tegra20 APB DMA controller.
4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/bitops.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
29 #include <linux/module.h>
31 #include <linux/of_device.h>
32 #include <linux/of_dma.h>
33 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/reset.h>
37 #include <linux/slab.h>
39 #include "dmaengine.h"
41 #define TEGRA_APBDMA_GENERAL 0x0
42 #define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
44 #define TEGRA_APBDMA_CONTROL 0x010
45 #define TEGRA_APBDMA_IRQ_MASK 0x01c
46 #define TEGRA_APBDMA_IRQ_MASK_SET 0x020
49 #define TEGRA_APBDMA_CHAN_CSR 0x00
50 #define TEGRA_APBDMA_CSR_ENB BIT(31)
51 #define TEGRA_APBDMA_CSR_IE_EOC BIT(30)
52 #define TEGRA_APBDMA_CSR_HOLD BIT(29)
53 #define TEGRA_APBDMA_CSR_DIR BIT(28)
54 #define TEGRA_APBDMA_CSR_ONCE BIT(27)
55 #define TEGRA_APBDMA_CSR_FLOW BIT(21)
56 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16
57 #define TEGRA_APBDMA_CSR_REQ_SEL_MASK 0x1F
58 #define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC
61 #define TEGRA_APBDMA_CHAN_STATUS 0x004
62 #define TEGRA_APBDMA_STATUS_BUSY BIT(31)
63 #define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30)
64 #define TEGRA_APBDMA_STATUS_HALT BIT(29)
65 #define TEGRA_APBDMA_STATUS_PING_PONG BIT(28)
66 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2
67 #define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC
69 #define TEGRA_APBDMA_CHAN_CSRE 0x00C
70 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31)
72 /* AHB memory address */
73 #define TEGRA_APBDMA_CHAN_AHBPTR 0x010
75 /* AHB sequence register */
76 #define TEGRA_APBDMA_CHAN_AHBSEQ 0x14
77 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31)
78 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28)
79 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28)
80 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28)
81 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28)
82 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)
83 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27)
84 #define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24)
85 #define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24)
86 #define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24)
87 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19)
88 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16
89 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE 0
92 #define TEGRA_APBDMA_CHAN_APBPTR 0x018
94 /* APB sequence register */
95 #define TEGRA_APBDMA_CHAN_APBSEQ 0x01c
96 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8 (0 << 28)
97 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28)
98 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28)
99 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64 (3 << 28)
100 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28)
101 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27)
102 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1 << 16)
104 /* Tegra148 specific registers */
105 #define TEGRA_APBDMA_CHAN_WCOUNT 0x20
107 #define TEGRA_APBDMA_CHAN_WORD_TRANSFER 0x24
110 * If any burst is in flight and DMA paused then this is the time to complete
111 * on-flight burst and update DMA status register.
113 #define TEGRA_APBDMA_BURST_COMPLETE_TIME 20
115 /* Channel base address offset from APBDMA base address */
116 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000
118 #define TEGRA_APBDMA_SLAVE_ID_INVALID (TEGRA_APBDMA_CSR_REQ_SEL_MASK + 1)
123 * tegra_dma_chip_data Tegra chip specific DMA data
124 * @nr_channels: Number of channels available in the controller.
125 * @channel_reg_size: Channel register size/stride.
126 * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
127 * @support_channel_pause: Support channel wise pause of dma.
128 * @support_separate_wcount_reg: Support separate word count register.
130 struct tegra_dma_chip_data
{
132 int channel_reg_size
;
134 bool support_channel_pause
;
135 bool support_separate_wcount_reg
;
138 /* DMA channel registers */
139 struct tegra_dma_channel_regs
{
141 unsigned long ahb_ptr
;
142 unsigned long apb_ptr
;
143 unsigned long ahb_seq
;
144 unsigned long apb_seq
;
145 unsigned long wcount
;
149 * tegra_dma_sg_req: Dma request details to configure hardware. This
150 * contains the details for one transfer to configure DMA hw.
151 * The client's request for data transfer can be broken into multiple
152 * sub-transfer as per requester details and hw support.
153 * This sub transfer get added in the list of transfer and point to Tegra
154 * DMA descriptor which manages the transfer details.
156 struct tegra_dma_sg_req
{
157 struct tegra_dma_channel_regs ch_regs
;
161 struct list_head node
;
162 struct tegra_dma_desc
*dma_desc
;
166 * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
167 * This descriptor keep track of transfer status, callbacks and request
170 struct tegra_dma_desc
{
171 struct dma_async_tx_descriptor txd
;
173 int bytes_transferred
;
174 enum dma_status dma_status
;
175 struct list_head node
;
176 struct list_head tx_list
;
177 struct list_head cb_node
;
181 struct tegra_dma_channel
;
183 typedef void (*dma_isr_handler
)(struct tegra_dma_channel
*tdc
,
186 /* tegra_dma_channel: Channel specific information */
187 struct tegra_dma_channel
{
188 struct dma_chan dma_chan
;
193 void __iomem
*chan_addr
;
196 struct tegra_dma
*tdma
;
199 /* Different lists for managing the requests */
200 struct list_head free_sg_req
;
201 struct list_head pending_sg_req
;
202 struct list_head free_dma_desc
;
203 struct list_head cb_desc
;
205 /* ISR handler and tasklet for bottom half of isr handling */
206 dma_isr_handler isr_handler
;
207 struct tasklet_struct tasklet
;
209 /* Channel-slave specific configuration */
210 unsigned int slave_id
;
211 struct dma_slave_config dma_sconfig
;
212 struct tegra_dma_channel_regs channel_reg
;
215 /* tegra_dma: Tegra DMA specific information */
217 struct dma_device dma_dev
;
220 struct reset_control
*rst
;
221 spinlock_t global_lock
;
222 void __iomem
*base_addr
;
223 const struct tegra_dma_chip_data
*chip_data
;
226 * Counter for managing global pausing of the DMA controller.
227 * Only applicable for devices that don't support individual
230 u32 global_pause_count
;
232 /* Some register need to be cache before suspend */
235 /* Last member of the structure */
236 struct tegra_dma_channel channels
[0];
239 static inline void tdma_write(struct tegra_dma
*tdma
, u32 reg
, u32 val
)
241 writel(val
, tdma
->base_addr
+ reg
);
244 static inline u32
tdma_read(struct tegra_dma
*tdma
, u32 reg
)
246 return readl(tdma
->base_addr
+ reg
);
249 static inline void tdc_write(struct tegra_dma_channel
*tdc
,
252 writel(val
, tdc
->chan_addr
+ reg
);
255 static inline u32
tdc_read(struct tegra_dma_channel
*tdc
, u32 reg
)
257 return readl(tdc
->chan_addr
+ reg
);
260 static inline struct tegra_dma_channel
*to_tegra_dma_chan(struct dma_chan
*dc
)
262 return container_of(dc
, struct tegra_dma_channel
, dma_chan
);
265 static inline struct tegra_dma_desc
*txd_to_tegra_dma_desc(
266 struct dma_async_tx_descriptor
*td
)
268 return container_of(td
, struct tegra_dma_desc
, txd
);
271 static inline struct device
*tdc2dev(struct tegra_dma_channel
*tdc
)
273 return &tdc
->dma_chan
.dev
->device
;
276 static dma_cookie_t
tegra_dma_tx_submit(struct dma_async_tx_descriptor
*tx
);
277 static int tegra_dma_runtime_suspend(struct device
*dev
);
278 static int tegra_dma_runtime_resume(struct device
*dev
);
280 /* Get DMA desc from free list, if not there then allocate it. */
281 static struct tegra_dma_desc
*tegra_dma_desc_get(
282 struct tegra_dma_channel
*tdc
)
284 struct tegra_dma_desc
*dma_desc
;
287 spin_lock_irqsave(&tdc
->lock
, flags
);
289 /* Do not allocate if desc are waiting for ack */
290 list_for_each_entry(dma_desc
, &tdc
->free_dma_desc
, node
) {
291 if (async_tx_test_ack(&dma_desc
->txd
)) {
292 list_del(&dma_desc
->node
);
293 spin_unlock_irqrestore(&tdc
->lock
, flags
);
294 dma_desc
->txd
.flags
= 0;
299 spin_unlock_irqrestore(&tdc
->lock
, flags
);
301 /* Allocate DMA desc */
302 dma_desc
= kzalloc(sizeof(*dma_desc
), GFP_NOWAIT
);
306 dma_async_tx_descriptor_init(&dma_desc
->txd
, &tdc
->dma_chan
);
307 dma_desc
->txd
.tx_submit
= tegra_dma_tx_submit
;
308 dma_desc
->txd
.flags
= 0;
312 static void tegra_dma_desc_put(struct tegra_dma_channel
*tdc
,
313 struct tegra_dma_desc
*dma_desc
)
317 spin_lock_irqsave(&tdc
->lock
, flags
);
318 if (!list_empty(&dma_desc
->tx_list
))
319 list_splice_init(&dma_desc
->tx_list
, &tdc
->free_sg_req
);
320 list_add_tail(&dma_desc
->node
, &tdc
->free_dma_desc
);
321 spin_unlock_irqrestore(&tdc
->lock
, flags
);
324 static struct tegra_dma_sg_req
*tegra_dma_sg_req_get(
325 struct tegra_dma_channel
*tdc
)
327 struct tegra_dma_sg_req
*sg_req
= NULL
;
330 spin_lock_irqsave(&tdc
->lock
, flags
);
331 if (!list_empty(&tdc
->free_sg_req
)) {
332 sg_req
= list_first_entry(&tdc
->free_sg_req
,
333 typeof(*sg_req
), node
);
334 list_del(&sg_req
->node
);
335 spin_unlock_irqrestore(&tdc
->lock
, flags
);
338 spin_unlock_irqrestore(&tdc
->lock
, flags
);
340 sg_req
= kzalloc(sizeof(struct tegra_dma_sg_req
), GFP_NOWAIT
);
345 static int tegra_dma_slave_config(struct dma_chan
*dc
,
346 struct dma_slave_config
*sconfig
)
348 struct tegra_dma_channel
*tdc
= to_tegra_dma_chan(dc
);
350 if (!list_empty(&tdc
->pending_sg_req
)) {
351 dev_err(tdc2dev(tdc
), "Configuration not allowed\n");
355 memcpy(&tdc
->dma_sconfig
, sconfig
, sizeof(*sconfig
));
356 if (tdc
->slave_id
== TEGRA_APBDMA_SLAVE_ID_INVALID
) {
357 if (sconfig
->slave_id
> TEGRA_APBDMA_CSR_REQ_SEL_MASK
)
359 tdc
->slave_id
= sconfig
->slave_id
;
361 tdc
->config_init
= true;
365 static void tegra_dma_global_pause(struct tegra_dma_channel
*tdc
,
366 bool wait_for_burst_complete
)
368 struct tegra_dma
*tdma
= tdc
->tdma
;
370 spin_lock(&tdma
->global_lock
);
372 if (tdc
->tdma
->global_pause_count
== 0) {
373 tdma_write(tdma
, TEGRA_APBDMA_GENERAL
, 0);
374 if (wait_for_burst_complete
)
375 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME
);
378 tdc
->tdma
->global_pause_count
++;
380 spin_unlock(&tdma
->global_lock
);
383 static void tegra_dma_global_resume(struct tegra_dma_channel
*tdc
)
385 struct tegra_dma
*tdma
= tdc
->tdma
;
387 spin_lock(&tdma
->global_lock
);
389 if (WARN_ON(tdc
->tdma
->global_pause_count
== 0))
392 if (--tdc
->tdma
->global_pause_count
== 0)
393 tdma_write(tdma
, TEGRA_APBDMA_GENERAL
,
394 TEGRA_APBDMA_GENERAL_ENABLE
);
397 spin_unlock(&tdma
->global_lock
);
400 static void tegra_dma_pause(struct tegra_dma_channel
*tdc
,
401 bool wait_for_burst_complete
)
403 struct tegra_dma
*tdma
= tdc
->tdma
;
405 if (tdma
->chip_data
->support_channel_pause
) {
406 tdc_write(tdc
, TEGRA_APBDMA_CHAN_CSRE
,
407 TEGRA_APBDMA_CHAN_CSRE_PAUSE
);
408 if (wait_for_burst_complete
)
409 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME
);
411 tegra_dma_global_pause(tdc
, wait_for_burst_complete
);
415 static void tegra_dma_resume(struct tegra_dma_channel
*tdc
)
417 struct tegra_dma
*tdma
= tdc
->tdma
;
419 if (tdma
->chip_data
->support_channel_pause
) {
420 tdc_write(tdc
, TEGRA_APBDMA_CHAN_CSRE
, 0);
422 tegra_dma_global_resume(tdc
);
426 static void tegra_dma_stop(struct tegra_dma_channel
*tdc
)
431 /* Disable interrupts */
432 csr
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_CSR
);
433 csr
&= ~TEGRA_APBDMA_CSR_IE_EOC
;
434 tdc_write(tdc
, TEGRA_APBDMA_CHAN_CSR
, csr
);
437 csr
&= ~TEGRA_APBDMA_CSR_ENB
;
438 tdc_write(tdc
, TEGRA_APBDMA_CHAN_CSR
, csr
);
440 /* Clear interrupt status if it is there */
441 status
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_STATUS
);
442 if (status
& TEGRA_APBDMA_STATUS_ISE_EOC
) {
443 dev_dbg(tdc2dev(tdc
), "%s():clearing interrupt\n", __func__
);
444 tdc_write(tdc
, TEGRA_APBDMA_CHAN_STATUS
, status
);
449 static void tegra_dma_start(struct tegra_dma_channel
*tdc
,
450 struct tegra_dma_sg_req
*sg_req
)
452 struct tegra_dma_channel_regs
*ch_regs
= &sg_req
->ch_regs
;
454 tdc_write(tdc
, TEGRA_APBDMA_CHAN_CSR
, ch_regs
->csr
);
455 tdc_write(tdc
, TEGRA_APBDMA_CHAN_APBSEQ
, ch_regs
->apb_seq
);
456 tdc_write(tdc
, TEGRA_APBDMA_CHAN_APBPTR
, ch_regs
->apb_ptr
);
457 tdc_write(tdc
, TEGRA_APBDMA_CHAN_AHBSEQ
, ch_regs
->ahb_seq
);
458 tdc_write(tdc
, TEGRA_APBDMA_CHAN_AHBPTR
, ch_regs
->ahb_ptr
);
459 if (tdc
->tdma
->chip_data
->support_separate_wcount_reg
)
460 tdc_write(tdc
, TEGRA_APBDMA_CHAN_WCOUNT
, ch_regs
->wcount
);
463 tdc_write(tdc
, TEGRA_APBDMA_CHAN_CSR
,
464 ch_regs
->csr
| TEGRA_APBDMA_CSR_ENB
);
467 static void tegra_dma_configure_for_next(struct tegra_dma_channel
*tdc
,
468 struct tegra_dma_sg_req
*nsg_req
)
470 unsigned long status
;
473 * The DMA controller reloads the new configuration for next transfer
474 * after last burst of current transfer completes.
475 * If there is no IEC status then this makes sure that last burst
476 * has not be completed. There may be case that last burst is on
477 * flight and so it can complete but because DMA is paused, it
478 * will not generates interrupt as well as not reload the new
480 * If there is already IEC status then interrupt handler need to
481 * load new configuration.
483 tegra_dma_pause(tdc
, false);
484 status
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_STATUS
);
487 * If interrupt is pending then do nothing as the ISR will handle
488 * the programing for new request.
490 if (status
& TEGRA_APBDMA_STATUS_ISE_EOC
) {
491 dev_err(tdc2dev(tdc
),
492 "Skipping new configuration as interrupt is pending\n");
493 tegra_dma_resume(tdc
);
497 /* Safe to program new configuration */
498 tdc_write(tdc
, TEGRA_APBDMA_CHAN_APBPTR
, nsg_req
->ch_regs
.apb_ptr
);
499 tdc_write(tdc
, TEGRA_APBDMA_CHAN_AHBPTR
, nsg_req
->ch_regs
.ahb_ptr
);
500 if (tdc
->tdma
->chip_data
->support_separate_wcount_reg
)
501 tdc_write(tdc
, TEGRA_APBDMA_CHAN_WCOUNT
,
502 nsg_req
->ch_regs
.wcount
);
503 tdc_write(tdc
, TEGRA_APBDMA_CHAN_CSR
,
504 nsg_req
->ch_regs
.csr
| TEGRA_APBDMA_CSR_ENB
);
505 nsg_req
->configured
= true;
507 tegra_dma_resume(tdc
);
510 static void tdc_start_head_req(struct tegra_dma_channel
*tdc
)
512 struct tegra_dma_sg_req
*sg_req
;
514 if (list_empty(&tdc
->pending_sg_req
))
517 sg_req
= list_first_entry(&tdc
->pending_sg_req
,
518 typeof(*sg_req
), node
);
519 tegra_dma_start(tdc
, sg_req
);
520 sg_req
->configured
= true;
524 static void tdc_configure_next_head_desc(struct tegra_dma_channel
*tdc
)
526 struct tegra_dma_sg_req
*hsgreq
;
527 struct tegra_dma_sg_req
*hnsgreq
;
529 if (list_empty(&tdc
->pending_sg_req
))
532 hsgreq
= list_first_entry(&tdc
->pending_sg_req
, typeof(*hsgreq
), node
);
533 if (!list_is_last(&hsgreq
->node
, &tdc
->pending_sg_req
)) {
534 hnsgreq
= list_first_entry(&hsgreq
->node
,
535 typeof(*hnsgreq
), node
);
536 tegra_dma_configure_for_next(tdc
, hnsgreq
);
540 static inline int get_current_xferred_count(struct tegra_dma_channel
*tdc
,
541 struct tegra_dma_sg_req
*sg_req
, unsigned long status
)
543 return sg_req
->req_len
- (status
& TEGRA_APBDMA_STATUS_COUNT_MASK
) - 4;
546 static void tegra_dma_abort_all(struct tegra_dma_channel
*tdc
)
548 struct tegra_dma_sg_req
*sgreq
;
549 struct tegra_dma_desc
*dma_desc
;
551 while (!list_empty(&tdc
->pending_sg_req
)) {
552 sgreq
= list_first_entry(&tdc
->pending_sg_req
,
553 typeof(*sgreq
), node
);
554 list_move_tail(&sgreq
->node
, &tdc
->free_sg_req
);
555 if (sgreq
->last_sg
) {
556 dma_desc
= sgreq
->dma_desc
;
557 dma_desc
->dma_status
= DMA_ERROR
;
558 list_add_tail(&dma_desc
->node
, &tdc
->free_dma_desc
);
560 /* Add in cb list if it is not there. */
561 if (!dma_desc
->cb_count
)
562 list_add_tail(&dma_desc
->cb_node
,
564 dma_desc
->cb_count
++;
567 tdc
->isr_handler
= NULL
;
570 static bool handle_continuous_head_request(struct tegra_dma_channel
*tdc
,
571 struct tegra_dma_sg_req
*last_sg_req
, bool to_terminate
)
573 struct tegra_dma_sg_req
*hsgreq
= NULL
;
575 if (list_empty(&tdc
->pending_sg_req
)) {
576 dev_err(tdc2dev(tdc
), "Dma is running without req\n");
582 * Check that head req on list should be in flight.
583 * If it is not in flight then abort transfer as
584 * looping of transfer can not continue.
586 hsgreq
= list_first_entry(&tdc
->pending_sg_req
, typeof(*hsgreq
), node
);
587 if (!hsgreq
->configured
) {
589 dev_err(tdc2dev(tdc
), "Error in dma transfer, aborting dma\n");
590 tegra_dma_abort_all(tdc
);
594 /* Configure next request */
596 tdc_configure_next_head_desc(tdc
);
600 static void handle_once_dma_done(struct tegra_dma_channel
*tdc
,
603 struct tegra_dma_sg_req
*sgreq
;
604 struct tegra_dma_desc
*dma_desc
;
607 sgreq
= list_first_entry(&tdc
->pending_sg_req
, typeof(*sgreq
), node
);
608 dma_desc
= sgreq
->dma_desc
;
609 dma_desc
->bytes_transferred
+= sgreq
->req_len
;
611 list_del(&sgreq
->node
);
612 if (sgreq
->last_sg
) {
613 dma_desc
->dma_status
= DMA_COMPLETE
;
614 dma_cookie_complete(&dma_desc
->txd
);
615 if (!dma_desc
->cb_count
)
616 list_add_tail(&dma_desc
->cb_node
, &tdc
->cb_desc
);
617 dma_desc
->cb_count
++;
618 list_add_tail(&dma_desc
->node
, &tdc
->free_dma_desc
);
620 list_add_tail(&sgreq
->node
, &tdc
->free_sg_req
);
622 /* Do not start DMA if it is going to be terminate */
623 if (to_terminate
|| list_empty(&tdc
->pending_sg_req
))
626 tdc_start_head_req(tdc
);
629 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel
*tdc
,
632 struct tegra_dma_sg_req
*sgreq
;
633 struct tegra_dma_desc
*dma_desc
;
636 sgreq
= list_first_entry(&tdc
->pending_sg_req
, typeof(*sgreq
), node
);
637 dma_desc
= sgreq
->dma_desc
;
638 dma_desc
->bytes_transferred
+= sgreq
->req_len
;
640 /* Callback need to be call */
641 if (!dma_desc
->cb_count
)
642 list_add_tail(&dma_desc
->cb_node
, &tdc
->cb_desc
);
643 dma_desc
->cb_count
++;
645 /* If not last req then put at end of pending list */
646 if (!list_is_last(&sgreq
->node
, &tdc
->pending_sg_req
)) {
647 list_move_tail(&sgreq
->node
, &tdc
->pending_sg_req
);
648 sgreq
->configured
= false;
649 st
= handle_continuous_head_request(tdc
, sgreq
, to_terminate
);
651 dma_desc
->dma_status
= DMA_ERROR
;
655 static void tegra_dma_tasklet(unsigned long data
)
657 struct tegra_dma_channel
*tdc
= (struct tegra_dma_channel
*)data
;
658 dma_async_tx_callback callback
= NULL
;
659 void *callback_param
= NULL
;
660 struct tegra_dma_desc
*dma_desc
;
664 spin_lock_irqsave(&tdc
->lock
, flags
);
665 while (!list_empty(&tdc
->cb_desc
)) {
666 dma_desc
= list_first_entry(&tdc
->cb_desc
,
667 typeof(*dma_desc
), cb_node
);
668 list_del(&dma_desc
->cb_node
);
669 callback
= dma_desc
->txd
.callback
;
670 callback_param
= dma_desc
->txd
.callback_param
;
671 cb_count
= dma_desc
->cb_count
;
672 dma_desc
->cb_count
= 0;
673 spin_unlock_irqrestore(&tdc
->lock
, flags
);
674 while (cb_count
-- && callback
)
675 callback(callback_param
);
676 spin_lock_irqsave(&tdc
->lock
, flags
);
678 spin_unlock_irqrestore(&tdc
->lock
, flags
);
681 static irqreturn_t
tegra_dma_isr(int irq
, void *dev_id
)
683 struct tegra_dma_channel
*tdc
= dev_id
;
684 unsigned long status
;
687 spin_lock_irqsave(&tdc
->lock
, flags
);
689 status
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_STATUS
);
690 if (status
& TEGRA_APBDMA_STATUS_ISE_EOC
) {
691 tdc_write(tdc
, TEGRA_APBDMA_CHAN_STATUS
, status
);
692 tdc
->isr_handler(tdc
, false);
693 tasklet_schedule(&tdc
->tasklet
);
694 spin_unlock_irqrestore(&tdc
->lock
, flags
);
698 spin_unlock_irqrestore(&tdc
->lock
, flags
);
699 dev_info(tdc2dev(tdc
),
700 "Interrupt already served status 0x%08lx\n", status
);
704 static dma_cookie_t
tegra_dma_tx_submit(struct dma_async_tx_descriptor
*txd
)
706 struct tegra_dma_desc
*dma_desc
= txd_to_tegra_dma_desc(txd
);
707 struct tegra_dma_channel
*tdc
= to_tegra_dma_chan(txd
->chan
);
711 spin_lock_irqsave(&tdc
->lock
, flags
);
712 dma_desc
->dma_status
= DMA_IN_PROGRESS
;
713 cookie
= dma_cookie_assign(&dma_desc
->txd
);
714 list_splice_tail_init(&dma_desc
->tx_list
, &tdc
->pending_sg_req
);
715 spin_unlock_irqrestore(&tdc
->lock
, flags
);
719 static void tegra_dma_issue_pending(struct dma_chan
*dc
)
721 struct tegra_dma_channel
*tdc
= to_tegra_dma_chan(dc
);
724 spin_lock_irqsave(&tdc
->lock
, flags
);
725 if (list_empty(&tdc
->pending_sg_req
)) {
726 dev_err(tdc2dev(tdc
), "No DMA request\n");
730 tdc_start_head_req(tdc
);
732 /* Continuous single mode: Configure next req */
735 * Wait for 1 burst time for configure DMA for
738 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME
);
739 tdc_configure_next_head_desc(tdc
);
743 spin_unlock_irqrestore(&tdc
->lock
, flags
);
746 static int tegra_dma_terminate_all(struct dma_chan
*dc
)
748 struct tegra_dma_channel
*tdc
= to_tegra_dma_chan(dc
);
749 struct tegra_dma_sg_req
*sgreq
;
750 struct tegra_dma_desc
*dma_desc
;
752 unsigned long status
;
753 unsigned long wcount
;
756 spin_lock_irqsave(&tdc
->lock
, flags
);
757 if (list_empty(&tdc
->pending_sg_req
)) {
758 spin_unlock_irqrestore(&tdc
->lock
, flags
);
765 /* Pause DMA before checking the queue status */
766 tegra_dma_pause(tdc
, true);
768 status
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_STATUS
);
769 if (status
& TEGRA_APBDMA_STATUS_ISE_EOC
) {
770 dev_dbg(tdc2dev(tdc
), "%s():handling isr\n", __func__
);
771 tdc
->isr_handler(tdc
, true);
772 status
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_STATUS
);
774 if (tdc
->tdma
->chip_data
->support_separate_wcount_reg
)
775 wcount
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_WORD_TRANSFER
);
779 was_busy
= tdc
->busy
;
782 if (!list_empty(&tdc
->pending_sg_req
) && was_busy
) {
783 sgreq
= list_first_entry(&tdc
->pending_sg_req
,
784 typeof(*sgreq
), node
);
785 sgreq
->dma_desc
->bytes_transferred
+=
786 get_current_xferred_count(tdc
, sgreq
, wcount
);
788 tegra_dma_resume(tdc
);
791 tegra_dma_abort_all(tdc
);
793 while (!list_empty(&tdc
->cb_desc
)) {
794 dma_desc
= list_first_entry(&tdc
->cb_desc
,
795 typeof(*dma_desc
), cb_node
);
796 list_del(&dma_desc
->cb_node
);
797 dma_desc
->cb_count
= 0;
799 spin_unlock_irqrestore(&tdc
->lock
, flags
);
803 static enum dma_status
tegra_dma_tx_status(struct dma_chan
*dc
,
804 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
806 struct tegra_dma_channel
*tdc
= to_tegra_dma_chan(dc
);
807 struct tegra_dma_desc
*dma_desc
;
808 struct tegra_dma_sg_req
*sg_req
;
811 unsigned int residual
;
813 ret
= dma_cookie_status(dc
, cookie
, txstate
);
814 if (ret
== DMA_COMPLETE
)
817 spin_lock_irqsave(&tdc
->lock
, flags
);
819 /* Check on wait_ack desc status */
820 list_for_each_entry(dma_desc
, &tdc
->free_dma_desc
, node
) {
821 if (dma_desc
->txd
.cookie
== cookie
) {
822 ret
= dma_desc
->dma_status
;
827 /* Check in pending list */
828 list_for_each_entry(sg_req
, &tdc
->pending_sg_req
, node
) {
829 dma_desc
= sg_req
->dma_desc
;
830 if (dma_desc
->txd
.cookie
== cookie
) {
831 ret
= dma_desc
->dma_status
;
836 dev_dbg(tdc2dev(tdc
), "cookie %d not found\n", cookie
);
840 if (dma_desc
&& txstate
) {
841 residual
= dma_desc
->bytes_requested
-
842 (dma_desc
->bytes_transferred
%
843 dma_desc
->bytes_requested
);
844 dma_set_residue(txstate
, residual
);
847 spin_unlock_irqrestore(&tdc
->lock
, flags
);
851 static inline int get_bus_width(struct tegra_dma_channel
*tdc
,
852 enum dma_slave_buswidth slave_bw
)
855 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
856 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8
;
857 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
858 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16
;
859 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
860 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32
;
861 case DMA_SLAVE_BUSWIDTH_8_BYTES
:
862 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64
;
864 dev_warn(tdc2dev(tdc
),
865 "slave bw is not supported, using 32bits\n");
866 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32
;
870 static inline int get_burst_size(struct tegra_dma_channel
*tdc
,
871 u32 burst_size
, enum dma_slave_buswidth slave_bw
, int len
)
877 * burst_size from client is in terms of the bus_width.
878 * convert them into AHB memory width which is 4 byte.
880 burst_byte
= burst_size
* slave_bw
;
881 burst_ahb_width
= burst_byte
/ 4;
883 /* If burst size is 0 then calculate the burst size based on length */
884 if (!burst_ahb_width
) {
886 return TEGRA_APBDMA_AHBSEQ_BURST_1
;
887 else if ((len
>> 4) & 0x1)
888 return TEGRA_APBDMA_AHBSEQ_BURST_4
;
890 return TEGRA_APBDMA_AHBSEQ_BURST_8
;
892 if (burst_ahb_width
< 4)
893 return TEGRA_APBDMA_AHBSEQ_BURST_1
;
894 else if (burst_ahb_width
< 8)
895 return TEGRA_APBDMA_AHBSEQ_BURST_4
;
897 return TEGRA_APBDMA_AHBSEQ_BURST_8
;
900 static int get_transfer_param(struct tegra_dma_channel
*tdc
,
901 enum dma_transfer_direction direction
, unsigned long *apb_addr
,
902 unsigned long *apb_seq
, unsigned long *csr
, unsigned int *burst_size
,
903 enum dma_slave_buswidth
*slave_bw
)
907 *apb_addr
= tdc
->dma_sconfig
.dst_addr
;
908 *apb_seq
= get_bus_width(tdc
, tdc
->dma_sconfig
.dst_addr_width
);
909 *burst_size
= tdc
->dma_sconfig
.dst_maxburst
;
910 *slave_bw
= tdc
->dma_sconfig
.dst_addr_width
;
911 *csr
= TEGRA_APBDMA_CSR_DIR
;
915 *apb_addr
= tdc
->dma_sconfig
.src_addr
;
916 *apb_seq
= get_bus_width(tdc
, tdc
->dma_sconfig
.src_addr_width
);
917 *burst_size
= tdc
->dma_sconfig
.src_maxburst
;
918 *slave_bw
= tdc
->dma_sconfig
.src_addr_width
;
923 dev_err(tdc2dev(tdc
), "Dma direction is not supported\n");
929 static void tegra_dma_prep_wcount(struct tegra_dma_channel
*tdc
,
930 struct tegra_dma_channel_regs
*ch_regs
, u32 len
)
932 u32 len_field
= (len
- 4) & 0xFFFC;
934 if (tdc
->tdma
->chip_data
->support_separate_wcount_reg
)
935 ch_regs
->wcount
= len_field
;
937 ch_regs
->csr
|= len_field
;
940 static struct dma_async_tx_descriptor
*tegra_dma_prep_slave_sg(
941 struct dma_chan
*dc
, struct scatterlist
*sgl
, unsigned int sg_len
,
942 enum dma_transfer_direction direction
, unsigned long flags
,
945 struct tegra_dma_channel
*tdc
= to_tegra_dma_chan(dc
);
946 struct tegra_dma_desc
*dma_desc
;
948 struct scatterlist
*sg
;
949 unsigned long csr
, ahb_seq
, apb_ptr
, apb_seq
;
950 struct list_head req_list
;
951 struct tegra_dma_sg_req
*sg_req
= NULL
;
953 enum dma_slave_buswidth slave_bw
;
955 if (!tdc
->config_init
) {
956 dev_err(tdc2dev(tdc
), "dma channel is not configured\n");
960 dev_err(tdc2dev(tdc
), "Invalid segment length %d\n", sg_len
);
964 if (get_transfer_param(tdc
, direction
, &apb_ptr
, &apb_seq
, &csr
,
965 &burst_size
, &slave_bw
) < 0)
968 INIT_LIST_HEAD(&req_list
);
970 ahb_seq
= TEGRA_APBDMA_AHBSEQ_INTR_ENB
;
971 ahb_seq
|= TEGRA_APBDMA_AHBSEQ_WRAP_NONE
<<
972 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT
;
973 ahb_seq
|= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32
;
975 csr
|= TEGRA_APBDMA_CSR_ONCE
| TEGRA_APBDMA_CSR_FLOW
;
976 csr
|= tdc
->slave_id
<< TEGRA_APBDMA_CSR_REQ_SEL_SHIFT
;
977 if (flags
& DMA_PREP_INTERRUPT
)
978 csr
|= TEGRA_APBDMA_CSR_IE_EOC
;
980 apb_seq
|= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1
;
982 dma_desc
= tegra_dma_desc_get(tdc
);
984 dev_err(tdc2dev(tdc
), "Dma descriptors not available\n");
987 INIT_LIST_HEAD(&dma_desc
->tx_list
);
988 INIT_LIST_HEAD(&dma_desc
->cb_node
);
989 dma_desc
->cb_count
= 0;
990 dma_desc
->bytes_requested
= 0;
991 dma_desc
->bytes_transferred
= 0;
992 dma_desc
->dma_status
= DMA_IN_PROGRESS
;
994 /* Make transfer requests */
995 for_each_sg(sgl
, sg
, sg_len
, i
) {
998 mem
= sg_dma_address(sg
);
999 len
= sg_dma_len(sg
);
1001 if ((len
& 3) || (mem
& 3) ||
1002 (len
> tdc
->tdma
->chip_data
->max_dma_count
)) {
1003 dev_err(tdc2dev(tdc
),
1004 "Dma length/memory address is not supported\n");
1005 tegra_dma_desc_put(tdc
, dma_desc
);
1009 sg_req
= tegra_dma_sg_req_get(tdc
);
1011 dev_err(tdc2dev(tdc
), "Dma sg-req not available\n");
1012 tegra_dma_desc_put(tdc
, dma_desc
);
1016 ahb_seq
|= get_burst_size(tdc
, burst_size
, slave_bw
, len
);
1017 dma_desc
->bytes_requested
+= len
;
1019 sg_req
->ch_regs
.apb_ptr
= apb_ptr
;
1020 sg_req
->ch_regs
.ahb_ptr
= mem
;
1021 sg_req
->ch_regs
.csr
= csr
;
1022 tegra_dma_prep_wcount(tdc
, &sg_req
->ch_regs
, len
);
1023 sg_req
->ch_regs
.apb_seq
= apb_seq
;
1024 sg_req
->ch_regs
.ahb_seq
= ahb_seq
;
1025 sg_req
->configured
= false;
1026 sg_req
->last_sg
= false;
1027 sg_req
->dma_desc
= dma_desc
;
1028 sg_req
->req_len
= len
;
1030 list_add_tail(&sg_req
->node
, &dma_desc
->tx_list
);
1032 sg_req
->last_sg
= true;
1033 if (flags
& DMA_CTRL_ACK
)
1034 dma_desc
->txd
.flags
= DMA_CTRL_ACK
;
1037 * Make sure that mode should not be conflicting with currently
1040 if (!tdc
->isr_handler
) {
1041 tdc
->isr_handler
= handle_once_dma_done
;
1042 tdc
->cyclic
= false;
1045 dev_err(tdc2dev(tdc
), "DMA configured in cyclic mode\n");
1046 tegra_dma_desc_put(tdc
, dma_desc
);
1051 return &dma_desc
->txd
;
1054 static struct dma_async_tx_descriptor
*tegra_dma_prep_dma_cyclic(
1055 struct dma_chan
*dc
, dma_addr_t buf_addr
, size_t buf_len
,
1056 size_t period_len
, enum dma_transfer_direction direction
,
1057 unsigned long flags
)
1059 struct tegra_dma_channel
*tdc
= to_tegra_dma_chan(dc
);
1060 struct tegra_dma_desc
*dma_desc
= NULL
;
1061 struct tegra_dma_sg_req
*sg_req
= NULL
;
1062 unsigned long csr
, ahb_seq
, apb_ptr
, apb_seq
;
1065 dma_addr_t mem
= buf_addr
;
1067 enum dma_slave_buswidth slave_bw
;
1069 if (!buf_len
|| !period_len
) {
1070 dev_err(tdc2dev(tdc
), "Invalid buffer/period len\n");
1074 if (!tdc
->config_init
) {
1075 dev_err(tdc2dev(tdc
), "DMA slave is not configured\n");
1080 * We allow to take more number of requests till DMA is
1081 * not started. The driver will loop over all requests.
1082 * Once DMA is started then new requests can be queued only after
1083 * terminating the DMA.
1086 dev_err(tdc2dev(tdc
), "Request not allowed when dma running\n");
1091 * We only support cycle transfer when buf_len is multiple of
1094 if (buf_len
% period_len
) {
1095 dev_err(tdc2dev(tdc
), "buf_len is not multiple of period_len\n");
1100 if ((len
& 3) || (buf_addr
& 3) ||
1101 (len
> tdc
->tdma
->chip_data
->max_dma_count
)) {
1102 dev_err(tdc2dev(tdc
), "Req len/mem address is not correct\n");
1106 if (get_transfer_param(tdc
, direction
, &apb_ptr
, &apb_seq
, &csr
,
1107 &burst_size
, &slave_bw
) < 0)
1110 ahb_seq
= TEGRA_APBDMA_AHBSEQ_INTR_ENB
;
1111 ahb_seq
|= TEGRA_APBDMA_AHBSEQ_WRAP_NONE
<<
1112 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT
;
1113 ahb_seq
|= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32
;
1115 csr
|= TEGRA_APBDMA_CSR_FLOW
;
1116 if (flags
& DMA_PREP_INTERRUPT
)
1117 csr
|= TEGRA_APBDMA_CSR_IE_EOC
;
1118 csr
|= tdc
->slave_id
<< TEGRA_APBDMA_CSR_REQ_SEL_SHIFT
;
1120 apb_seq
|= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1
;
1122 dma_desc
= tegra_dma_desc_get(tdc
);
1124 dev_err(tdc2dev(tdc
), "not enough descriptors available\n");
1128 INIT_LIST_HEAD(&dma_desc
->tx_list
);
1129 INIT_LIST_HEAD(&dma_desc
->cb_node
);
1130 dma_desc
->cb_count
= 0;
1132 dma_desc
->bytes_transferred
= 0;
1133 dma_desc
->bytes_requested
= buf_len
;
1134 remain_len
= buf_len
;
1136 /* Split transfer equal to period size */
1137 while (remain_len
) {
1138 sg_req
= tegra_dma_sg_req_get(tdc
);
1140 dev_err(tdc2dev(tdc
), "Dma sg-req not available\n");
1141 tegra_dma_desc_put(tdc
, dma_desc
);
1145 ahb_seq
|= get_burst_size(tdc
, burst_size
, slave_bw
, len
);
1146 sg_req
->ch_regs
.apb_ptr
= apb_ptr
;
1147 sg_req
->ch_regs
.ahb_ptr
= mem
;
1148 sg_req
->ch_regs
.csr
= csr
;
1149 tegra_dma_prep_wcount(tdc
, &sg_req
->ch_regs
, len
);
1150 sg_req
->ch_regs
.apb_seq
= apb_seq
;
1151 sg_req
->ch_regs
.ahb_seq
= ahb_seq
;
1152 sg_req
->configured
= false;
1153 sg_req
->last_sg
= false;
1154 sg_req
->dma_desc
= dma_desc
;
1155 sg_req
->req_len
= len
;
1157 list_add_tail(&sg_req
->node
, &dma_desc
->tx_list
);
1161 sg_req
->last_sg
= true;
1162 if (flags
& DMA_CTRL_ACK
)
1163 dma_desc
->txd
.flags
= DMA_CTRL_ACK
;
1166 * Make sure that mode should not be conflicting with currently
1169 if (!tdc
->isr_handler
) {
1170 tdc
->isr_handler
= handle_cont_sngl_cycle_dma_done
;
1174 dev_err(tdc2dev(tdc
), "DMA configuration conflict\n");
1175 tegra_dma_desc_put(tdc
, dma_desc
);
1180 return &dma_desc
->txd
;
1183 static int tegra_dma_alloc_chan_resources(struct dma_chan
*dc
)
1185 struct tegra_dma_channel
*tdc
= to_tegra_dma_chan(dc
);
1186 struct tegra_dma
*tdma
= tdc
->tdma
;
1189 dma_cookie_init(&tdc
->dma_chan
);
1190 tdc
->config_init
= false;
1192 ret
= pm_runtime_get_sync(tdma
->dev
);
1199 static void tegra_dma_free_chan_resources(struct dma_chan
*dc
)
1201 struct tegra_dma_channel
*tdc
= to_tegra_dma_chan(dc
);
1202 struct tegra_dma
*tdma
= tdc
->tdma
;
1203 struct tegra_dma_desc
*dma_desc
;
1204 struct tegra_dma_sg_req
*sg_req
;
1205 struct list_head dma_desc_list
;
1206 struct list_head sg_req_list
;
1207 unsigned long flags
;
1209 INIT_LIST_HEAD(&dma_desc_list
);
1210 INIT_LIST_HEAD(&sg_req_list
);
1212 dev_dbg(tdc2dev(tdc
), "Freeing channel %d\n", tdc
->id
);
1215 tegra_dma_terminate_all(dc
);
1217 spin_lock_irqsave(&tdc
->lock
, flags
);
1218 list_splice_init(&tdc
->pending_sg_req
, &sg_req_list
);
1219 list_splice_init(&tdc
->free_sg_req
, &sg_req_list
);
1220 list_splice_init(&tdc
->free_dma_desc
, &dma_desc_list
);
1221 INIT_LIST_HEAD(&tdc
->cb_desc
);
1222 tdc
->config_init
= false;
1223 tdc
->isr_handler
= NULL
;
1224 spin_unlock_irqrestore(&tdc
->lock
, flags
);
1226 while (!list_empty(&dma_desc_list
)) {
1227 dma_desc
= list_first_entry(&dma_desc_list
,
1228 typeof(*dma_desc
), node
);
1229 list_del(&dma_desc
->node
);
1233 while (!list_empty(&sg_req_list
)) {
1234 sg_req
= list_first_entry(&sg_req_list
, typeof(*sg_req
), node
);
1235 list_del(&sg_req
->node
);
1238 pm_runtime_put(tdma
->dev
);
1240 tdc
->slave_id
= TEGRA_APBDMA_SLAVE_ID_INVALID
;
1243 static struct dma_chan
*tegra_dma_of_xlate(struct of_phandle_args
*dma_spec
,
1244 struct of_dma
*ofdma
)
1246 struct tegra_dma
*tdma
= ofdma
->of_dma_data
;
1247 struct dma_chan
*chan
;
1248 struct tegra_dma_channel
*tdc
;
1250 if (dma_spec
->args
[0] > TEGRA_APBDMA_CSR_REQ_SEL_MASK
) {
1251 dev_err(tdma
->dev
, "Invalid slave id: %d\n", dma_spec
->args
[0]);
1255 chan
= dma_get_any_slave_channel(&tdma
->dma_dev
);
1259 tdc
= to_tegra_dma_chan(chan
);
1260 tdc
->slave_id
= dma_spec
->args
[0];
1265 /* Tegra20 specific DMA controller information */
1266 static const struct tegra_dma_chip_data tegra20_dma_chip_data
= {
1268 .channel_reg_size
= 0x20,
1269 .max_dma_count
= 1024UL * 64,
1270 .support_channel_pause
= false,
1271 .support_separate_wcount_reg
= false,
1274 /* Tegra30 specific DMA controller information */
1275 static const struct tegra_dma_chip_data tegra30_dma_chip_data
= {
1277 .channel_reg_size
= 0x20,
1278 .max_dma_count
= 1024UL * 64,
1279 .support_channel_pause
= false,
1280 .support_separate_wcount_reg
= false,
1283 /* Tegra114 specific DMA controller information */
1284 static const struct tegra_dma_chip_data tegra114_dma_chip_data
= {
1286 .channel_reg_size
= 0x20,
1287 .max_dma_count
= 1024UL * 64,
1288 .support_channel_pause
= true,
1289 .support_separate_wcount_reg
= false,
1292 /* Tegra148 specific DMA controller information */
1293 static const struct tegra_dma_chip_data tegra148_dma_chip_data
= {
1295 .channel_reg_size
= 0x40,
1296 .max_dma_count
= 1024UL * 64,
1297 .support_channel_pause
= true,
1298 .support_separate_wcount_reg
= true,
1301 static int tegra_dma_probe(struct platform_device
*pdev
)
1303 struct resource
*res
;
1304 struct tegra_dma
*tdma
;
1307 const struct tegra_dma_chip_data
*cdata
;
1309 cdata
= of_device_get_match_data(&pdev
->dev
);
1311 dev_err(&pdev
->dev
, "Error: No device match data found\n");
1315 tdma
= devm_kzalloc(&pdev
->dev
, sizeof(*tdma
) + cdata
->nr_channels
*
1316 sizeof(struct tegra_dma_channel
), GFP_KERNEL
);
1320 tdma
->dev
= &pdev
->dev
;
1321 tdma
->chip_data
= cdata
;
1322 platform_set_drvdata(pdev
, tdma
);
1324 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1325 tdma
->base_addr
= devm_ioremap_resource(&pdev
->dev
, res
);
1326 if (IS_ERR(tdma
->base_addr
))
1327 return PTR_ERR(tdma
->base_addr
);
1329 tdma
->dma_clk
= devm_clk_get(&pdev
->dev
, NULL
);
1330 if (IS_ERR(tdma
->dma_clk
)) {
1331 dev_err(&pdev
->dev
, "Error: Missing controller clock\n");
1332 return PTR_ERR(tdma
->dma_clk
);
1335 tdma
->rst
= devm_reset_control_get(&pdev
->dev
, "dma");
1336 if (IS_ERR(tdma
->rst
)) {
1337 dev_err(&pdev
->dev
, "Error: Missing reset\n");
1338 return PTR_ERR(tdma
->rst
);
1341 spin_lock_init(&tdma
->global_lock
);
1343 pm_runtime_enable(&pdev
->dev
);
1344 if (!pm_runtime_enabled(&pdev
->dev
))
1345 ret
= tegra_dma_runtime_resume(&pdev
->dev
);
1347 ret
= pm_runtime_get_sync(&pdev
->dev
);
1350 pm_runtime_disable(&pdev
->dev
);
1354 /* Reset DMA controller */
1355 reset_control_assert(tdma
->rst
);
1357 reset_control_deassert(tdma
->rst
);
1359 /* Enable global DMA registers */
1360 tdma_write(tdma
, TEGRA_APBDMA_GENERAL
, TEGRA_APBDMA_GENERAL_ENABLE
);
1361 tdma_write(tdma
, TEGRA_APBDMA_CONTROL
, 0);
1362 tdma_write(tdma
, TEGRA_APBDMA_IRQ_MASK_SET
, 0xFFFFFFFFul
);
1364 pm_runtime_put(&pdev
->dev
);
1366 INIT_LIST_HEAD(&tdma
->dma_dev
.channels
);
1367 for (i
= 0; i
< cdata
->nr_channels
; i
++) {
1368 struct tegra_dma_channel
*tdc
= &tdma
->channels
[i
];
1370 tdc
->chan_addr
= tdma
->base_addr
+
1371 TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET
+
1372 (i
* cdata
->channel_reg_size
);
1374 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, i
);
1377 dev_err(&pdev
->dev
, "No irq resource for chan %d\n", i
);
1380 tdc
->irq
= res
->start
;
1381 snprintf(tdc
->name
, sizeof(tdc
->name
), "apbdma.%d", i
);
1382 ret
= request_irq(tdc
->irq
, tegra_dma_isr
, 0, tdc
->name
, tdc
);
1385 "request_irq failed with err %d channel %d\n",
1390 tdc
->dma_chan
.device
= &tdma
->dma_dev
;
1391 dma_cookie_init(&tdc
->dma_chan
);
1392 list_add_tail(&tdc
->dma_chan
.device_node
,
1393 &tdma
->dma_dev
.channels
);
1396 tdc
->slave_id
= TEGRA_APBDMA_SLAVE_ID_INVALID
;
1398 tasklet_init(&tdc
->tasklet
, tegra_dma_tasklet
,
1399 (unsigned long)tdc
);
1400 spin_lock_init(&tdc
->lock
);
1402 INIT_LIST_HEAD(&tdc
->pending_sg_req
);
1403 INIT_LIST_HEAD(&tdc
->free_sg_req
);
1404 INIT_LIST_HEAD(&tdc
->free_dma_desc
);
1405 INIT_LIST_HEAD(&tdc
->cb_desc
);
1408 dma_cap_set(DMA_SLAVE
, tdma
->dma_dev
.cap_mask
);
1409 dma_cap_set(DMA_PRIVATE
, tdma
->dma_dev
.cap_mask
);
1410 dma_cap_set(DMA_CYCLIC
, tdma
->dma_dev
.cap_mask
);
1412 tdma
->global_pause_count
= 0;
1413 tdma
->dma_dev
.dev
= &pdev
->dev
;
1414 tdma
->dma_dev
.device_alloc_chan_resources
=
1415 tegra_dma_alloc_chan_resources
;
1416 tdma
->dma_dev
.device_free_chan_resources
=
1417 tegra_dma_free_chan_resources
;
1418 tdma
->dma_dev
.device_prep_slave_sg
= tegra_dma_prep_slave_sg
;
1419 tdma
->dma_dev
.device_prep_dma_cyclic
= tegra_dma_prep_dma_cyclic
;
1420 tdma
->dma_dev
.src_addr_widths
= BIT(DMA_SLAVE_BUSWIDTH_1_BYTE
) |
1421 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES
) |
1422 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES
) |
1423 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES
);
1424 tdma
->dma_dev
.dst_addr_widths
= BIT(DMA_SLAVE_BUSWIDTH_1_BYTE
) |
1425 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES
) |
1426 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES
) |
1427 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES
);
1428 tdma
->dma_dev
.directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
1430 * XXX The hardware appears to support
1431 * DMA_RESIDUE_GRANULARITY_BURST-level reporting, but it's
1432 * only used by this driver during tegra_dma_terminate_all()
1434 tdma
->dma_dev
.residue_granularity
= DMA_RESIDUE_GRANULARITY_SEGMENT
;
1435 tdma
->dma_dev
.device_config
= tegra_dma_slave_config
;
1436 tdma
->dma_dev
.device_terminate_all
= tegra_dma_terminate_all
;
1437 tdma
->dma_dev
.device_tx_status
= tegra_dma_tx_status
;
1438 tdma
->dma_dev
.device_issue_pending
= tegra_dma_issue_pending
;
1440 ret
= dma_async_device_register(&tdma
->dma_dev
);
1443 "Tegra20 APB DMA driver registration failed %d\n", ret
);
1447 ret
= of_dma_controller_register(pdev
->dev
.of_node
,
1448 tegra_dma_of_xlate
, tdma
);
1451 "Tegra20 APB DMA OF registration failed %d\n", ret
);
1452 goto err_unregister_dma_dev
;
1455 dev_info(&pdev
->dev
, "Tegra20 APB DMA driver register %d channels\n",
1456 cdata
->nr_channels
);
1459 err_unregister_dma_dev
:
1460 dma_async_device_unregister(&tdma
->dma_dev
);
1463 struct tegra_dma_channel
*tdc
= &tdma
->channels
[i
];
1465 free_irq(tdc
->irq
, tdc
);
1466 tasklet_kill(&tdc
->tasklet
);
1469 pm_runtime_disable(&pdev
->dev
);
1470 if (!pm_runtime_status_suspended(&pdev
->dev
))
1471 tegra_dma_runtime_suspend(&pdev
->dev
);
1475 static int tegra_dma_remove(struct platform_device
*pdev
)
1477 struct tegra_dma
*tdma
= platform_get_drvdata(pdev
);
1479 struct tegra_dma_channel
*tdc
;
1481 dma_async_device_unregister(&tdma
->dma_dev
);
1483 for (i
= 0; i
< tdma
->chip_data
->nr_channels
; ++i
) {
1484 tdc
= &tdma
->channels
[i
];
1485 free_irq(tdc
->irq
, tdc
);
1486 tasklet_kill(&tdc
->tasklet
);
1489 pm_runtime_disable(&pdev
->dev
);
1490 if (!pm_runtime_status_suspended(&pdev
->dev
))
1491 tegra_dma_runtime_suspend(&pdev
->dev
);
1496 static int tegra_dma_runtime_suspend(struct device
*dev
)
1498 struct tegra_dma
*tdma
= dev_get_drvdata(dev
);
1500 clk_disable_unprepare(tdma
->dma_clk
);
1504 static int tegra_dma_runtime_resume(struct device
*dev
)
1506 struct tegra_dma
*tdma
= dev_get_drvdata(dev
);
1509 ret
= clk_prepare_enable(tdma
->dma_clk
);
1511 dev_err(dev
, "clk_enable failed: %d\n", ret
);
1517 #ifdef CONFIG_PM_SLEEP
1518 static int tegra_dma_pm_suspend(struct device
*dev
)
1520 struct tegra_dma
*tdma
= dev_get_drvdata(dev
);
1524 /* Enable clock before accessing register */
1525 ret
= pm_runtime_get_sync(dev
);
1529 tdma
->reg_gen
= tdma_read(tdma
, TEGRA_APBDMA_GENERAL
);
1530 for (i
= 0; i
< tdma
->chip_data
->nr_channels
; i
++) {
1531 struct tegra_dma_channel
*tdc
= &tdma
->channels
[i
];
1532 struct tegra_dma_channel_regs
*ch_reg
= &tdc
->channel_reg
;
1534 /* Only save the state of DMA channels that are in use */
1535 if (!tdc
->config_init
)
1538 ch_reg
->csr
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_CSR
);
1539 ch_reg
->ahb_ptr
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_AHBPTR
);
1540 ch_reg
->apb_ptr
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_APBPTR
);
1541 ch_reg
->ahb_seq
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_AHBSEQ
);
1542 ch_reg
->apb_seq
= tdc_read(tdc
, TEGRA_APBDMA_CHAN_APBSEQ
);
1543 if (tdma
->chip_data
->support_separate_wcount_reg
)
1544 ch_reg
->wcount
= tdc_read(tdc
,
1545 TEGRA_APBDMA_CHAN_WCOUNT
);
1549 pm_runtime_put(dev
);
1553 static int tegra_dma_pm_resume(struct device
*dev
)
1555 struct tegra_dma
*tdma
= dev_get_drvdata(dev
);
1559 /* Enable clock before accessing register */
1560 ret
= pm_runtime_get_sync(dev
);
1564 tdma_write(tdma
, TEGRA_APBDMA_GENERAL
, tdma
->reg_gen
);
1565 tdma_write(tdma
, TEGRA_APBDMA_CONTROL
, 0);
1566 tdma_write(tdma
, TEGRA_APBDMA_IRQ_MASK_SET
, 0xFFFFFFFFul
);
1568 for (i
= 0; i
< tdma
->chip_data
->nr_channels
; i
++) {
1569 struct tegra_dma_channel
*tdc
= &tdma
->channels
[i
];
1570 struct tegra_dma_channel_regs
*ch_reg
= &tdc
->channel_reg
;
1572 /* Only restore the state of DMA channels that are in use */
1573 if (!tdc
->config_init
)
1576 if (tdma
->chip_data
->support_separate_wcount_reg
)
1577 tdc_write(tdc
, TEGRA_APBDMA_CHAN_WCOUNT
,
1579 tdc_write(tdc
, TEGRA_APBDMA_CHAN_APBSEQ
, ch_reg
->apb_seq
);
1580 tdc_write(tdc
, TEGRA_APBDMA_CHAN_APBPTR
, ch_reg
->apb_ptr
);
1581 tdc_write(tdc
, TEGRA_APBDMA_CHAN_AHBSEQ
, ch_reg
->ahb_seq
);
1582 tdc_write(tdc
, TEGRA_APBDMA_CHAN_AHBPTR
, ch_reg
->ahb_ptr
);
1583 tdc_write(tdc
, TEGRA_APBDMA_CHAN_CSR
,
1584 (ch_reg
->csr
& ~TEGRA_APBDMA_CSR_ENB
));
1588 pm_runtime_put(dev
);
1593 static const struct dev_pm_ops tegra_dma_dev_pm_ops
= {
1594 SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend
, tegra_dma_runtime_resume
,
1596 SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend
, tegra_dma_pm_resume
)
1599 static const struct of_device_id tegra_dma_of_match
[] = {
1601 .compatible
= "nvidia,tegra148-apbdma",
1602 .data
= &tegra148_dma_chip_data
,
1604 .compatible
= "nvidia,tegra114-apbdma",
1605 .data
= &tegra114_dma_chip_data
,
1607 .compatible
= "nvidia,tegra30-apbdma",
1608 .data
= &tegra30_dma_chip_data
,
1610 .compatible
= "nvidia,tegra20-apbdma",
1611 .data
= &tegra20_dma_chip_data
,
1615 MODULE_DEVICE_TABLE(of
, tegra_dma_of_match
);
1617 static struct platform_driver tegra_dmac_driver
= {
1619 .name
= "tegra-apbdma",
1620 .pm
= &tegra_dma_dev_pm_ops
,
1621 .of_match_table
= tegra_dma_of_match
,
1623 .probe
= tegra_dma_probe
,
1624 .remove
= tegra_dma_remove
,
1627 module_platform_driver(tegra_dmac_driver
);
1629 MODULE_ALIAS("platform:tegra20-apbdma");
1630 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1631 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1632 MODULE_LICENSE("GPL v2");