2 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
3 * Copyright 2011-2012 Calxeda, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
17 * Adapted from the highbank_mc_edac driver.
20 #include <asm/cacheflush.h>
21 #include <linux/ctype.h>
22 #include <linux/edac.h>
23 #include <linux/genalloc.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regmap.h>
30 #include <linux/types.h>
31 #include <linux/uaccess.h>
33 #include "altera_edac.h"
34 #include "edac_core.h"
35 #include "edac_module.h"
37 #define EDAC_MOD_STR "altera_edac"
38 #define EDAC_VERSION "1"
39 #define EDAC_DEVICE "Altera"
41 static const struct altr_sdram_prv_data c5_data
= {
42 .ecc_ctrl_offset
= CV_CTLCFG_OFST
,
43 .ecc_ctl_en_mask
= CV_CTLCFG_ECC_AUTO_EN
,
44 .ecc_stat_offset
= CV_DRAMSTS_OFST
,
45 .ecc_stat_ce_mask
= CV_DRAMSTS_SBEERR
,
46 .ecc_stat_ue_mask
= CV_DRAMSTS_DBEERR
,
47 .ecc_saddr_offset
= CV_ERRADDR_OFST
,
48 .ecc_daddr_offset
= CV_ERRADDR_OFST
,
49 .ecc_cecnt_offset
= CV_SBECOUNT_OFST
,
50 .ecc_uecnt_offset
= CV_DBECOUNT_OFST
,
51 .ecc_irq_en_offset
= CV_DRAMINTR_OFST
,
52 .ecc_irq_en_mask
= CV_DRAMINTR_INTREN
,
53 .ecc_irq_clr_offset
= CV_DRAMINTR_OFST
,
54 .ecc_irq_clr_mask
= (CV_DRAMINTR_INTRCLR
| CV_DRAMINTR_INTREN
),
55 .ecc_cnt_rst_offset
= CV_DRAMINTR_OFST
,
56 .ecc_cnt_rst_mask
= CV_DRAMINTR_INTRCLR
,
57 .ce_ue_trgr_offset
= CV_CTLCFG_OFST
,
58 .ce_set_mask
= CV_CTLCFG_GEN_SB_ERR
,
59 .ue_set_mask
= CV_CTLCFG_GEN_DB_ERR
,
62 static const struct altr_sdram_prv_data a10_data
= {
63 .ecc_ctrl_offset
= A10_ECCCTRL1_OFST
,
64 .ecc_ctl_en_mask
= A10_ECCCTRL1_ECC_EN
,
65 .ecc_stat_offset
= A10_INTSTAT_OFST
,
66 .ecc_stat_ce_mask
= A10_INTSTAT_SBEERR
,
67 .ecc_stat_ue_mask
= A10_INTSTAT_DBEERR
,
68 .ecc_saddr_offset
= A10_SERRADDR_OFST
,
69 .ecc_daddr_offset
= A10_DERRADDR_OFST
,
70 .ecc_irq_en_offset
= A10_ERRINTEN_OFST
,
71 .ecc_irq_en_mask
= A10_ECC_IRQ_EN_MASK
,
72 .ecc_irq_clr_offset
= A10_INTSTAT_OFST
,
73 .ecc_irq_clr_mask
= (A10_INTSTAT_SBEERR
| A10_INTSTAT_DBEERR
),
74 .ecc_cnt_rst_offset
= A10_ECCCTRL1_OFST
,
75 .ecc_cnt_rst_mask
= A10_ECC_CNT_RESET_MASK
,
76 .ce_ue_trgr_offset
= A10_DIAGINTTEST_OFST
,
77 .ce_set_mask
= A10_DIAGINT_TSERRA_MASK
,
78 .ue_set_mask
= A10_DIAGINT_TDERRA_MASK
,
81 /*********************** EDAC Memory Controller Functions ****************/
83 /* The SDRAM controller uses the EDAC Memory Controller framework. */
85 static irqreturn_t
altr_sdram_mc_err_handler(int irq
, void *dev_id
)
87 struct mem_ctl_info
*mci
= dev_id
;
88 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
89 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
90 u32 status
, err_count
= 1, err_addr
;
92 regmap_read(drvdata
->mc_vbase
, priv
->ecc_stat_offset
, &status
);
94 if (status
& priv
->ecc_stat_ue_mask
) {
95 regmap_read(drvdata
->mc_vbase
, priv
->ecc_daddr_offset
,
97 if (priv
->ecc_uecnt_offset
)
98 regmap_read(drvdata
->mc_vbase
, priv
->ecc_uecnt_offset
,
100 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
101 err_count
, err_addr
);
103 if (status
& priv
->ecc_stat_ce_mask
) {
104 regmap_read(drvdata
->mc_vbase
, priv
->ecc_saddr_offset
,
106 if (priv
->ecc_uecnt_offset
)
107 regmap_read(drvdata
->mc_vbase
, priv
->ecc_cecnt_offset
,
109 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED
, mci
, err_count
,
110 err_addr
>> PAGE_SHIFT
,
111 err_addr
& ~PAGE_MASK
, 0,
112 0, 0, -1, mci
->ctl_name
, "");
113 /* Clear IRQ to resume */
114 regmap_write(drvdata
->mc_vbase
, priv
->ecc_irq_clr_offset
,
115 priv
->ecc_irq_clr_mask
);
122 static ssize_t
altr_sdr_mc_err_inject_write(struct file
*file
,
123 const char __user
*data
,
124 size_t count
, loff_t
*ppos
)
126 struct mem_ctl_info
*mci
= file
->private_data
;
127 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
128 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
130 dma_addr_t dma_handle
;
133 ptemp
= dma_alloc_coherent(mci
->pdev
, 16, &dma_handle
, GFP_KERNEL
);
135 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
136 edac_printk(KERN_ERR
, EDAC_MC
,
137 "Inject: Buffer Allocation error\n");
141 regmap_read(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
143 read_reg
&= ~(priv
->ce_set_mask
| priv
->ue_set_mask
);
145 /* Error are injected by writing a word while the SBE or DBE
146 * bit in the CTLCFG register is set. Reading the word will
147 * trigger the SBE or DBE error and the corresponding IRQ.
150 edac_printk(KERN_ALERT
, EDAC_MC
,
151 "Inject Double bit error\n");
152 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
153 (read_reg
| priv
->ue_set_mask
));
155 edac_printk(KERN_ALERT
, EDAC_MC
,
156 "Inject Single bit error\n");
157 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
158 (read_reg
| priv
->ce_set_mask
));
161 ptemp
[0] = 0x5A5A5A5A;
162 ptemp
[1] = 0xA5A5A5A5;
164 /* Clear the error injection bits */
165 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
, read_reg
);
166 /* Ensure it has been written out */
170 * To trigger the error, we need to read the data back
171 * (the data was written with errors above).
172 * The ACCESS_ONCE macros and printk are used to prevent the
173 * the compiler optimizing these reads out.
175 reg
= ACCESS_ONCE(ptemp
[0]);
176 read_reg
= ACCESS_ONCE(ptemp
[1]);
180 edac_printk(KERN_ALERT
, EDAC_MC
, "Read Data [0x%X, 0x%X]\n",
183 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
188 static const struct file_operations altr_sdr_mc_debug_inject_fops
= {
190 .write
= altr_sdr_mc_err_inject_write
,
191 .llseek
= generic_file_llseek
,
194 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info
*mci
)
196 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
202 edac_debugfs_create_file("inject_ctrl", S_IWUSR
, mci
->debugfs
, mci
,
203 &altr_sdr_mc_debug_inject_fops
);
206 /* Get total memory size from Open Firmware DTB */
207 static unsigned long get_total_mem(void)
209 struct device_node
*np
= NULL
;
210 const unsigned int *reg
, *reg_end
;
212 unsigned long start
, size
, total_mem
= 0;
214 for_each_node_by_type(np
, "memory") {
215 aw
= of_n_addr_cells(np
);
216 sw
= of_n_size_cells(np
);
217 reg
= (const unsigned int *)of_get_property(np
, "reg", &len
);
218 reg_end
= reg
+ (len
/ sizeof(u32
));
222 start
= of_read_number(reg
, aw
);
224 size
= of_read_number(reg
, sw
);
227 } while (reg
< reg_end
);
229 edac_dbg(0, "total_mem 0x%lx\n", total_mem
);
233 static const struct of_device_id altr_sdram_ctrl_of_match
[] = {
234 { .compatible
= "altr,sdram-edac", .data
= (void *)&c5_data
},
235 { .compatible
= "altr,sdram-edac-a10", .data
= (void *)&a10_data
},
238 MODULE_DEVICE_TABLE(of
, altr_sdram_ctrl_of_match
);
240 static int a10_init(struct regmap
*mc_vbase
)
242 if (regmap_update_bits(mc_vbase
, A10_INTMODE_OFST
,
243 A10_INTMODE_SB_INT
, A10_INTMODE_SB_INT
)) {
244 edac_printk(KERN_ERR
, EDAC_MC
,
245 "Error setting SB IRQ mode\n");
249 if (regmap_write(mc_vbase
, A10_SERRCNTREG_OFST
, 1)) {
250 edac_printk(KERN_ERR
, EDAC_MC
,
251 "Error setting trigger count\n");
258 static int a10_unmask_irq(struct platform_device
*pdev
, u32 mask
)
260 void __iomem
*sm_base
;
263 if (!request_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
),
264 dev_name(&pdev
->dev
))) {
265 edac_printk(KERN_ERR
, EDAC_MC
,
266 "Unable to request mem region\n");
270 sm_base
= ioremap(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
272 edac_printk(KERN_ERR
, EDAC_MC
,
273 "Unable to ioremap device\n");
279 iowrite32(mask
, sm_base
);
284 release_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
289 static int altr_sdram_probe(struct platform_device
*pdev
)
291 const struct of_device_id
*id
;
292 struct edac_mc_layer layers
[2];
293 struct mem_ctl_info
*mci
;
294 struct altr_sdram_mc_data
*drvdata
;
295 const struct altr_sdram_prv_data
*priv
;
296 struct regmap
*mc_vbase
;
297 struct dimm_info
*dimm
;
299 int irq
, irq2
, res
= 0;
300 unsigned long mem_size
, irqflags
= 0;
302 id
= of_match_device(altr_sdram_ctrl_of_match
, &pdev
->dev
);
306 /* Grab the register range from the sdr controller in device tree */
307 mc_vbase
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
309 if (IS_ERR(mc_vbase
)) {
310 edac_printk(KERN_ERR
, EDAC_MC
,
311 "regmap for altr,sdr-syscon lookup failed.\n");
315 /* Check specific dependencies for the module */
316 priv
= of_match_node(altr_sdram_ctrl_of_match
,
317 pdev
->dev
.of_node
)->data
;
319 /* Validate the SDRAM controller has ECC enabled */
320 if (regmap_read(mc_vbase
, priv
->ecc_ctrl_offset
, &read_reg
) ||
321 ((read_reg
& priv
->ecc_ctl_en_mask
) != priv
->ecc_ctl_en_mask
)) {
322 edac_printk(KERN_ERR
, EDAC_MC
,
323 "No ECC/ECC disabled [0x%08X]\n", read_reg
);
327 /* Grab memory size from device tree. */
328 mem_size
= get_total_mem();
330 edac_printk(KERN_ERR
, EDAC_MC
, "Unable to calculate memory size\n");
334 /* Ensure the SDRAM Interrupt is disabled */
335 if (regmap_update_bits(mc_vbase
, priv
->ecc_irq_en_offset
,
336 priv
->ecc_irq_en_mask
, 0)) {
337 edac_printk(KERN_ERR
, EDAC_MC
,
338 "Error disabling SDRAM ECC IRQ\n");
342 /* Toggle to clear the SDRAM Error count */
343 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
344 priv
->ecc_cnt_rst_mask
,
345 priv
->ecc_cnt_rst_mask
)) {
346 edac_printk(KERN_ERR
, EDAC_MC
,
347 "Error clearing SDRAM ECC count\n");
351 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
352 priv
->ecc_cnt_rst_mask
, 0)) {
353 edac_printk(KERN_ERR
, EDAC_MC
,
354 "Error clearing SDRAM ECC count\n");
358 irq
= platform_get_irq(pdev
, 0);
360 edac_printk(KERN_ERR
, EDAC_MC
,
361 "No irq %d in DT\n", irq
);
365 /* Arria10 has a 2nd IRQ */
366 irq2
= platform_get_irq(pdev
, 1);
368 layers
[0].type
= EDAC_MC_LAYER_CHIP_SELECT
;
370 layers
[0].is_virt_csrow
= true;
371 layers
[1].type
= EDAC_MC_LAYER_CHANNEL
;
373 layers
[1].is_virt_csrow
= false;
374 mci
= edac_mc_alloc(0, ARRAY_SIZE(layers
), layers
,
375 sizeof(struct altr_sdram_mc_data
));
379 mci
->pdev
= &pdev
->dev
;
380 drvdata
= mci
->pvt_info
;
381 drvdata
->mc_vbase
= mc_vbase
;
382 drvdata
->data
= priv
;
383 platform_set_drvdata(pdev
, mci
);
385 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
386 edac_printk(KERN_ERR
, EDAC_MC
,
387 "Unable to get managed device resource\n");
392 mci
->mtype_cap
= MEM_FLAG_DDR3
;
393 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
;
394 mci
->edac_cap
= EDAC_FLAG_SECDED
;
395 mci
->mod_name
= EDAC_MOD_STR
;
396 mci
->mod_ver
= EDAC_VERSION
;
397 mci
->ctl_name
= dev_name(&pdev
->dev
);
398 mci
->scrub_mode
= SCRUB_SW_SRC
;
399 mci
->dev_name
= dev_name(&pdev
->dev
);
402 dimm
->nr_pages
= ((mem_size
- 1) >> PAGE_SHIFT
) + 1;
404 dimm
->dtype
= DEV_X8
;
405 dimm
->mtype
= MEM_DDR3
;
406 dimm
->edac_mode
= EDAC_SECDED
;
408 res
= edac_mc_add_mc(mci
);
412 /* Only the Arria10 has separate IRQs */
414 /* Arria10 specific initialization */
415 res
= a10_init(mc_vbase
);
419 res
= devm_request_irq(&pdev
->dev
, irq2
,
420 altr_sdram_mc_err_handler
,
421 IRQF_SHARED
, dev_name(&pdev
->dev
), mci
);
423 edac_mc_printk(mci
, KERN_ERR
,
424 "Unable to request irq %d\n", irq2
);
429 res
= a10_unmask_irq(pdev
, A10_DDR0_IRQ_MASK
);
433 irqflags
= IRQF_SHARED
;
436 res
= devm_request_irq(&pdev
->dev
, irq
, altr_sdram_mc_err_handler
,
437 irqflags
, dev_name(&pdev
->dev
), mci
);
439 edac_mc_printk(mci
, KERN_ERR
,
440 "Unable to request irq %d\n", irq
);
445 /* Infrastructure ready - enable the IRQ */
446 if (regmap_update_bits(drvdata
->mc_vbase
, priv
->ecc_irq_en_offset
,
447 priv
->ecc_irq_en_mask
, priv
->ecc_irq_en_mask
)) {
448 edac_mc_printk(mci
, KERN_ERR
,
449 "Error enabling SDRAM ECC IRQ\n");
454 altr_sdr_mc_create_debugfs_nodes(mci
);
456 devres_close_group(&pdev
->dev
, NULL
);
461 edac_mc_del_mc(&pdev
->dev
);
463 devres_release_group(&pdev
->dev
, NULL
);
466 edac_printk(KERN_ERR
, EDAC_MC
,
467 "EDAC Probe Failed; Error %d\n", res
);
472 static int altr_sdram_remove(struct platform_device
*pdev
)
474 struct mem_ctl_info
*mci
= platform_get_drvdata(pdev
);
476 edac_mc_del_mc(&pdev
->dev
);
478 platform_set_drvdata(pdev
, NULL
);
484 * If you want to suspend, need to disable EDAC by removing it
485 * from the device tree or defconfig.
488 static int altr_sdram_prepare(struct device
*dev
)
490 pr_err("Suspend not allowed when EDAC is enabled.\n");
495 static const struct dev_pm_ops altr_sdram_pm_ops
= {
496 .prepare
= altr_sdram_prepare
,
500 static struct platform_driver altr_sdram_edac_driver
= {
501 .probe
= altr_sdram_probe
,
502 .remove
= altr_sdram_remove
,
504 .name
= "altr_sdram_edac",
506 .pm
= &altr_sdram_pm_ops
,
508 .of_match_table
= altr_sdram_ctrl_of_match
,
512 module_platform_driver(altr_sdram_edac_driver
);
514 /************************* EDAC Parent Probe *************************/
516 static const struct of_device_id altr_edac_device_of_match
[];
518 static const struct of_device_id altr_edac_of_match
[] = {
519 { .compatible
= "altr,socfpga-ecc-manager" },
522 MODULE_DEVICE_TABLE(of
, altr_edac_of_match
);
524 static int altr_edac_probe(struct platform_device
*pdev
)
526 of_platform_populate(pdev
->dev
.of_node
, altr_edac_device_of_match
,
531 static struct platform_driver altr_edac_driver
= {
532 .probe
= altr_edac_probe
,
534 .name
= "socfpga_ecc_manager",
535 .of_match_table
= altr_edac_of_match
,
538 module_platform_driver(altr_edac_driver
);
540 /************************* EDAC Device Functions *************************/
543 * EDAC Device Functions (shared between various IPs).
544 * The discrete memories use the EDAC Device framework. The probe
545 * and error handling functions are very similar between memories
546 * so they are shared. The memory allocation and freeing for EDAC
547 * trigger testing are different for each memory.
550 const struct edac_device_prv_data ocramecc_data
;
551 const struct edac_device_prv_data l2ecc_data
;
553 static irqreturn_t
altr_edac_device_handler(int irq
, void *dev_id
)
555 irqreturn_t ret_value
= IRQ_NONE
;
556 struct edac_device_ctl_info
*dci
= dev_id
;
557 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
558 const struct edac_device_prv_data
*priv
= drvdata
->data
;
560 if (irq
== drvdata
->sb_irq
) {
561 if (priv
->ce_clear_mask
)
562 writel(priv
->ce_clear_mask
, drvdata
->base
);
563 edac_device_handle_ce(dci
, 0, 0, drvdata
->edac_dev_name
);
564 ret_value
= IRQ_HANDLED
;
565 } else if (irq
== drvdata
->db_irq
) {
566 if (priv
->ue_clear_mask
)
567 writel(priv
->ue_clear_mask
, drvdata
->base
);
568 edac_device_handle_ue(dci
, 0, 0, drvdata
->edac_dev_name
);
569 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
570 ret_value
= IRQ_HANDLED
;
578 static ssize_t
altr_edac_device_trig(struct file
*file
,
579 const char __user
*user_buf
,
580 size_t count
, loff_t
*ppos
)
583 u32
*ptemp
, i
, error_mask
;
587 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
588 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
589 const struct edac_device_prv_data
*priv
= drvdata
->data
;
590 void *generic_ptr
= edac_dci
->dev
;
592 if (!user_buf
|| get_user(trig_type
, user_buf
))
595 if (!priv
->alloc_mem
)
599 * Note that generic_ptr is initialized to the device * but in
600 * some alloc_functions, this is overridden and returns data.
602 ptemp
= priv
->alloc_mem(priv
->trig_alloc_sz
, &generic_ptr
);
604 edac_printk(KERN_ERR
, EDAC_DEVICE
,
605 "Inject: Buffer Allocation error\n");
609 if (trig_type
== ALTR_UE_TRIGGER_CHAR
)
610 error_mask
= priv
->ue_set_mask
;
612 error_mask
= priv
->ce_set_mask
;
614 edac_printk(KERN_ALERT
, EDAC_DEVICE
,
615 "Trigger Error Mask (0x%X)\n", error_mask
);
617 local_irq_save(flags
);
618 /* write ECC corrupted data out. */
619 for (i
= 0; i
< (priv
->trig_alloc_sz
/ sizeof(*ptemp
)); i
++) {
620 /* Read data so we're in the correct state */
622 if (ACCESS_ONCE(ptemp
[i
]))
624 /* Toggle Error bit (it is latched), leave ECC enabled */
625 writel(error_mask
, drvdata
->base
);
626 writel(priv
->ecc_enable_mask
, drvdata
->base
);
629 /* Ensure it has been written out */
631 local_irq_restore(flags
);
634 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Mem Not Cleared\n");
636 /* Read out written data. ECC error caused here */
637 for (i
= 0; i
< ALTR_TRIGGER_READ_WRD_CNT
; i
++)
638 if (ACCESS_ONCE(ptemp
[i
]) != i
)
639 edac_printk(KERN_ERR
, EDAC_DEVICE
,
640 "Read doesn't match written data\n");
643 priv
->free_mem(ptemp
, priv
->trig_alloc_sz
, generic_ptr
);
648 static const struct file_operations altr_edac_device_inject_fops
= {
650 .write
= altr_edac_device_trig
,
651 .llseek
= generic_file_llseek
,
654 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info
*edac_dci
,
655 const struct edac_device_prv_data
*priv
)
657 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
659 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
662 drvdata
->debugfs_dir
= edac_debugfs_create_dir(drvdata
->edac_dev_name
);
663 if (!drvdata
->debugfs_dir
)
666 if (!edac_debugfs_create_file(priv
->dbgfs_name
, S_IWUSR
,
667 drvdata
->debugfs_dir
, edac_dci
,
668 &altr_edac_device_inject_fops
))
669 debugfs_remove_recursive(drvdata
->debugfs_dir
);
672 static const struct of_device_id altr_edac_device_of_match
[] = {
673 #ifdef CONFIG_EDAC_ALTERA_L2C
674 { .compatible
= "altr,socfpga-l2-ecc", .data
= (void *)&l2ecc_data
},
676 #ifdef CONFIG_EDAC_ALTERA_OCRAM
677 { .compatible
= "altr,socfpga-ocram-ecc",
678 .data
= (void *)&ocramecc_data
},
682 MODULE_DEVICE_TABLE(of
, altr_edac_device_of_match
);
685 * altr_edac_device_probe()
686 * This is a generic EDAC device driver that will support
687 * various Altera memory devices such as the L2 cache ECC and
688 * OCRAM ECC as well as the memories for other peripherals.
689 * Module specific initialization is done by passing the
690 * function index in the device tree.
692 static int altr_edac_device_probe(struct platform_device
*pdev
)
694 struct edac_device_ctl_info
*dci
;
695 struct altr_edac_device_dev
*drvdata
;
698 struct device_node
*np
= pdev
->dev
.of_node
;
699 char *ecc_name
= (char *)np
->name
;
700 static int dev_instance
;
702 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
703 edac_printk(KERN_ERR
, EDAC_DEVICE
,
704 "Unable to open devm\n");
708 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
710 edac_printk(KERN_ERR
, EDAC_DEVICE
,
711 "Unable to get mem resource\n");
716 if (!devm_request_mem_region(&pdev
->dev
, r
->start
, resource_size(r
),
717 dev_name(&pdev
->dev
))) {
718 edac_printk(KERN_ERR
, EDAC_DEVICE
,
719 "%s:Error requesting mem region\n", ecc_name
);
724 dci
= edac_device_alloc_ctl_info(sizeof(*drvdata
), ecc_name
,
725 1, ecc_name
, 1, 0, NULL
, 0,
729 edac_printk(KERN_ERR
, EDAC_DEVICE
,
730 "%s: Unable to allocate EDAC device\n", ecc_name
);
735 drvdata
= dci
->pvt_info
;
736 dci
->dev
= &pdev
->dev
;
737 platform_set_drvdata(pdev
, dci
);
738 drvdata
->edac_dev_name
= ecc_name
;
740 drvdata
->base
= devm_ioremap(&pdev
->dev
, r
->start
, resource_size(r
));
744 /* Get driver specific data for this EDAC device */
745 drvdata
->data
= of_match_node(altr_edac_device_of_match
, np
)->data
;
747 /* Check specific dependencies for the module */
748 if (drvdata
->data
->setup
) {
749 res
= drvdata
->data
->setup(pdev
, drvdata
->base
);
754 drvdata
->sb_irq
= platform_get_irq(pdev
, 0);
755 res
= devm_request_irq(&pdev
->dev
, drvdata
->sb_irq
,
756 altr_edac_device_handler
,
757 0, dev_name(&pdev
->dev
), dci
);
761 drvdata
->db_irq
= platform_get_irq(pdev
, 1);
762 res
= devm_request_irq(&pdev
->dev
, drvdata
->db_irq
,
763 altr_edac_device_handler
,
764 0, dev_name(&pdev
->dev
), dci
);
768 dci
->mod_name
= "Altera ECC Manager";
769 dci
->dev_name
= drvdata
->edac_dev_name
;
771 res
= edac_device_add_device(dci
);
775 altr_create_edacdev_dbgfs(dci
, drvdata
->data
);
777 devres_close_group(&pdev
->dev
, NULL
);
782 edac_device_free_ctl_info(dci
);
784 devres_release_group(&pdev
->dev
, NULL
);
785 edac_printk(KERN_ERR
, EDAC_DEVICE
,
786 "%s:Error setting up EDAC device: %d\n", ecc_name
, res
);
791 static int altr_edac_device_remove(struct platform_device
*pdev
)
793 struct edac_device_ctl_info
*dci
= platform_get_drvdata(pdev
);
794 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
796 debugfs_remove_recursive(drvdata
->debugfs_dir
);
797 edac_device_del_device(&pdev
->dev
);
798 edac_device_free_ctl_info(dci
);
803 static struct platform_driver altr_edac_device_driver
= {
804 .probe
= altr_edac_device_probe
,
805 .remove
= altr_edac_device_remove
,
807 .name
= "altr_edac_device",
808 .of_match_table
= altr_edac_device_of_match
,
811 module_platform_driver(altr_edac_device_driver
);
813 /*********************** OCRAM EDAC Device Functions *********************/
815 #ifdef CONFIG_EDAC_ALTERA_OCRAM
817 static void *ocram_alloc_mem(size_t size
, void **other
)
819 struct device_node
*np
;
823 np
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-ocram-ecc");
827 gp
= of_gen_pool_get(np
, "iram", 0);
832 sram_addr
= (void *)gen_pool_alloc(gp
, size
);
836 memset(sram_addr
, 0, size
);
837 /* Ensure data is written out */
840 /* Remember this handle for freeing later */
846 static void ocram_free_mem(void *p
, size_t size
, void *other
)
848 gen_pool_free((struct gen_pool
*)other
, (u32
)p
, size
);
852 * altr_ocram_check_deps()
853 * Test for OCRAM cache ECC dependencies upon entry because
854 * platform specific startup should have initialized the
855 * On-Chip RAM memory and enabled the ECC.
856 * Can't turn on ECC here because accessing un-initialized
857 * memory will cause CE/UE errors possibly causing an ABORT.
859 static int altr_ocram_check_deps(struct platform_device
*pdev
,
862 if (readl(base
) & ALTR_OCR_ECC_EN
)
865 edac_printk(KERN_ERR
, EDAC_DEVICE
,
866 "OCRAM: No ECC present or ECC disabled.\n");
870 const struct edac_device_prv_data ocramecc_data
= {
871 .setup
= altr_ocram_check_deps
,
872 .ce_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_SERR
),
873 .ue_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_DERR
),
874 .dbgfs_name
= "altr_ocram_trigger",
875 .alloc_mem
= ocram_alloc_mem
,
876 .free_mem
= ocram_free_mem
,
877 .ecc_enable_mask
= ALTR_OCR_ECC_EN
,
878 .ce_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJS
),
879 .ue_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJD
),
880 .trig_alloc_sz
= ALTR_TRIG_OCRAM_BYTE_SIZE
,
883 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
885 /********************* L2 Cache EDAC Device Functions ********************/
887 #ifdef CONFIG_EDAC_ALTERA_L2C
889 static void *l2_alloc_mem(size_t size
, void **other
)
891 struct device
*dev
= *other
;
892 void *ptemp
= devm_kzalloc(dev
, size
, GFP_KERNEL
);
897 /* Make sure everything is written out */
901 * Clean all cache levels up to LoC (includes L2)
902 * This ensures the corrupted data is written into
903 * L2 cache for readback test (which causes ECC error).
910 static void l2_free_mem(void *p
, size_t size
, void *other
)
912 struct device
*dev
= other
;
919 * altr_l2_check_deps()
920 * Test for L2 cache ECC dependencies upon entry because
921 * platform specific startup should have initialized the L2
922 * memory and enabled the ECC.
923 * Bail if ECC is not enabled.
924 * Note that L2 Cache Enable is forced at build time.
926 static int altr_l2_check_deps(struct platform_device
*pdev
,
929 if (readl(base
) & ALTR_L2_ECC_EN
)
932 edac_printk(KERN_ERR
, EDAC_DEVICE
,
933 "L2: No ECC present, or ECC disabled\n");
937 const struct edac_device_prv_data l2ecc_data
= {
938 .setup
= altr_l2_check_deps
,
941 .dbgfs_name
= "altr_l2_trigger",
942 .alloc_mem
= l2_alloc_mem
,
943 .free_mem
= l2_free_mem
,
944 .ecc_enable_mask
= ALTR_L2_ECC_EN
,
945 .ce_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJS
),
946 .ue_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJD
),
947 .trig_alloc_sz
= ALTR_TRIG_L2C_BYTE_SIZE
,
950 #endif /* CONFIG_EDAC_ALTERA_L2C */
952 MODULE_LICENSE("GPL v2");
953 MODULE_AUTHOR("Thor Thayer");
954 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");