2 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
3 * Copyright 2011-2012 Calxeda, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
17 * Adapted from the highbank_mc_edac driver.
20 #include <asm/cacheflush.h>
21 #include <linux/ctype.h>
22 #include <linux/edac.h>
23 #include <linux/genalloc.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regmap.h>
31 #include <linux/types.h>
32 #include <linux/uaccess.h>
34 #include "altera_edac.h"
35 #include "edac_core.h"
36 #include "edac_module.h"
38 #define EDAC_MOD_STR "altera_edac"
39 #define EDAC_VERSION "1"
40 #define EDAC_DEVICE "Altera"
42 static const struct altr_sdram_prv_data c5_data
= {
43 .ecc_ctrl_offset
= CV_CTLCFG_OFST
,
44 .ecc_ctl_en_mask
= CV_CTLCFG_ECC_AUTO_EN
,
45 .ecc_stat_offset
= CV_DRAMSTS_OFST
,
46 .ecc_stat_ce_mask
= CV_DRAMSTS_SBEERR
,
47 .ecc_stat_ue_mask
= CV_DRAMSTS_DBEERR
,
48 .ecc_saddr_offset
= CV_ERRADDR_OFST
,
49 .ecc_daddr_offset
= CV_ERRADDR_OFST
,
50 .ecc_cecnt_offset
= CV_SBECOUNT_OFST
,
51 .ecc_uecnt_offset
= CV_DBECOUNT_OFST
,
52 .ecc_irq_en_offset
= CV_DRAMINTR_OFST
,
53 .ecc_irq_en_mask
= CV_DRAMINTR_INTREN
,
54 .ecc_irq_clr_offset
= CV_DRAMINTR_OFST
,
55 .ecc_irq_clr_mask
= (CV_DRAMINTR_INTRCLR
| CV_DRAMINTR_INTREN
),
56 .ecc_cnt_rst_offset
= CV_DRAMINTR_OFST
,
57 .ecc_cnt_rst_mask
= CV_DRAMINTR_INTRCLR
,
58 .ce_ue_trgr_offset
= CV_CTLCFG_OFST
,
59 .ce_set_mask
= CV_CTLCFG_GEN_SB_ERR
,
60 .ue_set_mask
= CV_CTLCFG_GEN_DB_ERR
,
63 static const struct altr_sdram_prv_data a10_data
= {
64 .ecc_ctrl_offset
= A10_ECCCTRL1_OFST
,
65 .ecc_ctl_en_mask
= A10_ECCCTRL1_ECC_EN
,
66 .ecc_stat_offset
= A10_INTSTAT_OFST
,
67 .ecc_stat_ce_mask
= A10_INTSTAT_SBEERR
,
68 .ecc_stat_ue_mask
= A10_INTSTAT_DBEERR
,
69 .ecc_saddr_offset
= A10_SERRADDR_OFST
,
70 .ecc_daddr_offset
= A10_DERRADDR_OFST
,
71 .ecc_irq_en_offset
= A10_ERRINTEN_OFST
,
72 .ecc_irq_en_mask
= A10_ECC_IRQ_EN_MASK
,
73 .ecc_irq_clr_offset
= A10_INTSTAT_OFST
,
74 .ecc_irq_clr_mask
= (A10_INTSTAT_SBEERR
| A10_INTSTAT_DBEERR
),
75 .ecc_cnt_rst_offset
= A10_ECCCTRL1_OFST
,
76 .ecc_cnt_rst_mask
= A10_ECC_CNT_RESET_MASK
,
77 .ce_ue_trgr_offset
= A10_DIAGINTTEST_OFST
,
78 .ce_set_mask
= A10_DIAGINT_TSERRA_MASK
,
79 .ue_set_mask
= A10_DIAGINT_TDERRA_MASK
,
82 /*********************** EDAC Memory Controller Functions ****************/
84 /* The SDRAM controller uses the EDAC Memory Controller framework. */
86 static irqreturn_t
altr_sdram_mc_err_handler(int irq
, void *dev_id
)
88 struct mem_ctl_info
*mci
= dev_id
;
89 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
90 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
91 u32 status
, err_count
= 1, err_addr
;
93 regmap_read(drvdata
->mc_vbase
, priv
->ecc_stat_offset
, &status
);
95 if (status
& priv
->ecc_stat_ue_mask
) {
96 regmap_read(drvdata
->mc_vbase
, priv
->ecc_daddr_offset
,
98 if (priv
->ecc_uecnt_offset
)
99 regmap_read(drvdata
->mc_vbase
, priv
->ecc_uecnt_offset
,
101 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
102 err_count
, err_addr
);
104 if (status
& priv
->ecc_stat_ce_mask
) {
105 regmap_read(drvdata
->mc_vbase
, priv
->ecc_saddr_offset
,
107 if (priv
->ecc_uecnt_offset
)
108 regmap_read(drvdata
->mc_vbase
, priv
->ecc_cecnt_offset
,
110 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED
, mci
, err_count
,
111 err_addr
>> PAGE_SHIFT
,
112 err_addr
& ~PAGE_MASK
, 0,
113 0, 0, -1, mci
->ctl_name
, "");
114 /* Clear IRQ to resume */
115 regmap_write(drvdata
->mc_vbase
, priv
->ecc_irq_clr_offset
,
116 priv
->ecc_irq_clr_mask
);
123 static ssize_t
altr_sdr_mc_err_inject_write(struct file
*file
,
124 const char __user
*data
,
125 size_t count
, loff_t
*ppos
)
127 struct mem_ctl_info
*mci
= file
->private_data
;
128 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
129 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
131 dma_addr_t dma_handle
;
134 ptemp
= dma_alloc_coherent(mci
->pdev
, 16, &dma_handle
, GFP_KERNEL
);
136 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
137 edac_printk(KERN_ERR
, EDAC_MC
,
138 "Inject: Buffer Allocation error\n");
142 regmap_read(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
144 read_reg
&= ~(priv
->ce_set_mask
| priv
->ue_set_mask
);
146 /* Error are injected by writing a word while the SBE or DBE
147 * bit in the CTLCFG register is set. Reading the word will
148 * trigger the SBE or DBE error and the corresponding IRQ.
151 edac_printk(KERN_ALERT
, EDAC_MC
,
152 "Inject Double bit error\n");
153 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
154 (read_reg
| priv
->ue_set_mask
));
156 edac_printk(KERN_ALERT
, EDAC_MC
,
157 "Inject Single bit error\n");
158 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
159 (read_reg
| priv
->ce_set_mask
));
162 ptemp
[0] = 0x5A5A5A5A;
163 ptemp
[1] = 0xA5A5A5A5;
165 /* Clear the error injection bits */
166 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
, read_reg
);
167 /* Ensure it has been written out */
171 * To trigger the error, we need to read the data back
172 * (the data was written with errors above).
173 * The ACCESS_ONCE macros and printk are used to prevent the
174 * the compiler optimizing these reads out.
176 reg
= ACCESS_ONCE(ptemp
[0]);
177 read_reg
= ACCESS_ONCE(ptemp
[1]);
181 edac_printk(KERN_ALERT
, EDAC_MC
, "Read Data [0x%X, 0x%X]\n",
184 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
189 static const struct file_operations altr_sdr_mc_debug_inject_fops
= {
191 .write
= altr_sdr_mc_err_inject_write
,
192 .llseek
= generic_file_llseek
,
195 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info
*mci
)
197 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
203 edac_debugfs_create_file("inject_ctrl", S_IWUSR
, mci
->debugfs
, mci
,
204 &altr_sdr_mc_debug_inject_fops
);
207 /* Get total memory size from Open Firmware DTB */
208 static unsigned long get_total_mem(void)
210 struct device_node
*np
= NULL
;
211 const unsigned int *reg
, *reg_end
;
213 unsigned long start
, size
, total_mem
= 0;
215 for_each_node_by_type(np
, "memory") {
216 aw
= of_n_addr_cells(np
);
217 sw
= of_n_size_cells(np
);
218 reg
= (const unsigned int *)of_get_property(np
, "reg", &len
);
219 reg_end
= reg
+ (len
/ sizeof(u32
));
223 start
= of_read_number(reg
, aw
);
225 size
= of_read_number(reg
, sw
);
228 } while (reg
< reg_end
);
230 edac_dbg(0, "total_mem 0x%lx\n", total_mem
);
234 static const struct of_device_id altr_sdram_ctrl_of_match
[] = {
235 { .compatible
= "altr,sdram-edac", .data
= (void *)&c5_data
},
236 { .compatible
= "altr,sdram-edac-a10", .data
= (void *)&a10_data
},
239 MODULE_DEVICE_TABLE(of
, altr_sdram_ctrl_of_match
);
241 static int a10_init(struct regmap
*mc_vbase
)
243 if (regmap_update_bits(mc_vbase
, A10_INTMODE_OFST
,
244 A10_INTMODE_SB_INT
, A10_INTMODE_SB_INT
)) {
245 edac_printk(KERN_ERR
, EDAC_MC
,
246 "Error setting SB IRQ mode\n");
250 if (regmap_write(mc_vbase
, A10_SERRCNTREG_OFST
, 1)) {
251 edac_printk(KERN_ERR
, EDAC_MC
,
252 "Error setting trigger count\n");
259 static int a10_unmask_irq(struct platform_device
*pdev
, u32 mask
)
261 void __iomem
*sm_base
;
264 if (!request_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
),
265 dev_name(&pdev
->dev
))) {
266 edac_printk(KERN_ERR
, EDAC_MC
,
267 "Unable to request mem region\n");
271 sm_base
= ioremap(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
273 edac_printk(KERN_ERR
, EDAC_MC
,
274 "Unable to ioremap device\n");
280 iowrite32(mask
, sm_base
);
285 release_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
290 static int altr_sdram_probe(struct platform_device
*pdev
)
292 const struct of_device_id
*id
;
293 struct edac_mc_layer layers
[2];
294 struct mem_ctl_info
*mci
;
295 struct altr_sdram_mc_data
*drvdata
;
296 const struct altr_sdram_prv_data
*priv
;
297 struct regmap
*mc_vbase
;
298 struct dimm_info
*dimm
;
300 int irq
, irq2
, res
= 0;
301 unsigned long mem_size
, irqflags
= 0;
303 id
= of_match_device(altr_sdram_ctrl_of_match
, &pdev
->dev
);
307 /* Grab the register range from the sdr controller in device tree */
308 mc_vbase
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
310 if (IS_ERR(mc_vbase
)) {
311 edac_printk(KERN_ERR
, EDAC_MC
,
312 "regmap for altr,sdr-syscon lookup failed.\n");
316 /* Check specific dependencies for the module */
317 priv
= of_match_node(altr_sdram_ctrl_of_match
,
318 pdev
->dev
.of_node
)->data
;
320 /* Validate the SDRAM controller has ECC enabled */
321 if (regmap_read(mc_vbase
, priv
->ecc_ctrl_offset
, &read_reg
) ||
322 ((read_reg
& priv
->ecc_ctl_en_mask
) != priv
->ecc_ctl_en_mask
)) {
323 edac_printk(KERN_ERR
, EDAC_MC
,
324 "No ECC/ECC disabled [0x%08X]\n", read_reg
);
328 /* Grab memory size from device tree. */
329 mem_size
= get_total_mem();
331 edac_printk(KERN_ERR
, EDAC_MC
, "Unable to calculate memory size\n");
335 /* Ensure the SDRAM Interrupt is disabled */
336 if (regmap_update_bits(mc_vbase
, priv
->ecc_irq_en_offset
,
337 priv
->ecc_irq_en_mask
, 0)) {
338 edac_printk(KERN_ERR
, EDAC_MC
,
339 "Error disabling SDRAM ECC IRQ\n");
343 /* Toggle to clear the SDRAM Error count */
344 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
345 priv
->ecc_cnt_rst_mask
,
346 priv
->ecc_cnt_rst_mask
)) {
347 edac_printk(KERN_ERR
, EDAC_MC
,
348 "Error clearing SDRAM ECC count\n");
352 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
353 priv
->ecc_cnt_rst_mask
, 0)) {
354 edac_printk(KERN_ERR
, EDAC_MC
,
355 "Error clearing SDRAM ECC count\n");
359 irq
= platform_get_irq(pdev
, 0);
361 edac_printk(KERN_ERR
, EDAC_MC
,
362 "No irq %d in DT\n", irq
);
366 /* Arria10 has a 2nd IRQ */
367 irq2
= platform_get_irq(pdev
, 1);
369 layers
[0].type
= EDAC_MC_LAYER_CHIP_SELECT
;
371 layers
[0].is_virt_csrow
= true;
372 layers
[1].type
= EDAC_MC_LAYER_CHANNEL
;
374 layers
[1].is_virt_csrow
= false;
375 mci
= edac_mc_alloc(0, ARRAY_SIZE(layers
), layers
,
376 sizeof(struct altr_sdram_mc_data
));
380 mci
->pdev
= &pdev
->dev
;
381 drvdata
= mci
->pvt_info
;
382 drvdata
->mc_vbase
= mc_vbase
;
383 drvdata
->data
= priv
;
384 platform_set_drvdata(pdev
, mci
);
386 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
387 edac_printk(KERN_ERR
, EDAC_MC
,
388 "Unable to get managed device resource\n");
393 mci
->mtype_cap
= MEM_FLAG_DDR3
;
394 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
;
395 mci
->edac_cap
= EDAC_FLAG_SECDED
;
396 mci
->mod_name
= EDAC_MOD_STR
;
397 mci
->mod_ver
= EDAC_VERSION
;
398 mci
->ctl_name
= dev_name(&pdev
->dev
);
399 mci
->scrub_mode
= SCRUB_SW_SRC
;
400 mci
->dev_name
= dev_name(&pdev
->dev
);
403 dimm
->nr_pages
= ((mem_size
- 1) >> PAGE_SHIFT
) + 1;
405 dimm
->dtype
= DEV_X8
;
406 dimm
->mtype
= MEM_DDR3
;
407 dimm
->edac_mode
= EDAC_SECDED
;
409 res
= edac_mc_add_mc(mci
);
413 /* Only the Arria10 has separate IRQs */
415 /* Arria10 specific initialization */
416 res
= a10_init(mc_vbase
);
420 res
= devm_request_irq(&pdev
->dev
, irq2
,
421 altr_sdram_mc_err_handler
,
422 IRQF_SHARED
, dev_name(&pdev
->dev
), mci
);
424 edac_mc_printk(mci
, KERN_ERR
,
425 "Unable to request irq %d\n", irq2
);
430 res
= a10_unmask_irq(pdev
, A10_DDR0_IRQ_MASK
);
434 irqflags
= IRQF_SHARED
;
437 res
= devm_request_irq(&pdev
->dev
, irq
, altr_sdram_mc_err_handler
,
438 irqflags
, dev_name(&pdev
->dev
), mci
);
440 edac_mc_printk(mci
, KERN_ERR
,
441 "Unable to request irq %d\n", irq
);
446 /* Infrastructure ready - enable the IRQ */
447 if (regmap_update_bits(drvdata
->mc_vbase
, priv
->ecc_irq_en_offset
,
448 priv
->ecc_irq_en_mask
, priv
->ecc_irq_en_mask
)) {
449 edac_mc_printk(mci
, KERN_ERR
,
450 "Error enabling SDRAM ECC IRQ\n");
455 altr_sdr_mc_create_debugfs_nodes(mci
);
457 devres_close_group(&pdev
->dev
, NULL
);
462 edac_mc_del_mc(&pdev
->dev
);
464 devres_release_group(&pdev
->dev
, NULL
);
467 edac_printk(KERN_ERR
, EDAC_MC
,
468 "EDAC Probe Failed; Error %d\n", res
);
473 static int altr_sdram_remove(struct platform_device
*pdev
)
475 struct mem_ctl_info
*mci
= platform_get_drvdata(pdev
);
477 edac_mc_del_mc(&pdev
->dev
);
479 platform_set_drvdata(pdev
, NULL
);
485 * If you want to suspend, need to disable EDAC by removing it
486 * from the device tree or defconfig.
489 static int altr_sdram_prepare(struct device
*dev
)
491 pr_err("Suspend not allowed when EDAC is enabled.\n");
496 static const struct dev_pm_ops altr_sdram_pm_ops
= {
497 .prepare
= altr_sdram_prepare
,
501 static struct platform_driver altr_sdram_edac_driver
= {
502 .probe
= altr_sdram_probe
,
503 .remove
= altr_sdram_remove
,
505 .name
= "altr_sdram_edac",
507 .pm
= &altr_sdram_pm_ops
,
509 .of_match_table
= altr_sdram_ctrl_of_match
,
513 module_platform_driver(altr_sdram_edac_driver
);
515 /************************* EDAC Parent Probe *************************/
517 static const struct of_device_id altr_edac_device_of_match
[];
519 static const struct of_device_id altr_edac_of_match
[] = {
520 { .compatible
= "altr,socfpga-ecc-manager" },
523 MODULE_DEVICE_TABLE(of
, altr_edac_of_match
);
525 static int altr_edac_probe(struct platform_device
*pdev
)
527 of_platform_populate(pdev
->dev
.of_node
, altr_edac_device_of_match
,
532 static struct platform_driver altr_edac_driver
= {
533 .probe
= altr_edac_probe
,
535 .name
= "socfpga_ecc_manager",
536 .of_match_table
= altr_edac_of_match
,
539 module_platform_driver(altr_edac_driver
);
541 /************************* EDAC Device Functions *************************/
544 * EDAC Device Functions (shared between various IPs).
545 * The discrete memories use the EDAC Device framework. The probe
546 * and error handling functions are very similar between memories
547 * so they are shared. The memory allocation and freeing for EDAC
548 * trigger testing are different for each memory.
551 const struct edac_device_prv_data ocramecc_data
;
552 const struct edac_device_prv_data l2ecc_data
;
553 const struct edac_device_prv_data a10_l2ecc_data
;
555 static irqreturn_t
altr_edac_device_handler(int irq
, void *dev_id
)
557 irqreturn_t ret_value
= IRQ_NONE
;
558 struct edac_device_ctl_info
*dci
= dev_id
;
559 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
560 const struct edac_device_prv_data
*priv
= drvdata
->data
;
562 if (irq
== drvdata
->sb_irq
) {
563 if (priv
->ce_clear_mask
)
564 writel(priv
->ce_clear_mask
, drvdata
->base
);
565 edac_device_handle_ce(dci
, 0, 0, drvdata
->edac_dev_name
);
566 ret_value
= IRQ_HANDLED
;
567 } else if (irq
== drvdata
->db_irq
) {
568 if (priv
->ue_clear_mask
)
569 writel(priv
->ue_clear_mask
, drvdata
->base
);
570 edac_device_handle_ue(dci
, 0, 0, drvdata
->edac_dev_name
);
571 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
572 ret_value
= IRQ_HANDLED
;
580 static ssize_t
altr_edac_device_trig(struct file
*file
,
581 const char __user
*user_buf
,
582 size_t count
, loff_t
*ppos
)
585 u32
*ptemp
, i
, error_mask
;
589 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
590 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
591 const struct edac_device_prv_data
*priv
= drvdata
->data
;
592 void *generic_ptr
= edac_dci
->dev
;
594 if (!user_buf
|| get_user(trig_type
, user_buf
))
597 if (!priv
->alloc_mem
)
601 * Note that generic_ptr is initialized to the device * but in
602 * some alloc_functions, this is overridden and returns data.
604 ptemp
= priv
->alloc_mem(priv
->trig_alloc_sz
, &generic_ptr
);
606 edac_printk(KERN_ERR
, EDAC_DEVICE
,
607 "Inject: Buffer Allocation error\n");
611 if (trig_type
== ALTR_UE_TRIGGER_CHAR
)
612 error_mask
= priv
->ue_set_mask
;
614 error_mask
= priv
->ce_set_mask
;
616 edac_printk(KERN_ALERT
, EDAC_DEVICE
,
617 "Trigger Error Mask (0x%X)\n", error_mask
);
619 local_irq_save(flags
);
620 /* write ECC corrupted data out. */
621 for (i
= 0; i
< (priv
->trig_alloc_sz
/ sizeof(*ptemp
)); i
++) {
622 /* Read data so we're in the correct state */
624 if (ACCESS_ONCE(ptemp
[i
]))
626 /* Toggle Error bit (it is latched), leave ECC enabled */
627 writel(error_mask
, (drvdata
->base
+ priv
->set_err_ofst
));
628 writel(priv
->ecc_enable_mask
, (drvdata
->base
+
629 priv
->set_err_ofst
));
632 /* Ensure it has been written out */
634 local_irq_restore(flags
);
637 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Mem Not Cleared\n");
639 /* Read out written data. ECC error caused here */
640 for (i
= 0; i
< ALTR_TRIGGER_READ_WRD_CNT
; i
++)
641 if (ACCESS_ONCE(ptemp
[i
]) != i
)
642 edac_printk(KERN_ERR
, EDAC_DEVICE
,
643 "Read doesn't match written data\n");
646 priv
->free_mem(ptemp
, priv
->trig_alloc_sz
, generic_ptr
);
651 static const struct file_operations altr_edac_device_inject_fops
= {
653 .write
= altr_edac_device_trig
,
654 .llseek
= generic_file_llseek
,
657 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info
*edac_dci
,
658 const struct edac_device_prv_data
*priv
)
660 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
662 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
665 drvdata
->debugfs_dir
= edac_debugfs_create_dir(drvdata
->edac_dev_name
);
666 if (!drvdata
->debugfs_dir
)
669 if (!edac_debugfs_create_file(priv
->dbgfs_name
, S_IWUSR
,
670 drvdata
->debugfs_dir
, edac_dci
,
672 debugfs_remove_recursive(drvdata
->debugfs_dir
);
675 static const struct of_device_id altr_edac_device_of_match
[] = {
676 #ifdef CONFIG_EDAC_ALTERA_L2C
677 { .compatible
= "altr,socfpga-l2-ecc", .data
= (void *)&l2ecc_data
},
678 { .compatible
= "altr,socfpga-a10-l2-ecc",
679 .data
= (void *)&a10_l2ecc_data
},
681 #ifdef CONFIG_EDAC_ALTERA_OCRAM
682 { .compatible
= "altr,socfpga-ocram-ecc",
683 .data
= (void *)&ocramecc_data
},
687 MODULE_DEVICE_TABLE(of
, altr_edac_device_of_match
);
690 * altr_edac_device_probe()
691 * This is a generic EDAC device driver that will support
692 * various Altera memory devices such as the L2 cache ECC and
693 * OCRAM ECC as well as the memories for other peripherals.
694 * Module specific initialization is done by passing the
695 * function index in the device tree.
697 static int altr_edac_device_probe(struct platform_device
*pdev
)
699 struct edac_device_ctl_info
*dci
;
700 struct altr_edac_device_dev
*drvdata
;
703 struct device_node
*np
= pdev
->dev
.of_node
;
704 char *ecc_name
= (char *)np
->name
;
705 static int dev_instance
;
707 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
708 edac_printk(KERN_ERR
, EDAC_DEVICE
,
709 "Unable to open devm\n");
713 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
715 edac_printk(KERN_ERR
, EDAC_DEVICE
,
716 "Unable to get mem resource\n");
721 if (!devm_request_mem_region(&pdev
->dev
, r
->start
, resource_size(r
),
722 dev_name(&pdev
->dev
))) {
723 edac_printk(KERN_ERR
, EDAC_DEVICE
,
724 "%s:Error requesting mem region\n", ecc_name
);
729 dci
= edac_device_alloc_ctl_info(sizeof(*drvdata
), ecc_name
,
730 1, ecc_name
, 1, 0, NULL
, 0,
734 edac_printk(KERN_ERR
, EDAC_DEVICE
,
735 "%s: Unable to allocate EDAC device\n", ecc_name
);
740 drvdata
= dci
->pvt_info
;
741 dci
->dev
= &pdev
->dev
;
742 platform_set_drvdata(pdev
, dci
);
743 drvdata
->edac_dev_name
= ecc_name
;
745 drvdata
->base
= devm_ioremap(&pdev
->dev
, r
->start
, resource_size(r
));
749 /* Get driver specific data for this EDAC device */
750 drvdata
->data
= of_match_node(altr_edac_device_of_match
, np
)->data
;
752 /* Check specific dependencies for the module */
753 if (drvdata
->data
->setup
) {
754 res
= drvdata
->data
->setup(drvdata
);
759 drvdata
->sb_irq
= platform_get_irq(pdev
, 0);
760 res
= devm_request_irq(&pdev
->dev
, drvdata
->sb_irq
,
761 altr_edac_device_handler
,
762 0, dev_name(&pdev
->dev
), dci
);
766 drvdata
->db_irq
= platform_get_irq(pdev
, 1);
767 res
= devm_request_irq(&pdev
->dev
, drvdata
->db_irq
,
768 altr_edac_device_handler
,
769 0, dev_name(&pdev
->dev
), dci
);
773 dci
->mod_name
= "Altera ECC Manager";
774 dci
->dev_name
= drvdata
->edac_dev_name
;
776 res
= edac_device_add_device(dci
);
780 altr_create_edacdev_dbgfs(dci
, drvdata
->data
);
782 devres_close_group(&pdev
->dev
, NULL
);
787 edac_device_free_ctl_info(dci
);
789 devres_release_group(&pdev
->dev
, NULL
);
790 edac_printk(KERN_ERR
, EDAC_DEVICE
,
791 "%s:Error setting up EDAC device: %d\n", ecc_name
, res
);
796 static int altr_edac_device_remove(struct platform_device
*pdev
)
798 struct edac_device_ctl_info
*dci
= platform_get_drvdata(pdev
);
799 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
801 debugfs_remove_recursive(drvdata
->debugfs_dir
);
802 edac_device_del_device(&pdev
->dev
);
803 edac_device_free_ctl_info(dci
);
808 static struct platform_driver altr_edac_device_driver
= {
809 .probe
= altr_edac_device_probe
,
810 .remove
= altr_edac_device_remove
,
812 .name
= "altr_edac_device",
813 .of_match_table
= altr_edac_device_of_match
,
816 module_platform_driver(altr_edac_device_driver
);
818 /*********************** OCRAM EDAC Device Functions *********************/
820 #ifdef CONFIG_EDAC_ALTERA_OCRAM
822 static void *ocram_alloc_mem(size_t size
, void **other
)
824 struct device_node
*np
;
828 np
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-ocram-ecc");
832 gp
= of_gen_pool_get(np
, "iram", 0);
837 sram_addr
= (void *)gen_pool_alloc(gp
, size
);
841 memset(sram_addr
, 0, size
);
842 /* Ensure data is written out */
845 /* Remember this handle for freeing later */
851 static void ocram_free_mem(void *p
, size_t size
, void *other
)
853 gen_pool_free((struct gen_pool
*)other
, (u32
)p
, size
);
857 * altr_ocram_check_deps()
858 * Test for OCRAM cache ECC dependencies upon entry because
859 * platform specific startup should have initialized the
860 * On-Chip RAM memory and enabled the ECC.
861 * Can't turn on ECC here because accessing un-initialized
862 * memory will cause CE/UE errors possibly causing an ABORT.
864 static int altr_ocram_check_deps(struct altr_edac_device_dev
*device
)
866 void __iomem
*base
= device
->base
;
867 const struct edac_device_prv_data
*prv
= device
->data
;
869 if (readl(base
) & prv
->ecc_enable_mask
)
872 edac_printk(KERN_ERR
, EDAC_DEVICE
,
873 "OCRAM: No ECC present or ECC disabled.\n");
877 const struct edac_device_prv_data ocramecc_data
= {
878 .setup
= altr_ocram_check_deps
,
879 .ce_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_SERR
),
880 .ue_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_DERR
),
881 .dbgfs_name
= "altr_ocram_trigger",
882 .alloc_mem
= ocram_alloc_mem
,
883 .free_mem
= ocram_free_mem
,
884 .ecc_enable_mask
= ALTR_OCR_ECC_EN
,
885 .ce_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJS
),
886 .ue_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJD
),
887 .set_err_ofst
= ALTR_OCR_ECC_REG_OFFSET
,
888 .trig_alloc_sz
= ALTR_TRIG_OCRAM_BYTE_SIZE
,
889 .inject_fops
= &altr_edac_device_inject_fops
,
892 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
894 /********************* L2 Cache EDAC Device Functions ********************/
896 #ifdef CONFIG_EDAC_ALTERA_L2C
898 static void *l2_alloc_mem(size_t size
, void **other
)
900 struct device
*dev
= *other
;
901 void *ptemp
= devm_kzalloc(dev
, size
, GFP_KERNEL
);
906 /* Make sure everything is written out */
910 * Clean all cache levels up to LoC (includes L2)
911 * This ensures the corrupted data is written into
912 * L2 cache for readback test (which causes ECC error).
919 static void l2_free_mem(void *p
, size_t size
, void *other
)
921 struct device
*dev
= other
;
928 * altr_l2_check_deps()
929 * Test for L2 cache ECC dependencies upon entry because
930 * platform specific startup should have initialized the L2
931 * memory and enabled the ECC.
932 * Bail if ECC is not enabled.
933 * Note that L2 Cache Enable is forced at build time.
935 static int altr_l2_check_deps(struct altr_edac_device_dev
*device
)
937 void __iomem
*base
= device
->base
;
938 const struct edac_device_prv_data
*prv
= device
->data
;
940 if ((readl(base
) & prv
->ecc_enable_mask
) ==
941 prv
->ecc_enable_mask
)
944 edac_printk(KERN_ERR
, EDAC_DEVICE
,
945 "L2: No ECC present, or ECC disabled\n");
949 static irqreturn_t
altr_edac_a10_l2_irq(struct altr_edac_device_dev
*dci
,
953 regmap_write(dci
->edac
->ecc_mgr_map
,
954 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST
,
955 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB
);
956 edac_device_handle_ce(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
958 regmap_write(dci
->edac
->ecc_mgr_map
,
959 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST
,
960 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB
);
961 edac_device_handle_ue(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
962 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
967 const struct edac_device_prv_data l2ecc_data
= {
968 .setup
= altr_l2_check_deps
,
971 .dbgfs_name
= "altr_l2_trigger",
972 .alloc_mem
= l2_alloc_mem
,
973 .free_mem
= l2_free_mem
,
974 .ecc_enable_mask
= ALTR_L2_ECC_EN
,
975 .ce_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJS
),
976 .ue_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJD
),
977 .set_err_ofst
= ALTR_L2_ECC_REG_OFFSET
,
978 .trig_alloc_sz
= ALTR_TRIG_L2C_BYTE_SIZE
,
979 .inject_fops
= &altr_edac_device_inject_fops
,
982 const struct edac_device_prv_data a10_l2ecc_data
= {
983 .setup
= altr_l2_check_deps
,
984 .ce_clear_mask
= ALTR_A10_L2_ECC_SERR_CLR
,
985 .ue_clear_mask
= ALTR_A10_L2_ECC_MERR_CLR
,
986 .irq_status_mask
= A10_SYSMGR_ECC_INTSTAT_L2
,
987 .dbgfs_name
= "altr_l2_trigger",
988 .alloc_mem
= l2_alloc_mem
,
989 .free_mem
= l2_free_mem
,
990 .ecc_enable_mask
= ALTR_A10_L2_ECC_EN_CTL
,
991 .ce_set_mask
= ALTR_A10_L2_ECC_CE_INJ_MASK
,
992 .ue_set_mask
= ALTR_A10_L2_ECC_UE_INJ_MASK
,
993 .set_err_ofst
= ALTR_A10_L2_ECC_INJ_OFST
,
994 .ecc_irq_handler
= altr_edac_a10_l2_irq
,
995 .trig_alloc_sz
= ALTR_TRIG_L2C_BYTE_SIZE
,
996 .inject_fops
= &altr_edac_device_inject_fops
,
999 #endif /* CONFIG_EDAC_ALTERA_L2C */
1001 /********************* Arria10 EDAC Device Functions *************************/
1004 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1005 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1006 * manager manages the IRQs and the children.
1007 * Based on xgene_edac.c peripheral code.
1010 static irqreturn_t
altr_edac_a10_irq_handler(int irq
, void *dev_id
)
1012 irqreturn_t rc
= IRQ_NONE
;
1013 struct altr_arria10_edac
*edac
= dev_id
;
1014 struct altr_edac_device_dev
*dci
;
1016 bool sberr
= (irq
== edac
->sb_irq
) ? 1 : 0;
1017 int sm_offset
= sberr
? A10_SYSMGR_ECC_INTSTAT_SERR_OFST
:
1018 A10_SYSMGR_ECC_INTSTAT_DERR_OFST
;
1020 regmap_read(edac
->ecc_mgr_map
, sm_offset
, &irq_status
);
1022 if ((irq
!= edac
->sb_irq
) && (irq
!= edac
->db_irq
)) {
1025 list_for_each_entry(dci
, &edac
->a10_ecc_devices
, next
) {
1026 if (irq_status
& dci
->data
->irq_status_mask
)
1027 rc
= dci
->data
->ecc_irq_handler(dci
, sberr
);
1034 static int altr_edac_a10_device_add(struct altr_arria10_edac
*edac
,
1035 struct device_node
*np
)
1037 struct edac_device_ctl_info
*dci
;
1038 struct altr_edac_device_dev
*altdev
;
1039 char *ecc_name
= (char *)np
->name
;
1040 struct resource res
;
1043 const struct edac_device_prv_data
*prv
;
1044 /* Get matching node and check for valid result */
1045 const struct of_device_id
*pdev_id
=
1046 of_match_node(altr_edac_device_of_match
, np
);
1047 if (IS_ERR_OR_NULL(pdev_id
))
1050 /* Get driver specific data for this EDAC device */
1051 prv
= pdev_id
->data
;
1052 if (IS_ERR_OR_NULL(prv
))
1055 if (!devres_open_group(edac
->dev
, altr_edac_a10_device_add
, GFP_KERNEL
))
1058 rc
= of_address_to_resource(np
, 0, &res
);
1060 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1061 "%s: no resource address\n", ecc_name
);
1062 goto err_release_group
;
1065 edac_idx
= edac_device_alloc_index();
1066 dci
= edac_device_alloc_ctl_info(sizeof(*altdev
), ecc_name
,
1067 1, ecc_name
, 1, 0, NULL
, 0,
1071 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1072 "%s: Unable to allocate EDAC device\n", ecc_name
);
1074 goto err_release_group
;
1077 altdev
= dci
->pvt_info
;
1078 dci
->dev
= edac
->dev
;
1079 altdev
->edac_dev_name
= ecc_name
;
1080 altdev
->edac_idx
= edac_idx
;
1081 altdev
->edac
= edac
;
1082 altdev
->edac_dev
= dci
;
1084 altdev
->ddev
= *edac
->dev
;
1085 dci
->dev
= &altdev
->ddev
;
1086 dci
->ctl_name
= "Altera ECC Manager";
1087 dci
->mod_name
= ecc_name
;
1088 dci
->dev_name
= ecc_name
;
1090 altdev
->base
= devm_ioremap_resource(edac
->dev
, &res
);
1091 if (IS_ERR(altdev
->base
)) {
1092 rc
= PTR_ERR(altdev
->base
);
1093 goto err_release_group1
;
1096 /* Check specific dependencies for the module */
1097 if (altdev
->data
->setup
) {
1098 rc
= altdev
->data
->setup(altdev
);
1100 goto err_release_group1
;
1103 rc
= edac_device_add_device(dci
);
1105 dev_err(edac
->dev
, "edac_device_add_device failed\n");
1107 goto err_release_group1
;
1110 altr_create_edacdev_dbgfs(dci
, prv
);
1112 list_add(&altdev
->next
, &edac
->a10_ecc_devices
);
1114 devres_remove_group(edac
->dev
, altr_edac_a10_device_add
);
1119 edac_device_free_ctl_info(dci
);
1121 edac_printk(KERN_ALERT
, EDAC_DEVICE
, "%s: %d\n", __func__
, __LINE__
);
1122 devres_release_group(edac
->dev
, NULL
);
1123 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1124 "%s:Error setting up EDAC device: %d\n", ecc_name
, rc
);
1129 static int altr_edac_a10_probe(struct platform_device
*pdev
)
1131 struct altr_arria10_edac
*edac
;
1132 struct device_node
*child
;
1135 edac
= devm_kzalloc(&pdev
->dev
, sizeof(*edac
), GFP_KERNEL
);
1139 edac
->dev
= &pdev
->dev
;
1140 platform_set_drvdata(pdev
, edac
);
1141 INIT_LIST_HEAD(&edac
->a10_ecc_devices
);
1143 edac
->ecc_mgr_map
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
1144 "altr,sysmgr-syscon");
1145 if (IS_ERR(edac
->ecc_mgr_map
)) {
1146 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1147 "Unable to get syscon altr,sysmgr-syscon\n");
1148 return PTR_ERR(edac
->ecc_mgr_map
);
1151 edac
->sb_irq
= platform_get_irq(pdev
, 0);
1152 rc
= devm_request_irq(&pdev
->dev
, edac
->sb_irq
,
1153 altr_edac_a10_irq_handler
,
1154 IRQF_SHARED
, dev_name(&pdev
->dev
), edac
);
1156 edac_printk(KERN_ERR
, EDAC_DEVICE
, "No SBERR IRQ resource\n");
1160 edac
->db_irq
= platform_get_irq(pdev
, 1);
1161 rc
= devm_request_irq(&pdev
->dev
, edac
->db_irq
,
1162 altr_edac_a10_irq_handler
,
1163 IRQF_SHARED
, dev_name(&pdev
->dev
), edac
);
1165 edac_printk(KERN_ERR
, EDAC_DEVICE
, "No DBERR IRQ resource\n");
1169 for_each_child_of_node(pdev
->dev
.of_node
, child
) {
1170 if (!of_device_is_available(child
))
1172 if (of_device_is_compatible(child
, "altr,socfpga-a10-l2-ecc"))
1173 altr_edac_a10_device_add(edac
, child
);
1179 static const struct of_device_id altr_edac_a10_of_match
[] = {
1180 { .compatible
= "altr,socfpga-a10-ecc-manager" },
1183 MODULE_DEVICE_TABLE(of
, altr_edac_a10_of_match
);
1185 static struct platform_driver altr_edac_a10_driver
= {
1186 .probe
= altr_edac_a10_probe
,
1188 .name
= "socfpga_a10_ecc_manager",
1189 .of_match_table
= altr_edac_a10_of_match
,
1192 module_platform_driver(altr_edac_a10_driver
);
1194 MODULE_LICENSE("GPL v2");
1195 MODULE_AUTHOR("Thor Thayer");
1196 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");