2 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
3 * Copyright 2011-2012 Calxeda, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
17 * Adapted from the highbank_mc_edac driver.
20 #include <asm/cacheflush.h>
21 #include <linux/ctype.h>
22 #include <linux/edac.h>
23 #include <linux/genalloc.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqchip/chained_irq.h>
26 #include <linux/kernel.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/of_address.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_platform.h>
31 #include <linux/platform_device.h>
32 #include <linux/regmap.h>
33 #include <linux/types.h>
34 #include <linux/uaccess.h>
36 #include "altera_edac.h"
37 #include "edac_core.h"
38 #include "edac_module.h"
40 #define EDAC_MOD_STR "altera_edac"
41 #define EDAC_VERSION "1"
42 #define EDAC_DEVICE "Altera"
44 static const struct altr_sdram_prv_data c5_data
= {
45 .ecc_ctrl_offset
= CV_CTLCFG_OFST
,
46 .ecc_ctl_en_mask
= CV_CTLCFG_ECC_AUTO_EN
,
47 .ecc_stat_offset
= CV_DRAMSTS_OFST
,
48 .ecc_stat_ce_mask
= CV_DRAMSTS_SBEERR
,
49 .ecc_stat_ue_mask
= CV_DRAMSTS_DBEERR
,
50 .ecc_saddr_offset
= CV_ERRADDR_OFST
,
51 .ecc_daddr_offset
= CV_ERRADDR_OFST
,
52 .ecc_cecnt_offset
= CV_SBECOUNT_OFST
,
53 .ecc_uecnt_offset
= CV_DBECOUNT_OFST
,
54 .ecc_irq_en_offset
= CV_DRAMINTR_OFST
,
55 .ecc_irq_en_mask
= CV_DRAMINTR_INTREN
,
56 .ecc_irq_clr_offset
= CV_DRAMINTR_OFST
,
57 .ecc_irq_clr_mask
= (CV_DRAMINTR_INTRCLR
| CV_DRAMINTR_INTREN
),
58 .ecc_cnt_rst_offset
= CV_DRAMINTR_OFST
,
59 .ecc_cnt_rst_mask
= CV_DRAMINTR_INTRCLR
,
60 .ce_ue_trgr_offset
= CV_CTLCFG_OFST
,
61 .ce_set_mask
= CV_CTLCFG_GEN_SB_ERR
,
62 .ue_set_mask
= CV_CTLCFG_GEN_DB_ERR
,
65 static const struct altr_sdram_prv_data a10_data
= {
66 .ecc_ctrl_offset
= A10_ECCCTRL1_OFST
,
67 .ecc_ctl_en_mask
= A10_ECCCTRL1_ECC_EN
,
68 .ecc_stat_offset
= A10_INTSTAT_OFST
,
69 .ecc_stat_ce_mask
= A10_INTSTAT_SBEERR
,
70 .ecc_stat_ue_mask
= A10_INTSTAT_DBEERR
,
71 .ecc_saddr_offset
= A10_SERRADDR_OFST
,
72 .ecc_daddr_offset
= A10_DERRADDR_OFST
,
73 .ecc_irq_en_offset
= A10_ERRINTEN_OFST
,
74 .ecc_irq_en_mask
= A10_ECC_IRQ_EN_MASK
,
75 .ecc_irq_clr_offset
= A10_INTSTAT_OFST
,
76 .ecc_irq_clr_mask
= (A10_INTSTAT_SBEERR
| A10_INTSTAT_DBEERR
),
77 .ecc_cnt_rst_offset
= A10_ECCCTRL1_OFST
,
78 .ecc_cnt_rst_mask
= A10_ECC_CNT_RESET_MASK
,
79 .ce_ue_trgr_offset
= A10_DIAGINTTEST_OFST
,
80 .ce_set_mask
= A10_DIAGINT_TSERRA_MASK
,
81 .ue_set_mask
= A10_DIAGINT_TDERRA_MASK
,
84 /*********************** EDAC Memory Controller Functions ****************/
86 /* The SDRAM controller uses the EDAC Memory Controller framework. */
88 static irqreturn_t
altr_sdram_mc_err_handler(int irq
, void *dev_id
)
90 struct mem_ctl_info
*mci
= dev_id
;
91 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
92 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
93 u32 status
, err_count
= 1, err_addr
;
95 regmap_read(drvdata
->mc_vbase
, priv
->ecc_stat_offset
, &status
);
97 if (status
& priv
->ecc_stat_ue_mask
) {
98 regmap_read(drvdata
->mc_vbase
, priv
->ecc_daddr_offset
,
100 if (priv
->ecc_uecnt_offset
)
101 regmap_read(drvdata
->mc_vbase
, priv
->ecc_uecnt_offset
,
103 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
104 err_count
, err_addr
);
106 if (status
& priv
->ecc_stat_ce_mask
) {
107 regmap_read(drvdata
->mc_vbase
, priv
->ecc_saddr_offset
,
109 if (priv
->ecc_uecnt_offset
)
110 regmap_read(drvdata
->mc_vbase
, priv
->ecc_cecnt_offset
,
112 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED
, mci
, err_count
,
113 err_addr
>> PAGE_SHIFT
,
114 err_addr
& ~PAGE_MASK
, 0,
115 0, 0, -1, mci
->ctl_name
, "");
116 /* Clear IRQ to resume */
117 regmap_write(drvdata
->mc_vbase
, priv
->ecc_irq_clr_offset
,
118 priv
->ecc_irq_clr_mask
);
125 static ssize_t
altr_sdr_mc_err_inject_write(struct file
*file
,
126 const char __user
*data
,
127 size_t count
, loff_t
*ppos
)
129 struct mem_ctl_info
*mci
= file
->private_data
;
130 struct altr_sdram_mc_data
*drvdata
= mci
->pvt_info
;
131 const struct altr_sdram_prv_data
*priv
= drvdata
->data
;
133 dma_addr_t dma_handle
;
136 ptemp
= dma_alloc_coherent(mci
->pdev
, 16, &dma_handle
, GFP_KERNEL
);
138 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
139 edac_printk(KERN_ERR
, EDAC_MC
,
140 "Inject: Buffer Allocation error\n");
144 regmap_read(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
146 read_reg
&= ~(priv
->ce_set_mask
| priv
->ue_set_mask
);
148 /* Error are injected by writing a word while the SBE or DBE
149 * bit in the CTLCFG register is set. Reading the word will
150 * trigger the SBE or DBE error and the corresponding IRQ.
153 edac_printk(KERN_ALERT
, EDAC_MC
,
154 "Inject Double bit error\n");
155 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
156 (read_reg
| priv
->ue_set_mask
));
158 edac_printk(KERN_ALERT
, EDAC_MC
,
159 "Inject Single bit error\n");
160 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
,
161 (read_reg
| priv
->ce_set_mask
));
164 ptemp
[0] = 0x5A5A5A5A;
165 ptemp
[1] = 0xA5A5A5A5;
167 /* Clear the error injection bits */
168 regmap_write(drvdata
->mc_vbase
, priv
->ce_ue_trgr_offset
, read_reg
);
169 /* Ensure it has been written out */
173 * To trigger the error, we need to read the data back
174 * (the data was written with errors above).
175 * The ACCESS_ONCE macros and printk are used to prevent the
176 * the compiler optimizing these reads out.
178 reg
= ACCESS_ONCE(ptemp
[0]);
179 read_reg
= ACCESS_ONCE(ptemp
[1]);
183 edac_printk(KERN_ALERT
, EDAC_MC
, "Read Data [0x%X, 0x%X]\n",
186 dma_free_coherent(mci
->pdev
, 16, ptemp
, dma_handle
);
191 static const struct file_operations altr_sdr_mc_debug_inject_fops
= {
193 .write
= altr_sdr_mc_err_inject_write
,
194 .llseek
= generic_file_llseek
,
197 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info
*mci
)
199 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
205 edac_debugfs_create_file("inject_ctrl", S_IWUSR
, mci
->debugfs
, mci
,
206 &altr_sdr_mc_debug_inject_fops
);
209 /* Get total memory size from Open Firmware DTB */
210 static unsigned long get_total_mem(void)
212 struct device_node
*np
= NULL
;
213 const unsigned int *reg
, *reg_end
;
215 unsigned long start
, size
, total_mem
= 0;
217 for_each_node_by_type(np
, "memory") {
218 aw
= of_n_addr_cells(np
);
219 sw
= of_n_size_cells(np
);
220 reg
= (const unsigned int *)of_get_property(np
, "reg", &len
);
221 reg_end
= reg
+ (len
/ sizeof(u32
));
225 start
= of_read_number(reg
, aw
);
227 size
= of_read_number(reg
, sw
);
230 } while (reg
< reg_end
);
232 edac_dbg(0, "total_mem 0x%lx\n", total_mem
);
236 static const struct of_device_id altr_sdram_ctrl_of_match
[] = {
237 { .compatible
= "altr,sdram-edac", .data
= &c5_data
},
238 { .compatible
= "altr,sdram-edac-a10", .data
= &a10_data
},
241 MODULE_DEVICE_TABLE(of
, altr_sdram_ctrl_of_match
);
243 static int a10_init(struct regmap
*mc_vbase
)
245 if (regmap_update_bits(mc_vbase
, A10_INTMODE_OFST
,
246 A10_INTMODE_SB_INT
, A10_INTMODE_SB_INT
)) {
247 edac_printk(KERN_ERR
, EDAC_MC
,
248 "Error setting SB IRQ mode\n");
252 if (regmap_write(mc_vbase
, A10_SERRCNTREG_OFST
, 1)) {
253 edac_printk(KERN_ERR
, EDAC_MC
,
254 "Error setting trigger count\n");
261 static int a10_unmask_irq(struct platform_device
*pdev
, u32 mask
)
263 void __iomem
*sm_base
;
266 if (!request_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
),
267 dev_name(&pdev
->dev
))) {
268 edac_printk(KERN_ERR
, EDAC_MC
,
269 "Unable to request mem region\n");
273 sm_base
= ioremap(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
275 edac_printk(KERN_ERR
, EDAC_MC
,
276 "Unable to ioremap device\n");
282 iowrite32(mask
, sm_base
);
287 release_mem_region(A10_SYMAN_INTMASK_CLR
, sizeof(u32
));
292 static int altr_sdram_probe(struct platform_device
*pdev
)
294 const struct of_device_id
*id
;
295 struct edac_mc_layer layers
[2];
296 struct mem_ctl_info
*mci
;
297 struct altr_sdram_mc_data
*drvdata
;
298 const struct altr_sdram_prv_data
*priv
;
299 struct regmap
*mc_vbase
;
300 struct dimm_info
*dimm
;
302 int irq
, irq2
, res
= 0;
303 unsigned long mem_size
, irqflags
= 0;
305 id
= of_match_device(altr_sdram_ctrl_of_match
, &pdev
->dev
);
309 /* Grab the register range from the sdr controller in device tree */
310 mc_vbase
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
312 if (IS_ERR(mc_vbase
)) {
313 edac_printk(KERN_ERR
, EDAC_MC
,
314 "regmap for altr,sdr-syscon lookup failed.\n");
318 /* Check specific dependencies for the module */
319 priv
= of_match_node(altr_sdram_ctrl_of_match
,
320 pdev
->dev
.of_node
)->data
;
322 /* Validate the SDRAM controller has ECC enabled */
323 if (regmap_read(mc_vbase
, priv
->ecc_ctrl_offset
, &read_reg
) ||
324 ((read_reg
& priv
->ecc_ctl_en_mask
) != priv
->ecc_ctl_en_mask
)) {
325 edac_printk(KERN_ERR
, EDAC_MC
,
326 "No ECC/ECC disabled [0x%08X]\n", read_reg
);
330 /* Grab memory size from device tree. */
331 mem_size
= get_total_mem();
333 edac_printk(KERN_ERR
, EDAC_MC
, "Unable to calculate memory size\n");
337 /* Ensure the SDRAM Interrupt is disabled */
338 if (regmap_update_bits(mc_vbase
, priv
->ecc_irq_en_offset
,
339 priv
->ecc_irq_en_mask
, 0)) {
340 edac_printk(KERN_ERR
, EDAC_MC
,
341 "Error disabling SDRAM ECC IRQ\n");
345 /* Toggle to clear the SDRAM Error count */
346 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
347 priv
->ecc_cnt_rst_mask
,
348 priv
->ecc_cnt_rst_mask
)) {
349 edac_printk(KERN_ERR
, EDAC_MC
,
350 "Error clearing SDRAM ECC count\n");
354 if (regmap_update_bits(mc_vbase
, priv
->ecc_cnt_rst_offset
,
355 priv
->ecc_cnt_rst_mask
, 0)) {
356 edac_printk(KERN_ERR
, EDAC_MC
,
357 "Error clearing SDRAM ECC count\n");
361 irq
= platform_get_irq(pdev
, 0);
363 edac_printk(KERN_ERR
, EDAC_MC
,
364 "No irq %d in DT\n", irq
);
368 /* Arria10 has a 2nd IRQ */
369 irq2
= platform_get_irq(pdev
, 1);
371 layers
[0].type
= EDAC_MC_LAYER_CHIP_SELECT
;
373 layers
[0].is_virt_csrow
= true;
374 layers
[1].type
= EDAC_MC_LAYER_CHANNEL
;
376 layers
[1].is_virt_csrow
= false;
377 mci
= edac_mc_alloc(0, ARRAY_SIZE(layers
), layers
,
378 sizeof(struct altr_sdram_mc_data
));
382 mci
->pdev
= &pdev
->dev
;
383 drvdata
= mci
->pvt_info
;
384 drvdata
->mc_vbase
= mc_vbase
;
385 drvdata
->data
= priv
;
386 platform_set_drvdata(pdev
, mci
);
388 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
389 edac_printk(KERN_ERR
, EDAC_MC
,
390 "Unable to get managed device resource\n");
395 mci
->mtype_cap
= MEM_FLAG_DDR3
;
396 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
;
397 mci
->edac_cap
= EDAC_FLAG_SECDED
;
398 mci
->mod_name
= EDAC_MOD_STR
;
399 mci
->mod_ver
= EDAC_VERSION
;
400 mci
->ctl_name
= dev_name(&pdev
->dev
);
401 mci
->scrub_mode
= SCRUB_SW_SRC
;
402 mci
->dev_name
= dev_name(&pdev
->dev
);
405 dimm
->nr_pages
= ((mem_size
- 1) >> PAGE_SHIFT
) + 1;
407 dimm
->dtype
= DEV_X8
;
408 dimm
->mtype
= MEM_DDR3
;
409 dimm
->edac_mode
= EDAC_SECDED
;
411 res
= edac_mc_add_mc(mci
);
415 /* Only the Arria10 has separate IRQs */
417 /* Arria10 specific initialization */
418 res
= a10_init(mc_vbase
);
422 res
= devm_request_irq(&pdev
->dev
, irq2
,
423 altr_sdram_mc_err_handler
,
424 IRQF_SHARED
, dev_name(&pdev
->dev
), mci
);
426 edac_mc_printk(mci
, KERN_ERR
,
427 "Unable to request irq %d\n", irq2
);
432 res
= a10_unmask_irq(pdev
, A10_DDR0_IRQ_MASK
);
436 irqflags
= IRQF_SHARED
;
439 res
= devm_request_irq(&pdev
->dev
, irq
, altr_sdram_mc_err_handler
,
440 irqflags
, dev_name(&pdev
->dev
), mci
);
442 edac_mc_printk(mci
, KERN_ERR
,
443 "Unable to request irq %d\n", irq
);
448 /* Infrastructure ready - enable the IRQ */
449 if (regmap_update_bits(drvdata
->mc_vbase
, priv
->ecc_irq_en_offset
,
450 priv
->ecc_irq_en_mask
, priv
->ecc_irq_en_mask
)) {
451 edac_mc_printk(mci
, KERN_ERR
,
452 "Error enabling SDRAM ECC IRQ\n");
457 altr_sdr_mc_create_debugfs_nodes(mci
);
459 devres_close_group(&pdev
->dev
, NULL
);
464 edac_mc_del_mc(&pdev
->dev
);
466 devres_release_group(&pdev
->dev
, NULL
);
469 edac_printk(KERN_ERR
, EDAC_MC
,
470 "EDAC Probe Failed; Error %d\n", res
);
475 static int altr_sdram_remove(struct platform_device
*pdev
)
477 struct mem_ctl_info
*mci
= platform_get_drvdata(pdev
);
479 edac_mc_del_mc(&pdev
->dev
);
481 platform_set_drvdata(pdev
, NULL
);
487 * If you want to suspend, need to disable EDAC by removing it
488 * from the device tree or defconfig.
491 static int altr_sdram_prepare(struct device
*dev
)
493 pr_err("Suspend not allowed when EDAC is enabled.\n");
498 static const struct dev_pm_ops altr_sdram_pm_ops
= {
499 .prepare
= altr_sdram_prepare
,
503 static struct platform_driver altr_sdram_edac_driver
= {
504 .probe
= altr_sdram_probe
,
505 .remove
= altr_sdram_remove
,
507 .name
= "altr_sdram_edac",
509 .pm
= &altr_sdram_pm_ops
,
511 .of_match_table
= altr_sdram_ctrl_of_match
,
515 module_platform_driver(altr_sdram_edac_driver
);
517 /************************* EDAC Parent Probe *************************/
519 static const struct of_device_id altr_edac_device_of_match
[];
521 static const struct of_device_id altr_edac_of_match
[] = {
522 { .compatible
= "altr,socfpga-ecc-manager" },
525 MODULE_DEVICE_TABLE(of
, altr_edac_of_match
);
527 static int altr_edac_probe(struct platform_device
*pdev
)
529 of_platform_populate(pdev
->dev
.of_node
, altr_edac_device_of_match
,
534 static struct platform_driver altr_edac_driver
= {
535 .probe
= altr_edac_probe
,
537 .name
= "socfpga_ecc_manager",
538 .of_match_table
= altr_edac_of_match
,
541 module_platform_driver(altr_edac_driver
);
543 /************************* EDAC Device Functions *************************/
546 * EDAC Device Functions (shared between various IPs).
547 * The discrete memories use the EDAC Device framework. The probe
548 * and error handling functions are very similar between memories
549 * so they are shared. The memory allocation and freeing for EDAC
550 * trigger testing are different for each memory.
553 static const struct edac_device_prv_data ocramecc_data
;
554 static const struct edac_device_prv_data l2ecc_data
;
555 static const struct edac_device_prv_data a10_ocramecc_data
;
556 static const struct edac_device_prv_data a10_l2ecc_data
;
558 static irqreturn_t
altr_edac_device_handler(int irq
, void *dev_id
)
560 irqreturn_t ret_value
= IRQ_NONE
;
561 struct edac_device_ctl_info
*dci
= dev_id
;
562 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
563 const struct edac_device_prv_data
*priv
= drvdata
->data
;
565 if (irq
== drvdata
->sb_irq
) {
566 if (priv
->ce_clear_mask
)
567 writel(priv
->ce_clear_mask
, drvdata
->base
);
568 edac_device_handle_ce(dci
, 0, 0, drvdata
->edac_dev_name
);
569 ret_value
= IRQ_HANDLED
;
570 } else if (irq
== drvdata
->db_irq
) {
571 if (priv
->ue_clear_mask
)
572 writel(priv
->ue_clear_mask
, drvdata
->base
);
573 edac_device_handle_ue(dci
, 0, 0, drvdata
->edac_dev_name
);
574 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
575 ret_value
= IRQ_HANDLED
;
583 static ssize_t
altr_edac_device_trig(struct file
*file
,
584 const char __user
*user_buf
,
585 size_t count
, loff_t
*ppos
)
588 u32
*ptemp
, i
, error_mask
;
592 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
593 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
594 const struct edac_device_prv_data
*priv
= drvdata
->data
;
595 void *generic_ptr
= edac_dci
->dev
;
597 if (!user_buf
|| get_user(trig_type
, user_buf
))
600 if (!priv
->alloc_mem
)
604 * Note that generic_ptr is initialized to the device * but in
605 * some alloc_functions, this is overridden and returns data.
607 ptemp
= priv
->alloc_mem(priv
->trig_alloc_sz
, &generic_ptr
);
609 edac_printk(KERN_ERR
, EDAC_DEVICE
,
610 "Inject: Buffer Allocation error\n");
614 if (trig_type
== ALTR_UE_TRIGGER_CHAR
)
615 error_mask
= priv
->ue_set_mask
;
617 error_mask
= priv
->ce_set_mask
;
619 edac_printk(KERN_ALERT
, EDAC_DEVICE
,
620 "Trigger Error Mask (0x%X)\n", error_mask
);
622 local_irq_save(flags
);
623 /* write ECC corrupted data out. */
624 for (i
= 0; i
< (priv
->trig_alloc_sz
/ sizeof(*ptemp
)); i
++) {
625 /* Read data so we're in the correct state */
627 if (ACCESS_ONCE(ptemp
[i
]))
629 /* Toggle Error bit (it is latched), leave ECC enabled */
630 writel(error_mask
, (drvdata
->base
+ priv
->set_err_ofst
));
631 writel(priv
->ecc_enable_mask
, (drvdata
->base
+
632 priv
->set_err_ofst
));
635 /* Ensure it has been written out */
637 local_irq_restore(flags
);
640 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Mem Not Cleared\n");
642 /* Read out written data. ECC error caused here */
643 for (i
= 0; i
< ALTR_TRIGGER_READ_WRD_CNT
; i
++)
644 if (ACCESS_ONCE(ptemp
[i
]) != i
)
645 edac_printk(KERN_ERR
, EDAC_DEVICE
,
646 "Read doesn't match written data\n");
649 priv
->free_mem(ptemp
, priv
->trig_alloc_sz
, generic_ptr
);
654 static const struct file_operations altr_edac_device_inject_fops
= {
656 .write
= altr_edac_device_trig
,
657 .llseek
= generic_file_llseek
,
660 static ssize_t
altr_edac_a10_device_trig(struct file
*file
,
661 const char __user
*user_buf
,
662 size_t count
, loff_t
*ppos
);
664 static const struct file_operations altr_edac_a10_device_inject_fops
= {
666 .write
= altr_edac_a10_device_trig
,
667 .llseek
= generic_file_llseek
,
670 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info
*edac_dci
,
671 const struct edac_device_prv_data
*priv
)
673 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
675 if (!IS_ENABLED(CONFIG_EDAC_DEBUG
))
678 drvdata
->debugfs_dir
= edac_debugfs_create_dir(drvdata
->edac_dev_name
);
679 if (!drvdata
->debugfs_dir
)
682 if (!edac_debugfs_create_file(priv
->dbgfs_name
, S_IWUSR
,
683 drvdata
->debugfs_dir
, edac_dci
,
685 debugfs_remove_recursive(drvdata
->debugfs_dir
);
688 static const struct of_device_id altr_edac_device_of_match
[] = {
689 #ifdef CONFIG_EDAC_ALTERA_L2C
690 { .compatible
= "altr,socfpga-l2-ecc", .data
= &l2ecc_data
},
692 #ifdef CONFIG_EDAC_ALTERA_OCRAM
693 { .compatible
= "altr,socfpga-ocram-ecc", .data
= &ocramecc_data
},
697 MODULE_DEVICE_TABLE(of
, altr_edac_device_of_match
);
700 * altr_edac_device_probe()
701 * This is a generic EDAC device driver that will support
702 * various Altera memory devices such as the L2 cache ECC and
703 * OCRAM ECC as well as the memories for other peripherals.
704 * Module specific initialization is done by passing the
705 * function index in the device tree.
707 static int altr_edac_device_probe(struct platform_device
*pdev
)
709 struct edac_device_ctl_info
*dci
;
710 struct altr_edac_device_dev
*drvdata
;
713 struct device_node
*np
= pdev
->dev
.of_node
;
714 char *ecc_name
= (char *)np
->name
;
715 static int dev_instance
;
717 if (!devres_open_group(&pdev
->dev
, NULL
, GFP_KERNEL
)) {
718 edac_printk(KERN_ERR
, EDAC_DEVICE
,
719 "Unable to open devm\n");
723 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
725 edac_printk(KERN_ERR
, EDAC_DEVICE
,
726 "Unable to get mem resource\n");
731 if (!devm_request_mem_region(&pdev
->dev
, r
->start
, resource_size(r
),
732 dev_name(&pdev
->dev
))) {
733 edac_printk(KERN_ERR
, EDAC_DEVICE
,
734 "%s:Error requesting mem region\n", ecc_name
);
739 dci
= edac_device_alloc_ctl_info(sizeof(*drvdata
), ecc_name
,
740 1, ecc_name
, 1, 0, NULL
, 0,
744 edac_printk(KERN_ERR
, EDAC_DEVICE
,
745 "%s: Unable to allocate EDAC device\n", ecc_name
);
750 drvdata
= dci
->pvt_info
;
751 dci
->dev
= &pdev
->dev
;
752 platform_set_drvdata(pdev
, dci
);
753 drvdata
->edac_dev_name
= ecc_name
;
755 drvdata
->base
= devm_ioremap(&pdev
->dev
, r
->start
, resource_size(r
));
759 /* Get driver specific data for this EDAC device */
760 drvdata
->data
= of_match_node(altr_edac_device_of_match
, np
)->data
;
762 /* Check specific dependencies for the module */
763 if (drvdata
->data
->setup
) {
764 res
= drvdata
->data
->setup(drvdata
);
769 drvdata
->sb_irq
= platform_get_irq(pdev
, 0);
770 res
= devm_request_irq(&pdev
->dev
, drvdata
->sb_irq
,
771 altr_edac_device_handler
,
772 0, dev_name(&pdev
->dev
), dci
);
776 drvdata
->db_irq
= platform_get_irq(pdev
, 1);
777 res
= devm_request_irq(&pdev
->dev
, drvdata
->db_irq
,
778 altr_edac_device_handler
,
779 0, dev_name(&pdev
->dev
), dci
);
783 dci
->mod_name
= "Altera ECC Manager";
784 dci
->dev_name
= drvdata
->edac_dev_name
;
786 res
= edac_device_add_device(dci
);
790 altr_create_edacdev_dbgfs(dci
, drvdata
->data
);
792 devres_close_group(&pdev
->dev
, NULL
);
797 edac_device_free_ctl_info(dci
);
799 devres_release_group(&pdev
->dev
, NULL
);
800 edac_printk(KERN_ERR
, EDAC_DEVICE
,
801 "%s:Error setting up EDAC device: %d\n", ecc_name
, res
);
806 static int altr_edac_device_remove(struct platform_device
*pdev
)
808 struct edac_device_ctl_info
*dci
= platform_get_drvdata(pdev
);
809 struct altr_edac_device_dev
*drvdata
= dci
->pvt_info
;
811 debugfs_remove_recursive(drvdata
->debugfs_dir
);
812 edac_device_del_device(&pdev
->dev
);
813 edac_device_free_ctl_info(dci
);
818 static struct platform_driver altr_edac_device_driver
= {
819 .probe
= altr_edac_device_probe
,
820 .remove
= altr_edac_device_remove
,
822 .name
= "altr_edac_device",
823 .of_match_table
= altr_edac_device_of_match
,
826 module_platform_driver(altr_edac_device_driver
);
828 /*********************** OCRAM EDAC Device Functions *********************/
830 #ifdef CONFIG_EDAC_ALTERA_OCRAM
832 * Test for memory's ECC dependencies upon entry because platform specific
833 * startup should have initialized the memory and enabled the ECC.
834 * Can't turn on ECC here because accessing un-initialized memory will
835 * cause CE/UE errors possibly causing an ABORT.
837 static int altr_check_ecc_deps(struct altr_edac_device_dev
*device
)
839 void __iomem
*base
= device
->base
;
840 const struct edac_device_prv_data
*prv
= device
->data
;
842 if (readl(base
+ prv
->ecc_en_ofst
) & prv
->ecc_enable_mask
)
845 edac_printk(KERN_ERR
, EDAC_DEVICE
,
846 "%s: No ECC present or ECC disabled.\n",
847 device
->edac_dev_name
);
851 static void *ocram_alloc_mem(size_t size
, void **other
)
853 struct device_node
*np
;
857 np
= of_find_compatible_node(NULL
, NULL
, "altr,socfpga-ocram-ecc");
861 gp
= of_gen_pool_get(np
, "iram", 0);
866 sram_addr
= (void *)gen_pool_alloc(gp
, size
);
870 memset(sram_addr
, 0, size
);
871 /* Ensure data is written out */
874 /* Remember this handle for freeing later */
880 static void ocram_free_mem(void *p
, size_t size
, void *other
)
882 gen_pool_free((struct gen_pool
*)other
, (u32
)p
, size
);
885 static irqreturn_t
altr_edac_a10_ecc_irq(int irq
, void *dev_id
)
887 struct altr_edac_device_dev
*dci
= dev_id
;
888 void __iomem
*base
= dci
->base
;
890 if (irq
== dci
->sb_irq
) {
891 writel(ALTR_A10_ECC_SERRPENA
,
892 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
893 edac_device_handle_ce(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
896 } else if (irq
== dci
->db_irq
) {
897 writel(ALTR_A10_ECC_DERRPENA
,
898 base
+ ALTR_A10_ECC_INTSTAT_OFST
);
899 edac_device_handle_ue(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
900 if (dci
->data
->panic
)
901 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
911 static const struct edac_device_prv_data ocramecc_data
= {
912 .setup
= altr_check_ecc_deps
,
913 .ce_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_SERR
),
914 .ue_clear_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_DERR
),
915 .dbgfs_name
= "altr_ocram_trigger",
916 .alloc_mem
= ocram_alloc_mem
,
917 .free_mem
= ocram_free_mem
,
918 .ecc_enable_mask
= ALTR_OCR_ECC_EN
,
919 .ecc_en_ofst
= ALTR_OCR_ECC_REG_OFFSET
,
920 .ce_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJS
),
921 .ue_set_mask
= (ALTR_OCR_ECC_EN
| ALTR_OCR_ECC_INJD
),
922 .set_err_ofst
= ALTR_OCR_ECC_REG_OFFSET
,
923 .trig_alloc_sz
= ALTR_TRIG_OCRAM_BYTE_SIZE
,
924 .inject_fops
= &altr_edac_device_inject_fops
,
927 static const struct edac_device_prv_data a10_ocramecc_data
= {
928 .setup
= altr_check_ecc_deps
,
929 .ce_clear_mask
= ALTR_A10_ECC_SERRPENA
,
930 .ue_clear_mask
= ALTR_A10_ECC_DERRPENA
,
931 .irq_status_mask
= A10_SYSMGR_ECC_INTSTAT_OCRAM
,
932 .dbgfs_name
= "altr_ocram_trigger",
933 .ecc_enable_mask
= ALTR_A10_OCRAM_ECC_EN_CTL
,
934 .ecc_en_ofst
= ALTR_A10_ECC_CTRL_OFST
,
935 .ce_set_mask
= ALTR_A10_ECC_TSERRA
,
936 .ue_set_mask
= ALTR_A10_ECC_TDERRA
,
937 .set_err_ofst
= ALTR_A10_ECC_INTTEST_OFST
,
938 .ecc_irq_handler
= altr_edac_a10_ecc_irq
,
939 .inject_fops
= &altr_edac_a10_device_inject_fops
,
941 * OCRAM panic on uncorrectable error because sleep/resume
942 * functions and FPGA contents are stored in OCRAM. Prefer
943 * a kernel panic over executing/loading corrupted data.
948 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
950 /********************* L2 Cache EDAC Device Functions ********************/
952 #ifdef CONFIG_EDAC_ALTERA_L2C
954 static void *l2_alloc_mem(size_t size
, void **other
)
956 struct device
*dev
= *other
;
957 void *ptemp
= devm_kzalloc(dev
, size
, GFP_KERNEL
);
962 /* Make sure everything is written out */
966 * Clean all cache levels up to LoC (includes L2)
967 * This ensures the corrupted data is written into
968 * L2 cache for readback test (which causes ECC error).
975 static void l2_free_mem(void *p
, size_t size
, void *other
)
977 struct device
*dev
= other
;
984 * altr_l2_check_deps()
985 * Test for L2 cache ECC dependencies upon entry because
986 * platform specific startup should have initialized the L2
987 * memory and enabled the ECC.
988 * Bail if ECC is not enabled.
989 * Note that L2 Cache Enable is forced at build time.
991 static int altr_l2_check_deps(struct altr_edac_device_dev
*device
)
993 void __iomem
*base
= device
->base
;
994 const struct edac_device_prv_data
*prv
= device
->data
;
996 if ((readl(base
) & prv
->ecc_enable_mask
) ==
997 prv
->ecc_enable_mask
)
1000 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1001 "L2: No ECC present, or ECC disabled\n");
1005 static irqreturn_t
altr_edac_a10_l2_irq(int irq
, void *dev_id
)
1007 struct altr_edac_device_dev
*dci
= dev_id
;
1009 if (irq
== dci
->sb_irq
) {
1010 regmap_write(dci
->edac
->ecc_mgr_map
,
1011 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST
,
1012 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB
);
1013 edac_device_handle_ce(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
1016 } else if (irq
== dci
->db_irq
) {
1017 regmap_write(dci
->edac
->ecc_mgr_map
,
1018 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST
,
1019 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB
);
1020 edac_device_handle_ue(dci
->edac_dev
, 0, 0, dci
->edac_dev_name
);
1021 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1031 static const struct edac_device_prv_data l2ecc_data
= {
1032 .setup
= altr_l2_check_deps
,
1035 .dbgfs_name
= "altr_l2_trigger",
1036 .alloc_mem
= l2_alloc_mem
,
1037 .free_mem
= l2_free_mem
,
1038 .ecc_enable_mask
= ALTR_L2_ECC_EN
,
1039 .ce_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJS
),
1040 .ue_set_mask
= (ALTR_L2_ECC_EN
| ALTR_L2_ECC_INJD
),
1041 .set_err_ofst
= ALTR_L2_ECC_REG_OFFSET
,
1042 .trig_alloc_sz
= ALTR_TRIG_L2C_BYTE_SIZE
,
1043 .inject_fops
= &altr_edac_device_inject_fops
,
1046 static const struct edac_device_prv_data a10_l2ecc_data
= {
1047 .setup
= altr_l2_check_deps
,
1048 .ce_clear_mask
= ALTR_A10_L2_ECC_SERR_CLR
,
1049 .ue_clear_mask
= ALTR_A10_L2_ECC_MERR_CLR
,
1050 .irq_status_mask
= A10_SYSMGR_ECC_INTSTAT_L2
,
1051 .dbgfs_name
= "altr_l2_trigger",
1052 .alloc_mem
= l2_alloc_mem
,
1053 .free_mem
= l2_free_mem
,
1054 .ecc_enable_mask
= ALTR_A10_L2_ECC_EN_CTL
,
1055 .ce_set_mask
= ALTR_A10_L2_ECC_CE_INJ_MASK
,
1056 .ue_set_mask
= ALTR_A10_L2_ECC_UE_INJ_MASK
,
1057 .set_err_ofst
= ALTR_A10_L2_ECC_INJ_OFST
,
1058 .ecc_irq_handler
= altr_edac_a10_l2_irq
,
1059 .trig_alloc_sz
= ALTR_TRIG_L2C_BYTE_SIZE
,
1060 .inject_fops
= &altr_edac_device_inject_fops
,
1063 #endif /* CONFIG_EDAC_ALTERA_L2C */
1065 /********************* Arria10 EDAC Device Functions *************************/
1066 static const struct of_device_id altr_edac_a10_device_of_match
[] = {
1067 #ifdef CONFIG_EDAC_ALTERA_L2C
1068 { .compatible
= "altr,socfpga-a10-l2-ecc", .data
= &a10_l2ecc_data
},
1070 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1071 { .compatible
= "altr,socfpga-a10-ocram-ecc",
1072 .data
= &a10_ocramecc_data
},
1076 MODULE_DEVICE_TABLE(of
, altr_edac_a10_device_of_match
);
1079 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1080 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1081 * manager manages the IRQs and the children.
1082 * Based on xgene_edac.c peripheral code.
1085 static ssize_t
altr_edac_a10_device_trig(struct file
*file
,
1086 const char __user
*user_buf
,
1087 size_t count
, loff_t
*ppos
)
1089 struct edac_device_ctl_info
*edac_dci
= file
->private_data
;
1090 struct altr_edac_device_dev
*drvdata
= edac_dci
->pvt_info
;
1091 const struct edac_device_prv_data
*priv
= drvdata
->data
;
1092 void __iomem
*set_addr
= (drvdata
->base
+ priv
->set_err_ofst
);
1093 unsigned long flags
;
1096 if (!user_buf
|| get_user(trig_type
, user_buf
))
1099 local_irq_save(flags
);
1100 if (trig_type
== ALTR_UE_TRIGGER_CHAR
)
1101 writel(priv
->ue_set_mask
, set_addr
);
1103 writel(priv
->ce_set_mask
, set_addr
);
1104 /* Ensure the interrupt test bits are set */
1106 local_irq_restore(flags
);
1111 static void altr_edac_a10_irq_handler(struct irq_desc
*desc
)
1113 int dberr
, bit
, sm_offset
, irq_status
;
1114 struct altr_arria10_edac
*edac
= irq_desc_get_handler_data(desc
);
1115 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1116 int irq
= irq_desc_get_irq(desc
);
1118 dberr
= (irq
== edac
->db_irq
) ? 1 : 0;
1119 sm_offset
= dberr
? A10_SYSMGR_ECC_INTSTAT_DERR_OFST
:
1120 A10_SYSMGR_ECC_INTSTAT_SERR_OFST
;
1122 chained_irq_enter(chip
, desc
);
1124 regmap_read(edac
->ecc_mgr_map
, sm_offset
, &irq_status
);
1126 for_each_set_bit(bit
, (unsigned long *)&irq_status
, 32) {
1127 irq
= irq_linear_revmap(edac
->domain
, dberr
* 32 + bit
);
1129 generic_handle_irq(irq
);
1132 chained_irq_exit(chip
, desc
);
1135 static int validate_parent_available(struct device_node
*np
)
1137 struct device_node
*parent
;
1140 /* Ensure parent device is enabled if parent node exists */
1141 parent
= of_parse_phandle(np
, "altr,ecc-parent", 0);
1142 if (parent
&& !of_device_is_available(parent
))
1145 of_node_put(parent
);
1149 static int altr_edac_a10_device_add(struct altr_arria10_edac
*edac
,
1150 struct device_node
*np
)
1152 struct edac_device_ctl_info
*dci
;
1153 struct altr_edac_device_dev
*altdev
;
1154 char *ecc_name
= (char *)np
->name
;
1155 struct resource res
;
1158 const struct edac_device_prv_data
*prv
;
1159 /* Get matching node and check for valid result */
1160 const struct of_device_id
*pdev_id
=
1161 of_match_node(altr_edac_a10_device_of_match
, np
);
1162 if (IS_ERR_OR_NULL(pdev_id
))
1165 /* Get driver specific data for this EDAC device */
1166 prv
= pdev_id
->data
;
1167 if (IS_ERR_OR_NULL(prv
))
1170 if (validate_parent_available(np
))
1173 if (!devres_open_group(edac
->dev
, altr_edac_a10_device_add
, GFP_KERNEL
))
1176 rc
= of_address_to_resource(np
, 0, &res
);
1178 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1179 "%s: no resource address\n", ecc_name
);
1180 goto err_release_group
;
1183 edac_idx
= edac_device_alloc_index();
1184 dci
= edac_device_alloc_ctl_info(sizeof(*altdev
), ecc_name
,
1185 1, ecc_name
, 1, 0, NULL
, 0,
1189 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1190 "%s: Unable to allocate EDAC device\n", ecc_name
);
1192 goto err_release_group
;
1195 altdev
= dci
->pvt_info
;
1196 dci
->dev
= edac
->dev
;
1197 altdev
->edac_dev_name
= ecc_name
;
1198 altdev
->edac_idx
= edac_idx
;
1199 altdev
->edac
= edac
;
1200 altdev
->edac_dev
= dci
;
1202 altdev
->ddev
= *edac
->dev
;
1203 dci
->dev
= &altdev
->ddev
;
1204 dci
->ctl_name
= "Altera ECC Manager";
1205 dci
->mod_name
= ecc_name
;
1206 dci
->dev_name
= ecc_name
;
1208 altdev
->base
= devm_ioremap_resource(edac
->dev
, &res
);
1209 if (IS_ERR(altdev
->base
)) {
1210 rc
= PTR_ERR(altdev
->base
);
1211 goto err_release_group1
;
1214 /* Check specific dependencies for the module */
1215 if (altdev
->data
->setup
) {
1216 rc
= altdev
->data
->setup(altdev
);
1218 goto err_release_group1
;
1221 altdev
->sb_irq
= irq_of_parse_and_map(np
, 0);
1222 if (!altdev
->sb_irq
) {
1223 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error allocating SBIRQ\n");
1225 goto err_release_group1
;
1227 rc
= devm_request_irq(edac
->dev
, altdev
->sb_irq
,
1228 prv
->ecc_irq_handler
,
1229 IRQF_SHARED
, ecc_name
, altdev
);
1231 edac_printk(KERN_ERR
, EDAC_DEVICE
, "No DBERR IRQ resource\n");
1232 goto err_release_group1
;
1235 altdev
->db_irq
= irq_of_parse_and_map(np
, 1);
1236 if (!altdev
->db_irq
) {
1237 edac_printk(KERN_ERR
, EDAC_DEVICE
, "Error allocating DBIRQ\n");
1239 goto err_release_group1
;
1241 rc
= devm_request_irq(edac
->dev
, altdev
->db_irq
,
1242 prv
->ecc_irq_handler
,
1243 IRQF_SHARED
, ecc_name
, altdev
);
1245 edac_printk(KERN_ERR
, EDAC_DEVICE
, "No DBERR IRQ resource\n");
1246 goto err_release_group1
;
1249 rc
= edac_device_add_device(dci
);
1251 dev_err(edac
->dev
, "edac_device_add_device failed\n");
1253 goto err_release_group1
;
1256 altr_create_edacdev_dbgfs(dci
, prv
);
1258 list_add(&altdev
->next
, &edac
->a10_ecc_devices
);
1260 devres_remove_group(edac
->dev
, altr_edac_a10_device_add
);
1265 edac_device_free_ctl_info(dci
);
1267 devres_release_group(edac
->dev
, NULL
);
1268 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1269 "%s:Error setting up EDAC device: %d\n", ecc_name
, rc
);
1274 static void a10_eccmgr_irq_mask(struct irq_data
*d
)
1276 struct altr_arria10_edac
*edac
= irq_data_get_irq_chip_data(d
);
1278 regmap_write(edac
->ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_SET_OFST
,
1282 static void a10_eccmgr_irq_unmask(struct irq_data
*d
)
1284 struct altr_arria10_edac
*edac
= irq_data_get_irq_chip_data(d
);
1286 regmap_write(edac
->ecc_mgr_map
, A10_SYSMGR_ECC_INTMASK_CLR_OFST
,
1290 static int a10_eccmgr_irqdomain_map(struct irq_domain
*d
, unsigned int irq
,
1291 irq_hw_number_t hwirq
)
1293 struct altr_arria10_edac
*edac
= d
->host_data
;
1295 irq_set_chip_and_handler(irq
, &edac
->irq_chip
, handle_simple_irq
);
1296 irq_set_chip_data(irq
, edac
);
1297 irq_set_noprobe(irq
);
1302 struct irq_domain_ops a10_eccmgr_ic_ops
= {
1303 .map
= a10_eccmgr_irqdomain_map
,
1304 .xlate
= irq_domain_xlate_twocell
,
1307 static int altr_edac_a10_probe(struct platform_device
*pdev
)
1309 struct altr_arria10_edac
*edac
;
1310 struct device_node
*child
;
1312 edac
= devm_kzalloc(&pdev
->dev
, sizeof(*edac
), GFP_KERNEL
);
1316 edac
->dev
= &pdev
->dev
;
1317 platform_set_drvdata(pdev
, edac
);
1318 INIT_LIST_HEAD(&edac
->a10_ecc_devices
);
1320 edac
->ecc_mgr_map
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
1321 "altr,sysmgr-syscon");
1322 if (IS_ERR(edac
->ecc_mgr_map
)) {
1323 edac_printk(KERN_ERR
, EDAC_DEVICE
,
1324 "Unable to get syscon altr,sysmgr-syscon\n");
1325 return PTR_ERR(edac
->ecc_mgr_map
);
1328 edac
->irq_chip
.name
= pdev
->dev
.of_node
->name
;
1329 edac
->irq_chip
.irq_mask
= a10_eccmgr_irq_mask
;
1330 edac
->irq_chip
.irq_unmask
= a10_eccmgr_irq_unmask
;
1331 edac
->domain
= irq_domain_add_linear(pdev
->dev
.of_node
, 64,
1332 &a10_eccmgr_ic_ops
, edac
);
1333 if (!edac
->domain
) {
1334 dev_err(&pdev
->dev
, "Error adding IRQ domain\n");
1338 edac
->sb_irq
= platform_get_irq(pdev
, 0);
1339 if (edac
->sb_irq
< 0) {
1340 dev_err(&pdev
->dev
, "No SBERR IRQ resource\n");
1341 return edac
->sb_irq
;
1344 irq_set_chained_handler_and_data(edac
->sb_irq
,
1345 altr_edac_a10_irq_handler
,
1348 edac
->db_irq
= platform_get_irq(pdev
, 1);
1349 if (edac
->db_irq
< 0) {
1350 dev_err(&pdev
->dev
, "No DBERR IRQ resource\n");
1351 return edac
->db_irq
;
1353 irq_set_chained_handler_and_data(edac
->db_irq
,
1354 altr_edac_a10_irq_handler
,
1357 for_each_child_of_node(pdev
->dev
.of_node
, child
) {
1358 if (!of_device_is_available(child
))
1360 if (of_device_is_compatible(child
, "altr,socfpga-a10-l2-ecc"))
1361 altr_edac_a10_device_add(edac
, child
);
1362 else if (of_device_is_compatible(child
,
1363 "altr,socfpga-a10-ocram-ecc"))
1364 altr_edac_a10_device_add(edac
, child
);
1365 else if (of_device_is_compatible(child
,
1366 "altr,sdram-edac-a10"))
1367 of_platform_populate(pdev
->dev
.of_node
,
1368 altr_sdram_ctrl_of_match
,
1375 static const struct of_device_id altr_edac_a10_of_match
[] = {
1376 { .compatible
= "altr,socfpga-a10-ecc-manager" },
1379 MODULE_DEVICE_TABLE(of
, altr_edac_a10_of_match
);
1381 static struct platform_driver altr_edac_a10_driver
= {
1382 .probe
= altr_edac_a10_probe
,
1384 .name
= "socfpga_a10_ecc_manager",
1385 .of_match_table
= altr_edac_a10_of_match
,
1388 module_platform_driver(altr_edac_a10_driver
);
1390 MODULE_LICENSE("GPL v2");
1391 MODULE_AUTHOR("Thor Thayer");
1392 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");