drivers/edac/e7xxx_edac.c

   1 /*
   2  * Intel e7xxx Memory Controller kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * See "enum e7xxx_chips" below for supported chipsets
   8  *
   9  * Written by Thayne Harbaugh
  10  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  11  *      http://www.anime.net/~goemon/linux-ecc/
  12  *
  13  * Contributors:
  14  *      Eric Biederman (Linux Networx)
  15  *      Tom Zimmerman (Linux Networx)
  16  *      Jim Garlick (Lawrence Livermore National Labs)
  17  *      Dave Peterson (Lawrence Livermore National Labs)
  18  *      That One Guy (Some other place)
  19  *      Wang Zhenyu (intel.com)
  20  *
  21  * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/init.h>
  27 #include <linux/pci.h>
  28 #include <linux/pci_ids.h>
  29 #include <linux/slab.h>
  30 #include <linux/edac.h>
  31 #include "edac_core.h"
  32
  33 #define E7XXX_REVISION " Ver: 2.0.2 " __DATE__
  34 #define EDAC_MOD_STR    "e7xxx_edac"
  35
  36 #define e7xxx_printk(level, fmt, arg...) \
  37         edac_printk(level, "e7xxx", fmt, ##arg)
  38
  39 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
  40         edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
  41
  42 #ifndef PCI_DEVICE_ID_INTEL_7205_0
  43 #define PCI_DEVICE_ID_INTEL_7205_0      0x255d
  44 #endif                          /* PCI_DEVICE_ID_INTEL_7205_0 */
  45
  46 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
  47 #define PCI_DEVICE_ID_INTEL_7205_1_ERR  0x2551
  48 #endif                          /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
  49
  50 #ifndef PCI_DEVICE_ID_INTEL_7500_0
  51 #define PCI_DEVICE_ID_INTEL_7500_0      0x2540
  52 #endif                          /* PCI_DEVICE_ID_INTEL_7500_0 */
  53
  54 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
  55 #define PCI_DEVICE_ID_INTEL_7500_1_ERR  0x2541
  56 #endif                          /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
  57
  58 #ifndef PCI_DEVICE_ID_INTEL_7501_0
  59 #define PCI_DEVICE_ID_INTEL_7501_0      0x254c
  60 #endif                          /* PCI_DEVICE_ID_INTEL_7501_0 */
  61
  62 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
  63 #define PCI_DEVICE_ID_INTEL_7501_1_ERR  0x2541
  64 #endif                          /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
  65
  66 #ifndef PCI_DEVICE_ID_INTEL_7505_0
  67 #define PCI_DEVICE_ID_INTEL_7505_0      0x2550
  68 #endif                          /* PCI_DEVICE_ID_INTEL_7505_0 */
  69
  70 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
  71 #define PCI_DEVICE_ID_INTEL_7505_1_ERR  0x2551
  72 #endif                          /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
  73
  74 #define E7XXX_NR_CSROWS         8       /* number of csrows */
  75 #define E7XXX_NR_DIMMS          8       /* FIXME - is this correct? */
  76
  77 /* E7XXX register addresses - device 0 function 0 */
  78 #define E7XXX_DRB               0x60    /* DRAM row boundary register (8b) */
  79 #define E7XXX_DRA               0x70    /* DRAM row attribute register (8b) */
  80                                         /*
  81                                          * 31   Device width row 7 0=x8 1=x4
  82                                          * 27   Device width row 6
  83                                          * 23   Device width row 5
  84                                          * 19   Device width row 4
  85                                          * 15   Device width row 3
  86                                          * 11   Device width row 2
  87                                          *  7   Device width row 1
  88                                          *  3   Device width row 0
  89                                          */
  90 #define E7XXX_DRC               0x7C    /* DRAM controller mode reg (32b) */
  91                                         /*
  92                                          * 22    Number channels 0=1,1=2
  93                                          * 19:18 DRB Granularity 32/64MB
  94                                          */
  95 #define E7XXX_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
  96 #define E7XXX_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
  97 #define E7XXX_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
  98
  99 /* E7XXX register addresses - device 0 function 1 */
 100 #define E7XXX_DRAM_FERR         0x80    /* DRAM first error register (8b) */
 101 #define E7XXX_DRAM_NERR         0x82    /* DRAM next error register (8b) */
 102 #define E7XXX_DRAM_CELOG_ADD    0xA0    /* DRAM first correctable memory */
 103                                         /*     error address register (32b) */
 104                                         /*
 105                                          * 31:28 Reserved
 106                                          * 27:6  CE address (4k block 33:12)
 107                                          *  5:0  Reserved
 108                                          */
 109 #define E7XXX_DRAM_UELOG_ADD    0xB0    /* DRAM first uncorrectable memory */
 110                                         /*     error address register (32b) */
 111                                         /*
 112                                          * 31:28 Reserved
 113                                          * 27:6  CE address (4k block 33:12)
 114                                          *  5:0  Reserved
 115                                          */
 116 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0  /* DRAM first correctable memory */
 117                                         /*     error syndrome register (16b) */
 118
 119 enum e7xxx_chips {
 120         E7500 = 0,
 121         E7501,
 122         E7505,
 123         E7205,
 124 };
 125
 126 struct e7xxx_pvt {
 127         struct pci_dev *bridge_ck;
 128         u32 tolm;
 129         u32 remapbase;
 130         u32 remaplimit;
 131         const struct e7xxx_dev_info *dev_info;
 132 };
 133
 134 struct e7xxx_dev_info {
 135         u16 err_dev;
 136         const char *ctl_name;
 137 };
 138
 139 struct e7xxx_error_info {
 140         u8 dram_ferr;
 141         u8 dram_nerr;
 142         u32 dram_celog_add;
 143         u16 dram_celog_syndrome;
 144         u32 dram_uelog_add;
 145 };
 146
 147 static const struct e7xxx_dev_info e7xxx_devs[] = {
 148         [E7500] = {
 149                    .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
 150                    .ctl_name = "E7500"},
 151         [E7501] = {
 152                    .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
 153                    .ctl_name = "E7501"},
 154         [E7505] = {
 155                    .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
 156                    .ctl_name = "E7505"},
 157         [E7205] = {
 158                    .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
 159                    .ctl_name = "E7205"},
 160 };
 161
 162 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
 163 static inline int e7xxx_find_channel(u16 syndrome)
 164 {
 165         debugf3("%s()\n", __func__);
 166
 167         if ((syndrome & 0xff00) == 0)
 168                 return 0;
 169
 170         if ((syndrome & 0x00ff) == 0)
 171                 return 1;
 172
 173         if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
 174                 return 0;
 175
 176         return 1;
 177 }
 178
 179 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
 180                                       unsigned long page)
 181 {
 182         u32 remap;
 183         struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;
 184
 185         debugf3("%s()\n", __func__);
 186
 187         if ((page < pvt->tolm) ||
 188             ((page >= 0x100000) && (page < pvt->remapbase)))
 189                 return page;
 190
 191         remap = (page - pvt->tolm) + pvt->remapbase;
 192
 193         if (remap < pvt->remaplimit)
 194                 return remap;
 195
 196         e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
 197         return pvt->tolm - 1;
 198 }
 199
 200 static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
 201 {
 202         u32 error_1b, page;
 203         u16 syndrome;
 204         int row;
 205         int channel;
 206
 207         debugf3("%s()\n", __func__);
 208         /* read the error address */
 209         error_1b = info->dram_celog_add;
 210         /* FIXME - should use PAGE_SHIFT */
 211         page = error_1b >> 6;   /* convert the address to 4k page */
 212         /* read the syndrome */
 213         syndrome = info->dram_celog_syndrome;
 214         /* FIXME - check for -1 */
 215         row = edac_mc_find_csrow_by_page(mci, page);
 216         /* convert syndrome to channel */
 217         channel = e7xxx_find_channel(syndrome);
 218         edac_mc_handle_ce(mci, page, 0, syndrome, row, channel, "e7xxx CE");
 219 }
 220
 221 static void process_ce_no_info(struct mem_ctl_info *mci)
 222 {
 223         debugf3("%s()\n", __func__);
 224         edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
 225 }
 226
 227 static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
 228 {
 229         u32 error_2b, block_page;
 230         int row;
 231
 232         debugf3("%s()\n", __func__);
 233         /* read the error address */
 234         error_2b = info->dram_uelog_add;
 235         /* FIXME - should use PAGE_SHIFT */
 236         block_page = error_2b >> 6;     /* convert to 4k address */
 237         row = edac_mc_find_csrow_by_page(mci, block_page);
 238         edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
 239 }
 240
 241 static void process_ue_no_info(struct mem_ctl_info *mci)
 242 {
 243         debugf3("%s()\n", __func__);
 244         edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
 245 }
 246
 247 static void e7xxx_get_error_info(struct mem_ctl_info *mci,
 248                                  struct e7xxx_error_info *info)
 249 {
 250         struct e7xxx_pvt *pvt;
 251
 252         pvt = (struct e7xxx_pvt *)mci->pvt_info;
 253         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
 254         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);
 255
 256         if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
 257                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
 258                                       &info->dram_celog_add);
 259                 pci_read_config_word(pvt->bridge_ck,
 260                                      E7XXX_DRAM_CELOG_SYNDROME,
 261                                      &info->dram_celog_syndrome);
 262         }
 263
 264         if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
 265                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
 266                                       &info->dram_uelog_add);
 267
 268         if (info->dram_ferr & 3)
 269                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
 270
 271         if (info->dram_nerr & 3)
 272                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
 273 }
 274
 275 static int e7xxx_process_error_info(struct mem_ctl_info *mci,
 276                                     struct e7xxx_error_info *info,
 277                                     int handle_errors)
 278 {
 279         int error_found;
 280
 281         error_found = 0;
 282
 283         /* decode and report errors */
 284         if (info->dram_ferr & 1) {      /* check first error correctable */
 285                 error_found = 1;
 286
 287                 if (handle_errors)
 288                         process_ce(mci, info);
 289         }
 290
 291         if (info->dram_ferr & 2) {      /* check first error uncorrectable */
 292                 error_found = 1;
 293
 294                 if (handle_errors)
 295                         process_ue(mci, info);
 296         }
 297
 298         if (info->dram_nerr & 1) {      /* check next error correctable */
 299                 error_found = 1;
 300
 301                 if (handle_errors) {
 302                         if (info->dram_ferr & 1)
 303                                 process_ce_no_info(mci);
 304                         else
 305                                 process_ce(mci, info);
 306                 }
 307         }
 308
 309         if (info->dram_nerr & 2) {      /* check next error uncorrectable */
 310                 error_found = 1;
 311
 312                 if (handle_errors) {
 313                         if (info->dram_ferr & 2)
 314                                 process_ue_no_info(mci);
 315                         else
 316                                 process_ue(mci, info);
 317                 }
 318         }
 319
 320         return error_found;
 321 }
 322
 323 static void e7xxx_check(struct mem_ctl_info *mci)
 324 {
 325         struct e7xxx_error_info info;
 326
 327         debugf3("%s()\n", __func__);
 328         e7xxx_get_error_info(mci, &info);
 329         e7xxx_process_error_info(mci, &info, 1);
 330 }
 331
 332 /* Return 1 if dual channel mode is active.  Else return 0. */
 333 static inline int dual_channel_active(u32 drc, int dev_idx)
 334 {
 335         return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
 336 }
 337
 338 /* Return DRB granularity (0=32mb, 1=64mb). */
 339 static inline int drb_granularity(u32 drc, int dev_idx)
 340 {
 341         /* only e7501 can be single channel */
 342         return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
 343 }
 344
 345 static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
 346                               int dev_idx, u32 drc)
 347 {
 348         unsigned long last_cumul_size;
 349         int index;
 350         u8 value;
 351         u32 dra, cumul_size;
 352         int drc_chan, drc_drbg, drc_ddim, mem_dev;
 353         struct csrow_info *csrow;
 354
 355         pci_read_config_dword(pdev, E7XXX_DRA, &dra);
 356         drc_chan = dual_channel_active(drc, dev_idx);
 357         drc_drbg = drb_granularity(drc, dev_idx);
 358         drc_ddim = (drc >> 20) & 0x3;
 359         last_cumul_size = 0;
 360
 361         /* The dram row boundary (DRB) reg values are boundary address
 362          * for each DRAM row with a granularity of 32 or 64MB (single/dual
 363          * channel operation).  DRB regs are cumulative; therefore DRB7 will
 364          * contain the total memory contained in all eight rows.
 365          */
 366         for (index = 0; index < mci->nr_csrows; index++) {
 367                 /* mem_dev 0=x8, 1=x4 */
 368                 mem_dev = (dra >> (index * 4 + 3)) & 0x1;
 369                 csrow = &mci->csrows[index];
 370
 371                 pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
 372                 /* convert a 64 or 32 MiB DRB to a page size. */
 373                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
 374                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 375                         cumul_size);
 376                 if (cumul_size == last_cumul_size)
 377                         continue;       /* not populated */
 378
 379                 csrow->first_page = last_cumul_size;
 380                 csrow->last_page = cumul_size - 1;
 381                 csrow->nr_pages = cumul_size - last_cumul_size;
 382                 last_cumul_size = cumul_size;
 383                 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
 384                 csrow->mtype = MEM_RDDR;        /* only one type supported */
 385                 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
 386
 387                 /*
 388                  * if single channel or x8 devices then SECDED
 389                  * if dual channel and x4 then S4ECD4ED
 390                  */
 391                 if (drc_ddim) {
 392                         if (drc_chan && mem_dev) {
 393                                 csrow->edac_mode = EDAC_S4ECD4ED;
 394                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
 395                         } else {
 396                                 csrow->edac_mode = EDAC_SECDED;
 397                                 mci->edac_cap |= EDAC_FLAG_SECDED;
 398                         }
 399                 } else
 400                         csrow->edac_mode = EDAC_NONE;
 401         }
 402 }
 403
 404 static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
 405 {
 406         u16 pci_data;
 407         struct mem_ctl_info *mci = NULL;
 408         struct e7xxx_pvt *pvt = NULL;
 409         u32 drc;
 410         int drc_chan;
 411         struct e7xxx_error_info discard;
 412
 413         debugf0("%s(): mci\n", __func__);
 414
 415         /* make sure error reporting method is sane */
 416         switch (edac_op_state) {
 417         case EDAC_OPSTATE_POLL:
 418         case EDAC_OPSTATE_NMI:
 419                 break;
 420         default:
 421                 edac_op_state = EDAC_OPSTATE_POLL;
 422                 break;
 423         }
 424
 425         pci_read_config_dword(pdev, E7XXX_DRC, &drc);
 426
 427         drc_chan = dual_channel_active(drc, dev_idx);
 428         mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1);
 429
 430         if (mci == NULL)
 431                 return -ENOMEM;
 432
 433         debugf3("%s(): init mci\n", __func__);
 434         mci->mtype_cap = MEM_FLAG_RDDR;
 435         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
 436             EDAC_FLAG_S4ECD4ED;
 437         /* FIXME - what if different memory types are in different csrows? */
 438         mci->mod_name = EDAC_MOD_STR;
 439         mci->mod_ver = E7XXX_REVISION;
 440         mci->dev = &pdev->dev;
 441         debugf3("%s(): init pvt\n", __func__);
 442         pvt = (struct e7xxx_pvt *)mci->pvt_info;
 443         pvt->dev_info = &e7xxx_devs[dev_idx];
 444         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
 445                                         pvt->dev_info->err_dev, pvt->bridge_ck);
 446
 447         if (!pvt->bridge_ck) {
 448                 e7xxx_printk(KERN_ERR, "error reporting device not found:"
 449                              "vendor %x device 0x%x (broken BIOS?)\n",
 450                              PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
 451                 goto fail0;
 452         }
 453
 454         debugf3("%s(): more mci init\n", __func__);
 455         mci->ctl_name = pvt->dev_info->ctl_name;
 456         mci->dev_name = pci_name(pdev);
 457         mci->edac_check = e7xxx_check;
 458         mci->ctl_page_to_phys = ctl_page_to_phys;
 459         e7xxx_init_csrows(mci, pdev, dev_idx, drc);
 460         mci->edac_cap |= EDAC_FLAG_NONE;
 461         debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
 462         /* load the top of low memory, remap base, and remap limit vars */
 463         pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
 464         pvt->tolm = ((u32) pci_data) << 4;
 465         pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
 466         pvt->remapbase = ((u32) pci_data) << 14;
 467         pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
 468         pvt->remaplimit = ((u32) pci_data) << 14;
 469         e7xxx_printk(KERN_INFO,
 470                      "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
 471                      pvt->remapbase, pvt->remaplimit);
 472
 473         /* clear any pending errors, or initial state bits */
 474         e7xxx_get_error_info(mci, &discard);
 475
 476         /* Here we assume that we will never see multiple instances of this
 477          * type of memory controller.  The ID is therefore hardcoded to 0.
 478          */
 479         if (edac_mc_add_mc(mci, 0)) {
 480                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 481                 goto fail1;
 482         }
 483
 484         /* get this far and it's successful */
 485         debugf3("%s(): success\n", __func__);
 486         return 0;
 487
 488       fail1:
 489         pci_dev_put(pvt->bridge_ck);
 490
 491       fail0:
 492         edac_mc_free(mci);
 493
 494         return -ENODEV;
 495 }
 496
 497 /* returns count (>= 0), or negative on error */
 498 static int __devinit e7xxx_init_one(struct pci_dev *pdev,
 499                                     const struct pci_device_id *ent)
 500 {
 501         debugf0("%s()\n", __func__);
 502
 503         /* wake up and enable device */
 504         return pci_enable_device(pdev) ?
 505             -EIO : e7xxx_probe1(pdev, ent->driver_data);
 506 }
 507
 508 static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
 509 {
 510         struct mem_ctl_info *mci;
 511         struct e7xxx_pvt *pvt;
 512
 513         debugf0("%s()\n", __func__);
 514
 515         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 516                 return;
 517
 518         pvt = (struct e7xxx_pvt *)mci->pvt_info;
 519         pci_dev_put(pvt->bridge_ck);
 520         edac_mc_free(mci);
 521 }
 522
 523 static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
 524         {
 525          PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 526          E7205},
 527         {
 528          PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 529          E7500},
 530         {
 531          PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 532          E7501},
 533         {
 534          PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 535          E7505},
 536         {
 537          0,
 538          }                      /* 0 terminated list. */
 539 };
 540
 541 MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
 542
 543 static struct pci_driver e7xxx_driver = {
 544         .name = EDAC_MOD_STR,
 545         .probe = e7xxx_init_one,
 546         .remove = __devexit_p(e7xxx_remove_one),
 547         .id_table = e7xxx_pci_tbl,
 548 };
 549
 550 static int __init e7xxx_init(void)
 551 {
 552         return pci_register_driver(&e7xxx_driver);
 553 }
 554
 555 static void __exit e7xxx_exit(void)
 556 {
 557         pci_unregister_driver(&e7xxx_driver);
 558 }
 559
 560 module_init(e7xxx_init);
 561 module_exit(e7xxx_exit);
 562
 563 MODULE_LICENSE("GPL");
 564 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
 565               "Based on.work by Dan Hollis et al");
 566 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
 567 module_param(edac_op_state, int, 0444);
 568 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");