drivers/edac/edac_core.h

   1 /*
   2  * Defines, structures, APIs for edac_core module
   3  *
   4  * (C) 2007 Linux Networx (http://lnxi.com)
   5  * This file may be distributed under the terms of the
   6  * GNU General Public License.
   7  *
   8  * Written by Thayne Harbaugh
   9  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  10  *      http://www.anime.net/~goemon/linux-ecc/
  11  *
  12  * NMI handling support added by
  13  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  14  *
  15  * Refactored for multi-source files:
  16  *      Doug Thompson <norsk5@xmission.com>
  17  *
  18  */
  19
  20 #ifndef _EDAC_CORE_H_
  21 #define _EDAC_CORE_H_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/smp.h>
  28 #include <linux/pci.h>
  29 #include <linux/time.h>
  30 #include <linux/nmi.h>
  31 #include <linux/rcupdate.h>
  32 #include <linux/completion.h>
  33 #include <linux/kobject.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/sysdev.h>
  36 #include <linux/workqueue.h>
  37
  38 #define EDAC_MC_LABEL_LEN       31
  39 #define EDAC_DEVICE_NAME_LEN    31
  40 #define EDAC_ATTRIB_VALUE_LEN   15
  41 #define MC_PROC_NAME_MAX_LEN    7
  42
  43 #if PAGE_SHIFT < 20
  44 #define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  45 #else                           /* PAGE_SHIFT > 20 */
  46 #define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  47 #endif
  48
  49 #define edac_printk(level, prefix, fmt, arg...) \
  50         printk(level "EDAC " prefix ": " fmt, ##arg)
  51
  52 #define edac_printk_verbose(level, prefix, fmt, arg...) \
  53         printk(level "EDAC " prefix ": " "in %s, line at %d: " fmt,     \
  54                __FILE__, __LINE__, ##arg)
  55
  56 #define edac_mc_printk(mci, level, fmt, arg...) \
  57         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  58
  59 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  60         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  61
  62 /* edac_device printk */
  63 #define edac_device_printk(ctl, level, fmt, arg...) \
  64         printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
  65
  66 /* edac_pci printk */
  67 #define edac_pci_printk(ctl, level, fmt, arg...) \
  68         printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
  69
  70 /* prefixes for edac_printk() and edac_mc_printk() */
  71 #define EDAC_MC "MC"
  72 #define EDAC_PCI "PCI"
  73 #define EDAC_DEBUG "DEBUG"
  74
  75 #ifdef CONFIG_EDAC_DEBUG
  76 extern int edac_debug_level;
  77
  78 #ifndef CONFIG_EDAC_DEBUG_VERBOSE
  79 #define edac_debug_printk(level, fmt, arg...)                           \
  80         do {                                                            \
  81                 if (level <= edac_debug_level)                          \
  82                         edac_printk(KERN_DEBUG, EDAC_DEBUG,             \
  83                                     "%s: " fmt, __func__, ##arg);       \
  84         } while (0)
  85 #else  /* CONFIG_EDAC_DEBUG_VERBOSE */
  86 #define edac_debug_printk(level, fmt, arg...)                            \
  87         do {                                                             \
  88                 if (level <= edac_debug_level)                           \
  89                         edac_printk_verbose(KERN_DEBUG, EDAC_DEBUG, fmt, \
  90                                             ##arg);                     \
  91         } while (0)
  92 #endif
  93
  94 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  95 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  96 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  97 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  98 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  99
 100 #else                           /* !CONFIG_EDAC_DEBUG */
 101
 102 #define debugf0( ... )
 103 #define debugf1( ... )
 104 #define debugf2( ... )
 105 #define debugf3( ... )
 106 #define debugf4( ... )
 107
 108 #endif                          /* !CONFIG_EDAC_DEBUG */
 109
 110 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
 111         PCI_DEVICE_ID_ ## vend ## _ ## dev
 112
 113 #define edac_dev_name(dev) (dev)->dev_name
 114
 115 /* memory devices */
 116 enum dev_type {
 117         DEV_UNKNOWN = 0,
 118         DEV_X1,
 119         DEV_X2,
 120         DEV_X4,
 121         DEV_X8,
 122         DEV_X16,
 123         DEV_X32,                /* Do these parts exist? */
 124         DEV_X64                 /* Do these parts exist? */
 125 };
 126
 127 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 128 #define DEV_FLAG_X1             BIT(DEV_X1)
 129 #define DEV_FLAG_X2             BIT(DEV_X2)
 130 #define DEV_FLAG_X4             BIT(DEV_X4)
 131 #define DEV_FLAG_X8             BIT(DEV_X8)
 132 #define DEV_FLAG_X16            BIT(DEV_X16)
 133 #define DEV_FLAG_X32            BIT(DEV_X32)
 134 #define DEV_FLAG_X64            BIT(DEV_X64)
 135
 136 /* memory types */
 137 enum mem_type {
 138         MEM_EMPTY = 0,          /* Empty csrow */
 139         MEM_RESERVED,           /* Reserved csrow type */
 140         MEM_UNKNOWN,            /* Unknown csrow type */
 141         MEM_FPM,                /* Fast page mode */
 142         MEM_EDO,                /* Extended data out */
 143         MEM_BEDO,               /* Burst Extended data out */
 144         MEM_SDR,                /* Single data rate SDRAM */
 145         MEM_RDR,                /* Registered single data rate SDRAM */
 146         MEM_DDR,                /* Double data rate SDRAM */
 147         MEM_RDDR,               /* Registered Double data rate SDRAM */
 148         MEM_RMBS,               /* Rambus DRAM */
 149         MEM_DDR2,               /* DDR2 RAM */
 150         MEM_FB_DDR2,            /* fully buffered DDR2 */
 151         MEM_RDDR2,              /* Registered DDR2 RAM */
 152         MEM_XDR,                /* Rambus XDR */
 153 };
 154
 155 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 156 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 157 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 158 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 159 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 160 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 161 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 162 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 163 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 164 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 165 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 166 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 167 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 168 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 169 #define MEM_FLAG_XDR            BIT(MEM_XDR)
 170
 171 /* chipset Error Detection and Correction capabilities and mode */
 172 enum edac_type {
 173         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 174         EDAC_NONE,              /* Doesnt support ECC */
 175         EDAC_RESERVED,          /* Reserved ECC type */
 176         EDAC_PARITY,            /* Detects parity errors */
 177         EDAC_EC,                /* Error Checking - no correction */
 178         EDAC_SECDED,            /* Single bit error correction, Double detection */
 179         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 180         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 181         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 182         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 183 };
 184
 185 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 186 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 187 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 188 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 189 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 190 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 191 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 192 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 193 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 194
 195 /* scrubbing capabilities */
 196 enum scrub_type {
 197         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 198         SCRUB_NONE,             /* No scrubber */
 199         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 200         SCRUB_SW_SRC,           /* Software scrub only errors */
 201         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 202         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 203         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 204         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 205         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 206         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 207 };
 208
 209 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 210 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 211 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 212 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 213 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 214 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 215 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 216 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 217
 218 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 219
 220 /* EDAC internal operation states */
 221 #define OP_ALLOC                0x100
 222 #define OP_RUNNING_POLL         0x201
 223 #define OP_RUNNING_INTERRUPT    0x202
 224 #define OP_RUNNING_POLL_INTR    0x203
 225 #define OP_OFFLINE              0x300
 226
 227 /*
 228  * There are several things to be aware of that aren't at all obvious:
 229  *
 230  *
 231  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 232  *
 233  * These are some of the many terms that are thrown about that don't always
 234  * mean what people think they mean (Inconceivable!).  In the interest of
 235  * creating a common ground for discussion, terms and their definitions
 236  * will be established.
 237  *
 238  * Memory devices:      The individual chip on a memory stick.  These devices
 239  *                      commonly output 4 and 8 bits each.  Grouping several
 240  *                      of these in parallel provides 64 bits which is common
 241  *                      for a memory stick.
 242  *
 243  * Memory Stick:        A printed circuit board that agregates multiple
 244  *                      memory devices in parallel.  This is the atomic
 245  *                      memory component that is purchaseable by Joe consumer
 246  *                      and loaded into a memory socket.
 247  *
 248  * Socket:              A physical connector on the motherboard that accepts
 249  *                      a single memory stick.
 250  *
 251  * Channel:             Set of memory devices on a memory stick that must be
 252  *                      grouped in parallel with one or more additional
 253  *                      channels from other memory sticks.  This parallel
 254  *                      grouping of the output from multiple channels are
 255  *                      necessary for the smallest granularity of memory access.
 256  *                      Some memory controllers are capable of single channel -
 257  *                      which means that memory sticks can be loaded
 258  *                      individually.  Other memory controllers are only
 259  *                      capable of dual channel - which means that memory
 260  *                      sticks must be loaded as pairs (see "socket set").
 261  *
 262  * Chip-select row:     All of the memory devices that are selected together.
 263  *                      for a single, minimum grain of memory access.
 264  *                      This selects all of the parallel memory devices across
 265  *                      all of the parallel channels.  Common chip-select rows
 266  *                      for single channel are 64 bits, for dual channel 128
 267  *                      bits.
 268  *
 269  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
 270  *                      Motherboards commonly drive two chip-select pins to
 271  *                      a memory stick. A single-ranked stick, will occupy
 272  *                      only one of those rows. The other will be unused.
 273  *
 274  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 275  *                      access different sets of memory devices.  The two
 276  *                      rows cannot be accessed concurrently.
 277  *
 278  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 279  *                      A double-sided stick has two chip-select rows which
 280  *                      access different sets of memory devices.  The two
 281  *                      rows cannot be accessed concurrently.  "Double-sided"
 282  *                      is irrespective of the memory devices being mounted
 283  *                      on both sides of the memory stick.
 284  *
 285  * Socket set:          All of the memory sticks that are required for for
 286  *                      a single memory access or all of the memory sticks
 287  *                      spanned by a chip-select row.  A single socket set
 288  *                      has two chip-select rows and if double-sided sticks
 289  *                      are used these will occupy those chip-select rows.
 290  *
 291  * Bank:                This term is avoided because it is unclear when
 292  *                      needing to distinguish between chip-select rows and
 293  *                      socket sets.
 294  *
 295  * Controller pages:
 296  *
 297  * Physical pages:
 298  *
 299  * Virtual pages:
 300  *
 301  *
 302  * STRUCTURE ORGANIZATION AND CHOICES
 303  *
 304  *
 305  *
 306  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 307  */
 308
 309 struct channel_info {
 310         int chan_idx;           /* channel index */
 311         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 312         char label[EDAC_MC_LABEL_LEN + 1];      /* DIMM label on motherboard */
 313         struct csrow_info *csrow;       /* the parent */
 314 };
 315
 316 struct csrow_info {
 317         unsigned long first_page;       /* first page number in dimm */
 318         unsigned long last_page;        /* last page number in dimm */
 319         unsigned long page_mask;        /* used for interleaving -
 320                                          * 0UL for non intlv
 321                                          */
 322         u32 nr_pages;           /* number of pages in csrow */
 323         u32 grain;              /* granularity of reported error in bytes */
 324         int csrow_idx;          /* the chip-select row */
 325         enum dev_type dtype;    /* memory device type */
 326         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 327         u32 ce_count;           /* Correctable Errors for this csrow */
 328         enum mem_type mtype;    /* memory csrow type */
 329         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 330         struct mem_ctl_info *mci;       /* the parent */
 331
 332         struct kobject kobj;    /* sysfs kobject for this csrow */
 333
 334         /* channel information for this csrow */
 335         u32 nr_channels;
 336         struct channel_info *channels;
 337 };
 338
 339 /* mcidev_sysfs_attribute structure
 340  *      used for driver sysfs attributes and in mem_ctl_info
 341  *      sysfs top level entries
 342  */
 343 struct mcidev_sysfs_attribute {
 344         struct attribute attr;
 345         ssize_t (*show)(struct mem_ctl_info *,char *);
 346         ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
 347 };
 348
 349 /* MEMORY controller information structure
 350  */
 351 struct mem_ctl_info {
 352         struct list_head link;  /* for global list of mem_ctl_info structs */
 353
 354         struct module *owner;   /* Module owner of this control struct */
 355
 356         unsigned long mtype_cap;        /* memory types supported by mc */
 357         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 358         unsigned long edac_cap; /* configuration capabilities - this is
 359                                  * closely related to edac_ctl_cap.  The
 360                                  * difference is that the controller may be
 361                                  * capable of s4ecd4ed which would be listed
 362                                  * in edac_ctl_cap, but if channels aren't
 363                                  * capable of s4ecd4ed then the edac_cap would
 364                                  * not have that capability.
 365                                  */
 366         unsigned long scrub_cap;        /* chipset scrub capabilities */
 367         enum scrub_type scrub_mode;     /* current scrub mode */
 368
 369         /* Translates sdram memory scrub rate given in bytes/sec to the
 370            internal representation and configures whatever else needs
 371            to be configured.
 372          */
 373         int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 374
 375         /* Get the current sdram memory scrub rate from the internal
 376            representation and converts it to the closest matching
 377            bandwith in bytes/sec.
 378          */
 379         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 380
 381
 382         /* pointer to edac checking routine */
 383         void (*edac_check) (struct mem_ctl_info * mci);
 384
 385         /*
 386          * Remaps memory pages: controller pages to physical pages.
 387          * For most MC's, this will be NULL.
 388          */
 389         /* FIXME - why not send the phys page to begin with? */
 390         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 391                                            unsigned long page);
 392         int mc_idx;
 393         int nr_csrows;
 394         struct csrow_info *csrows;
 395         /*
 396          * FIXME - what about controllers on other busses? - IDs must be
 397          * unique.  dev pointer should be sufficiently unique, but
 398          * BUS:SLOT.FUNC numbers may not be unique.
 399          */
 400         struct device *dev;
 401         const char *mod_name;
 402         const char *mod_ver;
 403         const char *ctl_name;
 404         const char *dev_name;
 405         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 406         void *pvt_info;
 407         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 408         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 409         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 410         u32 ce_count;           /* Total Correctable Errors for this MC */
 411         unsigned long start_time;       /* mci load start time (in jiffies) */
 412
 413         /* this stuff is for safe removal of mc devices from global list while
 414          * NMI handlers may be traversing list
 415          */
 416         struct rcu_head rcu;
 417         struct completion complete;
 418
 419         /* edac sysfs device control */
 420         struct kobject edac_mci_kobj;
 421
 422         /* Additional top controller level attributes, but specified
 423          * by the low level driver.
 424          *
 425          * Set by the low level driver to provide attributes at the
 426          * controller level, same level as 'ue_count' and 'ce_count' above.
 427          * An array of structures, NULL terminated
 428          *
 429          * If attributes are desired, then set to array of attributes
 430          * If no attributes are desired, leave NULL
 431          */
 432         struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 433
 434         /* work struct for this MC */
 435         struct delayed_work work;
 436
 437         /* the internal state of this controller instance */
 438         int op_state;
 439 };
 440
 441 /*
 442  * The following are the structures to provide for a generic
 443  * or abstract 'edac_device'. This set of structures and the
 444  * code that implements the APIs for the same, provide for
 445  * registering EDAC type devices which are NOT standard memory.
 446  *
 447  * CPU caches (L1 and L2)
 448  * DMA engines
 449  * Core CPU swithces
 450  * Fabric switch units
 451  * PCIe interface controllers
 452  * other EDAC/ECC type devices that can be monitored for
 453  * errors, etc.
 454  *
 455  * It allows for a 2 level set of hiearchry. For example:
 456  *
 457  * cache could be composed of L1, L2 and L3 levels of cache.
 458  * Each CPU core would have its own L1 cache, while sharing
 459  * L2 and maybe L3 caches.
 460  *
 461  * View them arranged, via the sysfs presentation:
 462  * /sys/devices/system/edac/..
 463  *
 464  *      mc/             <existing memory device directory>
 465  *      cpu/cpu0/..     <L1 and L2 block directory>
 466  *              /L1-cache/ce_count
 467  *                       /ue_count
 468  *              /L2-cache/ce_count
 469  *                       /ue_count
 470  *      cpu/cpu1/..     <L1 and L2 block directory>
 471  *              /L1-cache/ce_count
 472  *                       /ue_count
 473  *              /L2-cache/ce_count
 474  *                       /ue_count
 475  *      ...
 476  *
 477  *      the L1 and L2 directories would be "edac_device_block's"
 478  */
 479
 480 struct edac_device_counter {
 481         u32 ue_count;
 482         u32 ce_count;
 483 };
 484
 485 /* forward reference */
 486 struct edac_device_ctl_info;
 487 struct edac_device_block;
 488
 489 /* edac_dev_sysfs_attribute structure
 490  *      used for driver sysfs attributes in mem_ctl_info
 491  *      for extra controls and attributes:
 492  *              like high level error Injection controls
 493  */
 494 struct edac_dev_sysfs_attribute {
 495         struct attribute attr;
 496         ssize_t (*show)(struct edac_device_ctl_info *, char *);
 497         ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
 498 };
 499
 500 /* edac_dev_sysfs_block_attribute structure
 501  *
 502  *      used in leaf 'block' nodes for adding controls/attributes
 503  *
 504  *      each block in each instance of the containing control structure
 505  *      can have an array of the following. The show and store functions
 506  *      will be filled in with the show/store function in the
 507  *      low level driver.
 508  *
 509  *      The 'value' field will be the actual value field used for
 510  *      counting
 511  */
 512 struct edac_dev_sysfs_block_attribute {
 513         struct attribute attr;
 514         ssize_t (*show)(struct kobject *, struct attribute *, char *);
 515         ssize_t (*store)(struct kobject *, struct attribute *,
 516                         const char *, size_t);
 517         struct edac_device_block *block;
 518
 519         unsigned int value;
 520 };
 521
 522 /* device block control structure */
 523 struct edac_device_block {
 524         struct edac_device_instance *instance;  /* Up Pointer */
 525         char name[EDAC_DEVICE_NAME_LEN + 1];
 526
 527         struct edac_device_counter counters;    /* basic UE and CE counters */
 528
 529         int nr_attribs;         /* how many attributes */
 530
 531         /* this block's attributes, could be NULL */
 532         struct edac_dev_sysfs_block_attribute *block_attributes;
 533
 534         /* edac sysfs device control */
 535         struct kobject kobj;
 536 };
 537
 538 /* device instance control structure */
 539 struct edac_device_instance {
 540         struct edac_device_ctl_info *ctl;       /* Up pointer */
 541         char name[EDAC_DEVICE_NAME_LEN + 4];
 542
 543         struct edac_device_counter counters;    /* instance counters */
 544
 545         u32 nr_blocks;          /* how many blocks */
 546         struct edac_device_block *blocks;       /* block array */
 547
 548         /* edac sysfs device control */
 549         struct kobject kobj;
 550 };
 551
 552
 553 /*
 554  * Abstract edac_device control info structure
 555  *
 556  */
 557 struct edac_device_ctl_info {
 558         /* for global list of edac_device_ctl_info structs */
 559         struct list_head link;
 560
 561         struct module *owner;   /* Module owner of this control struct */
 562
 563         int dev_idx;
 564
 565         /* Per instance controls for this edac_device */
 566         int log_ue;             /* boolean for logging UEs */
 567         int log_ce;             /* boolean for logging CEs */
 568         int panic_on_ue;        /* boolean for panic'ing on an UE */
 569         unsigned poll_msec;     /* number of milliseconds to poll interval */
 570         unsigned long delay;    /* number of jiffies for poll_msec */
 571
 572         /* Additional top controller level attributes, but specified
 573          * by the low level driver.
 574          *
 575          * Set by the low level driver to provide attributes at the
 576          * controller level, same level as 'ue_count' and 'ce_count' above.
 577          * An array of structures, NULL terminated
 578          *
 579          * If attributes are desired, then set to array of attributes
 580          * If no attributes are desired, leave NULL
 581          */
 582         struct edac_dev_sysfs_attribute *sysfs_attributes;
 583
 584         /* pointer to main 'edac' class in sysfs */
 585         struct sysdev_class *edac_class;
 586
 587         /* the internal state of this controller instance */
 588         int op_state;
 589         /* work struct for this instance */
 590         struct delayed_work work;
 591
 592         /* pointer to edac polling checking routine:
 593          *      If NOT NULL: points to polling check routine
 594          *      If NULL: Then assumes INTERRUPT operation, where
 595          *              MC driver will receive events
 596          */
 597         void (*edac_check) (struct edac_device_ctl_info * edac_dev);
 598
 599         struct device *dev;     /* pointer to device structure */
 600
 601         const char *mod_name;   /* module name */
 602         const char *ctl_name;   /* edac controller  name */
 603         const char *dev_name;   /* pci/platform/etc... name */
 604
 605         void *pvt_info;         /* pointer to 'private driver' info */
 606
 607         unsigned long start_time;       /* edac_device load start time (jiffies) */
 608
 609         /* these are for safe removal of mc devices from global list while
 610          * NMI handlers may be traversing list
 611          */
 612         struct rcu_head rcu;
 613         struct completion removal_complete;
 614
 615         /* sysfs top name under 'edac' directory
 616          * and instance name:
 617          *      cpu/cpu0/...
 618          *      cpu/cpu1/...
 619          *      cpu/cpu2/...
 620          *      ...
 621          */
 622         char name[EDAC_DEVICE_NAME_LEN + 1];
 623
 624         /* Number of instances supported on this control structure
 625          * and the array of those instances
 626          */
 627         u32 nr_instances;
 628         struct edac_device_instance *instances;
 629
 630         /* Event counters for the this whole EDAC Device */
 631         struct edac_device_counter counters;
 632
 633         /* edac sysfs device control for the 'name'
 634          * device this structure controls
 635          */
 636         struct kobject kobj;
 637 };
 638
 639 /* To get from the instance's wq to the beginning of the ctl structure */
 640 #define to_edac_mem_ctl_work(w) \
 641                 container_of(w, struct mem_ctl_info, work)
 642
 643 #define to_edac_device_ctl_work(w) \
 644                 container_of(w,struct edac_device_ctl_info,work)
 645
 646 /*
 647  * The alloc() and free() functions for the 'edac_device' control info
 648  * structure. A MC driver will allocate one of these for each edac_device
 649  * it is going to control/register with the EDAC CORE.
 650  */
 651 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
 652                 unsigned sizeof_private,
 653                 char *edac_device_name, unsigned nr_instances,
 654                 char *edac_block_name, unsigned nr_blocks,
 655                 unsigned offset_value,
 656                 struct edac_dev_sysfs_block_attribute *block_attributes,
 657                 unsigned nr_attribs,
 658                 int device_index);
 659
 660 /* The offset value can be:
 661  *      -1 indicating no offset value
 662  *      0 for zero-based block numbers
 663  *      1 for 1-based block number
 664  *      other for other-based block number
 665  */
 666 #define BLOCK_OFFSET_VALUE_OFF  ((unsigned) -1)
 667
 668 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
 669
 670 #ifdef CONFIG_PCI
 671
 672 struct edac_pci_counter {
 673         atomic_t pe_count;
 674         atomic_t npe_count;
 675 };
 676
 677 /*
 678  * Abstract edac_pci control info structure
 679  *
 680  */
 681 struct edac_pci_ctl_info {
 682         /* for global list of edac_pci_ctl_info structs */
 683         struct list_head link;
 684
 685         int pci_idx;
 686
 687         struct sysdev_class *edac_class;        /* pointer to class */
 688
 689         /* the internal state of this controller instance */
 690         int op_state;
 691         /* work struct for this instance */
 692         struct delayed_work work;
 693
 694         /* pointer to edac polling checking routine:
 695          *      If NOT NULL: points to polling check routine
 696          *      If NULL: Then assumes INTERRUPT operation, where
 697          *              MC driver will receive events
 698          */
 699         void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
 700
 701         struct device *dev;     /* pointer to device structure */
 702
 703         const char *mod_name;   /* module name */
 704         const char *ctl_name;   /* edac controller  name */
 705         const char *dev_name;   /* pci/platform/etc... name */
 706
 707         void *pvt_info;         /* pointer to 'private driver' info */
 708
 709         unsigned long start_time;       /* edac_pci load start time (jiffies) */
 710
 711         /* these are for safe removal of devices from global list while
 712          * NMI handlers may be traversing list
 713          */
 714         struct rcu_head rcu;
 715         struct completion complete;
 716
 717         /* sysfs top name under 'edac' directory
 718          * and instance name:
 719          *      cpu/cpu0/...
 720          *      cpu/cpu1/...
 721          *      cpu/cpu2/...
 722          *      ...
 723          */
 724         char name[EDAC_DEVICE_NAME_LEN + 1];
 725
 726         /* Event counters for the this whole EDAC Device */
 727         struct edac_pci_counter counters;
 728
 729         /* edac sysfs device control for the 'name'
 730          * device this structure controls
 731          */
 732         struct kobject kobj;
 733         struct completion kobj_complete;
 734 };
 735
 736 #define to_edac_pci_ctl_work(w) \
 737                 container_of(w, struct edac_pci_ctl_info,work)
 738
 739 /* write all or some bits in a byte-register*/
 740 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 741                                    u8 mask)
 742 {
 743         if (mask != 0xff) {
 744                 u8 buf;
 745
 746                 pci_read_config_byte(pdev, offset, &buf);
 747                 value &= mask;
 748                 buf &= ~mask;
 749                 value |= buf;
 750         }
 751
 752         pci_write_config_byte(pdev, offset, value);
 753 }
 754
 755 /* write all or some bits in a word-register*/
 756 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 757                                     u16 value, u16 mask)
 758 {
 759         if (mask != 0xffff) {
 760                 u16 buf;
 761
 762                 pci_read_config_word(pdev, offset, &buf);
 763                 value &= mask;
 764                 buf &= ~mask;
 765                 value |= buf;
 766         }
 767
 768         pci_write_config_word(pdev, offset, value);
 769 }
 770
 771 /*
 772  * pci_write_bits32
 773  *
 774  * edac local routine to do pci_write_config_dword, but adds
 775  * a mask parameter. If mask is all ones, ignore the mask.
 776  * Otherwise utilize the mask to isolate specified bits
 777  *
 778  * write all or some bits in a dword-register
 779  */
 780 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 781                                     u32 value, u32 mask)
 782 {
 783         if (mask != 0xffffffff) {
 784                 u32 buf;
 785
 786                 pci_read_config_dword(pdev, offset, &buf);
 787                 value &= mask;
 788                 buf &= ~mask;
 789                 value |= buf;
 790         }
 791
 792         pci_write_config_dword(pdev, offset, value);
 793 }
 794
 795 #endif                          /* CONFIG_PCI */
 796
 797 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 798                                           unsigned nr_chans, int edac_index);
 799 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
 800 extern void edac_mc_free(struct mem_ctl_info *mci);
 801 extern struct mem_ctl_info *edac_mc_find(int idx);
 802 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
 803 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 804                                       unsigned long page);
 805
 806 /*
 807  * The no info errors are used when error overflows are reported.
 808  * There are a limited number of error logging registers that can
 809  * be exausted.  When all registers are exhausted and an additional
 810  * error occurs then an error overflow register records that an
 811  * error occured and the type of error, but doesn't have any
 812  * further information.  The ce/ue versions make for cleaner
 813  * reporting logic and function interface - reduces conditional
 814  * statement clutter and extra function arguments.
 815  */
 816 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 817                               unsigned long page_frame_number,
 818                               unsigned long offset_in_page,
 819                               unsigned long syndrome, int row, int channel,
 820                               const char *msg);
 821 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 822                                       const char *msg);
 823 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 824                               unsigned long page_frame_number,
 825                               unsigned long offset_in_page, int row,
 826                               const char *msg);
 827 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 828                                       const char *msg);
 829 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
 830                                   unsigned int channel0, unsigned int channel1,
 831                                   char *msg);
 832 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
 833                                   unsigned int channel, char *msg);
 834
 835 /*
 836  * edac_device APIs
 837  */
 838 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
 839 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
 840 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
 841                                 int inst_nr, int block_nr, const char *msg);
 842 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
 843                                 int inst_nr, int block_nr, const char *msg);
 844 extern int edac_device_alloc_index(void);
 845
 846 /*
 847  * edac_pci APIs
 848  */
 849 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
 850                                 const char *edac_pci_name);
 851
 852 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
 853
 854 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
 855                                 unsigned long value);
 856
 857 extern int edac_pci_alloc_index(void);
 858 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
 859 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
 860
 861 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
 862                                 struct device *dev,
 863                                 const char *mod_name);
 864
 865 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
 866 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
 867 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
 868
 869 /*
 870  * edac misc APIs
 871  */
 872 extern char *edac_op_state_to_string(int op_state);
 873
 874 #endif                          /* _EDAC_CORE_H_ */