2 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
4 * This file may be distributed under the terms of the
5 * GNU General Public License version 2 only.
7 * Copyright (c) 2010 by:
8 * Mauro Carvalho Chehab <mchehab@redhat.com>
10 * Red Hat Inc. http://www.redhat.com
12 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://www.intel.com/Assets/PDF/datasheet/318082.pdf
15 * TODO: The chipset allow checking for PCI Express errors also. Currently,
16 * the driver covers only memory error errors
18 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/pci_ids.h>
25 #include <linux/slab.h>
26 #include <linux/edac.h>
27 #include <linux/mmzone.h>
29 #include "edac_core.h"
32 * Alter this version for the I7300 module when modifications are made
34 #define I7300_REVISION " Ver: 1.0.0 " __DATE__
36 #define EDAC_MOD_STR "i7300_edac"
38 #define i7300_printk(level, fmt, arg...) \
39 edac_printk(level, "i7300", fmt, ##arg)
41 #define i7300_mc_printk(mci, level, fmt, arg...) \
42 edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
45 * Memory topology is organized as:
46 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
47 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
48 * Each channel can have to 8 DIMM sets (called as SLOTS)
49 * Slots should generally be filled in pairs
50 * Except on Single Channel mode of operation
51 * just slot 0/channel0 filled on this mode
52 * On normal operation mode, the two channels on a branch should be
53 * filled together for the same SLOT#
54 * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
55 * channels on both branches should be filled
58 /* Limits for i7300 */
60 #define MAX_BRANCHES 2
61 #define MAX_CH_PER_BRANCH 2
62 #define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES)
65 #define to_channel(ch, branch) ((((branch)) << 1) | (ch))
67 #define to_csrow(slot, ch, branch) \
68 (to_channel(ch, branch) | ((slot) << 2))
72 * All 3 functions of Device 16 (0,1,2) share the SAME DID and
73 * uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2),
74 * PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
75 * for device 21 (0,1).
78 /****************************************************
79 * i7300 Register definitions for memory enumberation
80 ****************************************************/
84 * Function 0: System Address (not documented)
85 * Function 1: Memory Branch Map, Control, Errors Register
88 /* OFFSETS for Function 0 */
89 #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
90 #define MAXCH 0x56 /* Max Channel Number */
91 #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
93 /* OFFSETS for Function 1 */
94 #define MC_SETTINGS 0x40
96 #define IS_MIRRORED(mc) ((mc) & (1 << 16))
97 #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5))
98 #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31))
99 #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8))
110 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
111 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
112 * seems that we cannot use this information directly for the same usage.
113 * Each memory slot may have up to 2 AMB interfaces, one for income and another
114 * for outcome interface to the next slot.
115 * For now, the driver just stores the AMB present registers, but rely only at
116 * the MTR info to detect memory.
117 * Datasheet is also not clear about how to map each AMBPRESENT registers to
118 * one of the 4 available channels.
120 #define AMBPRESENT_0 0x64
121 #define AMBPRESENT_1 0x66
123 const static u16 mtr_regs
[MAX_SLOTS
] = {
124 0x80, 0x84, 0x88, 0x8c,
125 0x82, 0x86, 0x8a, 0x8e
128 /* Defines to extract the vaious fields from the
129 * MTRx - Memory Technology Registers
131 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8))
132 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7))
133 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
134 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4)
135 #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0)
136 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
137 #define MTR_DRAM_BANKS_ADDR_BITS 2
138 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
139 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
140 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
142 #ifdef CONFIG_EDAC_DEBUG
144 static const char *numrow_toString
[] = {
152 static const char *numcol_toString
[] = {
153 "1,024 - 10 columns",
154 "2,048 - 11 columns",
155 "4,096 - 12 columns",
160 /************************************************
161 * i7300 Register definitions for error detection
162 ************************************************/
164 * Device 16.2: Global Error Registers
167 #define FERR_GLOBAL_HI 0x48
168 static const char *ferr_global_hi_name
[] = {
169 [3] = "FSB 3 Fatal Error",
170 [2] = "FSB 2 Fatal Error",
171 [1] = "FSB 1 Fatal Error",
172 [0] = "FSB 0 Fatal Error",
174 #define ferr_global_hi_is_fatal(errno) 1
176 #define FERR_GLOBAL_LO 0x40
177 static const char *ferr_global_lo_name
[] = {
178 [31] = "Internal MCH Fatal Error",
179 [30] = "Intel QuickData Technology Device Fatal Error",
180 [29] = "FSB1 Fatal Error",
181 [28] = "FSB0 Fatal Error",
182 [27] = "FBD Channel 3 Fatal Error",
183 [26] = "FBD Channel 2 Fatal Error",
184 [25] = "FBD Channel 1 Fatal Error",
185 [24] = "FBD Channel 0 Fatal Error",
186 [23] = "PCI Express Device 7Fatal Error",
187 [22] = "PCI Express Device 6 Fatal Error",
188 [21] = "PCI Express Device 5 Fatal Error",
189 [20] = "PCI Express Device 4 Fatal Error",
190 [19] = "PCI Express Device 3 Fatal Error",
191 [18] = "PCI Express Device 2 Fatal Error",
192 [17] = "PCI Express Device 1 Fatal Error",
193 [16] = "ESI Fatal Error",
194 [15] = "Internal MCH Non-Fatal Error",
195 [14] = "Intel QuickData Technology Device Non Fatal Error",
196 [13] = "FSB1 Non-Fatal Error",
197 [12] = "FSB 0 Non-Fatal Error",
198 [11] = "FBD Channel 3 Non-Fatal Error",
199 [10] = "FBD Channel 2 Non-Fatal Error",
200 [9] = "FBD Channel 1 Non-Fatal Error",
201 [8] = "FBD Channel 0 Non-Fatal Error",
202 [7] = "PCI Express Device 7 Non-Fatal Error",
203 [6] = "PCI Express Device 6 Non-Fatal Error",
204 [5] = "PCI Express Device 5 Non-Fatal Error",
205 [4] = "PCI Express Device 4 Non-Fatal Error",
206 [3] = "PCI Express Device 3 Non-Fatal Error",
207 [2] = "PCI Express Device 2 Non-Fatal Error",
208 [1] = "PCI Express Device 1 Non-Fatal Error",
209 [0] = "ESI Non-Fatal Error",
211 #define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1)
213 /* Device name and register DID (Device ID) */
214 struct i7300_dev_info
{
215 const char *ctl_name
; /* name for this device */
216 u16 fsb_mapping_errors
; /* DID for the branchmap,control */
219 /* Table of devices attributes supported by this driver */
220 static const struct i7300_dev_info i7300_devs
[] = {
223 .fsb_mapping_errors
= PCI_DEVICE_ID_INTEL_I7300_MCH_ERR
,
227 struct i7300_dimm_info
{
228 int megabytes
; /* size, 0 means not present */
231 /* driver private data structure */
233 struct pci_dev
*pci_dev_16_0_fsb_ctlr
; /* 16.0 */
234 struct pci_dev
*pci_dev_16_1_fsb_addr_map
; /* 16.1 */
235 struct pci_dev
*pci_dev_16_2_fsb_err_regs
; /* 16.2 */
236 struct pci_dev
*pci_dev_2x_0_fbd_branch
[MAX_BRANCHES
]; /* 21.0 and 22.0 */
238 u16 tolm
; /* top of low memory */
239 u64 ambase
; /* AMB BAR */
244 u16 mtr
[MAX_SLOTS
][MAX_BRANCHES
]; /* Memory Technlogy Reg */
245 u16 ambpresent
[MAX_CHANNELS
]; /* AMB present regs */
247 /* DIMM information matrix, allocating architecture maximums */
248 struct i7300_dimm_info dimm_info
[MAX_SLOTS
][MAX_CHANNELS
];
251 /* FIXME: Why do we need to have this static? */
252 static struct edac_pci_ctl_info
*i7300_pci
;
254 /********************************************
255 * i7300 Functions related to error detection
256 ********************************************/
258 struct i7300_error_info
{
259 int dummy
; /* FIXME */
262 const char *get_err_from_table(const char *table
[], int size
, int pos
)
270 #define GET_ERR_FROM_TABLE(table, pos) \
271 get_err_from_table(table, ARRAY_SIZE(table), pos)
274 * i7300_get_error_info Retrieve the hardware error information from
275 * the hardware and cache it in the 'info'
278 static void i7300_get_error_info(struct mem_ctl_info
*mci
,
279 struct i7300_error_info
*info
)
284 * i7300_process_error_global Retrieve the hardware error information from
285 * the hardware and cache it in the 'info'
288 static void i7300_process_error_global(struct mem_ctl_info
*mci
,
289 struct i7300_error_info
*info
)
291 struct i7300_pvt
*pvt
;
293 unsigned long errors
;
294 const char *specific
;
299 /* read in the 1st FATAL error register */
300 pci_read_config_dword(pvt
->pci_dev_16_2_fsb_err_regs
,
301 FERR_GLOBAL_HI
, &value
);
302 if (unlikely(value
)) {
304 errnum
= find_first_bit(&errors
,
305 ARRAY_SIZE(ferr_global_hi_name
));
306 specific
= GET_ERR_FROM_TABLE(ferr_global_hi_name
, errnum
);
307 is_fatal
= ferr_global_hi_is_fatal(errnum
);
309 /* Clear the error bit */
310 pci_write_config_dword(pvt
->pci_dev_16_2_fsb_err_regs
,
311 FERR_GLOBAL_HI
, value
);
316 pci_read_config_dword(pvt
->pci_dev_16_2_fsb_err_regs
,
317 FERR_GLOBAL_LO
, &value
);
318 if (unlikely(value
)) {
320 errnum
= find_first_bit(&errors
,
321 ARRAY_SIZE(ferr_global_lo_name
));
322 specific
= GET_ERR_FROM_TABLE(ferr_global_lo_name
, errnum
);
323 is_fatal
= ferr_global_lo_is_fatal(errnum
);
325 /* Clear the error bit */
326 pci_write_config_dword(pvt
->pci_dev_16_2_fsb_err_regs
,
327 FERR_GLOBAL_LO
, value
);
334 i7300_mc_printk(mci
, KERN_EMERG
, "%s misc error: %s\n",
335 is_fatal
? "Fatal" : "NOT fatal", specific
);
339 * i7300_process_error_info Retrieve the hardware error information from
340 * the hardware and cache it in the 'info'
343 static void i7300_process_error_info(struct mem_ctl_info
*mci
,
344 struct i7300_error_info
*info
)
346 i7300_process_error_global(mci
, info
);
350 * i7300_clear_error Retrieve any error from the hardware
351 * but do NOT process that error.
352 * Used for 'clearing' out of previous errors
353 * Called by the Core module.
355 static void i7300_clear_error(struct mem_ctl_info
*mci
)
357 struct i7300_error_info info
;
359 i7300_get_error_info(mci
, &info
);
363 * i7300_check_error Retrieve and process errors reported by the
364 * hardware. Called by the Core module.
366 static void i7300_check_error(struct mem_ctl_info
*mci
)
368 struct i7300_error_info info
;
369 debugf4("MC%d: " __FILE__
": %s()\n", mci
->mc_idx
, __func__
);
371 i7300_get_error_info(mci
, &info
);
372 i7300_process_error_info(mci
, &info
);
376 * i7300_enable_error_reporting
377 * Turn on the memory reporting features of the hardware
379 static void i7300_enable_error_reporting(struct mem_ctl_info
*mci
)
383 /************************************************
384 * i7300 Functions related to memory enumberation
385 ************************************************/
388 * determine_mtr(pvt, csrow, channel)
390 * return the proper MTR register as determine by the csrow and desired channel
392 static int decode_mtr(struct i7300_pvt
*pvt
,
393 int slot
, int ch
, int branch
,
394 struct i7300_dimm_info
*dinfo
,
395 struct csrow_info
*p_csrow
)
397 int mtr
, ans
, addrBits
, channel
;
399 channel
= to_channel(ch
, branch
);
401 mtr
= pvt
->mtr
[slot
][branch
];
402 ans
= MTR_DIMMS_PRESENT(mtr
) ? 1 : 0;
404 debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n",
406 ans
? "Present" : "NOT Present");
408 /* Determine if there is a DIMM present in this DIMM slot */
411 if (!amb_present
|| !ans
)
418 /* Start with the number of bits for a Bank
420 addrBits
= MTR_DRAM_BANKS_ADDR_BITS
;
421 /* Add thenumber of ROW bits */
422 addrBits
+= MTR_DIMM_ROWS_ADDR_BITS(mtr
);
423 /* add the number of COLUMN bits */
424 addrBits
+= MTR_DIMM_COLS_ADDR_BITS(mtr
);
425 /* add the number of RANK bits */
426 addrBits
+= MTR_DIMM_RANKS(mtr
);
428 addrBits
+= 6; /* add 64 bits per DIMM */
429 addrBits
-= 20; /* divide by 2^^20 */
430 addrBits
-= 3; /* 8 bits per bytes */
432 dinfo
->megabytes
= 1 << addrBits
;
434 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr
));
436 debugf2("\t\tELECTRICAL THROTTLING is %s\n",
437 MTR_DIMMS_ETHROTTLE(mtr
) ? "enabled" : "disabled");
439 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr
));
440 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr
) ? "double" : "single");
441 debugf2("\t\tNUMROW: %s\n", numrow_toString
[MTR_DIMM_ROWS(mtr
)]);
442 debugf2("\t\tNUMCOL: %s\n", numcol_toString
[MTR_DIMM_COLS(mtr
)]);
443 debugf2("\t\tSIZE: %d MB\n", dinfo
->megabytes
);
446 p_csrow
->nr_pages
= dinfo
->megabytes
<< 8;
447 p_csrow
->mtype
= MEM_FB_DDR2
;
450 * FIXME: the type of error detection actually depends of the
451 * mode of operation. When it is just one single memory chip, at
452 * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
453 * In normal or mirrored mode, it uses Single Device Data correction,
454 * with the possibility of using an extended algorithm for x8 memories
455 * See datasheet Sections 7.3.6 to 7.3.8
457 p_csrow
->edac_mode
= EDAC_S8ECD8ED
;
459 /* ask what device type on this row */
460 if (MTR_DRAM_WIDTH(mtr
)) {
461 debugf0("Scrub algorithm for x8 is on %s mode\n",
462 IS_SCRBALGO_ENHANCED(pvt
->mc_settings
) ?
463 "enhanced" : "normal");
465 p_csrow
->dtype
= DEV_X8
;
467 p_csrow
->dtype
= DEV_X4
;
475 * also will output a DIMM matrix map, if debug is enabled, for viewing
476 * how the DIMMs are populated
478 static void print_dimm_size(struct i7300_pvt
*pvt
)
480 struct i7300_dimm_info
*dinfo
;
481 char *p
, *mem_buffer
;
486 mem_buffer
= p
= kmalloc(space
, GFP_KERNEL
);
488 i7300_printk(KERN_ERR
, "MC: %s:%s() kmalloc() failed\n",
493 n
= snprintf(p
, space
, " ");
496 for (channel
= 0; channel
< MAX_CHANNELS
; channel
++) {
497 n
= snprintf(p
, space
, "channel %d | ", channel
);
501 debugf2("%s\n", mem_buffer
);
504 n
= snprintf(p
, space
, "-------------------------------"
505 "------------------------------");
508 debugf2("%s\n", mem_buffer
);
512 for (slot
= 0; slot
< MAX_SLOTS
; slot
++) {
513 n
= snprintf(p
, space
, "csrow/SLOT %d ", slot
);
517 for (channel
= 0; channel
< MAX_CHANNELS
; channel
++) {
518 dinfo
= &pvt
->dimm_info
[slot
][channel
];
519 n
= snprintf(p
, space
, "%4d MB | ", dinfo
->megabytes
);
524 debugf2("%s\n", mem_buffer
);
529 n
= snprintf(p
, space
, "-------------------------------"
530 "------------------------------");
533 debugf2("%s\n", mem_buffer
);
541 * i7300_init_csrows Initialize the 'csrows' table within
542 * the mci control structure with the
543 * addressing of memory.
547 * 1 no actual memory found on this MC
549 static int i7300_init_csrows(struct mem_ctl_info
*mci
)
551 struct i7300_pvt
*pvt
;
552 struct i7300_dimm_info
*dinfo
;
553 struct csrow_info
*p_csrow
;
556 int ch
, branch
, slot
, channel
;
560 empty
= 1; /* Assume NO memory */
562 debugf2("Memory Technology Registers:\n");
564 /* Get the AMB present registers for the four channels */
565 for (branch
= 0; branch
< MAX_BRANCHES
; branch
++) {
566 /* Read and dump branch 0's MTRs */
567 channel
= to_channel(0, branch
);
568 pci_read_config_word(pvt
->pci_dev_2x_0_fbd_branch
[branch
], AMBPRESENT_0
,
569 &pvt
->ambpresent
[channel
]);
570 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
571 channel
, pvt
->ambpresent
[channel
]);
573 channel
= to_channel(1, branch
);
574 pci_read_config_word(pvt
->pci_dev_2x_0_fbd_branch
[branch
], AMBPRESENT_1
,
575 &pvt
->ambpresent
[channel
]);
576 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
577 channel
, pvt
->ambpresent
[channel
]);
580 /* Get the set of MTR[0-7] regs by each branch */
581 for (slot
= 0; slot
< MAX_SLOTS
; slot
++) {
582 int where
= mtr_regs
[slot
];
583 for (branch
= 0; branch
< MAX_BRANCHES
; branch
++) {
584 pci_read_config_word(pvt
->pci_dev_2x_0_fbd_branch
[branch
],
586 &pvt
->mtr
[slot
][branch
]);
587 for (ch
= 0; ch
< MAX_BRANCHES
; ch
++) {
588 int channel
= to_channel(ch
, branch
);
590 dinfo
= &pvt
->dimm_info
[slot
][channel
];
591 p_csrow
= &mci
->csrows
[slot
];
593 mtr
= decode_mtr(pvt
, slot
, ch
, branch
,
595 /* if no DIMMS on this row, continue */
596 if (!MTR_DIMMS_PRESENT(mtr
))
599 p_csrow
->csrow_idx
= slot
;
601 /* FAKE OUT VALUES, FIXME */
602 p_csrow
->first_page
= 0 + slot
* 20;
603 p_csrow
->last_page
= 9 + slot
* 20;
604 p_csrow
->page_mask
= 0xfff;
614 static void decode_mir(int mir_no
, u16 mir
[MAX_MIR
])
617 debugf2("MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n",
619 (mir
[mir_no
] >> 4) & 0xfff,
620 (mir
[mir_no
] & 1) ? "B0" : "",
621 (mir
[mir_no
] & 2) ? "B1": "");
625 * i7300_get_mc_regs read in the necessary registers and
628 * Fills in the private data members
630 static int i7300_get_mc_regs(struct mem_ctl_info
*mci
)
632 struct i7300_pvt
*pvt
;
638 pci_read_config_dword(pvt
->pci_dev_16_0_fsb_ctlr
, AMBASE
,
639 (u32
*) &pvt
->ambase
);
641 debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt
->ambase
);
643 /* Get the Branch Map regs */
644 pci_read_config_word(pvt
->pci_dev_16_1_fsb_addr_map
, TOLM
, &pvt
->tolm
);
646 debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt
->tolm
,
649 actual_tolm
= (u32
) ((1000l * pvt
->tolm
) >> (30 - 28));
650 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
651 actual_tolm
/1000, actual_tolm
% 1000, pvt
->tolm
<< 28);
653 /* Get memory controller settings */
654 pci_read_config_dword(pvt
->pci_dev_16_1_fsb_addr_map
, MC_SETTINGS
,
657 debugf0("Memory controller operating on %s mode\n",
658 IS_MIRRORED(pvt
->mc_settings
) ? "mirrored" : "non-mirrored");
659 debugf0("Error detection is %s\n",
660 IS_ECC_ENABLED(pvt
->mc_settings
) ? "enabled" : "disabled");
661 debugf0("Retry is %s\n",
662 IS_RETRY_ENABLED(pvt
->mc_settings
) ? "enabled" : "disabled");
664 /* Get Memory Interleave Range registers */
665 pci_read_config_word(pvt
->pci_dev_16_1_fsb_addr_map
, MIR0
, &pvt
->mir
[0]);
666 pci_read_config_word(pvt
->pci_dev_16_1_fsb_addr_map
, MIR1
, &pvt
->mir
[1]);
667 pci_read_config_word(pvt
->pci_dev_16_1_fsb_addr_map
, MIR2
, &pvt
->mir
[2]);
669 /* Decode the MIR regs */
670 for (i
= 0; i
< MAX_MIR
; i
++)
671 decode_mir(i
, pvt
->mir
);
673 rc
= i7300_init_csrows(mci
);
677 /* Go and determine the size of each DIMM and place in an
679 print_dimm_size(pvt
);
684 /*************************************************
685 * i7300 Functions related to device probe/release
686 *************************************************/
689 * i7300_put_devices 'put' all the devices that we have
692 static void i7300_put_devices(struct mem_ctl_info
*mci
)
694 struct i7300_pvt
*pvt
;
699 /* Decrement usage count for devices */
700 for (branch
= 0; branch
< MAX_CH_PER_BRANCH
; branch
++)
701 pci_dev_put(pvt
->pci_dev_2x_0_fbd_branch
[branch
]);
702 pci_dev_put(pvt
->pci_dev_16_2_fsb_err_regs
);
703 pci_dev_put(pvt
->pci_dev_16_1_fsb_addr_map
);
707 * i7300_get_devices Find and perform 'get' operation on the MCH's
708 * device/functions we want to reference for this driver
710 * Need to 'get' device 16 func 1 and func 2
712 static int i7300_get_devices(struct mem_ctl_info
*mci
, int dev_idx
)
714 struct i7300_pvt
*pvt
;
715 struct pci_dev
*pdev
;
719 /* Attempt to 'get' the MCH register we want */
721 while (!pvt
->pci_dev_16_1_fsb_addr_map
|| !pvt
->pci_dev_16_2_fsb_err_regs
) {
722 pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
,
723 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR
, pdev
);
725 /* End of list, leave */
726 i7300_printk(KERN_ERR
,
727 "'system address,Process Bus' "
729 "vendor 0x%x device 0x%x ERR funcs "
732 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR
);
736 /* Store device 16 funcs 1 and 2 */
737 switch (PCI_FUNC(pdev
->devfn
)) {
739 pvt
->pci_dev_16_1_fsb_addr_map
= pdev
;
742 pvt
->pci_dev_16_2_fsb_err_regs
= pdev
;
747 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
748 pci_name(pvt
->pci_dev_16_0_fsb_ctlr
),
749 pvt
->pci_dev_16_0_fsb_ctlr
->vendor
, pvt
->pci_dev_16_0_fsb_ctlr
->device
);
750 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
751 pci_name(pvt
->pci_dev_16_1_fsb_addr_map
),
752 pvt
->pci_dev_16_1_fsb_addr_map
->vendor
, pvt
->pci_dev_16_1_fsb_addr_map
->device
);
753 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
754 pci_name(pvt
->pci_dev_16_2_fsb_err_regs
),
755 pvt
->pci_dev_16_2_fsb_err_regs
->vendor
, pvt
->pci_dev_16_2_fsb_err_regs
->device
);
757 pvt
->pci_dev_2x_0_fbd_branch
[0] = pci_get_device(PCI_VENDOR_ID_INTEL
,
758 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0
,
760 if (!pvt
->pci_dev_2x_0_fbd_branch
[0]) {
761 i7300_printk(KERN_ERR
,
762 "MC: 'BRANCH 0' device not found:"
763 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
764 PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0
);
768 pvt
->pci_dev_2x_0_fbd_branch
[1] = pci_get_device(PCI_VENDOR_ID_INTEL
,
769 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
,
771 if (!pvt
->pci_dev_2x_0_fbd_branch
[1]) {
772 i7300_printk(KERN_ERR
,
773 "MC: 'BRANCH 1' device not found:"
774 "vendor 0x%x device 0x%x Func 0 "
777 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
);
784 i7300_put_devices(mci
);
789 * i7300_probe1 Probe for ONE instance of device to see if it is
792 * 0 for FOUND a device
795 static int i7300_probe1(struct pci_dev
*pdev
, int dev_idx
)
797 struct mem_ctl_info
*mci
;
798 struct i7300_pvt
*pvt
;
800 int num_dimms_per_channel
;
803 if (dev_idx
>= ARRAY_SIZE(i7300_devs
))
806 debugf0("MC: " __FILE__
": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
809 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
));
811 /* We only are looking for func 0 of the set */
812 if (PCI_FUNC(pdev
->devfn
) != 0)
815 /* As we don't have a motherboard identification routine to determine
816 * actual number of slots/dimms per channel, we thus utilize the
817 * resource as specified by the chipset. Thus, we might have
818 * have more DIMMs per channel than actually on the mobo, but this
819 * allows the driver to support upto the chipset max, without
820 * some fancy mobo determination.
822 num_dimms_per_channel
= MAX_SLOTS
;
823 num_channels
= MAX_CHANNELS
;
824 num_csrows
= MAX_SLOTS
* MAX_CHANNELS
;
826 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
827 __func__
, num_channels
, num_dimms_per_channel
, num_csrows
);
829 /* allocate a new MC control structure */
830 mci
= edac_mc_alloc(sizeof(*pvt
), num_csrows
, num_channels
, 0);
835 debugf0("MC: " __FILE__
": %s(): mci = %p\n", __func__
, mci
);
837 mci
->dev
= &pdev
->dev
; /* record ptr to the generic device */
840 pvt
->pci_dev_16_0_fsb_ctlr
= pdev
; /* Record this device in our private */
842 /* 'get' the pci devices we want to reserve for our use */
843 if (i7300_get_devices(mci
, dev_idx
))
847 mci
->mtype_cap
= MEM_FLAG_FB_DDR2
;
848 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
;
849 mci
->edac_cap
= EDAC_FLAG_NONE
;
850 mci
->mod_name
= "i7300_edac.c";
851 mci
->mod_ver
= I7300_REVISION
;
852 mci
->ctl_name
= i7300_devs
[dev_idx
].ctl_name
;
853 mci
->dev_name
= pci_name(pdev
);
854 mci
->ctl_page_to_phys
= NULL
;
856 /* Set the function pointer to an actual operation function */
857 mci
->edac_check
= i7300_check_error
;
859 /* initialize the MC control structure 'csrows' table
860 * with the mapping and control information */
861 if (i7300_get_mc_regs(mci
)) {
862 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
863 " because i7300_init_csrows() returned nonzero "
865 mci
->edac_cap
= EDAC_FLAG_NONE
; /* no csrows found */
867 debugf1("MC: Enable error reporting now\n");
868 i7300_enable_error_reporting(mci
);
871 /* add this new MC control structure to EDAC's list of MCs */
872 if (edac_mc_add_mc(mci
)) {
873 debugf0("MC: " __FILE__
874 ": %s(): failed edac_mc_add_mc()\n", __func__
);
875 /* FIXME: perhaps some code should go here that disables error
876 * reporting if we just enabled it
881 i7300_clear_error(mci
);
883 /* allocating generic PCI control info */
884 i7300_pci
= edac_pci_create_generic_ctl(&pdev
->dev
, EDAC_MOD_STR
);
887 "%s(): Unable to create PCI control\n",
890 "%s(): PCI error report via EDAC not setup\n",
896 /* Error exit unwinding stack */
899 i7300_put_devices(mci
);
907 * i7300_init_one constructor for one instance of device
913 static int __devinit
i7300_init_one(struct pci_dev
*pdev
,
914 const struct pci_device_id
*id
)
918 debugf0("MC: " __FILE__
": %s()\n", __func__
);
921 rc
= pci_enable_device(pdev
);
925 /* now probe and enable the device */
926 return i7300_probe1(pdev
, id
->driver_data
);
930 * i7300_remove_one destructor for one instance of device
933 static void __devexit
i7300_remove_one(struct pci_dev
*pdev
)
935 struct mem_ctl_info
*mci
;
937 debugf0(__FILE__
": %s()\n", __func__
);
940 edac_pci_release_generic_ctl(i7300_pci
);
942 mci
= edac_mc_del_mc(&pdev
->dev
);
946 /* retrieve references to resources, and free those resources */
947 i7300_put_devices(mci
);
953 * pci_device_id table for which devices we are looking for
955 * The "E500P" device is the first device supported.
957 static const struct pci_device_id i7300_pci_tbl
[] __devinitdata
= {
958 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR
)},
959 {0,} /* 0 terminated list. */
962 MODULE_DEVICE_TABLE(pci
, i7300_pci_tbl
);
965 * i7300_driver pci_driver structure for this module
968 static struct pci_driver i7300_driver
= {
969 .name
= "i7300_edac",
970 .probe
= i7300_init_one
,
971 .remove
= __devexit_p(i7300_remove_one
),
972 .id_table
= i7300_pci_tbl
,
976 * i7300_init Module entry function
977 * Try to initialize this module for its devices
979 static int __init
i7300_init(void)
983 debugf2("MC: " __FILE__
": %s()\n", __func__
);
985 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
988 pci_rc
= pci_register_driver(&i7300_driver
);
990 return (pci_rc
< 0) ? pci_rc
: 0;
994 * i7300_exit() Module exit function
995 * Unregister the driver
997 static void __exit
i7300_exit(void)
999 debugf2("MC: " __FILE__
": %s()\n", __func__
);
1000 pci_unregister_driver(&i7300_driver
);
1003 module_init(i7300_init
);
1004 module_exit(i7300_exit
);
1006 MODULE_LICENSE("GPL");
1007 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1008 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1009 MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
1012 module_param(edac_op_state
, int, 0444);
1013 MODULE_PARM_DESC(edac_op_state
, "EDAC Error Reporting state: 0=Poll,1=NMI");