2 * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
3 * module (C) 2006 Tim Small
5 * This file may be distributed under the terms of the GNU General
8 * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
9 * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
12 * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
14 * Written with reference to 82443BX Host Bridge Datasheet:
15 * http://download.intel.com/design/chipsets/datashts/29063301.pdf
16 * references to this document given in [].
18 * This module doesn't support the 440LX, but it may be possible to
19 * make it do so (the 440LX's register definitions are different, but
20 * not completely so - I haven't studied them in enough detail to know
21 * how easy this would be).
24 #include <linux/module.h>
25 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/pci_ids.h>
31 #include <linux/edac.h>
32 #include "edac_core.h"
34 #define I82443_REVISION "0.1"
36 #define EDAC_MOD_STR "i82443bxgx_edac"
38 /* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
39 * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
40 * rows" "The 82443BX supports multiple-bit error detection and
41 * single-bit error correction when ECC mode is enabled and
42 * single/multi-bit error detection when correction is disabled.
43 * During writes to the DRAM, the 82443BX generates ECC for the data
44 * on a QWord basis. Partial QWord writes require a read-modify-write
45 * cycle when ECC is enabled."
48 /* "Additionally, the 82443BX ensures that the data is corrected in
49 * main memory so that accumulation of errors is prevented. Another
50 * error within the same QWord would result in a double-bit error
51 * which is unrecoverable. This is known as hardware scrubbing since
52 * it requires no software intervention to correct the data in memory."
55 /* [Also see page 100 (section 4.3), "DRAM Interface"]
56 * [Also see page 112 (section 4.6.1.4), ECC]
59 #define I82443BXGX_NR_CSROWS 8
60 #define I82443BXGX_NR_CHANS 1
61 #define I82443BXGX_NR_DIMMS 4
63 /* 82443 PCI Device 0 */
64 #define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
65 * config space offset */
66 #define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
68 #define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
70 #define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
71 #define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
72 #define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
73 #define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
74 #define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
76 #define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
78 /* 82443 PCI Device 0 */
79 #define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
80 * config space offset, Error Address
82 #define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
83 #define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
84 #define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
86 #define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
87 * config space offset. */
88 #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
89 #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
91 #define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
92 * config space offset. */
93 #define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
94 #define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
95 #define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
96 #define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
98 #define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
99 * config space offset. */
100 #define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
101 #define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
102 #define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
103 #define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
105 #define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
106 * config space offset. */
108 /* FIXME - don't poll when ECC disabled? */
110 struct i82443bxgx_edacmc_error_info
{
114 static struct edac_pci_ctl_info
*i82443bxgx_pci
;
116 static struct pci_dev
*mci_pdev
; /* init dev: in case that AGP code has
117 * already registered driver
120 static int i82443bxgx_registered
= 1;
122 static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info
*mci
,
123 struct i82443bxgx_edacmc_error_info
126 struct pci_dev
*pdev
;
127 pdev
= to_pci_dev(mci
->dev
);
128 pci_read_config_dword(pdev
, I82443BXGX_EAP
, &info
->eap
);
129 if (info
->eap
& I82443BXGX_EAP_OFFSET_SBE
)
130 /* Clear error to allow next error to be reported [p.61] */
131 pci_write_bits32(pdev
, I82443BXGX_EAP
,
132 I82443BXGX_EAP_OFFSET_SBE
,
133 I82443BXGX_EAP_OFFSET_SBE
);
135 if (info
->eap
& I82443BXGX_EAP_OFFSET_MBE
)
136 /* Clear error to allow next error to be reported [p.61] */
137 pci_write_bits32(pdev
, I82443BXGX_EAP
,
138 I82443BXGX_EAP_OFFSET_MBE
,
139 I82443BXGX_EAP_OFFSET_MBE
);
142 static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info
*mci
,
144 i82443bxgx_edacmc_error_info
145 *info
, int handle_errors
)
148 u32 eapaddr
, page
, pageoffset
;
150 /* bits 30:12 hold the 4kb block in which the error occurred
152 eapaddr
= (info
->eap
& 0xfffff000);
153 page
= eapaddr
>> PAGE_SHIFT
;
154 pageoffset
= eapaddr
- (page
<< PAGE_SHIFT
);
156 if (info
->eap
& I82443BXGX_EAP_OFFSET_SBE
) {
159 edac_mc_handle_ce(mci
, page
, pageoffset
,
160 /* 440BX/GX don't make syndrome information
162 0, edac_mc_find_csrow_by_page(mci
, page
), 0,
166 if (info
->eap
& I82443BXGX_EAP_OFFSET_MBE
) {
169 edac_mc_handle_ue(mci
, page
, pageoffset
,
170 edac_mc_find_csrow_by_page(mci
, page
),
177 static void i82443bxgx_edacmc_check(struct mem_ctl_info
*mci
)
179 struct i82443bxgx_edacmc_error_info info
;
181 debugf1("MC%d: %s: %s()\n", mci
->mc_idx
, __FILE__
, __func__
);
182 i82443bxgx_edacmc_get_error_info(mci
, &info
);
183 i82443bxgx_edacmc_process_error_info(mci
, &info
, 1);
186 static void i82443bxgx_init_csrows(struct mem_ctl_info
*mci
,
187 struct pci_dev
*pdev
,
188 enum edac_type edac_mode
,
191 struct csrow_info
*csrow
;
192 struct dimm_info
*dimm
;
195 u32 row_base
, row_high_limit
, row_high_limit_last
;
197 pci_read_config_byte(pdev
, I82443BXGX_DRAMC
, &dramc
);
198 row_high_limit_last
= 0;
199 for (index
= 0; index
< mci
->nr_csrows
; index
++) {
200 csrow
= &mci
->csrows
[index
];
201 dimm
= csrow
->channels
[0].dimm
;
203 pci_read_config_byte(pdev
, I82443BXGX_DRB
+ index
, &drbar
);
204 debugf1("MC%d: %s: %s() Row=%d DRB = %#0x\n",
205 mci
->mc_idx
, __FILE__
, __func__
, index
, drbar
);
206 row_high_limit
= ((u32
) drbar
<< 23);
207 /* find the DRAM Chip Select Base address and mask */
208 debugf1("MC%d: %s: %s() Row=%d, "
209 "Boundary Address=%#0x, Last = %#0x\n",
210 mci
->mc_idx
, __FILE__
, __func__
, index
, row_high_limit
,
211 row_high_limit_last
);
213 /* 440GX goes to 2GB, represented with a DRB of 0. */
214 if (row_high_limit_last
&& !row_high_limit
)
215 row_high_limit
= 1UL << 31;
217 /* This row is empty [p.49] */
218 if (row_high_limit
== row_high_limit_last
)
220 row_base
= row_high_limit_last
;
221 csrow
->first_page
= row_base
>> PAGE_SHIFT
;
222 csrow
->last_page
= (row_high_limit
>> PAGE_SHIFT
) - 1;
223 dimm
->nr_pages
= csrow
->last_page
- csrow
->first_page
+ 1;
224 /* EAP reports in 4kilobyte granularity [61] */
225 dimm
->grain
= 1 << 12;
227 /* I don't think 440BX can tell you device type? FIXME? */
228 dimm
->dtype
= DEV_UNKNOWN
;
229 /* Mode is global to all rows on 440BX */
230 dimm
->edac_mode
= edac_mode
;
231 row_high_limit_last
= row_high_limit
;
235 static int i82443bxgx_edacmc_probe1(struct pci_dev
*pdev
, int dev_idx
)
237 struct mem_ctl_info
*mci
;
239 u32 nbxcfg
, ecc_mode
;
241 enum edac_type edac_mode
;
243 debugf0("MC: %s: %s()\n", __FILE__
, __func__
);
245 /* Something is really hosed if PCI config space reads from
246 * the MC aren't working.
248 if (pci_read_config_dword(pdev
, I82443BXGX_NBXCFG
, &nbxcfg
))
251 mci
= edac_mc_alloc(0, I82443BXGX_NR_CSROWS
, I82443BXGX_NR_CHANS
, 0);
256 debugf0("MC: %s: %s(): mci = %p\n", __FILE__
, __func__
, mci
);
257 mci
->dev
= &pdev
->dev
;
258 mci
->mtype_cap
= MEM_FLAG_EDO
| MEM_FLAG_SDR
| MEM_FLAG_RDR
;
259 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_EC
| EDAC_FLAG_SECDED
;
260 pci_read_config_byte(pdev
, I82443BXGX_DRAMC
, &dramc
);
261 switch ((dramc
>> I82443BXGX_DRAMC_OFFSET_DT
) & (BIT(0) | BIT(1))) {
262 case I82443BXGX_DRAMC_DRAM_IS_EDO
:
265 case I82443BXGX_DRAMC_DRAM_IS_SDRAM
:
268 case I82443BXGX_DRAMC_DRAM_IS_RSDRAM
:
272 debugf0("Unknown/reserved DRAM type value "
273 "in DRAMC register!\n");
274 mtype
= -MEM_UNKNOWN
;
277 if ((mtype
== MEM_SDR
) || (mtype
== MEM_RDR
))
278 mci
->edac_cap
= mci
->edac_ctl_cap
;
280 mci
->edac_cap
= EDAC_FLAG_NONE
;
282 mci
->scrub_cap
= SCRUB_FLAG_HW_SRC
;
283 pci_read_config_dword(pdev
, I82443BXGX_NBXCFG
, &nbxcfg
);
284 ecc_mode
= ((nbxcfg
>> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY
) &
287 mci
->scrub_mode
= (ecc_mode
== I82443BXGX_NBXCFG_INTEGRITY_SCRUB
)
288 ? SCRUB_HW_SRC
: SCRUB_NONE
;
291 case I82443BXGX_NBXCFG_INTEGRITY_NONE
:
292 edac_mode
= EDAC_NONE
;
294 case I82443BXGX_NBXCFG_INTEGRITY_EC
:
297 case I82443BXGX_NBXCFG_INTEGRITY_ECC
:
298 case I82443BXGX_NBXCFG_INTEGRITY_SCRUB
:
299 edac_mode
= EDAC_SECDED
;
302 debugf0("%s(): Unknown/reserved ECC state "
303 "in NBXCFG register!\n", __func__
);
304 edac_mode
= EDAC_UNKNOWN
;
308 i82443bxgx_init_csrows(mci
, pdev
, edac_mode
, mtype
);
310 /* Many BIOSes don't clear error flags on boot, so do this
311 * here, or we get "phantom" errors occurring at module-load
313 pci_write_bits32(pdev
, I82443BXGX_EAP
,
314 (I82443BXGX_EAP_OFFSET_SBE
|
315 I82443BXGX_EAP_OFFSET_MBE
),
316 (I82443BXGX_EAP_OFFSET_SBE
|
317 I82443BXGX_EAP_OFFSET_MBE
));
319 mci
->mod_name
= EDAC_MOD_STR
;
320 mci
->mod_ver
= I82443_REVISION
;
321 mci
->ctl_name
= "I82443BXGX";
322 mci
->dev_name
= pci_name(pdev
);
323 mci
->edac_check
= i82443bxgx_edacmc_check
;
324 mci
->ctl_page_to_phys
= NULL
;
326 if (edac_mc_add_mc(mci
)) {
327 debugf3("%s(): failed edac_mc_add_mc()\n", __func__
);
331 /* allocating generic PCI control info */
332 i82443bxgx_pci
= edac_pci_create_generic_ctl(&pdev
->dev
, EDAC_MOD_STR
);
333 if (!i82443bxgx_pci
) {
335 "%s(): Unable to create PCI control\n",
338 "%s(): PCI error report via EDAC not setup\n",
342 debugf3("MC: %s: %s(): success\n", __FILE__
, __func__
);
350 EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1
);
352 /* returns count (>= 0), or negative on error */
353 static int __devinit
i82443bxgx_edacmc_init_one(struct pci_dev
*pdev
,
354 const struct pci_device_id
*ent
)
358 debugf0("MC: %s: %s()\n", __FILE__
, __func__
);
360 /* don't need to call pci_enable_device() */
361 rc
= i82443bxgx_edacmc_probe1(pdev
, ent
->driver_data
);
363 if (mci_pdev
== NULL
)
364 mci_pdev
= pci_dev_get(pdev
);
369 static void __devexit
i82443bxgx_edacmc_remove_one(struct pci_dev
*pdev
)
371 struct mem_ctl_info
*mci
;
373 debugf0("%s: %s()\n", __FILE__
, __func__
);
376 edac_pci_release_generic_ctl(i82443bxgx_pci
);
378 if ((mci
= edac_mc_del_mc(&pdev
->dev
)) == NULL
)
384 EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one
);
386 static DEFINE_PCI_DEVICE_TABLE(i82443bxgx_pci_tbl
) = {
387 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
)},
388 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
)},
389 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443GX_0
)},
390 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443GX_2
)},
391 {0,} /* 0 terminated list. */
394 MODULE_DEVICE_TABLE(pci
, i82443bxgx_pci_tbl
);
396 static struct pci_driver i82443bxgx_edacmc_driver
= {
397 .name
= EDAC_MOD_STR
,
398 .probe
= i82443bxgx_edacmc_init_one
,
399 .remove
= __devexit_p(i82443bxgx_edacmc_remove_one
),
400 .id_table
= i82443bxgx_pci_tbl
,
403 static int __init
i82443bxgx_edacmc_init(void)
406 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
409 pci_rc
= pci_register_driver(&i82443bxgx_edacmc_driver
);
413 if (mci_pdev
== NULL
) {
414 const struct pci_device_id
*id
= &i82443bxgx_pci_tbl
[0];
416 i82443bxgx_registered
= 0;
418 while (mci_pdev
== NULL
&& id
->vendor
!= 0) {
419 mci_pdev
= pci_get_device(id
->vendor
,
422 id
= &i82443bxgx_pci_tbl
[i
];
425 debugf0("i82443bxgx pci_get_device fail\n");
430 pci_rc
= i82443bxgx_edacmc_init_one(mci_pdev
, i82443bxgx_pci_tbl
);
433 debugf0("i82443bxgx init fail\n");
442 pci_unregister_driver(&i82443bxgx_edacmc_driver
);
445 if (mci_pdev
!= NULL
)
446 pci_dev_put(mci_pdev
);
451 static void __exit
i82443bxgx_edacmc_exit(void)
453 pci_unregister_driver(&i82443bxgx_edacmc_driver
);
455 if (!i82443bxgx_registered
)
456 i82443bxgx_edacmc_remove_one(mci_pdev
);
459 pci_dev_put(mci_pdev
);
462 module_init(i82443bxgx_edacmc_init
);
463 module_exit(i82443bxgx_edacmc_exit
);
465 MODULE_LICENSE("GPL");
466 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
467 MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
469 module_param(edac_op_state
, int, 0444);
470 MODULE_PARM_DESC(edac_op_state
, "EDAC Error Reporting state: 0=Poll,1=NMI");